Semiconductor device and manufacturing process

Abstract

Method for manufacturing a semiconductor device, comprising: Providing a semiconductor substrate (102) with a first principal surface (104) and a second principal surface (106) opposite the first principal surface (104), wherein the semiconductor substrate (102) comprises a first dopant and a second dopant, and a covalent atomic radius of a material of the semiconductor substrate (102) is i) greater than a covalent atomic radius of the first dopant and less than a covalent atomic radius of the second dopant, or ii) less than a covalent atomic radius of the first dopant and greater than a covalent atomic radius of the second dopant, and wherein a vertical extension of the first dopant into the semiconductor substrate (102) from the first principal surface (104) terminates at a base of a first semiconductor substrate region (108) at a first vertical distance (t1) to the first principal surface (104); thereafter Formation of a semiconductor layer (110) in contact with the first main surface (104), Formation of source or drain regions of field-effect transistors, or emitter or collector regions of IGBTs, or cathode or anode regions of diodes or thyristors, or emitter or base or collector regions of bipolar transistors in the semiconductor layer (110); and Reducing the thickness of the semiconductor substrate (102) by removing material from the semiconductor substrate (102) from the second main surface (106) at least to the first semiconductor substrate region (108), wherein, after reducing the thickness of the semiconductor substrate (102), a vertical concentration profile N1(y) of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate (102) and the semiconductor layer (110) at the first main surface (104) to a surface of the semiconductor substrate (102) opposite the interface (114), and the opposite surface of the semiconductor substrate (102) being the surface from which the thickness of the semiconductor substrate was reduced, and wherein the dose, energy, and heat balance for broadening a vertical concentration profile N1(y) of the first dopant and the dose, energy, and heat balance for broadeninga vertical concentration profile N2(y) of the second dopant is coordinated to . ∫ 0t | N 1 ( y ) − N 2 ( y ) | dy ∫ 0 t N 1 ( y ) dy < 100% , to satisfy, where t is a thickness of the semiconductor substrate (102) after a -reduction of the thickness of the semiconductor substrate (102).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor device and to a method for manufacturing a semiconductor device with a doped semiconductor substrate. BACKGROUND

[0002] In the fabrication of semiconductor devices, semiconductor substrates, such as semiconductor wafers, are used as the starting point for the manufacturing process. Depending on the size of the semiconductor substrate and the size of the chip, a large number of semiconductor chips can be produced from a single semiconductor substrate, for example, by cutting wafers. Alternatively, a single semiconductor chip can be produced from a single semiconductor substrate, for example, a semiconductor power thyristor or a semiconductor power diode. Semiconductor devices and manufacturing processes are described by way of example in the publications DE 10 2005 014 157 A1, US 2006 / 0 131 649 A1, US 2010 / 0 261 319 A1, EP 1 920 469 B1 and US 2016 / 0 197 164 A1.Since the characteristics of the semiconductor substrate can influence the reliability of the manufacturing process as well as the device parameters of the semiconductor chips formed in the semiconductor substrate, it is desirable to improve the characteristics of semiconductor substrates for the manufacture of devices and to provide semiconductor devices based on improved semiconductor substrates. SUMMARY

[0003] The invention is defined in the independent patent claims. Further developments are the subject of the dependent patent claims.

[0004] The present disclosure relates to a method for manufacturing a semiconductor device. The method comprises providing a semiconductor substrate with a first principal surface and a second principal surface opposite the first principal surface, wherein the semiconductor substrate comprises a first dopant and a second dopant, and a covalent atomic radius of one of the semiconductor substrate materials is i) greater than the covalent atomic radius of the first dopant and less than the covalent atomic radius of the second dopant, or ii) less than the covalent atomic radius of the first dopant and greater than the covalent atomic radius of the second dopant. A vertical extension of the first dopant into the semiconductor substrate from the first principal surface terminates at the base of a first semiconductor substrate region at a first vertical distance from the first principal surface.The process further comprises forming a semiconductor layer on the first main surface and forming semiconductor device elements in the semiconductor layer. The process further comprises reducing the thickness of the semiconductor substrate by removing material from the semiconductor substrate from the second main surface at least as far as the first semiconductor substrate region.

[0005] The present disclosure further relates to a semiconductor device with a semiconductor substrate. The semiconductor substrate comprises a first dopant and a second dopant, wherein a covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than a covalent atomic radius of the first dopant and larger than a covalent atomic radius of the second dopant. The semiconductor device further comprises a semiconductor layer on the semiconductor substrate and semiconductor device elements in the semiconductor layer. A vertical concentration profile N1(y) of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate and the semiconductor layer to a surface of the semiconductor substrate opposite the interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are enclosed to provide a further understanding of the embodiments and are incorporated into and form part of this description. The drawings illustrate the embodiments and, together with the description, serve to explain the principles of the embodiments. Further embodiments are described in detail in the following description and the claims. Fig. Figures 1A to 1D are schematic cross-sectional views of a semiconductor substrate to illustrate an embodiment of a method for manufacturing a semiconductor device. Fig. Figure 2 is a schematic cross-sectional view of a semiconductor substrate to illustrate a process for introducing a first dopant through a first main surface into the semiconductor substrate. Fig. Figure 3 is a schematic cross-sectional view of a semiconductor substrate to illustrate a process for forming a diffusion barrier on the first main surface of the semiconductor substrate after the introduction of the first dopant. Fig. Figure 4 is a schematic cross-sectional view of a semiconductor substrate to illustrate a coordination of vertical dopant concentration profiles of first and second dopants. Fig. Figure 5 is a schematic cross-sectional view of a semiconductor substrate to illustrate vertical dopant concentration profiles of the first dopant, which decrease between opposite sides of the semiconductor substrate. Fig. 6A and Fig. Figure 6B shows schematic cross-sectional views of a semiconductor substrate to illustrate processes for introducing the first dopant into the semiconductor substrate through opposing surfaces, followed by the formation of a sealing layer on one of the opposing surfaces. Fig. 7A and Fig. Figure 7B shows schematic cross-sectional views of a semiconductor substrate to illustrate processes for introducing arsenic and phosphorus into the semiconductor substrate in conjunction with different heat balances for drive-in to coordinate an optimal overlap of arsenic and phosphorus concentration profiles. DETAILED DESCRIPTION

[0007] The following detailed description refers to the accompanying drawings, which form part thereof and in which specific embodiments are shown for illustrative purposes, illustrating how a SiC device can be implemented in practice. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of this disclosure. For example, features illustrated or described for one embodiment may be used in or in connection with other embodiments to arrive at yet another embodiment. It is intended that this disclosure includes such modifications and changes. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference symbols in the various drawings, unless otherwise stated.

[0008] The terms "have," "contain," "comprise," "exhibit," and similar terms are open-ended, indicating the presence of the identified structures, elements, or features, but not excluding the presence of additional elements or features. Indefinite and definite articles should encompass both the plural and singular unless the context clearly indicates otherwise.

[0009] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question, or a low-resistance connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more intermediate elements suitable for signal / power transmission may be present between the electrically coupled elements, for example, elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0010] Ranges specified for a parameter include the boundary values. For example, a range for a parameter y from a to b is read as a ≤ y ≤ b. A parameter y with a value of at least c is read as c ≤ y, and a parameter y with a value of at most d is read as y ≤ d.

[0011] IGFETs (insulated gate field-effect transistors) are voltage-controlled devices that include MOSFETs (metal-oxide-semiconductor FETs) and other FETs with gate electrodes based on doped semiconductor material and / or gate dielectrics that are not based exclusively on an oxide.

[0012] Fig. Figures 1A to 1D are schematic cross-sectional views of a semiconductor substrate 102 to illustrate an embodiment for manufacturing a semiconductor device.

[0013] Referring to the schematic cross-sectional view of Fig. In 1A, a semiconductor substrate 102 is provided, wherein the semiconductor substrate 102 has a first main surface 104 and a second main surface 106, which is opposite the first main surface 104 along a vertical direction y. The semiconductor substrate 102 comprises a first dopant and a second dopant. For illustrative purposes, the first dopant is shown in Fig. 1A is exemplified by the symbol "o". Similarly, in Fig. 1A The second dopant is represented by the symbol “x” as an example. The term dopant here refers to a type of dopant, for example, an element such as phosphorus, which is an n-type dopant in silicon, or arsenic, which is another n-type dopant in silicon. The first and second dopants are different. The semiconductor substrate 102 can be a semiconductor wafer made of a crystalline material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), or an A III B V -semiconductors. The semiconductor substrate 102 can, for example, have a diameter of 200 mm, 300 mm or 450 mm.

[0014] The covalent atomic radius of a material of the semiconductor substrate 102 is i) larger than the covalent atomic radius of the first dopant and smaller than the covalent atomic radius of the second dopant, or ii) smaller than the covalent atomic radius of the first dopant and larger than the covalent atomic radius of the second dopant. To illustrate case i), if silicon (Si) is used as the material of the semiconductor substrate 102, the first dopant can be phosphorus (P). Silicon has a covalent atomic radius of 111 pm, which is larger than the covalent atomic radius of phosphorus, which is 107 pm. The second dopant can be arsenic, with a covalent atomic radius of 119 pm. The covalent atomic radius of silicon is smaller than the covalent atomic radius of arsenic.To illustrate case ii), if silicon (Si) is used as the material of the semiconductor substrate 102, the first dopant can be arsenic, and the second dopant can be phosphorus. According to the [reference] in [reference], Fig. In the illustrated example 1A, a vertical extension of the first dopant into the semiconductor substrate 102 from the first main surface 104 ends at a bottom 109 of a first semiconductor substrate region 108 at a first vertical distance t1 from the first main surface 104. In a second substrate region, which is directly adjacent to the first semiconductor substrate region 108 at the bottom side 109, the first dopant is absent or at least less than 10 14 dopants per cm 3The second substrate region can extend to the second main surface 106 or can be located between the first semiconductor substrate region 108 and a third substrate region. In the latter case, the first dopant can again be present in the third substrate region, which can extend, for example, to the second main surface 106.

[0015] Referring to the schematic cross-sectional view of Fig. 1B further comprises the formation of a semiconductor layer 110 on the first main surface 104. The semiconductor layer can be formed by a layering process, for example, CVD (chemical vapor deposition) such as LPCVD (low-pressure CVD) or APCVD (atmospheric pressure CVD), VPE (gas-phase epitaxy), LPE (liquid-phase epitaxy), or MBE (molecular beam epitaxy). The material of the semiconductor layer 110 can be the same as the material of the semiconductor substrate 102 or it can be different from the material of the semiconductor substrate 102. In the latter case, this can make it possible to adjust electrical characteristics in the semiconductor layer 110, for example, by a voltage-induced increase in mobility.

[0016] Referring to the schematic cross-sectional view of Fig. 1C further comprises the formation of semiconductor device elements 1121, 1122 in the semiconductor layer 110. The semiconductor device elements 1121, 1122 can be doped semiconductor regions, for example n-doped and / or p-doped semiconductor regions, for functional purposes, for example source or drain regions of insulated-gate field-effect transistors (IGFETs) such as metal-oxide-semiconductor FETs (MOSFETs) or insulated-gate bipolar transistors (IGBTs), cathode or anode regions of diodes or thyristors / silicon-controlled rectifiers, emitter or base or collector regions of bipolar junction or planar transistors (BJTs), junction orTransition termination structures such as a variation of lateral doping (VLD) or a joint termination extension (JTE), transition insulation, resistors, electrodes such as gate or field electrodes, insulating materials, for example oxides and / or nitrides, for functional purposes such as a gate dielectric, a field dielectric, device insulation such as shallow or deep trench insulation (STI, DTI).

[0017] Referring to the schematic cross-sectional view of Fig. 1D further comprises reducing the thickness of the semiconductor substrate 102 by removing material from the semiconductor substrate 102 from the second main surface 106 at least as far as the first semiconductor substrate region 108. The semiconductor substrate 102 and the semiconductor layer 110 can, for example, be mechanically supported or carried by a carrier attached to a semiconductor layer 110. Material from the semiconductor substrate 102 can be removed by chemical processes, for example by etching such as dry etching or wet etching, by mechanical processes, for example by abrasive machining such as grinding or polishing, or by chemical-mechanical processes, such as chemical-mechanical polishing (CMP).In one or more embodiments, a combination of more than one process can be used to remove material from the semiconductor substrate 102, for example, a first process with a higher material removal rate than a second process following the first. This can, for example, enable fine-tuning of a target wafer thickness. The process for removing material from the semiconductor substrate 102 from the second surface 106 can also include a so-called TAIKO process. The TAIKO process is a wafer thinning process in which an outer support ring along the edge of the wafer is not thinned during the thinning process. The outer support ring can provide improved handling of thin wafers during subsequent processing. For example, wafers thinned using the TAIKO process can typically retain their stiffness without being attached to an additional support.

[0018] The above method enables the improvement of the characteristics of highly doped, i.e., low-resistance or high-conductivity, semiconductor substrates for device fabrication by reducing a total stress or lattice mismatch in the semiconductor substrate 102. While the first dopant can cause an increase (decrease) of a lattice constant with respect to the semiconductor substrate 102, the second dopant can counteract this increase (decrease). This allows for low-resistance semiconductor substrates with respect to a given wafer curvature.

[0019] Referring to the in Fig. Figure 2, a schematic cross-sectional view, illustrates the steps for providing the semiconductor substrate 102 in one or more embodiments. These steps include introducing the first dopant through the first main surface 104 into the semiconductor substrate 102 by at least one diffusion process, one ion implantation process, and one plasma-based ion implantation process. The introduction of the first dopant through the first main surface 104 is schematically illustrated by arrows designated by reference numeral 112.Plasma-based ion implantation is known by a variety of names and acronyms, including, but not limited to, the following: plasma source ion implantation (PSII), plasma immersion ion implantation (PIII or PI3), plasma ion implantation (PII or PI2), plasma ion plating (PIP), plasma immersion ion implantation and deposition (PIIID), metal plasma immersion ion implantation and deposition (MePIIID), ion plating (IonClad), plasma doping (PLAD), and plasma ion immersion processing (PIIP). Some of these names are synonymous; others emphasize a particular aspect, such as the presence of metal ions. The steps for providing the semiconductor substrate 102 further include introducing the second dopant through the first main surface 104 into the semiconductor substrate 102 by at least one diffusion process, one ion implantation process and one plasma-based ion implantation process.The processes for introducing the first dopant and the second dopant may be different from each other, may be partially different from each other, or may be the same.

[0020] In one or more embodiments, the first vertical distance t1 lies in a range of 2 µm to 50 µm or from 5 µm to 30 µm. The first vertical distance t1 can be set to a desired value by adjusting process parameters such as ion implantation parameters, for example, an ion implantation energy, an implantation dose, and a subsequent heat balance for activating and broadening a dopant profile by diffusion.

[0021] In one or more embodiments, the first dopant is introduced into the semiconductor substrate 102 through the first main surface 104 by means of a diffusion process that is carried out simultaneously with an oxidation process of the semiconductor substrate 102. The oxidation process, for example at temperatures ranging from 800°C to 1200°C, can lead to an oxidation-enhanced diffusion process of the first dopant in the semiconductor substrate 102, for example caused by the influence of the oxidation process on vacancy and interstitial silicon atoms in a silicon-based semiconductor substrate 102. This can simplify the setting of a target profile for the first dopant in the semiconductor substrate 102.

[0022] In one or more embodiments, the first dopant is introduced by a plasma-based ion implantation process at a dose in the range of 10 16 cm -2up to 10 18 cm -2 The first main surface 104 is introduced into the semiconductor substrate 102. Plasma-based ion implantation processes can enable high concentration values ​​of the first (second) dopant in the semiconductor substrate 102 and therefore a low-resistance semiconductor substrate 102.

[0023] Referring to the schematic cross-sectional view of Fig. 3. According to one or more embodiments, a diffusion barrier 113, for example a CVD oxide, is formed on the first main surface 104 of the semiconductor substrate 102 after the introduction of the first dopant, and subsequently a vertical concentration profile of the first dopant is broadened by a thermal diffusion process. Broadening the vertical concentration profile can increase an initial vertical distance ti between a base of the vertical concentration profile and the first main surface 104 by a value Δt up to, for example, the first vertical distance t1.

[0024] In one or more embodiments, the first dopant and the second dopant are sequentially introduced into the semiconductor substrate 102 through the first primary surface via an ion implantation process or a plasma-based ion implantation process at different doses and / or energies. This allows for precise control of the dose of the first and second dopants. A vertical concentration profile of the first dopant and a vertical concentration profile of the second dopant can be superimposed by coordinating i) a dose, energy, and heat balance to broaden the vertical concentration profile of the first dopant and ii) a dose, energy, and heat balance to broaden the vertical concentration profile of the second dopant. This can, for example, improve the reduction of wafer warping and stress.

[0025] Referring to the schematic graphic representation of Fig. 4 In one or more embodiments, the dose, energy and heat balance for broadening a vertical concentration profile N1(y) of the first dopant and the dose, energy and heat balance for broadening a vertical concentration profile N2(y) of the second dopant are coordinated to obtain the following equation (1) ∫0t|N1(y)−N2(y)|dy∫0tN1(y)dy<100%, to satisfy, where t is the thickness of the semiconductor substrate 102 after a reduction of the thickness of the semiconductor substrate 102, i.e., not including the thickness of the semiconductor layer 110. Dose, energy, and heat balance can be adjusted even more precisely to satisfy the following equation (2) ∫0t|N1(y)−N2(y)|dy∫0tN1(y)dy<50%, or even the following equation (3) ∫0t|N1(y)−N2(y)|dy∫0tN1(y)dy<10%, to fulfill.

[0026] By precisely adjusting the dose, energy, and heat balance with respect to the first and second dopants, for example, a reduction in wafer warping and stress can be further improved.

[0027] Referring to the schematic cross-sectional view of Fig. 5 In one or more embodiments, after reducing the thickness of the semiconductor substrate 102 to a value t, a vertical concentration profile N1(y) of the first dopant decreases along at least 80% of a distance between an interface 114 of the semiconductor substrate 102 and the semiconductor layer 110 to a surface of the semiconductor substrate 102 opposite the interface 114. The distance corresponds to the thickness t. The vertical concentration profile N1 can decrease continuously, as shown by exemplary profiles N11, N12, N13, N14 in the graphical representation of Fig. Figure 5 illustrates this. In one or more embodiments, the concentration N1b of the first dopant at a vertical distance tb to the interface 114 is 10 times lower, 5 times lower, or 3 times lower than the concentration N1a of the first dopant at a vertical distance ta to the interface 114, wherein the difference between tb and ta, i.e., tb - ta, is greater than 80% of the distance t between the interface 114 of the semiconductor substrate 102 and the semiconductor layer 110 to the surface of the semiconductor substrate 102 opposite the interface 114. In one or more embodiments, a backside doping process can be performed from the side opposite the interface 114, for example, by ion implantation or by plasma-based ion implantation in combination with an optional melting or non-melting laser annealing step.This can, for example, improve the contact resistance between the semiconductor substrate 102 and a backside metallization layer.

[0028] The method can further comprise forming a first load terminal contact L1 on a surface of the semiconductor layer 110, for example, a source contact of an IGFET or IGBT, an emitter contact of a BJT, an anode contact of a diode, or a thyristor. The method can further comprise forming a second load terminal contact L2 on a surface of the semiconductor substrate 102 opposite the interface 114, for example, a drain contact of an IGFET, a collector contact of an IGBT or BJT, or a cathode contact of a diode or thyristor. Depending on the specific device type of the semiconductor device, a control terminal contact C can be formed on the surface of the semiconductor layer 110, for example, a gate contact of an IGFET, IGBT, or thyristor, or a base contact of a BJT.

[0029] In one or more embodiments, the average concentration of the vertical concentration profile N1(y) of the first dopant between the interface 114 of the semiconductor substrate 102 and the semiconductor layer 110 and a surface of the semiconductor substrate opposite the interface lies in a range of 5×10 18 cm -3 up to 5×10 20 cm -3 .

[0030] In one or more embodiments, the second dopant forms a background doping of the semiconductor substrate in a range of 10 18 cm -3 up to 10 21 cm -3 In one or more embodiments, the second dopant is arsenic, and the first dopant is phosphorus.

[0031] In one or more embodiments, the first dopant is an element consisting of arsenic, phosphorus, and antimony, and the second dopant is another element consisting of arsenic, phosphorus, and antimony, provided that a covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than a covalent atomic radius of the first dopant and larger than a covalent atomic radius of the second dopant.In one or more other embodiments, the first dopant is an element of boron, aluminum, and gallium, and the second dopant is another element of boron, aluminum, and gallium, provided that a covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant, or ii) smaller than a covalent atomic radius of the first dopant and larger than a covalent atomic radius of the second dopant.

[0032] Referring to the schematic cross-sectional view of Fig. 6A comprises, in one or more embodiments, providing the semiconductor substrate 102 and further introducing the first dopant through the first main surface 104 and through the second main surface 106 into the semiconductor substrate 102 by means of at least one diffusion process, one ion implantation process, and one plasma-based ion implantation process. For example, furnace doping can enable the first dopant to be introduced into the semiconductor substrate through the first main surface 104 and through the second main surface 106 simultaneously. Referring to the schematic cross-sectional view of Fig. In step 6B, a sealing layer 116 is formed on the second main surface 106 of the semiconductor substrate 102 before the thickness of the semiconductor substrate is reduced. The formation of the sealing layer 116 can enable autodoping during subsequent processing of the semiconductor substrate 102, for example, during the step with respect to Fig. 1B to 1C illustrated processes to prevent.

[0033] Referring to the schematic graphic representations of Fig. 7A and Fig. In step 7B, arsenic is introduced as the first dopant into the semiconductor substrate 102, and phosphorus is introduced as the second dopant. Due to the different diffusion coefficients of arsenic and phosphorus, different heat balances can be used to determine dopant concentration profiles N. As , N Pof arsenic and phosphorus. In one or more embodiments, a first ion implantation and plasma-based ion implantation process of arsenic and a first process for driving in the implanted arsenic can be followed by a second ion implantation or plasma-based ion implantation process of phosphorus and a second process for driving in both the implanted arsenic and the implanted phosphorus. This allows different heat balances to be applied to arsenic and phosphorus to achieve optimal overlap of the dopant concentration profiles N. AS , N P to coordinate arsenic and phosphorus, as in Fig. Figure 7B illustrates the results of a TCAD (Technology Computer-Aided Design) simulation.

[0034] In one or more embodiments, the thickness of the semiconductor substrate is reduced to a value in the range of 2 µm to 50 µm or from 5 µm to 30 µm.

Claims

[1] Method for manufacturing a semiconductor device, comprising: Providing a semiconductor substrate (102) with a first principal surface (104) and a second principal surface (106) opposite the first principal surface (104), wherein the semiconductor substrate (102) comprises a first dopant and a second dopant, and a covalent atomic radius of a material of the semiconductor substrate (102) is i) greater than a covalent atomic radius of the first dopant and less than a covalent atomic radius of the second dopant, or ii) less than a covalent atomic radius of the first dopant and greater than a covalent atomic radius of the second dopant, and wherein a vertical extension of the first dopant into the semiconductor substrate (102) from the first principal surface (104) terminates at a base of a first semiconductor substrate region (108) at a first vertical distance (t1) to the first principal surface (104); thereafter Formation of a semiconductor layer (110) in contact with the first main surface (104), Formation of source or drain regions of field-effect transistors, or emitter or collector regions of IGBTs, or cathode or anode regions of diodes or thyristors, or emitter or base or collector regions of bipolar transistors in the semiconductor layer (110); and Reducing the thickness of the semiconductor substrate (102) by removing material from the semiconductor substrate (102) from the second main surface (106) at least to the first semiconductor substrate region (108), wherein, after reducing the thickness of the semiconductor substrate (102), a vertical concentration profile N1(y) of the first dopant decreases along at least 80% of a distance between an interface of the semiconductor substrate (102) and the semiconductor layer (110) at the first main surface (104) to a surface of the semiconductor substrate (102) opposite the interface (114), and the opposite surface of the semiconductor substrate (102) being the surface from which the thickness of the semiconductor substrate was reduced, and wherein the dose, energy, and heat balance for broadening a vertical concentration profile N1(y) of the first dopant and the dose, energy, and heat balance for broadeninga vertical concentration profile N2(y) of the second dopant is coordinated in order to. ∫0t|N1(y)−N2(y)|dy∫0tN1(y)dy<100%, to satisfy, where t is a thickness of the semiconductor substrate (102) after a -reduction of the thickness of the semiconductor substrate (102). [2] Method according to claim 1, wherein providing the semiconductor substrate comprises: Introducing the first dopant through the first main surface (104) into the semiconductor substrate (102) by at least one diffusion process, one ion implantation process, and one plasma-based ion implantation process; and Introducing the second dopant through the first main surface (104) into the semiconductor substrate (102) by at least one diffusion process, one ion implantation process and one plasma-based ion implantation process. [3] Method according to one of the preceding claims, wherein the first dopant is introduced through the first main surface (104) into the semiconductor substrate (102) by a diffusion process which is carried out simultaneously with an oxidation process of the semiconductor substrate (102). [4] Method according to one of claims 1 to 2, wherein the first dopant is introduced through the first main surface into the semiconductor substrate by means of a plasma-based ion implantation process at a dose in the range of 10 16 cm -2 up to 10 18 cm -2 is being introduced. [5] Method according to claim 4, wherein a diffusion barrier (113) is formed on the first main surface (104) of the semiconductor substrate (102) after introduction of the first dopant and a vertical concentration profile of the first dopant is then broadened by a thermal diffusion process. [6] Method according to one of claims 1 to 2, wherein the first dopant and the second dopant are successively introduced through the first main surface (104) into the semiconductor substrate (102) by an ion implantation process or by a plasma-based ion implantation process at different doses and / or energies. [7] Method according to one of the preceding claims, wherein an average concentration of a vertical concentration profile N1(y) of the first dopant between an interface (114) of the semiconductor substrate (102) and the semiconductor layer (110) to a surface of the semiconductor substrate (102) opposite the interface in a range of 5×10 18 cm -3 up to 5×10 20 cm -3 lies. [8] Method according to one of the preceding claims, wherein the second dopant provides a background doping of the semiconductor substrate (102) in a range of 10 18 cm-3 up to 10 21 cm -3 educates. [9] Method according to any of the preceding claims, wherein the first dopant is an element of arsenic, phosphorus and antimony and the second dopant is another element of arsenic, phosphorus and antimony. [10] Method according to any of the preceding claims, wherein the first dopant is an element of boron, aluminium and gallium and the second dopant is another element of boron, aluminium and gallium. [11] Method according to any of the preceding claims, comprising providing the semiconductor substrate (102): Introducing the first dopant through the first main surface (104) and through the second main surface (106) into the semiconductor substrate (102) by at least one diffusion process, one ion implantation process and one plasma-based ion implantation process; and thereafter, but before reducing the thickness of the semiconductor substrate (102): Forming a sealing layer (116) on the second main surface (106) of the semiconductor substrate (102). [12] Semiconductor device comprising: a semiconductor substrate (102) comprising a first dopant and a second dopant, wherein a covalent atomic radius of a material of the semiconductor substrate is i) larger than a covalent atomic radius of the first dopant and smaller than a covalent atomic radius of the second dopant or ii) smaller than a covalent atomic radius of the first dopant and larger than a covalent atomic radius of the second dopant; a semiconductor layer (110) in contact with a first main surface (104) of the semiconductor substrate (102); Source or drain regions of field-effect transistors, or emitter or collector regions of IGBTs, or cathode or anode regions of diodes or thyristors, or emitter or base or collector regions of bipolar transistors in the semiconductor layer (110); and wherein a vertical concentration profile N1(y) of the first dopant decreases along at least 80% of a distance between an interface (114) of the semiconductor substrate (102) and the semiconductor layer (110) at the first main surface (104) to a second main surface (106) of the semiconductor substrate (102) opposite the interface (114), and wherein a vertical concentration profile N1(y) of the first dopant and a vertical concentration profile N2(y) of the second dopant ∫0t|N1(y)−N2(y)|dy∫0tN1(y)dy<100%, satisfy, where t is a thickness of the semiconductor substrate (102) after a reduction of the thickness of the semiconductor substrate (102). [13] Semiconductor device according to the previous claim, wherein an average concentration of a vertical concentration profile N1(y) of the first dopant between an interface (114) of the semiconductor substrate (102) and the semiconductor layer (110) to a surface of the semiconductor substrate (102) opposite the interface (114) in a range of 5×10 18 cm -3 up to 5×10 20 cm -3 . lies. [14] Semiconductor device according to one of the two preceding claims, wherein the first dopant is an element consisting of arsenic, phosphorus and antimony and the second dopant is another element consisting of arsenic, phosphorus and antimony. [15] Semiconductor device according to one of claims 13 to 14, wherein the first dopant is an element of boron, aluminium and gallium and the second dopant is another element of boron, aluminium and gallium.

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