SEMICONDUCTOR HOUSING AND METHOD FOR ITS MANUFACTURE

Abstract

Housing that includes: a first housing structure comprising: a first chip (100) having a first active side and a first backside, the first active side comprising a first bond pad (104) and a first insulating layer; a second chip (200) bonded to the first chip (100), the second chip having a second active side and a second backside, the second active side comprising a second bond pad (206) and a second insulating layer (208), the second active side of the second chip facing the first active side of the first chip, the second insulating layer being bonded to the first insulating layer by dielectric-to-dielectric bonds; and a conductive bonding material bonded to the first bonding pad (104) and the second bonding pad (206), the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bonding pads (104, 206); wherein the conductive bonding material is partially enclosed by one of the bond pads.

Description

GENERAL STATE OF THE ART

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). Most often, this improvement in integration density has resulted from repeated reductions in the minimum device size, allowing more components to be integrated into a given area. As the demand for ever smaller electronic components has increased, a need has arisen for smaller and more creative packaging techniques for semiconductor chips. One example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package to provide a high level of integration and high component density.PoP technology generally enables the production of semiconductor devices with improved functionalities and a small footprint on a printed circuit board (PCB).

[0002] US 7 547 625 B2 relates to a method for joining two elements, consisting of producing a first micropattern on a first element, which comprises a first metal layer, and producing a second micropattern, which comprises a second metal layer, on a second element.

[0003] US 9 190 380 B2 relates to a method for producing a BBUL substrate having a high-density interconnect element embedded therein, comprising arranging a first chip containing a first plurality of high-density interconnect pads on a substrate carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description with reference to the accompanying figures. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of discussion. The Fig. 1 to 3, 4A to 4C, and 5 to 14 illustrate cross-sections of intermediate steps during a process for forming a package structure in accordance with some embodiments. The Fig. 15 to 21 illustrate cross-sectional views of the intermediate steps during a process for forming a housing structure in accordance with some embodiments. The Fig. 22 to 28 illustrate cross-sectional views of the intermediate steps during a process for forming a housing structure in accordance with some embodiments. The Fig. 29 to 34 illustrate cross-sectional views of the intermediate steps during a process for forming a housing structure in accordance with some embodiments. The Fig. 35 to 38 illustrate cross-sectional views of the intermediate steps during a process for forming a housing structure in accordance with some embodiments. DETAILED DESCRIPTION

[0005] The invention is as defined in the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. The formation of a first feature over or on top of a second feature in the following description may, for example, include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Furthermore, the present disclosure may repeat reference numerals and / or reference letters throughout the various examples. This repetition is intended for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatial reference terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one feature or features to one or more other features or features as illustrated in the figures. The spatial reference terms may be intended to encompass different orientations of the component during use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatial reference descriptors used herein will be interpreted accordingly.

[0007] Embodiments discussed herein may be discussed in a specific context, namely, a package structure (i.e., a package-on-package (PoP) structure) comprising chips bonded together using a hybrid bonding technique. The chips may be bonded face-to-face (F2F) or face-to-back (F2B). For example, in an F2F bonding configuration, the active surfaces of the chips are bonded to each other, while in an F2B bonding configuration, an active surface of one chip is bonded to a backside surface of another chip. Additionally, hybrid bonding between the chips includes dielectric bonding and metal bonding. By including solder bonding (instead of, for example, copper-to-copper bonding), the bonding temperature of the hybrid bond can be significantly reduced.

[0008] Furthermore, the teachings of this disclosure apply to any package structure having one or more semiconductor chips. Other embodiments contemplate other applications, such as different package types or different configurations, which would be readily apparent to one of ordinary skill in the art upon reading this disclosure. It should be noted that embodiments discussed herein do not necessarily illustrate every component or feature that may be present in a structure. For example, multiple components may be omitted from a figure, such as when discussion of one of the components may be sufficient to convey aspects of the embodiment. Furthermore, method embodiments discussed herein may be discussed as being performed in a particular order; however, other method embodiments may be performed in any logical order.

[0009] The Fig. 1 to 3, 4A to 4O, and 5 to 14 illustrate cross-sections of intermediate steps during a process for forming a package structure in accordance with some embodiments.

[0010] Fig. 1 illustrates an integrated circuit chip 100 at an intermediate processing step. The integrated circuit chip 100 may be a logic chip (e.g., central processing unit, mobile application processor, ASIC, GPU, FPGA, microcontroller, etc.), a memory chip (e.g., dynamic random access memory (DRAM) chip), a wide I / O chip, an M-RAM chip, an R-RAM chip, a NAND chip, a static random access memory (SRAM, etc.) chip, a memory cube (e.g., HBM, HMC, etc.).), a high data rate transceiver chip, an I / O interface chip, an IPD chip (for example, an integrated passive device), a power management chip (for example, a power management integrated circuit (PMIC) chip), a radio frequency (RF) chip, a sensor chip, a micro-electro-mechanical (Micro-Electro-Mechanical-System (MEMS)) chip, signal processing chips (for example, a digital signal processing - DSP) chip), a front-end chip (for example, an analog front-end - AFE) chip, a monolithic 3D heterogeneous stacking chip, the like, or a combination of these.

[0011] Before the intermediate step, which is Fig. 1, the integrated circuit chip 100 may be processed according to established manufacturing processes to form integrated circuits within the integrated circuit chip 100. The integrated circuit chip 100 includes, for example, a semiconductor substrate 102, such as silicon, which may be doped or undoped, or an active layer made of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 may include other semiconductor material, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Components such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on the semiconductor substrate 102, and may be connected by interconnect structures formed, for example, by metallization structures in one or more dielectric layers on the semiconductor substrate 102 to form an integrated circuit. The interconnect structures are formed using a damascene and / or dual-damascene process in some embodiments.

[0012] The integrated circuit chip further includes pads, such as copper pads or aluminum pads, or a combination thereof, to which external connections are made. In some embodiments, these pads 104 may be used in a hybrid bonding configuration to bond the integrated circuit chip 100 to another chip or structure. The pads 104 are located on what may be called an active side of the integrated circuit chip 100. Insulating layers are also located on the active side of the integrated circuit chip 100. In some embodiments, the insulating layers are formed from a polymer, which may be a photosensitive material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like.In other embodiments, the insulating layers are formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide; phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG); a combination of these; or the like. The insulating layers may be formed by spin-coating, lamination, chemical vapor deposition (CVD), the like, or a combination of these.

[0013] In some embodiments, pads 104 may be called connectors 104 and may be conductive pillars (e.g., comprising a metal such as copper). Pads 104 may be formed, for example, by metal deposition, electroplating, a combination of these, or the like. The active side of integrated circuit chip 100 (including pads 104 and insulating layers) may be planarized by a planarization process, such as chemical mechanical polishing (CMP), to ensure planar surfaces for subsequent bonding.

[0014] Fig. 1 further illustrates conductive pillars 106 formed on some of the pads 104. As illustrated, the conductive pillars 106 may taper from the top to the bottom due to the high aspect ratio and relatively small dimensions of the pillars. The conductive pillars 106 extend through the subsequently formed encapsulation 390 (see Fig. 6) and may be referred to below as vias 106. As an example of forming the vias 106, a seed layer is formed over the active side of the integrated circuit chip, for example, the interconnects and pads 104, as illustrated. In some embodiments, the seed layer is a metal layer comprising a single layer or a composite layer comprising a plurality of sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating, lamination, or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the vias.Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the photoresist openings and on the exposed portions of the seed layer. The conductive material may be formed by electroplating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, nickel, titanium, tungsten, aluminum, a combination of these, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as by using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as wet or dry etching.The remaining sections of the seed layer and the conductive material form the vias 106.

[0015] In some embodiments, the pads 104 with the conductive pillars 106 thereon are formed with configurations (e.g., the pads 104 with conductive pillars may not be formed, such as by the recessed pad 312 in Fig. 4A, recessed), which are formed differently than the pads 104 without conductive pillars 106. In one embodiment, all pads 104 are formed with the same configuration.

[0016] Fig. 2 illustrates an integrated circuit chip 200 at an intermediate processing step. The integrated circuit chip 200 may be a logic chip (e.g., central processing unit, ASIC, FPGA, microcontroller, etc.), a memory chip (e.g., a DRAM chip, a wide I / O chip, etc., an M-RAM chip, a NAND chip, an SRAM chip, etc.), a memory cube (e.g., HBM, HMC, etc.), a high data rate transceiver chip, an I / O interface chip, an IPD chip (e.g., integrated passive component), a power management chip (e.g., a PMIC chip), an RF chip, a sensor chip, a MEMS chip, signal processing chips (e.g., a DSP chip), a front-end chip (e.g., AFE chips), a monolithic 3D heterogeneous stacking chip, the like, or a combination thereof. In some embodiments, integrated circuit chip 100 is a logic chip and integrated circuit chip 200 is a memory chip.

[0017] Before the intermediate step, which is Fig. 2, the integrated circuit chip 200 may be processed according to applicable manufacturing processes to form integrated circuits in the integrated circuit chip 200. The integrated circuit chip 200 includes, for example, a semiconductor substrate 202, such as silicon, which may be doped or undoped, or an active layer made of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 202 may include other semiconductor material, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Components such as transistors, diodes, capacitors, resistors, etc.may be formed in and / or on the semiconductor substrate 102, and may be connected by interconnect structures formed, for example, by metallization structures in one or more dielectric layers on the semiconductor substrate 202 to form an integrated circuit. The interconnect structures are formed using a damascene and / or dual-damascene process in some embodiments.

[0018] The integrated circuit chip 200 further includes vias 204 and pads 206. The vias 204 may extend through the semiconductor substrate 202 at this point in processing, or, as shown in Fig. 2, extend partially through the semiconductor substrate 202 at this point in processing. In the partial embodiment, the semiconductor substrate 202 may be thinned (see, for example, Fig. 11) so that the vias 204 may extend through the semiconductor substrate 202. The vias 204 may be formed, for example, by etching openings into the substrate 202 and then depositing a conductive material into the openings. These openings for the vias 204 may all be formed simultaneously in a same process or in separate processes. Openings in the substrate 202 may be formed using an appropriate photolithographic mask and etching process. For example, a photoresist may be formed and patterned over the substrate 202, and one or more etching processes (for example, a wet etching process or a dry etching process) are used to remove those portions of the substrate 202 where the vias 204 are desired.The openings may be formed from the active side of the integrated circuit chip 200 (i.e., the bottom side of the integrated circuit chip 200 in . Fig. 2) by forming and patterning a mask on the active side of the integrated circuit chip 200.

[0019] The openings can be filled, for example, with a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material. The liner can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The liner can be formed using a chemical vapor deposition (CVD) process, such as plasma-enhanced CVD (PECVD). Other alternative processes, such as sputtering or metal organic chemical vapor deposition (MOCVD), can alternatively be used.

[0020] The conductive material of the vias 204 may include one or more conductive materials, copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or other conductive metals, a combination thereof, or the like. The conductive material may be formed, for example, by depositing a seed layer (not shown) and using electroplating, electroless plating, or the like to deposit conductive material on the seed layer, filling and overfilling the openings for the vias 204. Once the openings for the vias 204 have been filled, excess liner and excess conductive material outside the openings for the vias 204 may be removed by an abrasive process, such as chemical mechanical polishing (CMP), although any suitable removal process may be used.As one of ordinary skill in the art will appreciate, the above-described process for forming the vias 204 is only one method for forming the vias 204, and other methods are intended to be within the scope of the embodiments. In some embodiments, the vias are formed from the backside of the integrated circuit chip 200.

[0021] Although two vias 204 are illustrated in the integrated circuit chip 200, it is to be understood that there may be more or fewer vias 204 in each integrated circuit chip 200.

[0022] The pads 206 may be copper pads or aluminum pads, or a combination thereof, to which external connections are made. In some embodiments, these pads 206 may be used in a hybrid bonding configuration to bond the integrated circuit chip 200 to another chip or other structure. The pads 206 are located on what may be called the active side of the integrated circuit chip 200. The pads 206 may be formed on and electrically coupled to the vias 204. One or more insulating layers 208 are also located on the active side of the integrated circuit chip 200. The insulating layers 208 may be inorganic or organic layers. In some embodiments, the insulating layers 208 are formed from a polymer, which may be a photosensitive material, such as PBO, polyimide, BCB, or the like.In other embodiments, the insulating layers 208 are formed from a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The insulating layers 208 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The active side of the integrated circuit chip 200 (including pads 206 and insulating layers 208) may be planarized by a planarization process such as CMP to ensure planar surfaces for subsequent bonding.

[0023] In some embodiments, the pads 206 may be called connectors 206 and may be conductive pillars or vias (comprising, for example, a metal such as copper, aluminum, or a combination thereof). The seed layer may be formed, for example, by electroplating or the like. In some embodiments, either one or both of the pads 104 and 206 include a solder material to be used when the integrated circuit chips 100 and 200 are mated. This structure is described in more detail in the Fig. 4A to 4O.

[0024] Fig. 3 illustrates integrated circuit chip 200 bonded to integrated circuit chip 100 by hybrid bonding. To implement hybrid bonding, integrated circuit chips 100 and 200 are first pre-bonded through their insulating layers on their active sides (e.g., 208) by gently pressing integrated circuit chips 100 and 200 together. Although one integrated circuit chip 100 and one integrated circuit chip 200 are illustrated, hybrid bonding may be performed at the wafer level (e.g., chip-to-wafer or wafer-to-wafer), wherein multiple integrated circuit chips 100 are formed in a wafer, and multiple integrated circuit chips 200 identical to the illustrated integrated circuit chip 200 are pre-bonded and configured as rows and columns on the wafer.

[0025] After all of the integrated circuit chips 100 and 200 have been pre-bonded, a reflow process is performed to cause the solder to melt (i.e., solder material between the pads 104 and 206) and interdiffusion of the solder and metals in at least one of the pads 104 and 206. The reflow temperature may be lowered to less than about 200°C to avoid damaging the insulating layers and bonding chips. For example, the reflow temperature may be in the range between about 150°C and about 200°C. The annealing time may be between about 2 hours and 3 hours.In accordance with some embodiments, thermal compression bonding (TBC) may be applied to locally heat the bonding interfaces to reduce bonding time and thermomechanical stress at the bond joints due to a mismatch in the coefficient of thermal expansion (CTE) among the upper circuit die, the lower circuit die, and the bonding tool.

[0026] Through hybrid bonding, pads 104 and 206 are solder bonded together to form a bond interconnect 300. The insulating layer of integrated circuit chip 100 is also bonded to insulating layer 208 with bonds formed therebetween. For example, the atoms (such as oxygen atoms) in one of the insulating layers form chemical or covalent bonds (such as OH bonds) with the atoms (such as hydrogen atoms) in the other of the insulating layers. The resulting bonds between the insulating layers are dielectric-to-dielectric bonds, which may be inorganic-to-polymer, polymer-to-polymer, or inorganic-to-inorganic bonds, according to various embodiments.Furthermore, the surface insulating layers of the two integrated circuit chips 100 and / or 200 may be different from each other (for example, one being a polymer layer and the other being an inorganic layer), and therefore two types of inorganic-to-polymer, polymer-to-polymer, and inorganic-to-inorganic bonds may exist simultaneously in the same package.

[0027] The Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D, Fig. 4E, Fig. 4F, Fig. 4G, Fig. 4H, Fig. 4I, Fig. 4 years, Fig. 4K, Fig. 4L, Fig. 4M, Fig. 4N and Fig. 4O illustrate detailed views of different configurations of a bond connection 300 from Fig. 3. In each of the illustrated configurations, the integrated circuit chips 100 and 200 could be either the upper exemplary chip (i.e., the upper bonding interface 350) in the Fig. 4A to 4O, or the lower exemplary chip (i.e., the lower bonding interface 350) in the Fig. 4A to 4O.

[0028] Fig. Figure 4A illustrates a bond configuration 300A with dielectric bonding and a recessed bond pad. In Fig. 4A, a first chip includes a semiconductor substrate 302, dielectric layers 304, 308, and 310 on the semiconductor substrate 302, a metallization layer 306 in the dielectric layer 304, and a recessed bond pad 312 in the dielectric layer 310 and on the metallization layer 306. In Fig. 4A, a second chip includes a semiconductor substrate 320, dielectric layers 322, 326, and 328 on the semiconductor substrate 320, a metallization layer 324 in the dielectric layer 322, a bond pad 330 in the dielectric layer 328 and on the metallization layer 324, and a protruding bump including layers 332 and 334. Interface 350 illustrates the bonding interface between the dielectric layers 310 and 328.

[0029] In this embodiment, the dielectric layers 304, 308, 310, 322, 326, 328 are formed from a nitride, such as silicon nitride; an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layers 308 and 326 may be used as etch stop layers when forming the bond pads 312 and 330 on the respective chips and may be made of a different material composition than the surrounding dielectric layers. The surfaces of the dielectric layers 310 and 328 at the bonding interface 350 (including their respective conductive features 330 and 312) may be planarized by a planarization process, such as CMP, to ensure planar surfaces for bonding.

[0030] Metallization layers 306 and 324, as well as bond pad 330, may be formed from a conductive material, including a metal such as copper, titanium, tungsten, aluminum, or the like. The conductive material may be formed by electroplating, such as electroplating or electroless plating, or the like. These structures may be formed by a damascene process and may include a diffusion barrier layer, an adhesion layer, or the like, a seed layer, and a conductive material. The diffusion barrier layer and / or the adhesion layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The diffusion barrier layer and / or the adhesion layer may be formed using a CVD process, such as PECVD. However, other alternative processes, such as sputtering or MOCVD, may be used.In some embodiments, the seed layer is a metal layer that is a single layer or a composite layer comprising a plurality of sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like.

[0031] The recessed bond pad 312 may include multiple layers formed in the recess of the dielectric layer 310. The layers may include a seed layer 312A, a diffusion barrier layer 312B, and a conductive material layer 312C. Additionally, there may be a diffusion barrier layer and / or an adhesion layer between the seed layer 312A and the dielectric layer 310.

[0032] The diffusion barrier layer and / or the adhesion layer may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The diffusion barrier layer and / or the adhesion layer may be formed using a CVD process, such as PECVD. However, other alternative processes, such as sputtering or MOCVD, may be used.

[0033] In some embodiments, seed layer 312A is a metal layer that may be a single layer or a composite layer comprising a plurality of sublayers formed from different materials. In some embodiments, seed layer 312A comprises a titanium layer and a copper layer over the titanium layer. Seed layer 312A may be formed, for example, using PVD or the like.

[0034] In some embodiments, the diffusion barrier layer 312B comprises a nickel layer. The diffusion barrier layer 312B may be formed, for example, using PVD or the like. The diffusion barrier layer 312B provides diffusion protection such that the solder material 334 does not diffuse into the metallization layer 306. Other materials may be used in place of the diffusion barrier as long as they provide a suitable amount of diffusion protection.

[0035] The layer of conductive material 312C may comprise one or more conductive materials, copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or other conductive metals, or the like. The layer of conductive material 312C may be formed, for example, by electroplating, electroless plating, or the like to deposit a conductive material. The layers 312A, 312B, and 312C of the bond pad 312 do not fill the recess in the dielectric layer 310, so that the bond pad 312 is recessed in the dielectric layer 310. This recessed bond pad 312 may allow for a thinner package by reducing the pitch of the bonded package.After forming the conductive material layer 312C, excess portions of the layers 312A, 312B, and 312C outside the recess (e.g., along a top surface of the dielectric layer 310 before the dies are bonded) may be removed by a grinding process such as CMP. In this embodiment, the combined thickness of the layers 312A, 312B, and 312C is less than the thickness of the dielectric layer 310.

[0036] Bump layers 332 and 334 include a diffusion barrier layer 332 and a solder layer 334. Diffusion barrier layer 332 may be formed on bond pad 330. In some embodiments, diffusion barrier layer 332 comprises a nickel layer. Diffusion barrier layer 332 may be formed, for example, using PVD or the like. Diffusion barrier layer 332 provides diffusion protection such that solder material 334 does not diffuse into pad / via 330. Other materials may be used in place of the diffusion barrier as long as they provide a suitable amount of diffusion protection.

[0037] Solder layer 334 may be formed on diffusion barrier layer 332. Solder layer 334 may be formed from a solder material including copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. Solder layer 334 may be formed by vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. Solder layer 334 is bonded to the recessed bond pad by a solder reflow process (described in detail above) or a heat compression bonding process. Solder layer 334 has a lower reflow temperature than both the conductive material layer 312C of bond pad 312 and pad / via 330. This allows a lower reflow temperature to be used when bonding the chips together.

[0038] As illustrated, the bond connections 300A to 3300 of the Fig. 4A to 4O, a void or gap 336 surrounding the solder layer 334 and located between the bond pad 312 and the dielectric layer 322 / 328. This void / gap 336 may remain unfilled and be visible in the finished product.

[0039] Fig. Figure 4B illustrates another configuration 300B of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4A, except that in this embodiment, the bonding interface 350 includes polymer layers 340 and 342 instead of dielectric layers and therefore includes polymer bonding. Details associated with this embodiment that are similar to those of the embodiments described above are not repeated here.

[0040] In this embodiment, each of the chips includes a polymer layer as the bonding layer. Polymer layer 340 is formed on the first chip, and polymer layer 342 is formed on the second chip. Polymer layers 340 and 342 may be photosensitive material, such as PBO, polyimide, BCB, or the like. Insulating layers 340 may be formed by spin coating, lamination, the like, or a combination thereof.

[0041] Fig. 4C illustrates another configuration 300C of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4B, except that in this embodiment, the bonding pad 312 is not recessed into an insulating layer. Details related to this embodiment that are similar to those of the embodiments described above will not be repeated here.

[0042] In this embodiment, bond pad 312 is not recessed, but is substantially planar across metallization layer 306. Polymer layer 340 extends above the top surface of bond pad 312, and polymer layer 342 extends from dielectric layer 322 of the second chip such that bump layers 332 and 334 have space between bond pad 312 and pad / via 324.

[0043] Fig. 4D illustrates another configuration 300D of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4A, except that in this embodiment, the bonding interface 350 is a solder bond rather than a dielectric bond because the dielectric layers 310 and 328 are separated from each other. Details related to this embodiment that are similar to those of the embodiments described above will not be repeated here.

[0044] In this embodiment, the dielectric layers 310 and 328 of the chips are spaced apart from each other after the bonding process. This embodiment is not necessarily ideal, as the spacing height is larger and the connection strength may be reduced compared to the other embodiments.

[0045] Fig. 4E illustrates another configuration 300E of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4A except that in this embodiment, the metallization layer 306 is deposited over the via 204 / via 466 (see Fig. 15 for 466) and is electrically coupled thereto. Details related to this embodiment that are similar to those of the embodiments described above are not repeated here.

[0046] In this embodiment, the via 204 / via 466 is formed through one of the integrated circuit chips 100 and / or 200.

[0047] Fig. Figure 4F illustrates another configuration 300F of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4E, except that metallization layer 306 is omitted in this embodiment and via 204 / via 466 is directly coupled to recessed pad 312. Details related to this embodiment that are similar to those of the embodiments described above are not repeated here.

[0048] In this embodiment, the width of the via 204 / via 466 adjacent to the recessed pad 312 is smaller than the width of the recessed pad 312.

[0049] Fig. 4G illustrates another configuration 300G of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4F except that the width of the via 204 / via 466 adjacent the recessed pad 312 is greater than the width of the recessed pad 312. Details associated with this embodiment that are similar to those of the embodiments described above are not repeated here.

[0050] Fig. 4H illustrates another configuration 300H of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4F except that the width of the via 204 / via 466 adjacent to the recessed pad 312 is the same as the width of the recessed pad 312. Details associated with this embodiment that are similar to those of the embodiments described above are not repeated here.

[0051] Fig. 41 illustrates another configuration 300I of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4F, except that in this embodiment, there is more than one via 204 / via 466 adjacent to the recessed pad 312. Details associated with this embodiment that are similar to those of the embodiments described above are not repeated here.

[0052] Fig. 4J illustrates another configuration 300J of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4E, except that in this embodiment, there is more than one via 204 / via 466 adjacent to the recessed pad 312. Details associated with this embodiment that are similar to those of the embodiments described above are not repeated here.

[0053] Fig. 4K illustrates another configuration 300K of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4J except that in this embodiment, the width of the via 204 / via 466 adjacent to the recessed pad 312 is the same as the width of the recessed pad 312. Details associated with this embodiment that are similar to those of the embodiments described above are not repeated here.

[0054] Fig. 4L illustrates another configuration 300L of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4F, except that in this embodiment, recessed pad 312 is omitted and solder material 334 is coupled directly to via 204 / via 466. Details related to this embodiment that are similar to those of the embodiments described above are not repeated here.

[0055] In this embodiment, the via 204 / via 466 may be recessed such that a portion of the solder material 334 extends below a top surface of the via 204 / via 466 and / or the surface of the dielectric layer 304. In some embodiments, the width of the void 336 is greater than the width of the via 204 / via 466 adjacent to the solder material 334.

[0056] Fig. 4M illustrates another configuration 300M of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4L except that in this embodiment, the width of the void 336 is smaller than the width of the via 204 / via 466 adjacent to the solder material 334. Details associated with this embodiment that are similar to those of the embodiments described above are not repeated here.

[0057] Fig. 4N illustrates another configuration 300N of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4L except that in this embodiment, the width of the void 336 is equal to the width of the via 204 / via 466 adjacent to the solder material 334. Details associated with this embodiment that are similar to those of the embodiments described above are not repeated here.

[0058] Fig. 4O illustrates another configuration 300O of the bond connection 300 of the Fig. 3. This embodiment is similar to the previous embodiment of the Fig. 4J, except that in this embodiment, the recessed pad 312 is omitted and solder material 334 is directly coupled to the metallization layer 306. Details related to this embodiment that are similar to those of the embodiments described above are not repeated here.

[0059] For each of the configurations of the Fig. 4A, 4B, 4C, 4E to 4O, hybrid bonding involves pre-bonding insulation layers (e.g., 310, 328, 340, and / or 342) on the active sides of the chips by gently pressing the integrated circuit chips together. After pre-bonding, the reflow process is performed to cause the reflow of the solder layer 334.

[0060] In Fig. 5, an encapsulation 390 is applied to the various components of the Fig. 3. The encapsulant 390 may be a molding compound, an epoxy, an oxide, or the like, and may be applied by compression molding, transfer molding, lamination, flowable CVD, or the like. In some embodiments, the encapsulant may be an oxide layer, such as silicon oxide, tetraethylorthosilicate (TEOS) silicon oxide, or the like. In some embodiments, the encapsulant may be a nitride layer, such as silicon oxide or the like. In some embodiments, the encapsulant may be a composite organic and inorganic encapsulant material, or the like. The encapsulant 390 may be formed over the wafer having the integrated circuit die 100 such that the conductive pillars 106 and the integrated circuit die 200 are recessed or covered. The encapsulant 390 may then be cured.The semiconductor substrate 102 of the integrated circuit chips 100 may have a thickness T1 of about 775 µm.

[0061] In Fig. 6, the semiconductor substrate 102 may be thinned to a thickness T2 that is smaller than the thickness T1. The thinning process may include a grinding process, such as mechanical grinding, CMP, an etching process, or a combination thereof. In some embodiments, the thickness T2 is in a range from about 50 µm to about 150 µm.

[0062] After the thinning process, the package including integrated circuit chips 100 and 200 may be singulated, such as by sawing or dicing, to form a plurality of packages 392, each package 392 including at least one integrated circuit chip 100 and one integrated circuit chip 200. In some embodiments, singulation occurs in scribe trench regions between package regions.

[0063] Fig. Figure 7 illustrates a support substrate 400, a release layer 402 formed on the support substrate 400, and a dielectric layer 404 formed on the release layer 402. The support substrate 400 may be a glass support substrate, a ceramic support substrate, or the like. The support substrate 400 may be a wafer so that multiple packages can be formed on the support substrate 400 simultaneously. The release layer 402 may be formed from a polymer-based material that can be removed along with the support substrate 400 from overlying structures formed in subsequent steps. In some embodiments, the release layer 402 is an epoxy-based thermal release material that loses its adhesive property when heated, such as a light-to-heat conversion (LTHC) release coating.In other embodiments, the release layer 402 may be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light. The release layer 402 may be dispensed and cured as a liquid, may be a laminate film laminated to the carrier substrate 400, or the like. The top surface of the release layer 402 may be planarized and may have a high degree of coplanarity.

[0064] The dielectric layer 404 is formed on the separation layer 402. The bottom surface of the dielectric layer 404 may be in contact with the top surface of the separation layer 402. In some embodiments, the dielectric layer 404 is formed from a polymer, such as PBO, polyimide, BCB, or the like. In other embodiments, the dielectric layer 404 is formed from a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 404 may be formed by any acceptable deposition process, such as spin-coating, chemical vapor deposition (CVD), lamination, or the like, or a combination thereof. In some embodiments, one or more metallization structures are formed on or in the dielectric layer 404 to form a redistribution structure.This redistribution structure can be called a backside redistribution structure.

[0065] Furthermore, Fig. 7 electrical connectors 406 are formed. The electrical connectors 406 extend through the subsequently formed encapsulation 408 (see Fig. 9) and may be referred to below as vias 406. As an example for forming vias 406, a seed layer is formed over the underlying structure, for example, dielectric layer 404. In some embodiments, the seed layer is a metal layer comprising a single layer or a composite layer comprising a plurality of sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating, lamination, or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to vias 406.Patterning creates openings through the photoresist to expose the seed layer. A conductive material is formed in the photoresist openings and on the exposed portions of the seed layer. The conductive material may be formed by electroplating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as wet or dry etching.The remaining portions of the seed layer and conductive material form the vias 406.

[0066] In Fig. 8, the package 392 is attached to the release layer 402. Although one package 392 is illustrated as attached, it is understood that more or fewer packages 392 may be attached in each package area. Although not shown, the package 392 may be attached by an adhesive layer (not shown). The adhesive may be any suitable adhesive, epoxy, die attach film (DAF), or the like.

[0067] In Fig. 9, an encapsulant 408 is formed on the various components. The encapsulant 408 may be a molding compound, epoxy, or the like, and may be applied by compression molding, lamination, transfer molding, or the like. The encapsulant 408 may be formed over the carrier substrate 400 such that the electrical connectors 406 and the housing 392 are recessed or covered. The encapsulant 408 may then be cured. The encapsulants 408 and 390 may be made of the same or different materials.

[0068] In Fig. 10, the encapsulation 408 may be subjected to a grinding process to expose the electrical connectors 406, conductive pillars 106, and vias 204. Surfaces of the electrical connectors 406, conductive pillars 106, vias 204, the semiconductor substrate 202, and the encapsulation 408 are flush after the grinding process. In some embodiments, grinding may be omitted, for example, if the electrical connectors 406, the conductive pillars 106, and the vias 204 are already exposed. The electrical connectors 406 and the conductive pillars 106 may be referred to as vias 406 and 106, respectively, below.

[0069] In Fig. 11, a front-side redistribution structure 410 is formed. The front-side redistribution structure 410 includes one or more dielectric layers 414 and one or more metallization structures 412.

[0070] Forming the front-side redistribution structure 410 may be performed by depositing the dielectric layer 414 on the encapsulant 408, the vias 406, vias 204, and vias 106. In some embodiments, the vias 106 and 204 may have conductive pads formed on their top surfaces to guide the overlying metallization structures 412 upon impingement upon and electrically coupling with the respective vias 106 and 204 (see, for example, Fig. 23 with pads 494). In some embodiments, the dielectric layer 414 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. In other embodiments, the dielectric layer 414 is formed from a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 414 may be formed by spin coating, lamination, CVD, the like, or a combination thereof.

[0071] Next, the dielectric layer 414 is patterned. The patterning forms openings to expose portions of the vias 406, 106, and 204. The patterning may be performed by any acceptable process, such as by exposing the dielectric layer 414 to light if the dielectric layer 414 is a photosensitive material, or by ablation, for example, using laser ablation, or by etching, for example, using anisotropic etching. If the dielectric layer 414 is a photosensitive material, the dielectric layer 414 may be developed after exposure.

[0072] Next, the metallization structure 412 with vias is formed on the dielectric layer 414. As an example of forming the metallization structure 412, a seed layer (not shown) is formed over the dielectric layer 414 and in openings through the dielectric layer 414. In some embodiments, the seed layer is a metal layer comprising a single layer or a composite layer comprising a plurality of sublayers formed from different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning.The pattern of the photoresist corresponds to the metallization pattern 412. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the photoresist openings and on the exposed portions of the seed layer. The conductive material may be formed by electroplating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed. The photoresist may be removed by an acceptable ashing or stripping process, such as by using an oxygen plasma or the like. After the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as wet or dry etching.The remaining portions of the seed layer and conductive material form the metallization structure 412 and vias. The vias are formed in openings through the dielectric layer 414, for example, vias 406, 106, and 204.

[0073] This process may be repeated with more dielectric layers 414 and more metallization structures and vias 412 to continue forming the redistribution structure 410. The materials and processes used to form these layers of the redistribution structure 410 may be similar to what was described above, and the description will not be repeated here. In some embodiments, the redistribution structure 410 is formed by a damascene process. In some embodiments, some of the layers of the redistribution structure 410 are formed by a dual damascene process, and other layers are formed by the process described in the preceding paragraphs, for example, a semi-additive process (SAP).

[0074] The front-side redistribution structure 410 is shown as an example. More or fewer dielectric layers and metallization structures may be formed in the front-side redistribution structure 410. If fewer dielectric layers and metallization structures are to be formed, the steps and processes discussed above may be omitted. If more dielectric layers and metallization structures are to be formed, the steps and processes discussed above may be repeated. One of ordinary skill in the art will readily understand which steps and processes would be omitted or repeated.

[0075] In Fig. 12, pads (not shown) are formed on an outer surface of the 410, and conductive connectors 416 are formed on the pads. The pads are used to couple the conductive connectors 416 and may be called under bump metallurgies (UBMs). The pads may be formed through openings in the topmost dielectric layer 414 of the redistribution structure 410 to the topmost metallization structure 412. As an example of forming the pads, a seed layer (not shown) is formed over the dielectric layer 414. In some embodiments, the seed layer is a metal layer comprising a single layer or a composite layer comprising a plurality of sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like.A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the pads. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the photoresist openings and on the exposed portions of the seed layer. The conductive material may be formed by electroplating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed. The photoresist may be removed by an acceptable ashing or stripping process, such as by using an oxygen plasma or the like.After the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as wet or dry etching. The remaining portions of the seed layer and conductive material form the pads. In the embodiment where the pads are formed differently, more photoresist and patterning steps can be employed.

[0076] Furthermore, Fig. 12 conductive connectors 416 are formed on the pads / UMBs. The conductive connectors 416 may be ball matrix array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG)-formed bumps, or the like. The conductive connectors 416 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 416 are formed by initially forming a solder layer by commonly used methods such as vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. Once a solder layer has been formed on the structure, reflow may be performed to form the material into the desired bump shapes.In another embodiment, the conductive connectors 416 are metal pillars (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the metal pillar connectors 416. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by an electroplating process.

[0077] In Fig. 13, a carrier substrate stripping is performed to separate the carrier substrate 400 from the dielectric layer 404. The first housing 420 is thereby formed in each of the housing regions of the carrier. In accordance with some embodiments, the stripping comprises projecting a light, such as a laser light or a UV light, onto the separation layer 402 such that the separation layer 402 dissolves under the heat of the light and the carrier substrate 400 can be removed. Openings are formed through the dielectric layer 404 to expose portions of the metallization structure vias 406. The openings may be formed, for example, using laser drilling, etching, or the like.

[0078] Fig. 14 illustrates a cross-sectional view of a portion of a package structure in accordance with some embodiments. The package structure may be called a package-on-package (PoP) structure. In Fig. 14, a second package 450 is attached to the first package 420. The second package 450 includes a substrate 430 and one or more stacked chips 440 (440A and 440B) coupled to the substrate 430. Although a single stack of chips 440 (440A and 440B) is illustrated, in other embodiments, a plurality of stacked chips 440 (each having one or more stacked chips) may be arranged side by side, coupled to a same surface of the substrate 430. The substrate 430 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used.Additionally, the substrate may be a silicon oxide-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate 430, in an alternative embodiment, is based on an insulating core, such as a resin core with glass fiber reinforcement. An exemplary core material is glass fiber resin, such as FR4. Alternatives for core material include bismaleimide triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build-up films, such as Ajinomoto Build-Up Film (ABF), or other laminates may be used for the substrate 430.

[0079] The substrate 430 may include active and passive components (not shown). As one of ordinary skill in the art will appreciate, a wide variety of active components and passive components, such as transistors, capacitors, resistors, combinations thereof, and the like, may be used to create the desired structural and functional design requirements for the second package 450. The components may be formed using any convenient method.

[0080] The substrate 430 may also include metallization layers (not shown) and vias 432. The metallization layers may be formed over the active and passive components and are designed to connect the various components to form functional circuits. The metallization layers may be formed from alternating layers of dielectric (e.g., low-λ dielectric material) and conductive material (e.g., copper), with vias connecting the conductive material layers, and may be formed by any suitable process (such as deposition, damascene, dual-damascene, or the like). In some embodiments, the substrate 430 is substantially free of active and passive components.

[0081] The substrate 430 may have bond pads 434 on a first side of the substrate 430 to couple the stacked chips 440, and bond pads 436 on a second side of the substrate 430, the second side being opposite the first side of the substrate 430, to couple to the conductive connectors 438. In some embodiments, the bond pads 434 and 436 are formed by forming recesses (not shown) in dielectric layers (not shown) on the first and second sides of the substrate 430. The recesses may be formed to allow the bond pads 434 and 436 to be embedded in the dielectric layers. In other embodiments, the recesses are omitted, as the bond pads 434 and 436 may be formed on the dielectric layer.In some embodiments, bond pads 434 and 436 include a thin seed layer (not shown) comprised of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of bond pads 434 and 436 may be deposited over the thin seed layer. The conductive material may be formed by an electrochemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. In one embodiment, the conductive material of bond pads 434 and 436 may be comprised of copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

[0082] In one embodiment, bond pads 434 and 436 are UBMs comprising three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will understand that there are many suitable arrangements of materials and layers, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement, that are suitable for forming bond pads 434 and 436. Any suitable materials or layers of materials that can be used for bond pads 434 and 436 are considered within the scope of the present application. In some embodiments, vias 432 extend through substrate 430 and couple at least one bond pad 434 to at least one bond pad 436.

[0083] In the illustrated embodiment, the stacked chips 440 are coupled to the substrate 430 by wire bonds 442, although other connections, such as conductive bumps, may be used. In one embodiment, the stacked chips 440 are stacked memory chips. The stacked chips 440 may be, for example, memory chips such as low-power (LP) double data rate (DDR) memory modules, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4 memory modules, or the like.

[0084] The stacked chips 440 and the wire bonds 442 may be encapsulated by a molding material 444. The molding material 444 may be molded onto the stacked chips 440 and the wire bonds 442, for example, using compression molding. In some embodiments, the molding material 444 is a molding composite, a polymer, an epoxy, a silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure the molding material 444, where the curing may be a heat cure, a UV cure, the like, or a combination thereof.

[0085] In some embodiments, the stacked chips 440 and the bond wires 442 are embedded in the mold material 444, and after the mold material 444 cures, a planarization step, such as grinding, is performed to remove excess portions of the mold material 444 and provide a substantially planar surface for the second package 450.

[0086] After the second package 450 is formed, the second package 450 is mechanically and electrically bonded to the first package 420 through conductive connectors 438, bond pads 436, and vias 406 (or backside redistribution structure, if present). In some embodiments, the stacked chips 440 may be coupled to the package 392 through wire bonds 442, bond pads 434 and 436, vias 432, the conductive connectors 438, vias 406, and redistribution structure 410.

[0087] The conductive connectors 438 may be similar to the conductive connectors 416 described above, and the description will not be repeated here, although the conductive connectors 438 and the conductive connectors 416 need not be the same. The conductive connectors 438 may be disposed on a side of the substrate 430 opposite the stacked chips 440. In some embodiments, a solder resist (not separately labeled) may also be formed on the side of the substrate opposite the stacked chips 440. The conductive connectors 438 may be disposed in openings in the solder resist to electrically and mechanically couple to conductive features (e.g., the bond pads 436) in the substrate 430. The solder resist may be used to protect surfaces of the substrate 430 from external damage.

[0088] In some embodiments, prior to bonding the conductive connectors 438, the conductive connectors 438 are coated with a flux (not shown), such as a no-clean flux. The conductive connectors 438 may be dipped in the flux, or the flux may be sprayed onto the conductive connectors 438. In another embodiment, the flux may be applied to the surfaces of the vias 406 (or, if present, the backside redistribution structure).

[0089] In some embodiments, the conductive connectors 438 may have an optional epoxy flux (not shown) formed thereon before being reflowed, with at least some of the epoxy portion of the epoxy flux remaining after the second housing 450 is attached to the first housing 420.

[0090] An underfill (not shown) may be formed between the first housing 420 and the second housing 450 and surrounding the conductive connectors 438. The underfill may reduce stress and protect the connections resulting from reflow of the conductive connectors 438. The underfill may be formed by a capillary flow process after the second housing 450 is attached, or may be formed by a suitable deposition process before the second housing 450 is attached. In embodiments where the epoxy flux is formed, it may act as the underfill.

[0091] The bonding between the second housing 450 and the first housing 420 may be a solder bond. In one embodiment, the second housing 450 is bonded to the first housing 420 through a reflow process. During this reflow process, the conductive connectors 438 are in contact with the bond pads 436 and the vias 406 (or the backside redistribution structure, if present) to physically and electrically couple the second housing 450 to the first housing 420. After the bonding process, an intermetallic compound (IMC, not shown) may form at the interface of the vias 406 (or the backside redistribution structure, if present) and the conductive connectors 438, and also at the interface between the conductive connectors 438 and the bond pads 436 (not shown).In one embodiment, an underfill material may be applied after the bonding process to cover the conductive bonding connectors to provide extra protection from adverse environmental conditions, for example, moisture, particulates, and chemical corrosion, or the like.

[0092] A singulation process is performed by sawing along scribe trench regions, for example, between the package regions. The resulting singulated first and second packages 420 and 450 originate from one of the package regions. In some embodiments, the singulation process is performed after the second package 450 has been attached to the first package 420. In other embodiments (not shown), the singulation process is performed before the second package 450 is attached to the first package 420, such as after the carrier substrate 400 has been detached.

[0093] Further processing can be done on the housing structure of the Fig. 15. The housing structure of the Fig. 15 can be mounted, for example, on a package substrate using the conductive connectors 416.

[0094] The Fig. 15 to 21 illustrate cross-sectional views of another housing structure in accordance with some embodiments. The embodiment in FIGS. Fig. 15 to 21 is the embodiment shown in the Fig. 1 to 14, except that this embodiment includes vias 466 in the integrated circuit chip 100, and the integrated circuit chip 200 does not include vias. In addition, the integrated circuit chips 100 and 200 are reversed in the package structure, for example, the integrated circuit chip 100 is located above the integrated circuit chip 200 when they are attached to the carrier substrate 400 (see Fig. 18). Details related to this embodiment that are similar to those of the embodiments described above will not be repeated here.

[0095] In Fig. 15 illustrates the integrated circuit chip 100 including the vias 466. Details associated with this embodiment of the integrated circuit chip 100 that were described with those of the previously described embodiments of the integrated circuit chip 100 will not be repeated here.

[0096] In this embodiment, the vias 466 extend from the pad 104 on the active side of the integrated circuit chip 100 into the semiconductor substrate 102 of the integrated circuit chip 100. The formation of the vias 466 may be similar to that of the vias 204 of the integrated circuit chip 200 in the previous embodiment, and the description will not be repeated here.

[0097] Although two vias 466 are illustrated in the integrated circuit chip 100, it is to be understood that there may be more or fewer vias 204 in each integrated circuit chip 100.

[0098] Fig. 16 illustrates further processing on the structure of the Fig. 15. The processing between these two figures is similar to the processing described above with reference to the Fig. 2 and Fig. 3 was illustrated and described, where Fig. 3 an equivalent intermediate stage as Fig. 6, and the descriptions are not repeated here.

[0099] In Fig. 16, the integrated circuit chips 100 and 200 are bonded with bonds 300. The bonds 300 may be any of the bond configurations 300A to 300O in the Fig. 4A to 4O.

[0100] Fig. 17 illustrates further processing on the structure of the Fig. 16. The processing between these two figures is similar to the processing described above with reference to the Fig. 3 to 5, where Fig. 5 an equivalent intermediate stage as Fig. 17, and the descriptions are not repeated here. The bonded integrated circuit chips 100 and 200 are encapsulated with encapsulant 464 to form a package 470.

[0101] Fig. Figure 18 illustrates the mounting of the housing 470 on a carrier substrate 400 similar to that shown above in Figures Fig. 7 and Fig. 8, and the descriptions are not repeated here. In Fig. 18, the package 470 is attached to the carrier with the integrated circuit chip 200 closer to the carrier substrate than the integrated circuit chip 100.

[0102] Fig. 19 illustrates further processing on the structure of the Fig. 18. The processing between these two figures is similar to the processing described above with reference to the Fig. 9 and Fig. 10 was illustrated and described, where Fig. 10 an equivalent intermediate as Fig. 19, and the descriptions are not repeated here. The housing 470 is encapsulated with encapsulant 472, and the top surface is planarized.

[0103] In Fig. 19, the encapsulation 472 may be subjected to a grinding process to expose the electrical connectors 406 and vias 466. Surfaces of the electrical connectors 406, vias 466, the semiconductor substrate 102, and the encapsulation 472 are flush after the grinding process.

[0104] Fig. 20 illustrates further processing on the structure of the Fig. 19. The processing between these two figures is similar to the processing described above with reference to the Fig. 10 and Fig. 11 was illustrated and described, where Fig. 11 an equivalent intermediate stage as Fig. 20 and the descriptions are not repeated here. In Fig. 20, the front side redistribution structure 410 is formed to overlie and electrically couple the vias 406 and vias 466.

[0105] Fig. 21 illustrates further processing on the structure of the Fig. 20. The processing between these two figures is similar to the processing described above with reference to the Fig. 12 to 14, where Fig. 14 an equivalent intermediate stage as Fig. 21 and the descriptions are not repeated here. In Fig. 21, a second housing 450 is attached to the housing structure 476 of the Fig. 20 bonded.

[0106] Further processing can be done on the housing structure of the Fig. 21. The housing structure of the Fig. 21 can be mounted, for example, on a package substrate using the conductive connectors 416.

[0107] The Fig. 22 to 28 illustrate cross-sectional views of another housing structure in accordance with some embodiments. The embodiment in Fig. 22 to 28 is the embodiment shown in the Fig. 15 to 21, except that this embodiment has integrated circuit chips 100 and 200 bonded front-to-back instead of front-to-front. In addition, the integrated circuit chips 100 include chip connectors 488 and an insulating layer 490 on the pads 104 on the active side of the integrated circuit chip 100. These chip connectors 488 and this insulating layer 490 may protect the pads 104 during a subsequent planarization process. Details associated with this embodiment that are similar to those of the embodiments described above will not be repeated here.

[0108] The chip connectors 488 may be formed from similar materials and by similar processes as the pads 104 described above, and the description will not be repeated here. In this embodiment, the chip connectors could be copper pillars, and the pads 104 could be aluminum contact pads. The insulating layer 490 could be similar to the insulating layer 208 described above, and the description will not be repeated here.

[0109] In Fig. 23, the active side of the integrated circuit chip 100 is attached to a carrier substrate 498. The carrier substrate 498 is similar to the carrier substrate 400 described above, and the description will not be repeated here. The backside of the integrated circuit chip 100 is thinned to expose the vias 466. The thinning may be similar to the thinning process described above in Fig. 6, and the description is not repeated here. After the thinning process, insulating layers 492 and 496 and pads 494 are formed on the backside of the integrated circuit chip 100. The insulating layers 492 and 496 and pads 494 are used in the bonding of the integrated circuit chip 100 to the integrated circuit chip 200. The pads 494 are electrically coupled to the exposed vias 466. The pads 494 can be formed from similar materials and by similar processes as the pads 104 described above, and the description is not repeated here. The insulating layers 492 and 496 can be formed from similar materials and by similar processes as the insulating layer 208 described above, and the description is not repeated here.

[0110] In Fig. 24, the integrated circuit chip 100 is bonded to the integrated circuit chip 200. The bonding was carried out in the Fig. 2 and Fig. 3 above, and the descriptions are not repeated here. In Fig. 24, the integrated circuit chips 100 and 200 are bonded with bonds 300. The bonds 300 may be any of the bond configurations 300A to 300O in the Fig. 4A to 4O.

[0111] Fig. 25 illustrates further processing on the structure of the Fig. 24. The processing between these two figures is similar to the processing described above with reference to the Fig. 3 to 5, where Fig. 5 an equivalent intermediate stage as Fig. 25, and the descriptions are not repeated here. The bonded integrated circuit chips 100 and 200 are encapsulated with encapsulant 499 to form a package 500.

[0112] Fig. Figure 26 illustrates the mounting of the housing 500 on a carrier substrate 400 similar to that shown above in Figures Fig. 7 and Fig. 8, and the descriptions are not repeated here. In Fig. 26, the package 500 is attached to the carrier with the integrated circuit chip 200 closer to the carrier substrate than the integrated circuit chip 100.

[0113] Fig. 26 illustrates further processing on the structure of the Fig. 25. The processing between these two figures is similar to the processing described above with reference to the Fig. 9 and Fig. 10 was illustrated and described, where Fig. 10 an equivalent intermediate as Fig. 26, and the descriptions are not repeated here. The housing 500 is encapsulated with encapsulant 502, and the top surface is planarized.

[0114] In Fig. 26, the encapsulation 502 may be subjected to a grinding process to expose the electrical connectors 406 and connectors 488. Surfaces of the electrical connectors 406, vias 488, the insulating layer 490, and the encapsulation 502 are flush after the grinding process.

[0115] Fig. 27 illustrates further processing on the structure of the Fig. 26. The processing between these two figures is similar to the processing described above with reference to the Fig. 10 and Fig. 11 was illustrated and described, where Fig. 11 an equivalent intermediate stage as Fig. 27 and the descriptions are not repeated here. In Fig. 27, the redistribution structure 410 is formed to overlie and electrically couple the vias 406 and vias 488.

[0116] Fig. 28 illustrates further processing on the structure of the Fig. 27. The processing between these two figures is similar to the processing described above with reference to the Fig. 12 to 14, where Fig. 14 an equivalent intermediate stage as Fig. 28 and the descriptions are not repeated here. In Fig. 28, a second housing 450 is attached to the housing structure 500 of the Fig. 27 bonded.

[0117] Further processing can be done on the housing structure of the Fig. 28. The housing structure of the Fig. 28 can be mounted, for example, on a package substrate using the conductive connectors 416.

[0118] The Fig. 29 to 34 illustrate cross-sectional views of another housing structure in accordance with some embodiments. The embodiment in Fig. 29 to 34 is the embodiment shown in the Fig. 22 to 28, except that in this embodiment, the integrated circuit chip 100 does not include chip connectors 488 and insulating layer 490 on the pads 104 on the active side of the integrated circuit chip 100. Removing the chip connectors 488 and insulating layer 490 requires additional carrier substrate bonding / peeling to protect the pads 104. Details related to this embodiment that are similar to those of the embodiments described above will not be repeated here.

[0119] Fig. Figure 29 illustrates the integrated circuit chip 100 connected to the integrated circuit chip 200 as shown above in Fig. 24, and the description is not repeated here. The bonding was described above in the Fig. 2 and Fig. 3, and the descriptions are not repeated here. In Fig. 29, the integrated circuit chips 100 and 200 are bonded with bonds 300. The bonds 300 may be any of the bond configurations 300A to 300O in the Fig. 4A to 4O.

[0120] Fig. 30 illustrates further processing on the structure of the Fig. 29. The processing between these two figures is similar to the processing described above with reference to the Fig. 3 to 8, where Fig. 8 an equivalent intermediate stage as Fig. 30, and the descriptions are not repeated here. The bonded integrated circuit chips 100 and 200 are encapsulated with encapsulant 522 to form a package 524.

[0121] Fig. Figure 30 further illustrates the mounting of the housing 524 on a carrier substrate 400 similar to that shown above in Figures Fig. 7 and Fig. 8, and the descriptions are not repeated here. In Fig. 30, the package 524 is attached to the carrier with the integrated circuit chip 100 closer to the carrier substrate 400 than the integrated circuit chip 200.

[0122] Fig. 31 illustrates further processing on the structure of the Fig. 30. The processing between these two figures is similar to the processing described above with reference to the Fig. 9 and Fig. 10 was illustrated and described, where Fig. 10 an equivalent intermediate as Fig. 31, and the descriptions are not repeated here. The housing 524 is encapsulated with encapsulant 526, and the top surface is planarized.

[0123] In Fig. 31, the encapsulation 526 may be subjected to a grinding process to expose the electrical connectors 406. Surfaces of the electrical connectors 406 and the encapsulation 526 are flush after the grinding process.

[0124] Fig. 32 illustrates further processing on the structure of the Fig. 31. In Fig. 32, the carrier substrate 400 is detached, and the structure is turned over and bonded to another carrier substrate 530. The detachment process was described above, and the description will not be repeated here. In Fig. 32, the housing 524 is attached to the carrier with the integrated circuit chip 200 closer to the carrier substrate 530 than the integrated circuit chip 100. In Fig. 32, the exposed surfaces of the encapsulation 526, dielectric connector 406 and pads 104 as well as the semiconductor substrate are flush without a grinding process.

[0125] Fig. 33 illustrates further processing on the structure of the Fig. 32. The processing between these two figures is similar to the processing described above with reference to the Fig. 10 and Fig. 11 was illustrated and described, where Fig. 11 an equivalent intermediate stage as Fig. 33 and the descriptions are not repeated here. In Fig. 33, the redistribution structure 410 and the conductive connectors 416 are formed to overlie and electrically couple the vias 406 and pads 104.

[0126] Fig. 34 illustrates further processing on the structure of the Fig. 33. The processing between these two figures is similar to the processing described above with reference to the Fig. 12 to 14, where Fig. 14 an equivalent intermediate stage as Fig. 34 and the descriptions are not repeated here. In Fig. 34, a second housing 450 is attached to the housing structure 540 of the Fig. 33 bonded.

[0127] Further processing can be done on the housing structure of the Fig. 34. The housing structure of the Fig. 34 can be mounted, for example, on a package substrate using the conductive connectors 416.

[0128] The Fig. 35 to 38 illustrate cross-sectional views of another housing structure in accordance with some embodiments. The embodiment in Fig. 35 to 38 is the embodiment shown in the Fig. 1 to 14, except that in this embodiment, a gap exists between the dielectric layers of integrated circuit chips 100 and 200 after bonding. Details related to this embodiment that are similar to those of the embodiments described above will not be repeated here.

[0129] Fig. Figure 35 illustrates the integrated circuit chip 100 connected to the integrated circuit chip 200 as shown above in Figures Fig. 2 and Fig. 3, and the descriptions are not repeated here. In Fig. 35, the integrated circuit chips 100 and 200 are bonded with bonds 300. The bonds 300 in this embodiment are the bond configuration 300D in Fig. 4D. This embodiment includes the spacing gap between the dielectric layers of integrated circuit chips 100 and 200.

[0130] Fig. 36 illustrates further processing on the structure of the Fig. 35. In Fig. 36, a sealing layer 546 is formed over the various components to seal the bonding interface between the integrated circuit chips 100 and 200. Sealing the bonding interface may aid the reliability of this embodiment compared to not sealing the bonding interface in this configuration. The sealing layer 546 may be formed from similar materials and by similar processes as the insulating layer 208 described above, and the description will not be repeated here. In accordance with one embodiment, the sealing layer may be formed from polymeric materials, for example, a parylene, a polyimide, a BCB, and a PBO, or the like. The formation methods may be spraying, blasting, coating, or the like.

[0131] Fig. 37 illustrates further processing on the structure of the Fig. 36. The processing between these two figures is similar to the processing described above with reference to Fig. 5 was illustrated and described, where Fig. 5 an equivalent intermediate stage as Fig. 37, and the descriptions are not repeated here. The bonded integrated circuit chips 100 and 200 are encapsulated with encapsulant 548 to form a package.

[0132] Fig. 38 illustrates further processing on the structure of the Fig. 37. The processing between these two figures is similar to the processing described above with reference to the Fig. 5 to 14, where Fig. 14 an equivalent intermediate stage as Fig. 38 and the descriptions are not repeated here. In Fig. 38, a second housing 450 is attached to the housing structure 562, which contains the bonded integrated circuit chips of the Fig. 37, bonded.

[0133] Further processing can be done on the housing structure of the Fig. 38. The housing structure of the Fig. 38 can be mounted, for example, on a package substrate using the conductive connectors 416.

[0134] By forming a PoP structure comprising chips bonded using a hybrid bonding technique using solder instead of the typical copper-to-copper bonding of hybrid bonding. The bonding temperature of hybrid bonding can be significantly lowered. Additionally, the bond pads of the structures can be recessed to reduce the height of the package structure. The chips can be bonded face-to-face (F2F) or face-to-back (F2B). For example, in an F2F bonding configuration, the active surfaces (faces) of the chips are bonded together, while in an F2B bonding configuration, an active surface of one chip is bonded to a back surface of another chip.

[0135] In one embodiment, a package comprises a first package structure comprising a first chip having a first active side and a first backside, the active side comprising a first bond pad and a first insulating layer, a second chip bonded to the first chip, the second chip having a second active side and a second backside, the second active side comprising a second bond pad and a second insulating layer, the second active side of the second chip facing the first active side of the first chip, the second insulating layer being bonded to the first insulating layer by dielectric-to-dielectric bonds, and a conductive bonding material bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature that is lower than reflow temperatures of the first and second bond pads.

[0136] Embodiments may include one or more of the following features: The package wherein the first insulating layer is bonded to the second insulating layer with respective bonds comprising OH bonds. The package wherein the first bond pad is recessed into the first insulating layer. The package wherein the first insulating layer and the second insulating layer are both made of a polymer. The package wherein the first insulating layer and the second insulating layer are both formed of silicon nitride, silicon oxide, phosphor glass (PSG), borosilicate glass (BSG), boron-doped phosphor glass (BPSG), or a combination thereof. The package wherein a void surrounds the conductive bonding material and lies between the first and second bond pads.The package, wherein the first package structure further comprises a conductive pad on the first active side of the first chip, a first via electrically coupled to the conductive pad, a first encapsulation on the first chip and laterally encapsulating the second chip and the via, the first via extending through the first encapsulation; and a first redistribution structure over the second chip, the first via, and the first encapsulation, the first redistribution structure electrically coupled to the first via.The package, wherein the first package structure further comprises a second via adjacent to the first chip and a second encapsulant encapsulating the first chip, the first encapsulant, and the second via, the second via extending through the second encapsulant, the first redistribution structure electrically coupled to the second via. The package may further comprise a second package structure bonded to the second via by a first conductive connector.

[0137] In one embodiment, a method comprises forming a first package, bonding a first side of a first chip to a second side of a second chip with a conductive bonding material, and first and second insulating layers, the first side comprising a first bond pad and the first insulating layer, the second side comprising a second bond pad and the second insulating layer, the second side of the second chip facing the first side of the first chip, the second insulating layer being bonded to the first insulating layer by dielectric-to-dielectric bonds, the conductive bonding material being bonded to the first bond pad and the second bond pad, the conductive bonding material having a reflow temperature that is lower than reflow temperatures of the first and second bond pads.

[0138] Embodiments may include one or more of the following features. The method, wherein forming the first package further comprises forming a first conductive pillar and electrically coupled to a third bond pad on the first side of the first chip, and encapsulating the first chip, the second chip, and the first conductive pillar with a first encapsulant. The method, wherein forming the first package further comprises forming an electrical connector over a carrier substrate that attaches the bonded first and second chips to the carrier substrate adjacent to the electrical connector, the first chip being adjacent to the carrier substrate, encapsulating the first and second bonded chips, the first encapsulant, and the electrical connectors with a second encapsulant, and forming a first redistribution structure over the first chip, the second chip, the first encapsulant,the second encapsulation and the electrical connector, wherein the first redistribution structure is electrically coupled to the first conductive pillar and the electrical connector. The method further comprises removing the carrier substrate and bonding a second housing to the electrical connector of the first housing using a first conductive connector, wherein the second housing is proximate to the first housing. The method, wherein forming the first housing further comprises forming a via in the first chip, encapsulating the first chip and the second chip with a first encapsulation, forming an electrical connector over a carrier substrate, attaching the encapsulation and the bonded first and second chips to the carrier substrate adjacent to the electrical connector, wherein the second chip is adjacent to the carrier substrate,encapsulating the bonded first and second chips, the first encapsulation, and the electrical connector with a second encapsulation; planarizing the encapsulation, wherein the electrical connector and the via in the first chip are exposed after planarization; forming a first redistribution structure over the first chip, the second chip, the first encapsulation, the second encapsulation, and the electrical connector, wherein the first redistribution structure is electrically coupled to the via in the first chip and the electrical connector; and forming conductive connectors over and electrically coupled to the first redistribution structure. The method wherein the first insulating layer and the second insulating layer are both made of a polymer. The method wherein the first insulating layer and the second insulating layer are both made of silicon nitride, silicon oxide,Phosphor glass (PSG), borosilicate glass (BSG), boron-doped phosphor glass (BPSG) or a combination of these.

[0139] In one embodiment, a method comprises forming a first insulating layer over a first side of a first wafer, patterning a recess in the first insulating layer, conformally depositing a conductive material in the recess and over the first insulating layer, wherein a thickness of the conductive material is less than a thickness of the first insulating layer, removing portions of the conductive material outside the recess to form a first bond pad, wherein the first bond pad and the first insulating layer are located on a first active side of a first chip in the first wafer, forming a second chip having a second active side, wherein the second active side has a second bond pad and a second insulating layer, forming a conductive bump on the second bond pad, wherein the conductive bump has a reflow temperature,which is lower than reflow temperatures of the first and second bond pads, bonding the conductive bump on the second bond pad to the first bond pad; and bonding the second insulating layer of the second chip to the first insulating layer.

[0140] Embodiments may include one or more of the following features. The method further comprises forming a first conductive pillar and electrically coupled to a third bond pad on the first active side of the first chip; encapsulating the first wafer, the second chip, and the first conductive pillar with a first encapsulant; and singulating the first wafer and the first encapsulant, wherein the singulating forms a first package structure comprising the first chip, the second chip, the first conductive pillar, and the first encapsulant.The method further comprises forming an electrical connector over a carrier substrate, attaching the first package structure to the carrier substrate adjacent to the electrical connector, wherein the first chip is adjacent to the carrier substrate; encapsulating the first package structure and the electrical connector with a second encapsulant; and forming a first redistribution structure over the first package structure, the second encapsulant, and the electrical connector, the first redistribution structure electrically coupled to the first conductive pillar and the electrical connector.

Claims

[1] Housing comprising: a first housing structure comprising: a first chip (100) having a first active side and a first backside, the first active side comprising a first bond pad (104) and a first insulating layer; a second chip (200) bonded to the first chip (100), the second chip having a second active side and a second backside, the second active side comprising a second bonding pad (206) and a second insulating layer (208), the second active side of the second chip facing the first active side of the first chip, the second insulating layer being bonded to the first insulating layer by dielectric-to-dielectric bonds; and a conductive bonding material bonded to the first bonding pad (104) and the second bonding pad (206), the conductive bonding material having a reflow temperature lower than reflow temperatures of the first and second bonding pads (104, 206); wherein the conductive bonding material is partially enclosed by one of the bond pads. [2] The package of claim 1, wherein the first insulating layer is bonded to the second insulating layer (208) with respective bonds comprising OH bonds. [3] The package according to claim 1 or 2, wherein the first bonding pad (312) is recessed into the first insulating layer (308). [4] A housing according to any one of the preceding claims, wherein the first insulating layer (340) and the second insulating layer (340) are both made of a polymer. [5] A package according to any one of the preceding claims, wherein the first insulating layer (414) and the second insulating layer (206) are both made of silicon nitride, silicon oxide, phosphor glass, PSG, borosilicate glass, BSG, boron-doped phosphor glass, BPSG, or a combination thereof. [6] A package according to any one of the preceding claims, wherein a void (336) surrounds the conductive bonding material and is located between the first and second bond pads (104, 206). [7] Housing according to one of the preceding claims, wherein the first housing structure further comprises: a conductive pad (436) on the first active side of the first chip; a first via (432) coupled to the conductive pad (336); a first encapsulation (408) on the first chip (100) and laterally encapsulating the second chip (200) and the first via (432), the first via extending through the first encapsulation; and a first redistribution structure (410) over the second chip, the first via (332) and the first encapsulation (308), the first redistribution structure (410) being electrically coupled to the first via. [8] The housing of claim 7, wherein the first housing structure further comprises: a second via (204) adjacent to the first chip; and a second encapsulation (473) encapsulating the first chip, the first encapsulation, and the second via, the second via extending through the second encapsulation, the first redistribution structure being electrically coupled to the second via. [9] A housing according to claim 8, further comprising: a second housing structure (450) bonded to the second via by a first conductive connector (416). [10] A package according to any one of the preceding claims, wherein the conductive bonding material is a solder material, and wherein the first and second bonding pads (104, 206) comprise copper or aluminum. [11] Procedure comprising: Forming a first housing (420) comprising: Bonding a first side of a first chip (100) to a second side of a second chip (200) with a conductive bonding material and first and second insulating layers (208), the first side comprising a first bonding pad (104) and the first insulating layer, the second side (206) comprising a second bonding pad and the second insulating layer (208), the second side of the second chip facing the first side of the first chip, the second insulating layer (208) being bonded to the first insulating layer by dielectric-to-dielectric bonds, the conductive bonding material being bonded to the first bonding pad (104) and the second bonding pad (206), the conductive bonding material having a reflow temperature that is lower than reflow temperatures of the first and second bonding pads; wherein forming the first housing (392) further comprises: Forming a first conductive pillar (406) on and electrically coupled to a third bond pad on the first side of the first chip; and Encapsulating the first chip, the second chip and the first conductive column with a first encapsulation (408); and wherein forming the first housing further comprises: Forming an electrical connector (406) over a carrier substrate (400); Attaching the bonded first and second chips (100, 200) to the carrier substrate adjacent to the electrical connector (406), the first chip being adjacent to the carrier substrate; Encapsulating the bonded first and second chips, the first encapsulation (390) and the electrical connector (406) with a second encapsulation (408); and Forming a first redistribution structure (410) over the first chip (100), the second chip (200), the first encapsulation (390), the second encapsulation (408), and the electrical connector (406), wherein the first redistribution structure (410) is electrically coupled to the first conductive pillar (106) and the electrical connector (406). [12] The method of claim 11, further comprising: Removing the carrier substrate (400); and Bonding a second housing (450) to the electrical connector (406) of the first housing (420) using a first conductive connector (406), wherein the second housing (450) is proximate to the first chip. [13] The method of any one of the preceding claims 11 or 12, wherein forming the first housing (420) further comprises: forming a via in the first chip (432); Encapsulating the first chip and the second chip with a first encapsulation (464); Forming an electrical connector (406) over a carrier substrate (400); Attaching the encapsulation (464) and the bonded first and second chips to the carrier substrate (400) adjacent to the electrical connector, the chip being adjacent to the carrier substrate; Encapsulating the bonded first and second chips, the first encapsulation (464) and the electrical connector (406) with a second encapsulation (472); Planarizing the encapsulation, wherein the electrical connector (406) and the via (466) in the first chip (100) are exposed after planarization; Forming a first redistribution structure (410) over the first chip (100), the second chip (200), the first encapsulation (464), the second encapsulation, and the electrical connector, wherein the first redistribution structure (410) is electrically coupled to the via (466) in the first chip (100) and the electrical connector (406); and Forming electrical connectors (412) over and electrically coupled to the first redistribution structure (410). [14] The method of any one of the preceding claims 11 to 13, wherein the first insulating layer and the second insulating layer (208) are both made of a polymer. [15] The method of any one of the preceding claims 11 to 14, wherein the first insulating layer and the second insulating layer (208) are both made of silicon nitride, silicon oxide, phosphor glass (PSG), borosilicate glass (BSG), boron-doped phosphor glass (BPSG), or a combination thereof. [16] Procedure comprising: Forming a first insulating layer (414) over a first side of a first wafer; Structuring a recess in the first insulating layer (414); conformally depositing a conductive material (412) in the recess and over the first insulating layer (414), wherein a thickness of the conductive material is less than a thickness of the first insulating layer (414); Removing portions of the conductive material (412) outside the recess to form a first bond pad, wherein the first bond pad and the first insulating layer (414) are located on a first active side of a first chip (100) in the first wafer; Forming a second chip (200) comprising a second active side, the second active side comprising a second bond pad (206) and a second insulating layer (208); Forming a conductive bump (332) on the second bond pad (206), the conductive bump having a reflow temperature lower than reflow temperatures of the first and second bond pads; Bonding the conductive bump (332) on the second bond pad (206) to the first bond pad (104); and Bonding the second insulating layer (208) of the second chip (200) to the first insulating layer. [17] The method of claim 16, further comprising: Forming a first conductive pillar (106) on and electrically coupled to a third bond pad on the first active side of the first chip; Encapsulating the first wafer, the second chip (200) and the first conductive column (204) with a first encapsulation (390); and Dicing the first wafer and the first encapsulant (390), wherein the dicing forms a first package structure comprising the first chip (100), the second chip (200), the first conductive pillar (106), and the first encapsulant (390). [18] The method of claim 17, further comprising: Forming an electrical connector (406) over a carrier substrate (400); Attaching the first package structure (420) to the carrier substrate adjacent to the electrical connector (406), wherein the first chip (100) is adjacent to the carrier substrate; Encapsulating the first housing structure (420) and the electrical connector (406) with a second encapsulation (408); and Forming a first redistribution structure (410) over the first housing structure (420), the second encapsulation (408) and the electrical connector (406), wherein the first redistribution structure (410) is electrically coupled to the first conductive pillar (106) and the electrical connector (406).

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