Multi-function overlay marks for noise reduction and extracting information about focus and critical dimension

Abstract

Device comprising: a first superposition mark (200A) comprising: a first component (210) arranged in a first region of the first superposition mark (200A), the first component (210) comprising multiple grids (230) extending in a first direction; a second component (211) arranged in a second region of the first superposition mark (200A), the second component (211) comprising multiple grids (230) extending in the first direction; a third component (220) arranged in a third region of the first superposition mark (200A), the third component (220) comprising multiple grids (231) extending in a second direction different from the first direction; and a fourth component (221) arranged in a fourth region of the first superposition mark (200A), the fourth component (221) comprising multiple grids (231).extending in the second direction, wherein: the first region is aligned with the second region, and the third region is aligned with the fourth region; wherein at least one section (240) of the first superposition mark (200A) is located adjacent to an edge of an integrated circuit chip or an edge of a test line and has a lower feature density than another section (250) of the first superposition mark (200A); wherein the first component (210) and the second component (211) each have a boundary located in the at least one section (240).

Description

PRIOR ARTThe semiconductor integrated circuit (IC) industry has experienced very rapid growth. Technological advances in IC materials and designs have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and similar advances in IC processing and manufacturing are required to implement these advances. The functional density (i.e., the number of interconnected devices per chip area) has fundamentally increased as integrated circuits develop, while the geometric size (i.e., the smallest component (or trace) that can be generated using a fabrication process) has become smaller.Overlay marks are used to measure the overlay or alignment between different layers of an IC. However, conventional overlay marks still have deficiencies. For example, the measurement accuracy of a conventional overlay mark may be affected by the position of the overlay mark, such as the pattern density of the IC features surrounding the overlay mark. Although conventional overlay marks may be used to measure overlay, as another example, they are unable to determine focus or critical dimension (CD) information. Thus, although existing overlay marks are generally suitable for their intended purposes, they are not fully satisfactory in all respects.US 2013 / 0 200 535 A1 discloses a method in which an overlay mark with line patterns in an X direction and line patterns in a Y direction is used, wherein first and second lines are arranged alternately in the respective direction in all regions of the overlay mark.WO 2016 / 030 255 A2 describes a method in which asymmetry of a plurality of periodic structures is measured and used together with information about an overlap of the periodic structures to determine performance parameters of a lithographic process that can contain focus information.SUMMARY OF THE INVENTIONThe present invention relates to a device according to claim 1, a method according to claim 9 and a method according to claim 18.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying figures. It is emphasized that, according to the standard industry method, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 is a schematic view of a lithographic system constructed in accordance with some embodiments of the present invention. FIG. 2 is a cross-sectional view of an EUV mask constructed in accordance with some embodiments of the present invention. FIG. 3 shows a simplified partial cross-sectional view of overlay mark 100 in accordance with some embodiments of the present invention. FIGS. 4A-4B show superimposed simplified cross-sectional partial views of an upper layer 130A and a lower layer 130B, in accordance with some embodiments of the present invention. FIG. 5 shows a top view of an embodiment of a overlay mark on a wafer in accordance with some embodiments of the present invention. FIG. 6A is a simplified top view of a portion of a wafer in accordance with some embodiments of the present invention. FIG. 6B is a simplified top view of a test line oriented vertically, in accordance with some embodiments of the present invention. FIG. 6C is a simplified top view of a test line horizontally oriented, in accordance with some embodiments of the present invention. FIGS. 7A-7B each show a cross-sectional profile of a plurality of gratings of an overlay mark. FIGS. 8-10 show a top view of an embodiment of a overlay mark on a wafer in accordance with some embodiments of the present invention. FIG. 11 illustrates multiple overlay marks arranged as an M×N array around a main structure, in accordance with some embodiments of the present invention. FIG. 12 illustrates top and bottom views of a component of a overlay mark according to some embodiments of the present invention. FIG. 13 illustrates top and bottom views of a component of a overlay mark according to some embodiments of the present invention. FIG. 14 shows a top view of a overlay mark in accordance with some embodiments of the present invention. FIG. 15A shows the partial plan views of an upper layer and a lower layer of an FR region of a overlay mark according to some embodiments of the present invention. FIG. 15B shows the partial plan views of an upper layer and a lower layer of an FL region of a overlay mark according to some embodiments of the present invention. FIG. 16 illustrates various graphs corresponding to a sub-pattern overlay mark and a non-sub-pattern overlay mark, respectively, in accordance with some embodiments of the present invention. FIGS. 17A-17B show partial plan views of portions of a overlay mark having sub-structures in accordance with some embodiments of the present invention. FIGS. 18A through 18E show the top views of some embodiments of sub-structures in a overlay mark according to some embodiments of the present invention. FIG. 19 shows a graph of a critical dimension (CD) versus focus, in accordance with some embodiments of the present invention. FIGS. 20A-20B show a combination mark 700 and a compound mark 701, respectively, in accordance with some embodiments of the present invention. FIGS. 21A, 21B, and 21C show the top views of a overlay mark according to some embodiments of the present invention. FIG. 22 is graphs showing the relationship between diffraction light intensity and CD according to some embodiments of the present invention. FIGS. 23-26 are flowcharts showing the process flows associated with the overlay marks, according to some embodiments of the present invention. FIGS. 27-32 show side cross-sectional side views of an apparatus at various stages of manufacture in accordance with embodiments of the present invention.DETAILED DESCRIPTIONThe following invention provides many different embodiments, or examples, for implementing different features of the present subject matter. Concrete examples of components and arrangements are described below in order to simplify the present invention. These are of course merely examples. For example, forming a first feature over or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or embodiments discussed.Moreover, terms relating to spatial relativeity, such as "below," "below," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature (to other elements or features) as depicted in the figures. The terms relating to spatial relativeness are intended to encompass different orientations of the device being used or operated in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or otherwise oriented) and the spatially relative terms used herein may likewise be construed accordingly.To ensure accurate alignment (also referred to as overlay) between the various layers in a fabricated semiconductor device, overlay marks (different from alignment marks used to align a mask to a tooling table during lithography) are used to measure the alignment between the layers. However, conventional overlay marks may have deficiencies. For example, conventional overlay marks may be susceptible to being adversely affected by noise. As another example, conventional overlay marks may not be able to extract focus or critical dimension information.To overcome the problems discussed above, the present invention provides embodiments of overlay marks that can reduce noise and are also capable of extracting focus and critical dimension information. The various aspects of the present invention are discussed in greater detail below with reference to Figures 1-24. First, an EUV lithography system is discussed below with reference to FIGS. 1-2 as an example of a lithography context in which the overlay mark of the present invention may be used, although it should be understood that the overlay mark discussed herein may also be used for other types of non-EUV lithography contexts. Next, the details of the overlay mark according to embodiments of the present invention will be discussed with reference to FIGS. 3 to 24.FIG. 1 shows a schematic view diagram of an EUV lithography system 10 constructed in accordance with some embodiments. The EUV lithography system 10 may be generally referred to as a scanner configured to perform lithographic exposure processes with a respective radiation source and exposure mode. The EUV lithography system 10 is configured to expose a photoresist layer to EUV light or an EUV radiation. The photoresist layer is a material sensitive to the EUV light. The EUV lithography system 10 uses a radiation source 12 to generate EUV light, such as EUV light having a wavelength ranging between about 1 nm and 100 nm. In a particular example, the radiation source 12 generates EUV light having a wavelength centered at 13.5 nm. Accordingly, the radiation source 12 is also referred to as an EUV radiation source 12.The lithography system 10 also uses an illumination device 14. In various embodiments, the illumination device 14 includes various optical refraction components, such as a single lens or a lens system including multiple lenses (zone plates), or alternatively reflection optics (for the EUV lithography system), such as a single mirror or a mirror system including multiple mirrors, for directing light from the radiation source 12 onto a mask table 16, in particular onto a mask 18 mounted on the mask table 16. In the present embodiment, in which the radiation source 12 generates light in the EUV wavelength range, the illumination device 14 uses reflection optics. In some embodiments, the lighting device 14 includes a dipole lighting component.In some embodiments, the illuminator 14 is operable to configure the mirrors to provide appropriate illumination to the mask 18. In one example, the mirrors of the illumination device 14 are switchable to reflect the EUV light to different illumination positions. In some embodiments, a stage prior to the illuminator 14 may additionally include other switchable mirrors that are controllable to direct the EUV light to different illumination positions with the mirrors of the illuminator 14. In some embodiments, the illumination device 14 is configured to provide on-axis illumination (ONI) to the mask 18. In one example, a disk illuminator 14 having a partial coherence of at most 0.3 is used. In some embodiments, the illuminator 14 is configured to provide off-axis illumination (OAI) to the mask 18. In one example, the lighting device 14 is a dipole lighting device. The dipole illumination device has a partial coherence of at most 0.3 in some embodiments.Lithography system 10 also includes a mask table 16 configured to mount a mask 18. In some embodiments, the mask table 16 includes an electrostatic chuck (e-chuck) to secure the mask 18. This is because gas molecules absorb EUV light and the lithography system for EUV lithography patterning is maintained in a vacuum environment to avoid the EUV intensity loss. In the invention, the terms mask, photomask and reticle are used interchangeably and refer to the same subject matter.In the present embodiment, lithography system 10 is an EUV lithography system and mask 18 is a reflective mask. An example structure of mask 18 is provided for illustrative purposes. The mask 18 includes a substrate having a suitable material, such as a low thermal expansion material (LTEM) or fused silica. In various examples, the LTEM comprises TiO2-doped SiO2or other suitable low thermal expansion materials. In some embodiments, the LTEM comprises 5 to 20 weight percent TiO2and has a coefficient of thermal expansion less than about 1.0 x 10-6 / °C. For example, in some embodiments, the TiO2-doped SiO2material of the LTEM has such a coefficient of thermal expansion that it varies by less than 60 parts per billion for each temperature change of 1 degree Celsius. Of course, other suitable materials having a thermal expansion coefficient less than or equal to that of the TiO2-doped SiO2may be used.Mask 18 also includes a reflective ML deposited on the substrate. The ML includes multiple film pairs, such as molybdenum-silicon (Mo / Si) film pairs (e.g., a layer of molybdenum above or below a layer of silicon in each film pair). Alternatively, the ML may comprise molybdenum beryllium (Mo / Be) film pairs or other suitable materials configurable to strongly reflect the EUV light.The mask 18 may further include a capping layer such as ruthenium (Ru) disposed on the ML for protection. The mask 18 further includes an absorption layer disposed over the ML. The absorption layer is patterned to define an integrated circuit (IC) layer. Alternatively, another reflective layer may be deposited over the ML and is patterned to define an integrated circuit layer, thereby forming an EUV phase shift mask.The lithography system 10 also includes a projection optical module (or projection optical box (POB)) 20 for imaging the pattern of the mask 18 onto a target 26 mounted on a substrate table 28 of the lithography system 10. The light directed from the mask 18, diffracted into different orders of diffraction and carrying the image of the structure defined on the mask, is collected by the POB 20. The POB 20 may include a magnification of less than one (whereby the size of the "image" on a target (such as target 26 discussed below) is less than the size of the corresponding "object" on the mask). The illumination device 14 and the POB 20 are collectively referred to as an optical module of the lithography system 10.Lithography system 10 also includes a pupil phase modulator 22 for modulating the optical phase of the light directed from mask 18 so that the light has a phase distribution on a projection pupil plane 24. In the optical module, there is a plane having a field distribution corresponding to a Fourier transform of the object (the mask 18 in the present case). This plane is referred to as a projection pupil plane. The pupil phase modulator 22 provides a mechanism for modulating the optical phase of the light on the projection pupil plane 24. In some embodiments, the pupil phase modulator 22 includes a mechanism to adjust the reflective mirrors of the POB 20 for phase modulation. For example, the mirrors of the POBs 20 are switchable and controlled to reflect the EUV light, thereby modulating the phase of the light by the POBs 20.In some embodiments, the pupil phase modulator 22 uses a pupil filter disposed on the projection pupil plane. A pupil filter filters out certain spatial frequency components of the EUV light from the mask 18. Specifically, the pupil filter is a phase pupil filter that functions to modulate a phase distribution of the light guided by the POB 20. However, using a phase pupil filter is limited in some lithography systems (such as an EUV lithography system) because all materials absorb EUV light.As discussed above, lithography system 10 also includes substrate table 28 for mounting a target 26 to be patterned, such as a semiconductor substrate. In the present embodiment, the semiconductor substrate is a semiconductor wafer, such as a silicon wafer or other type of wafer. The target 26 is coated with the photoresist layer sensitive to the radiation beam, e.g., an EUV light in the present embodiment. Various components, including those described above, are jointly integrated and are operable to perform lithographic exposure processes. Lithography system 10 may further include other modules or may be integrated (or coupled) with other modules.The mask 18 and the method of forming the same will be further described in accordance with some embodiments. In some embodiments, the mask manufacturing process includes two operations: a mask blank manufacturing process and a mask patterning process. During the fabrication process of the blanket mask, a blanket mask is formed by depositing appropriate layers (e.g., reflective multi-layers) on an appropriate substrate. The blanket mask is then patterned during the mask patterning process to obtain a desired integrated circuit (IC) layer design. The patterned mask is then used to transfer circuit patterns (e.g., the design of a layer of an IC) to a semiconductor wafer. The structures may be transferred over and over to multiple wafers using different lithography processes. A set of masks is used to build a complete IC.The mask 18 includes a suitable structure, such as a binary intensity mask (BIM) and a phase shifting mask (PSM), in various embodiments. An example of a BIM includes absorption regions (also referred to as opaque regions) and reflection regions structured to define an IC structure to be transferred to the target. In the opaque regions, an absorbent is present and incident light is almost completely absorbed by the absorbent. In the reflection regions, the absorbent is removed and the incident light is diffracted by a multilayer (ML). The PSM may be an attenuated PSM (AttPS) or an alternating PSM (AltPS). An example of a PSM includes a first reflective layer (such as a reflective ML) and a second reflective layer structured according to an IC structure. In some examples, an AttPS typically has a reflectivity of 2% to 15% of its absorbent, while an AltPS typically has a reflectivity greater than 50% of its absorbent.An example of the mask 18 is shown in FIG. 2. The mask 18 is an EUV mask in the illustrated embodiment and includes a substrate 30 made of an LTEM. The LTEM material may include TiO2-doped SiO2and / or other low thermal expansion materials known in the art. In some embodiments, a conductive layer 32 is additionally disposed thereunder on the back surface of the LTEM substrate 30 for the electrostatic chuck purpose. In one example, the conductive layer 32 comprises chromium nitride (CrN). In other embodiments, other suitable compositions, such as a tantalum-containing material, are possible.The EUV mask 18 includes a reflective multilayer (ML) structure 34 disposed over the LTEM substrate 30. The ML structure 34 may be selected to provide high reflectivity for a selected type of radiation / wavelength. The ML structure 34 includes multiple film pairs, such as Mo / Si film pairs (e.g., a layer of molybdenum over or under a layer of silicon in each film pair). Alternatively, the ML structure 34 may comprise Mo / Be film pairs or any materials having a refractive index difference that are highly reflective at EUV wavelengths.With continued reference to FIG. 2, the EUV mask 18 also includes a capping layer 36 disposed over the ML structure 34 to prevent oxidation of the ML. In some embodiments, the capping layer 36 comprises silicon having a thickness in a range from about 4 nm to about 7 nm. The EUV mask 18 may further include a buffer layer 38 disposed over the capping layer 36 to serve as an etch stop layer in an absorption layer patterning or repair process, which will be described below. The buffer layer 38 has different etching characteristics than the absorption layer disposed above it. The buffer layer 38 includes ruthenium (Ru), Ru compositions such as RuB, RuSi, chromium (Cr), chromium oxide, and chromium nitride in various examples.The EUV mask 18 also includes an absorbent material layer 40 (also referred to as an absorption layer) formed over the buffer layer 38. In some embodiments, the layer of absorbent 40 absorbs the EUV radiation directed onto the mask. In various embodiments, the layer of absorbent material may be made of tantalum boron nitride (TaN), tantalum boron oxide (TaBO), or chromium (Cr), Rad (Ra), or a suitable oxide or nitride (or a suitable alloy) of one or more of the following materials: actium, radium, tellurium, zinc, copper, and aluminum.The EUV lithography system discussed above in FIGS. 1-2 is just one example of a lithography system in which overlay marks may be used. However, the overlay marks of the present invention may be used for other types of lithography systems. The overlay marks of the present invention will now be discussed in more detail below.FIG. 3 shows a simplified partial lateral cross-sectional view of a superposition mark 100. Overlay mark 100 includes an upper layer 100A and a lower layer 100B. In some embodiments, the upper layer 100A includes a patterned resist layer and the lower layer 100B includes a patterned material layer on a wafer. In other embodiments, the upper layer 100A and the lower layer 100B may include different patterned layers on a wafer. It should be understood that the upper layer 100A may be patterned using one photomask, and the lower layer 100B may be patterned using another photomask.The upper layer 100A and the lower layer 100B each comprise a plurality of structured components, also referred to as gratings. For example, the upper layer 100A includes a plurality of gratings 110A, and the lower layer 100B includes a plurality of gratings 110B. The gratings 100A and 110B are elongated features that extend in a particular direction, for example, in a direction perpendicular to the cross-section in which the cross-sectional view of FIG. 3 is drawn. In some embodiments, the grids 110A are periodically distributed and / or the grids 110B are periodically distributed. In other words, the gratings 110A are spaced apart from each other by a constant distance, and the gratings 110B are spaced apart from each other by a constant distance.A superposition between the upper layer 100A and the lower layer 100B may be measured by light diffraction. For example, in response to incident light projected onto overlay mark 100, different orders of diffracted light may be produced as a result. In FIG. 3, the zeroth-order diffracted light is shown as I 0 a +1-order diffracted light is shown as I +1 and a -1-order diffracted light is shown as I -1. The intensities of the various orders of diffraction of light can be measured with the aid of an optical measurement tool. In some embodiments, the optical measurement tool includes a scatterometry tool. It should be appreciated that in some embodiments, the optical measurement tool may also be configured to generate the incident light. Based on the measured I +1- and I -1- data, asymmetry information (As) associated with overlay mark 100 may be defined as As=I +1- I -1.The asymmetry information is used for determining superposition. For example, if I -1 is greater than I +1, it may indicate a false orientation between the upper and lower layers 100A and 100B, where the upper layer 100A is "offset leftward" as compared to the lower layer 100B. For example, if I +1 is greater than I -1, it may indicate a false alignment between the upper and lower layers 100A and 100B, with the upper layer 100A "offset to the right" as compared to the lower layer 100B. When I +1 is equal to I -1 it may represent a substantial alignment between the top layer 100A and the bottom layer 100B. If the determined overlay does not meet specifications, then the top layer 100A may be removed (e.g., using a photoresist strip or ashing process) and a new top layer may be formed or defined using adjusted parameters (e.g., position of the photomask). The new top layer may further comprise a photoresist layer patterned by the photomask, for example. The new upper layer should have a better overlay with the lower layer 100B as a result of the adjusted parameters.Referring to Figures 4A-4B, superimposed simplified cross-sectional partial views of an upper layer 130A and a lower layer 130B are illustrated. The upper layer 130A and the lower layer 130B may be two different layers of a overlay mark on a photomask. The upper layer 130A and the lower layer 130B each include a plurality of gratings 140A and 140B, respectively. A known bias voltage may be induced between the upper layer 130A and the lower layer 130B. For example, FIG. 4A shows a known bias voltage -d between the top layer 130A and 130B. In other words, the gratings 140A in the upper layer 130A may be "offset leftward" with respect to the gratings 140B in the lower layer 130B. On the other hand, FIG. 4B shows a known bias voltage +d between the upper layer 130A and 130B. In other words, the gratings 140A in the upper layer 130A may be "right offset" with respect to the gratings 140B in the lower layer 130B. The known bias voltages +d or -d may be intentionally configured or implemented as part of the design of the photomask.When a wafer is manufactured, the actual total displacement between an upper layer and a lower layer includes the known bias voltages (+d or -d) as well as a superposition (referred to herein as OV or OVL). The superposition refers to the misalignment between the upper and lower layers during wafer fabrication, which is undesirable and should be minimized. Asymmetry is a function of displacement and is therefore a function of superposition, for example as expressed below: As=K*(OV+d) where Asrepresents asymmetry, K represents a slope of a linear function (function of asymmetry and displacement), OV überlagerung, and d represents the known biases. In this equation, Asmay be measured (e.g., by measuring the diffraction of light discussed above with reference to FIG. 3 ) and d is known. Therefore, K and OV are two variables that can be calculated using two equations. In the two equations below, for example, As +d and As -d two different asymmetry calculations are made, one with a superposition mark, the upper and lower layers having a +d bias voltage, and the other with a superposition mark, the upper and lower layers having a -d bias voltage. After the asymmetry information As +d and A -d has been calculated, the superpositions OV and K can also be calculated.Referring to FIG. 5, a top view of an embodiment of a overlay mark 200A on a wafer is illustrated. Overlay mark 200A may include multiple components or portions, for example four different components 210- 211 and 220- 221, as shown in FIG. 5. For example, components 210-211 are aligned with each other in the Y direction, and components 220-221 are aligned with each other in the Y direction, for example.Components 210- 211 each include multiple grids (such as grid 230) extending in the Y direction, and components 220- 221 each include multiple grids (such as grid 231) extending in the X direction that is perpendicular to the Y direction. Each of the components 210- 211 and 220- 221 also includes an upper layer and a lower layer, similar to the upper and lower layers 100A and 100B shown in FIG. 3. In each of the components 210- 211 and 220- 221 of the overlay mark 220A, the gratings are arranged in both the upper layer and the lower layer.A known bias voltage is induced in each of the components 210-211 and 220-221. For component 210, a known bias voltage +d is induced in the X direction - that is, the gratings in their upper layer are offset from the gratings in their lower layer by +d in the X direction. For component 211, a known bias voltage -d is induced in the X direction - that is, the gratings in their upper layer are offset from the gratings in their lower layer by -d in the X direction. For component 220, a known bias voltage -d is induced in the Y direction - that is, the gratings in their upper layer are offset from the gratings in their lower layer by -d in the Y direction. For component 221, a known bias voltage +d is induced in the Y-direction - that is, the gratings in their upper layer are offset from the gratings in their lower layer by +d in the Y-direction. Components 210- 211 may be used to obtain two asymmetry measurements (e.g., As +d and As d) in the X direction, so that it becomes possible to determine the overlap in the X direction. The components 220- 221 may be used to achieve two asymmetry measurements (e.g., As -d and As +d) in the Y direction, so that it becomes possible to determine the overlap in the Y direction.According to various aspects of the present invention, regions 240 of overlay mark 200A are disposed in a region having a lower pattern density than regions 250 of overlay mark 200A. In some embodiments, the lower structure density region may include an edge of an IC or an edge of a test line. For example, with reference to FIGS. 6A, 6B, and 6C, which illustrate some example situations where different pattern densities may be present. More specifically, FIG. 6A is a simplified plan view of a portion of a wafer 270 (e.g., an IC chip on the wafer), FIG. 6B is a simplified plan view of a test line 271 vertically aligned (aligned in the Y direction), and FIG. 6C is a simplified plan view of a test line 272 horizontally aligned (aligned in the X direction). For the portion of wafer 270 in FIG. 6A, its edge regions (such as edge regions 280- 281) may have a lower pattern density than the remainder of the portion of wafer 270. Likewise, for test lines 271- 272, their edge regions (such as edge regions 282 and 283, for example) may also have a lower pattern density than the rest of the test lines.The differences in pattern density may result in different profiles for patterned features, such as the gratings in a overlay mark. An example of the different grid profiles due to the pattern density difference is shown in Figures 7A-7B. More specifically, FIG. 7A shows a cross-sectional profile of a plurality of gratings 300 to 303 of a overlay mark, and FIG. 7B shows a cross-sectional profile of a plurality of gratings 310 to 313 of an overlay mark. Gratings 300- 303 and 310- 313 may be embodiments of gratings 230 or 231 discussed above with reference to FIG. 5. The gratings 300- 303 and 310- 313 are illustrated herein as "trenches", but it should be understood that they may be "islands" in other embodiments.In FIG. 7A, the areas of the wafer (or test line) in which the gratings 300 to 303 are arranged may have comparatively similar pattern densities. Therefore, all grids 300 to 3003 have similar lateral cross-sectional view profiles, for example in terms of their shapes, widths or heights. In comparison, in FIG. 7B, the regions of the wafer (or test line) in which the gratings 310 to 313 are arranged may have different pattern densities. For example, the region of the wafer (or test line) in which the grid 310 is arranged may have a lower pattern density than the regions of the wafer (or test line) in which the grids 311 to 313 are arranged. This may occur when the grid 310 is disposed near an edge of the wafer or test line, such as in regions 280-282 in FIGS. 6A-6C. Thus, the lateral cross-sectional view profile of the grid 310 is different than the lateral cross-sectional view profile of the grids 311-313. Some of these differences may include differences in the shape (e.g., more or less trapezoidal), or width and / or height of the grids. The differences of the gratings 311- 313 (due to pattern density differences) may result in unwanted noise that could negatively affect the overlay measurement accuracy.Referring again to FIG. 5, in particular, the present invention places the components 210-211 and 220-221 of overlay mark 200A in a novel configuration to eliminate or minimize the effects of this noise (caused by differences in pattern density). For example, since the regions 240 have lower pattern densities than the regions 250, the overlay mark 200A is arranged such that the components 210- 211 each have a boundary (e.g., the left boundary) disposed in the regions 240, where these boundaries are aligned with one another. In other words, components 210- 211 are respectively disposed in the "upper left" and "lower left" corners of overlay mark 200A in FIG. 5, and components 220- 221 are respectively disposed in the "upper right" and "lower right" corners of overlay mark 200A in FIG. 5. It should be noted that components 210-211 each have gratings oriented to extend in the Y direction at known biases +d and -d in the X direction, respectively, while components 220-221 each have gratings oriented to extend in the X direction at known biases +d and -d in the Y direction.The configuration of components 210- 211 and 220- 221 shown in FIG. 5 minimizes the noise discussed above. Because components 210- 211 each have gratings (e.g., the leftmost gratings) in region 240 having the lower pattern density, components 210- 211 each have gratings in similar positions therein having distorted cross-sectional profiles (as compared to the gratings in the remaining components 210- 211). Thus, the components 210- 211 continue to have cross-sectional profiles similar to each other because they each have one or more gratings distorted due to being disposed in a region of low pattern density. As discussed above, the X-direction overlay may be calculated using the components 210- 211 of the overlay mark 200A. In this case, the noise generated as a result of the distorted gratings in the low pattern density region 240 may be cancelled because the components 210 and 211 respectively have the distorted gratings in the same or similar positions therein. Therefore, the overlay mark 200A can achieve better overlay measurement accuracy than conventional overlay marks.FIGS. 8-10 show top views of other embodiments of overlay marks, illustrated as overlay marks 200B, 200C, and 200D, respectively, on a wafer. These embodiments of overlay marks 200B, 200C, and 200D are similar to the embodiment of overlay mark 200A shown in FIG. 5 in some aspects. Therefore, for purposes of consistency and clarity, similar elements are identified the same in Figures 5 and 8-10. For example, overlay marks 200A, 200B, 200C, and 200D each include components 210-211 having gratings that each extend in the Y direction, but with +d and -d biases in the X direction, respectively. Overlay marks 200A, 200B, 200C, and 200D also each include components 220-221 having gratings that each extend in the X direction, but with +d and -d biases in the Y direction, respectively. In addition, reference numerals 240 are also used to indicate regions with a low pattern density (e.g., as compared to regions 250), and reference numerals 250 are also used to indicate regions with a high pattern density (e.g., as compared to regions 240).In the embodiment illustrated in FIG. 8, component 221 is implemented in the "upper left" corner of overlay mark 200B, component 220 is implemented in the "lower left" corner of overlay mark 200B, component 211 is implemented in the "upper right" corner of overlay mark 200B, and component 210 is implemented in the "lower right" corner of overlay mark 200B. Thus, components 210- 211 are oriented in the Y direction and components 220- 221 are oriented in the Y direction.Although the positions of the components 210- 211 and 220- 221 are different from the overlay mark 200A, both the overlay marks 200A and 200B implement two components adjacent to each other in the Y direction (such as components 210- 211 adjacent to each other or components 220- 221 adjacent to each other), where adjacent components each have gratings extending in the same direction, whether it is the X direction (e.g., components 220- 221) or the Y direction (e.g., components 210- 211).In the embodiment illustrated in FIG. 9, component 211 is implemented in the "upper left" corner of overlay mark 200C, component 221 is implemented in the "lower left" corner of overlay mark 200C, component 210 is implemented in the "upper right" corner of overlay mark 200C, and component 220 is implemented in the "lower right" corner of overlay mark 200C. Thus, components 210- 211 are oriented in the X direction and components 220- 221 are oriented in the X direction.Also different from the overlay marks 200A and 200B are the positions of the low pattern density regions 240 and the high pattern density regions 250 of the overlay mark 200C. As shown in FIG. 9, the uppermost (in the Y direction) boundaries of the components 210- 211 are located in the low pattern density regions 240, and the lowermost (in the Y direction) boundaries of the components 210- 211-which are common boundaries with the components 221- 220, respectively-are located in the pattern density region 250 which does not have a low pattern density. For example, the regions 240 may be at or near an edge of an IC chip or at or near an edge of a test line. Due to the particular configuration illustrated in FIG. 9, the noise introduced by the low pattern density regions 240 affects the components 210- 211 in a similar manner, and therefore, the noise can be cancelled when performing the overlay calculations.In the embodiment illustrated in FIG. 10, component 221 is implemented in the "upper left" corner of overlay mark 200D, component 211 is implemented in the "lower left" corner of overlay mark 200D, component 220 is implemented in the "upper right" corner of overlay mark 200D, and component 210 is implemented in the "lower right" corner of overlay mark 200D. Thus, components 210- 211 are oriented in the X direction and components 220- 221 are oriented in the X direction.The positions of the regions 240- 250 are similar to those of FIG. 9, note that each of the overlay marks 200C and 200D implement two components adjacent to each other in the X direction (such as components 210- 211 adjacent to each other or components 220- 221 adjacent to each other), where adjacent components each have gratings extending in the same direction, whether it is the X direction (e.g., components 220- 221) or the Y direction (e.g., components 210- 211).It is understood that additional embodiments of the overlay mark are also possible. For example, in an alternative embodiment, the overlay mark may be arranged similar to overlay mark 200A, but with interchanged positions of components 220 and 221. As another example, in an alternative embodiment, the overlay mark may be arranged similar to overlay mark 200A, but with interchanged positions of components 210 and 211. Regardless of the particular embodiment, the overlay mark of the present invention can achieve better overlay measurement performance because the arrangement discussed above enables the smoke caused by the pattern density differences to be canceled or substantially reduced.Referring to FIG. 11, multiple overlay marks 400 may be arranged as an M x N array around a main structure 405 on a wafer according to various aspects of the present invention. M represents the number of rows in the array, and N represents the number of columns in the array. In some embodiments, a main structure 405 may be a portion of an IC that includes structures corresponding to active regions, sources / drains, interconnects, etc. The main structure 405 may include regions with a poor structure density uniformity, for example regions with much higher structure densities than other regions. The main structure 405 may also include regions of poor CD uniformity, for example regions with larger CD differences.The M x N array of overlay marks 400 may include multiple overlay marks, such as the eight overlay marks 400A- 400H depicted in FIG. 11. At least some of these overlay marks 400A- 400H may include multiple components similar to components 410- 411 and / or 420- 421 discussed above. For example, overlay marks 400A, 400B, 400C, and 400D are disposed on 4 different sides (e.g., top, bottom, left, and right) of main structure 405. Overlay marks 400A- 400D each include a component 410 similar to component 210 discussed above, a component 411 similar to component 211 discussed above, a component 420 similar to component 220 discussed above, and a component 421 similar to component 221 discussed above. For example, each of these components 410- 411 and 420- 421 may include an upper layer and a lower layer, with a bias voltage of +d or a bias voltage of -d between the upper and lower layers. In some embodiments, the top layer may again comprise a patterned resist layer, while the bottom layer may comprise a patterned material layer on a substrate. In other embodiments, the top layer and the bottom layer may include different patterned layers on a substrate. Similar to components 210- 211 and 220- 221, components 410- 411 are configured to measure the X-direction overlap, and components 420- 421 are configured to measure the Y-direction overlap.For reasons similar to those discussed above with reference to FIGS. 5 and 8-10, the components in overlay marks 400A-400B (each facing the X-direction boundaries of main structure 405) are configured such that the two components 420-421 (for measuring Y-direction overlay) are disposed adjacent to each other in the X-direction and the two components 410-411 (for measuring X-direction overlay) are disposed adjacent to each other in the X-direction. As discussed above, this type of arrangement ensures that any noise that may occur at the horizontal edges of overlay marks 400A- 400B (the edges facing the "upper" and "lower" boundaries of main structure 405) is reduced or cancelled when the overlay is measured using asymmetry information with respect to diffracted light intensity.Also for reasons similar to those discussed above with reference to FIGS. 5 and 8-10, the components in overlay marks 400C-400D (each facing the Y-direction boundaries of main structure 405) are configured such that the two components 420-421 (for measuring Y-direction overlay) are disposed adjacent to each other in the Y-direction and the two components 410-411 (for measuring X-direction overlay) are disposed adjacent to each other in the Y-direction. Again, this type of arrangement ensures that any noise that may arise at the vertical edges of overlay marks 400C- 400D (the edges facing the "left" and "right" boundaries of main structure 405) is reduced or cancelled when the overlay is measured using asymmetry information with respect to diffracted light intensity.While overlay marks 400A- 400D are each disposed adjacent a corresponding boundary of main structure 405, overlay marks 400E- 400H are each disposed diagonally adjacent a corresponding corner of main structure 405. For example, overlay mark 400E is arranged diagonally adjacent to the "upper left" corner of main structure 405, overlay mark 400F is arranged diagonally adjacent to the "upper right" corner of main structure 405, overlay mark 400G is arranged diagonally adjacent to the "lower left" corner of main structure 405, and overlay mark 400H is arranged diagonally adjacent to the "lower right" corner of main structure 405.Due to the diagonal positions of the overlay marks 400A to 400D, their components are designed differently. For example, overlay marks 400E- 400H also include components 410- 411 similar to components 210- 211 discussed above. However, the components 410- 411 are arranged diagonally with respect to each other, and are not arranged immediately adjacent to each other in the X direction or the Y direction. Additionally, overlay marks 400E- 400H each include components 430A- 430B, as well as components 470A- 470B.The components 430A- 430B are configured to measure Y-direction superposition and therefore each include gratings extending in the X-direction. In this manner, components 430A- 430B collectively serve a function similar to component 420 (or component 421). In other words, components 430A- 430B are similar to component 420 divided into two sections, with the divided left section being similar to component 430A and the divided right section being similar to component 430B. However, unlike component 420 - where there is a constant bias voltage d (whether plus or minus) in the Y direction between its top and bottom layers - the gratings in components 470A and 470B have different bias voltages. In some embodiments, the top layer may include a patterned resist layer, while the bottom layer 100B may include a patterned material layer on a substrate. In other embodiments, the top layer and the bottom layer may include different patterned layers on a substrate.For example, with reference to FIG. 12, top and bottom layer views of components 430A- 430B are separately illustrated according to embodiments of the present invention. The components 430A and 430B have a common boundary 440 that extends in the Y direction. This boundary 440 may be imaginary and not visible in the actual overlay mark. In other words, boundary 400 merely indicates what the boundary line between components 430A and 430B would be.In the illustrated embodiment, the horizontally oriented gratings in component 430A are biased with +d, which means that the gratings are offset between the top layer and the bottom layer of component 430A by a distance +d in the Y direction. Meanwhile, the horizontally oriented gratings in component 430B are pre-strained with -d, which means that the gratings are offset between the upper layer and the lower layer of component 430B by a distance -d in the Y direction. In the illustrated embodiment, the different bias voltages between components 430A and 430B are represented as a dislocation of the gratings in the upper layer, but the gratings in the lower layer of components 430A and 430B remain un-displaced. However, this is merely an example. In other embodiments, the gratings in the top layer may be unaligned while the gratings in the bottom layer are offset by +d or -d for components 430A and 430B, respectively.Referring again to FIG. 11, components 470A- 470B are also configured to measure Y-direction superposition, and therefore each include gratings extending in the X-direction. In this manner, components 470A- 470B collectively serve a function similar to component 420 (or component 421). In other words, components 470A- 470B are similar to component 420 that is diagonally divided into two portions, with one diagonal portion (shaped as a right triangle) being similar to component 470A and the opposite diagonal portion (shaped as another right triangle) being similar to component 470B. However, unlike component 420 - where there is a constant bias voltage d (whether plus or minus) in the Y direction between its top and bottom layers - the gratings in components 470A and 470B have different bias voltages.For example, with reference to FIG. 13, top and bottom layer views of the components 470A- 470B are separately illustrated according to embodiments of the present invention. The components 470A and 470B have a common boundary 480 that extends diagonally in both the X direction and the Y direction. This boundary 480 may be imaginary and not visible in the actual overlay mark. In other words, the boundary 480 identifies only what the boundary line between the components 470A and 470B would be.It should be noted that the gratings disposed in each of the components 470A- 470B have unequal lengths in the X direction because the components 470A- 470B are shaped like triangles. In the illustrated embodiment, the horizontally oriented gratings in component 470A are biased with +d, which means that the gratings are offset between the top layer and the bottom layer of component 470A by a distance +d in the Y direction. Meanwhile, the horizontally oriented gratings in component 470B are pre-strained with -d, which means that the gratings are offset between the top layer and the bottom layer of component 470B by a distance -d in the Y direction. In the illustrated embodiment, the different bias voltages between components 470A and 470B are represented as a dislocation of the gratings in the upper layer, but the gratings in the lower layer of components 470A and 470B remain un-displaced. However, this is merely an example. In other embodiments, the gratings in the top layer may be unaligned while the gratings in the bottom layer are each offset by +d or -d for components 470A and 470B, respectively. It will also be appreciated that although the components 470A and 470B are implemented in each of the overlay marks 400E, 400F, 400G, and 400G, they may be rotated in different directions in different overlay marks.For reasons similar to those discussed above, the configuration of components 430A- 430B and 470A- 470B also suppresses noise caused by structure density problems of main structure 405. For example, the configuration of components 430A- 430B and 470A- 470B allows the gratings for measuring superposition to be arranged in the same direction at similar distances from the main structure 405. Therefore, even if the problems of pattern density (or CD uniformity) of the main pattern 405 cause noise that may occur at the boundaries of the overlay marks 400E to 400H, the noise is substantially reduced.In the embodiment shown in Figs. 11 to 13. The split components (e.g., components 430A- 430B and 470A- 470B) in the overlay marks have gratings that extend in the X direction so that it is configured to measure the Y direction overlay. However, this is merely an example. It will also be appreciated that in some other embodiments, the split components may include gratings that extend in the Y direction so that they are configured to measure the X-direction superposition. It should also be understood that the configuration of the M x N array of overlay marks 400 herein is not limited to the eight overlay marks 400A- 400H discussed above. In other embodiments, additional overlay marks similar to those discussed above may be implemented in each row and / or column of the array.FIG. 14 is a plan view of a overlay mark 500 according to another embodiment of the present invention. Overlay mark 500 may be used not only to measure an overlay, but also focus information, for example a focus that results in an optimal critical dimension (CD) for semiconductor features on a wafer, as discussed in more detail below.As shown in FIG. 14, overlay mark 500 may include components 510- 511 used to measure an X-direction overlay, similar to components 210- 211 discussed above. Overlay mark 500 may also include components 520- 521 used to measure Y-direction overlay, similar to components 220- 221 discussed above. Component 510 is located at the "upper left" corner of overlay mark 500, component 511 is located at the "lower left" corner of overlay mark 500, component 520 is located at the "upper right" corner of overlay mark 500, and component 521 is located at the "lower right" corner of overlay mark 500. Thus, component 510 is disposed directly adjacent to components 520-521 (and the same applies to component 511), and components 510 and 511 are also disposed diagonally adjacent to each other. However, it should be understood that the arrangement of components 510-511 and 520-521 shown in FIG. 14 is merely an example and that they may be arranged differently in other embodiments, for example similar to the embodiments shown in FIGS. 5 and 8-10.It will also be appreciated that components 510-511 and 520-521 may each have a built-in bias voltage with respect to their top layer and bottom layer, similar to the overlay marks discussed above with reference to FIGS. 5 and 8-10. For example, component 510 may have a +d bias between its upper and lower layers in the X direction, component 511 may have a -d bias between its upper and lower layers in the X direction, component 520 may have a -d bias between its upper and lower layers in the Y direction, and component 521 may have a +d bias between its upper and lower layers in the Y direction. In some embodiments, the top layer may again comprise a patterned resist layer, while the bottom layer may comprise a patterned material layer on a substrate. In other embodiments, the top layer and the bottom layer may include different patterned layers on a substrate.As shown in FIG. 14, each of the components 510- 511 and 520- 521 is divided into an area FR and an area FL, where the areas FR and FL each include one or more sub-structures (discussed in more detail below). In the illustrated embodiment, the FR regions in components 510 and 511 are oriented perpendicular to the FR regions in components 520-521. Similarly, the FL regions in components 510 and 511 are oriented perpendicular to the FL regions in components 520-521. The details of the area FR and the area FL are illustrated as examples in FIGS. 15A-15B. Specifically, FIG. 15A shows the partial plan views of an upper layer and a lower layer of the region FR (e.g., the region FR of the component 520), and FIG. 15B shows the partial plan views of an upper layer and a lower layer of the region FL (e.g., the region FL of the component 520).Referring to FIG. 15A, the upper layer of the region FR includes a plurality of elongated gratings 530 and a plurality of sub-structures 540. The elongated gratings may extend in the X direction or the Y direction depending on the component of the overlay mark 500 in which they are disposed. In the illustrated embodiment, the gratings 530 disposed in the components 510-511 (for measuring X-direction superposition) extend in the Y-direction, and the gratings 530 disposed in the components 520-521 (for measuring Y-direction superposition) extend in the X-direction. For example, the gratings 530 in the FR region of the component 510 are perpendicular to the gratings 530 in the FR region of the component 520.Sub-structures 540 include structures that are substantially smaller in size than gratings 530. In some embodiments, the size difference between each of the gratings 530 and each of the sub-structures 540 is at least an order of magnitude (e.g., x 10). The sub-structures 540 are added to achieve focus information, as discussed in more detail below. In the embodiment illustrated in FIG. 15A, sub-structures 540 are divided into multiple sub-groups, with sub-structures 540 in each sub-group being arranged as a "column" arranged to the right (in the X direction) of a corresponding one of the vertically oriented grids 530. It will be appreciated that for the FR range located in the components 520 or 521, the gratings 530 would be rotated 90 degrees so that they would extend in the X direction and the sub-structures 540 would be divided into sub-groups, in which case each sub-group is arranged as a "row" located "above" or "below" (in the Y direction) of a corresponding one of the horizontally oriented gratings 530.With further reference to Figure 15A, the lower layer of the region FR comprises a plurality of elongated gratings 550. The gratings 550 extend in the same direction that the gratings 530 extend (e.g., the Y direction in the components 510- 511 and the X direction in the components 520- 521). However, no sub-structures are present in the lower layer in this embodiment. However, it should be appreciated that in some other embodiments, the sub-structures 540 may be disposed in the lower layer instead of the upper layer.Referring to FIG. 15B, the area FL has many similarities with the area FR. For example, both regions FR and FL include an upper layer and a lower layer. A plurality of elongated gratings 530 are implemented in the upper layer, and a plurality of elongated gratings 550 are implemented in the lower layer. Also, for both regions FR and FL, one of the layers (here e.g. the top layer) comprises multiple sub-structures 540, but the other layer (here e.g. the bottom layer) does not. Unlike in the area FR, however, the sub-structures 540 are arranged to the left (in the X direction) of the gratings 530. If the region FR were implemented in the components 520- 521 (e.g., for measuring the Y-direction superposition), the sub-structures 540 would be arranged "below" or "above" (in the Y-direction) of the gratings 530. In this way, the regions FR and FL are symmetrical to each other.The presence of the sub-structures 540 in the regions FR or FL affects the diffraction intensity signal, thus manifesting a "minor lobe.". This is illustrated in FIG. 16, which includes a graph 570 and a graph 571 that each correspond to a overlay mark with the sub-structures (such as sub-structures 540) and an overlay mark without the sub-structures, respectively. More specifically, graph 570 and graph 571 each include an X-axis representing a displacement of position, which may include superposition and built-in bias between an upper layer and a lower layer. Graph 570 and graph 571 also each include a Y-axis representing a diffraction light intensity that may correspond to the asymmetry between the +1-order diffracted light and the -1-order diffracted light. For example, the asymmetry may include the asymmetry information discussed above (labeled As=I +1- I -1 ).Thus, graphs 570 and 571 show how the diffraction light intensity (e.g., As=I +1- I -1) varies as a function of positional offset (including superposition) between an upper layer and a lower layer of a respective superposition mark with the sub-structures and a superposition mark without the sub-structures. However, the presence of sub-structures (such as sub-structures 540 in FIGS. 15A-15B ) results in minor lobes in graph 570, for example minor lobes 580 and 581. The minor lobes 580 and 581 manifest themselves as a "bulge" or "protrusion" where a smooth line should otherwise be present in the graph 570. In other words, graph 570 would be substantially similar to graph 571 if sub-structures 540 were not implemented.In some embodiments, the minor lobes 580 may be caused by the sub-structures 540 from the region FR, and the minor lobes 581 may be caused by the sub-structures 540 from the region FL. The sub-lobes 580- 581 are associated with focus information (focus of exposure in a lithographic process) and may therefore be used to determine what the optimal focus is to achieve a good critical dimension. Since the minor lobes 580-581 are symmetrical to each other, they may be canceled for purposes of overlay determination. In this manner, the overlay mark (such as overlay mark 500) of the present invention can be used to provide both overlay and focus information.FIGS. 17A-17B show partial plan views of portions of a overlay mark having sub-structures according to embodiments of the present invention. Various parameters that may define the sub-structures (e.g., the number and position of the sub-structures) are also visually shown in FIGS. 17A-17B. In FIG. 17A, a plurality of rectangular sub-structures 540 are implemented adjacent to the gratings 530. The number of sub-structures 540 is denoted by a parameter N, where N>=1.The sub-structures may also be implemented around the gratings 530 in more than one direction. For example, as shown in FIG. 17B, one or more sub-structures 540A may be disposed on the "left" side of the grid 530. The parameter Nv>=l indicates that 1 or more of the sub-structures 540A are present in this area. The sub-structures may be arranged as a single column / row or an array having multiple columns and / or multiple rows. The parameter I v represents a distance between the grid 530 and the next one of the sub-structures 540A. The parameter P v represents a pitch (e.g., a sum of a dimension of one of the sub-structures and a distance between two of the adjacent sub-structures 540A) of the sub-structures 540A in the Y-direction. The parameter P vh represents a different pitch of the sub-structures in the X direction, for example, when there are two or more columns (columns extending in the Y direction) of the sub-structures 540A. The parameter P v is measured in the Y direction, while the parameter P vh is measured in the X direction.Another group of sub-structures 540B is arranged "directly above" the grid 530 in the Y-direction. The parameter Nhh>0 means that the number of sub-structures 540B in the "area above" the grid 530 may be 1 or more (when Nhh>0) or none at all (when Nhh=0). The parameter I hh represents a distance between the grid 530 and the next one of the sub-structures 540B. The parameter P hh represents a pitch of the sub-structures 540B in the Y direction.Another group of sub-structures 540C is disposed "directly under" the grid 530 in the Y-direction. The parameter Nhl>=0 means that the number of sub-structures 540C in the "area under" the grid 530 may be 1 or more (when Nhl>o) or none at all (when Nhh=0). The parameter I hl represents a distance between the grid 530 and the next one of the sub-structures 540C. The parameter P hl represents a pitch of the sub-structures 540C in the Y direction.Another group of sub-structures 540D is arranged "diagonally above" the grid 530 in the X direction and in the Y direction. The parameter Nch>=0 means that the number of sub-structures 540D in the "region diagonally above" the grid 530 may be 1 or more (when Nch>0) or none at all (when Nch=0). The parameter I ch represents a diagonal distance between the grid 530 and the next of the sub-structures 540D in the X and Y directions. The parameter P ch represents a diagonal pitch of the sub-structures 540D in the X and Y directions. An angle θ ch represents the diagonal angle of the sub-structures 540D.Another group of sub-structures 540E is arranged "diagonally below" the grid 530 in the X direction and in the Y direction. The parameter Ncl>=o means that the number of sub-structures 540E in the "region diagonally below" the grid 530 may be 1 or more (when Ncl>o) or none at all (when Ncl=o). The parameter I cl represents a diagonal distance between the grid 530 and the next of the sub-structures 540E in the X and Y directions. The parameter P cl represents a diagonal pitch of the sub-structures 540E in the X and Y directions. An angle θ cl represents the diagonal angle of the sub-structures 540E.The configuration of sub-structures 540A- 540E may be used to fine tune a lithography process window, for example, focus or exposure dose. The configuration of sub-structures 540A- 540E may also be used to adjust the minor lobe effect discussed above and modify a Bossing curve discussed below.Although the embodiments discussed above showed the sub-structures 540 to have somewhat rectangular top views, other designs are possible for the sub-structures. For example, with reference to Figures 18A-18E, the plan views of several embodiments of the sub-structures are illustrated.In the embodiment illustrated in FIG. 18A, sub-structures 540F are implemented adjacent to gratings 530. In this embodiment, sub-structures 540F comprise five polygons. Each polygon has three or more pages (i.e., n>=3, where n is the page of the polygon). The number of sides of the polygon can be designed to adjust the minor lobe effect produced by the grating diffraction. With different polygons, the overlay mark produces a slightly different depth of focus (DOF).In the embodiment illustrated in FIG. 18B, sub-structures 540G are implemented adjacent to gratings 530. In this embodiment, sub-structures 540G include four circles or circular structures. The sub-structures 540G may also be referred to as point symmetry sub-structures. The number, size, and / or position of the circular sub-structures 540G may be designed to easily adjust the minor lobe effect.In the embodiment illustrated in FIG. 18C, sub-structures 540H are implemented adjacent to gratings 530. In this embodiment, sub-structures 540H include five ellipsoidal structures. The sub-structures 540H may also be referred to as axis symmetry sub-structures. The number, size, and / or position of ellipsoidal sub-structures 540H may also be designed to easily adjust the minor lobe effect.In the embodiment illustrated in FIG. 18D, sub-structures 540I are implemented adjacent to gratings 530. In this embodiment, the sub-structures 540I are shaped as "lines" having plan view shapes similar to the gratings 530. One or more of the "linear" sub-structures 540I may be implemented on either side of the grid 530. Parameters such as horizontal / vertical dimensions of each substructure 540I, a distance between the grid 530 and the next substructure 540I, and / or a pitch of the sub-structures 540I may be designed to adjust the minor lobe effect.In the embodiment illustrated in FIG. 18E, combinations of different types of sub-structures may be implemented adjacent to the gratings 530. For example, the line-shaped sub-structures 540I may be implemented adjacent to the grids 530, and the rectangular sub-structures 540A may be implemented adjacent to the line-shaped sub-structures 530I. In other embodiments, sub-structures 540A, 540F, 540G, 540H, 540I may be mixed into different combinations and sub-combinations. In addition, any of the shapes of the sub-structures discussed herein may be used to implement sub-structures 540B- E disposed on different directions of the grid 530, as shown in FIG. 17B.It is also understood that the shapes and profiles of the gratings and sub-structures in the present invention discussed above may represent the design on a photomask. However, after these structures have been patterned on a wafer, they may lose their similarity to their original designs due to optical effects. For example, structures having rectangular or polygonal original designs may have more rounded or at least non-straight edges after being patterned on a wafer. Nevertheless, they may still cause the sub-lobes discussed above, which allow the overlay marks to be used here to determine both the overlay and focus.Referring again to FIG. 14, components 510- 511 are each used to measure the X-direction overlap, and components 520- 521 are each used to measure the Y-direction overlap. As such, the regions FR and FL in the components 510- 511 are disposed adjacent to each other in the Y direction, and the regions FR and FL in the components 520- 521 are disposed adjacent to each other in the X direction. In other words, for components 510- 511, regions FR and FL have a common boundary that extends in the X direction, while for components 520- 521, regions FR and FL have a common boundary that extends in the Y direction.The area FR or area FL in each of the components 510- 511 or 520- 521 may be configured to accommodate the sub-structures discussed above in FIGS. 15A-15B, 17A- 17B, or 18A- 18B. Because the x-direction overlay measurement does not interfere with the y-direction overlay measurement (and vice versa), the regions FR and FL in the components 510- 511 may have different sub-structures (or have different sub-structure designs) than the regions FR and FL in the components 520- 521, for example, in terms of the shape, size, number, and / or position of the sub-structures.Because overlay mark 500 includes regions FR and FL for each of components 510-511 and 520-521, the overlay mark allows more overlay measurements to be taken. For example, using the overlay calculation equations discussed above with reference to FIG. 4, one overlay may be measured for region FR, which may be expressed herein as OVL-FR, while another overlay may be measured for region FL, which may be expressed herein as OVL-FL. The OVL-FR and OVL-FL correspond to superposition in the same direction. For example, OVL-FR and OVL-FL could be an overlay in X-direction overlay when the regions FR and FL are implemented in the components 510-511 of overlay mark 500, or OVL-FR and OVL-FL could be an overlay in Y-direction overlay when the regions FR and FL are implemented in the components 520-521 of overlay mark 500.Overlay mark 500 may improve overlay measurement accuracy because each component 510- 511 and 520- 521 of overlay mark 500 may achieve two overlay measurements (for a total of 8 overlay measurements for each overlay mark 500), while overlay marks without regions FR and FL typically result in one overlay measurement per component (for a total of 4 overlay measurements for each overlay mark). In some embodiments, overlay data OVL-FR and OVL-FL may be added for each of components 510- 511 and 520- 521 and then divided by 2 to achieve average overlay. In other words, an average overlay measurement can be calculated as OVL = (OVL-FR + OVL-FL) / 2.Due to the implementation of the sub-structures causing the minor lobes 580- 581 shown in FIG. 16, focus is also related to the superposition in accordance with various aspects of the present invention. For example, the focus may be related to a difference between the overlay obtained using region FR (e.g., OVL-FR) and the overlay obtained using region FL (e.g., OVL-FL). Mathematically, this can be expressed as follows:In some embodiments, the correlation relationship between focus and superposition may be approximated by a linear equation, such as Focus=a*OVL+b, where a and b are constants. In other embodiments, the correlation relationship between focus and superposition may be expressed as a higher order equation (such as one comprising a polynomial). Regardless of the equation used to approximate the correlation relationship between focus and overlay, it should be understood that the constants (such as a and b) in the equation may be solved after sufficient overlay samples have been collected. With this equation, the focus can be determined after overlay data has been measured.FIG. 19 shows a critical dimension (CD) versus focus graph 600. For example, the X-axis of the graph 600 represents focus (e.g., focus length of an exposure process) and the Y-axis of the graph 600 represents the measured CD. More specifically, one or more test wafers may be used to generate the graph 600. Multiple overlay marks similar to overlay marks 500 may be implemented on the one or more test wafers. The focus (and / or exposure dose) used to make these overlay marks may vary somewhat from one another. As discussed above, the focus is related to the overlay. Therefore, the focus data associated with these different overlay marks on the wafer may be determined after the overlay data is obtained (e.g., using an asymmetry light diffraction intensity, as discussed above). The CD is measured corresponding to individual scan data of focus.Note that graph 600 includes a curve 610 and a curve 620. These curves are referred to as "Bossung curves". Curve 610 corresponds to measurements obtained using components 510 and / or 511, while curve 620 corresponds to measurements obtained using components 520 and / or 521. The curves 610 and 620 are offset from each other with respect to focus. This offset may be intentionally implemented by designing the sub-structures on the components 510- 511 to be different from the structures on the components 520- 521, e.g., the size of the structures or the density of the structures. As a result of each individual design / arrangement of sub-structures corresponding to a single curve, the differences between component 510 / 511 and component 520 / 521 (e.g., with respect to their sub-structures) result in the separation of curves 610 and 620 in FIG. 19.As shown in FIG. 19, curves 610 and 620 may intersect at an intersection 640. According to various aspects of the present invention, the focus corresponding to the intersection point 640 may represent an optimal focus. One reason that the intersection point 640 represents the optimal focus is that the intersection point 640 represents a focus that would simultaneously optimize the CD for both the curve 610 and the curve 620. Once again, curves 610 and 620 are obtained using components 510 and 511 that measure the X-direction overlay and the Y-direction overlay, respectively. Thus, optimizing the CD corresponding to both curves 610 and 620 represents the best CD uniformity performance for features on the wafer in both the X and Y directions. An optimal focus range 650 may also be achieved by expanding the optimal focus from the intersection point 640 in each direction along the X-axis in FIG. 19 until the focus values corresponding to the largest CD values in the curves 610 and 620, respectively, have been reached. This optimal focus region 650 may be used in future semiconductor fabrication to achieve optimized CD performance (e.g., in terms of CD uniformity).FIGS. 20A-20B show a combination mark 700 and a compound mark 701, respectively, in accordance with some of the present invention. The combination mark 700 and the composite mark 701 represent various embodiments of a superposition mark. They may each be similar to overlay mark 500 discussed above with reference to FIG. 14. However, the combination mark 700 and the compound mark 701 may each refer to 3 or more layers. For example, combination mark 700 and composite mark 701 may each include four components A, A' and B, B' which may be similar to components 510-511 and 520-521 discussed above. The difference between components A and A' is that component A corresponds to a +d offset / bias between its upper and lower layers, while component A' corresponds to a -d offset / bias between its upper and lower layers. Similarly, the difference between components B and B' is that component B corresponds to a +d offset / bias between its upper and lower layers, while component B' corresponds to a -d offset / bias between its upper and lower layers.For the combination mark 700, components A and A' are each configured to measure the overlap between an MD (e.g., metal zero) layer and a polysilicon layer. Since the X-direction orientation is important between the MD layer and the polysilicon layer, but their Y-direction orientation is not important, components A and A' are each designed to measure the X-direction overlap, but not in the Y-direction. Meanwhile, the components B and B' are designed to measure the overlap between the MD layer and an OD layer (active area). Since the Y-direction orientation is important between the MD layer and the OD in the active region, but their X-direction orientation is not important, components B and B' are each designed to measure the overlap in the Y-direction but not in the X-direction.The compound mark 701 has many similarities to the combination mark 700, but with a few small differences. One difference is that components A and A' in the compound mark 701 are configured to measure the overlap between a current layer and a pre-layer (e.g., below the current layer), and components B and B' in the compound mark 701 are configured to measure the overlap between a current layer and a post-layer (e.g., above the current layer). The current layer, the pre-layer, and / or the post-layer discussed herein are not limited to the metal zero layer, the polysilicon layer, or the OD layer in the active region, and may be any layer in semiconductor manufacturing.It is also understood that components A, A', B, and B' of the compound mark 701 are not limited to measuring the superposition in only one direction. For example, two different embodiments of the fiducial 701 may both be implemented on a single wafer. In a first embodiment of the compound mark 701, its components A and A' are each designed to measure the X-direction superposition, while its components B and B' are each designed to measure the Y-direction superposition. In a second embodiment of the compound mark 701, its components A and A' are each designed to measure the Y-direction superposition, while its components B and B' are each designed to measure the X-direction superposition. As such, multiple compound marks 701 may be used to measure both the X-direction overlay and the Y-direction overlay between a current layer, a pre-layer below the current layer, and a post-layer above the current layer.In addition to determining the focus information, the overlay marks may also be used herein to determine the CD information in accordance with various aspects of the present invention. For example, referring to Figs. 21A to 21C, a overlay mark 800 is shown. Overlay mark 800 is similar to overlay mark 500 discussed above with reference to FIG. 14, as overlay mark 800 also includes four components 810- 811 and 820- 821 that are similar to components 510- 511 and 520- 521 of overlay mark 500. Each of the components 810- 811 and 820.821 also includes an FR area and an FL area, which are again similar to the FR and FL areas of overlay mark 500 discussed above.In the embodiment illustrated here, FIG. 21A shows the top view of the configuration of overlay mark 800 (e.g., with respect to its components 810- 811 and 820- 821, as well as the FR and FL ranges therein), FIG. 21B shows the top view of one of the layers of component 810 (including its gratings 830 and sub-structures 840), and FIG. 21C shows the top view of one of the layers of component 820 (including its gratings 831 and sub-structures 840) in component 820. As discussed above, each of the components 810 and 820 may include an upper layer and a lower layer, with a bias / offset of +d or -d between the upper and lower layers. The sub-structures 840 may be located in one of the layers, but not necessarily in the other layer. In the embodiment illustrated in FIGS. 21B and 21C, the top layers for components 810 and 820 are illustrated, and sub-structures 540 are disposed in the top layer. However, it should be appreciated that sub-structures 540 may be implemented in the lower layers in another embodiment.As shown in FIG. 21A, component 810 is oriented perpendicularly with respect to component 820. This is illustrated in more detail in FIGS. 21B and 21C. For example, as shown in FIG. 21B corresponding to component 810, gratings 830 each extend in the Y direction and sub-structures 840 are arranged in different columns that also each extend in the Y direction. As shown in FIG. 21C, which corresponds to component 820, gratings 831 each extend in the X direction; and sub-structures 840 are arranged in different rows, which also each extend in the Y direction.As discussed above, to best extract the focus information from the overlay mark 800, the sub-structures 840 in FIG. 21B may be configured differently than the sub-structures 840 in FIG. 21C, for example, in terms of their number, shapes, sizes, etc. In addition, since the overlay mark 800 is used for extracting CD information, the gratings 830 in FIG. 21B are also designed differently from the gratings 831 in FIG. 21C. For example, gratings 830 in FIG. 21B each have a width 835 measured in the X direction, and gratings 831 in FIG. 21C each have a width 836 measured in the Y direction, where width 835 is not equal to width 836. In some embodiments, width 835 may be substantially less than width 836, for example, in some embodiments at least 25% less, or in other embodiments at least 50% less. In other words, the gratings 831 in component 820 are substantially "richer" than the gratings 830 in component 810. The difference of the grating widths 835- 836 between the gratings 830 and 831 means that the components 810 and 820 of the overlay mark 800 have different critical dimensions (CDs). In other words, the same overlay mark 800 may be designed such that different CDs are present.Although not specifically shown for simplicity, it should be understood that the discussion above may apply to components 811 and 821. In other words, component 811 may be substantially similar to component 810 except that its upper and lower layers are offset / biased in a different direction than component 810. Similarly, component 821 may be substantially similar to component 820 except that its upper and lower layers are offset / biased in a different direction than component 820. As such, component 821 may also have substantially "richer" meshes than component 811 (or component 810). Additionally, in some other embodiments, components 811 and 821 may also be configured such that their gratings have different widths than gratings 830 and 831 discussed above.The difference in grating sizes between the various components of overlay mark 800 allows extraction of the CD information. This is illustrated in FIG. 22, which shows a graph 910 and a graph 920. Graph 910 has an X axis representing critical dimension (CD) and a Y axis representing diffraction intensity (I). Graph 910 includes a curve 930 that shows a relationship between CD and diffraction intensity, i.e., as they each vary in relation to one another. Graph 920 has an X axis representing the critical dimension (CD) and a Y axis representing a derivative of the diffraction intensity to CD (dI / dDC). Graph 920 includes a curve 940 showing a relationship between the CD and dI / dCD, i.e., as they each vary in relation to each other. In other words, curve 940 may be a derivative of curve 930 or, in other words, curve 930 is an integral of curve 940. It should be understood that the curves 930 and 940 illustrated herein are for illustrative purposes only and that they are not necessarily 100% mathematically accurate, or necessarily reflect the true behavior of the underlying variables they represent.As discussed above, overlay mark 800 is configured to have different CDs (e.g., widths of gratings for the various components of overlay mark 800). The diffraction light intensity can be measured for each of the components of overlay mark 800 and this yields various points on curve 930. It is understood that exposure energy is directly related to diffraction light intensity. Therefore, as the exposure energy is varied, this may further change the relationship between the diffraction light intensity and CD, which may correspond to different points on the curve 930. This may be repeated for one or more overlay marks, similar to overlay mark 800, to collect multiple measurements. In some embodiments, curve 940 is first obtained by measuring information on CD and diffraction light intensity using an SEM tool (scanning electron microscope) or an overlay measurement tool, for example, and then curve 930 is derived by plotting an integral of curve 940.If curve 930 is available, CD predictions may be made. For example, curves 930 and 940 may be generated or derived using one or more overlay marks 800 on a test wafer. After curves 930 and 940 are available, the CDs of features on subsequently fabricated wafers can be predicted by measuring the diffraction light intensity using overlay marks on the subsequently fabricated wafers, for example. Since the relationship between the diffracted light intensity and the CD is now known (e.g., based on curve 930), the CD can be determined via measurement of the diffracted light intensity. Accordingly, the overlay marks discussed herein can be used not only to measure overlay (which is a major function of conventional overlay marks), but also to measure focus information as well as critical dimension (CD) information.FIG. 23 shows a flow diagram of a method 1000 for measuring focus using a overlay mark of the present invention. The overlay mark may be overlay marks 200A- 200D, 4004- 400F, 500, 700- 701, or 800 discussed above. The method 1000 comprises a step 1010 and a step 1020, in which a diffraction light intensity is measured, for example in a similar manner to that discussed above with reference to FIG. 3. In both steps 1010 and 1020, the diffracted light intensity for the +1-order diffracted light (e.g., I +1) and the -1-order diffracted light (e.g., I -1) is measured. However, in step 1010, the diffraction light intensity for a displacement of +d between the upper and lower layers (e.g., as discussed above with reference to FIG. 4B ) is measured, while in step 1020, the diffraction light intensity for a displacement of -d between the upper and lower layers (e.g., as discussed above with reference to FIG. 4A ) is measured. For example, step 1010 may be performed using the components of the overlay mark having a +d bias between their upper and lower layers, as in the case of components 210 or 221 of overlay mark 200A of FIG. 5, while step 1020 may be performed using the components of the overlay mark having a -d bias between their upper and lower layers, as in the case of components 220 or 211 of overlay mark 200A of FIG. 5.The method 1000 comprises steps 1030 and 1040, in which asymmetry information is achieved. Step 1030 is performed after step 1010, wherein the +1 order and -1 order of the diffraction light intensity (measured using the offset +d) are used to calculate the asymmetry in the case of an offset +d, which is expressed as As +d= I +1- I -1. Step 1040 is performed after step 1020, wherein the +1 order and -1 order of the diffraction light intensity (measured using the offset -d) are used to calculate the asymmetry in the case of an offset of -d, which is expressed as As -d= I +1- I -1.The method 1000 then proceeds to step 1050, in which a superposition is calculated based on the asymmetry information obtained in steps 1030 and 1040. In one embodiment, the overlay is calculated using the following equation, where OVLrepresents the calculated overlay, and drepresents the amount of offset or bias between the upper and lower layers of the overlay mark.The method 1000 then proceeds to step 1060, where the overlay is achieved for both the FR range and the FL range. As discussed above, overlay marks 500 or 800 each include multiple components, each component including an FR area and an FL area that is symmetric to the FR area (see, for example, FIGS. 15A-15B ). The overlay for the FR region may be measured according to steps 1010- 1050 discussed above, and then the same process is repeated for the FL region. The overlay corresponding to the FR region may be represented as OVL-F R in FIG. 23, and the overlay corresponding to the FL region may be represented as OVL-F L in FIG. 23. Thus, at the end of step 1060, two overlay measurements are obtained: one for the FR range and the other for the FL range.The method 1000 then proceeds to step 1070, in which the two overlay measurements OVL-F R and OVL-F L are averaged together to obtain a more accurate overlay. Step 1070 also extracts focus information from the two overlay measurements OVL-F R and OVL-F L. As discussed above with reference to FIG. 16, the focus is related to a difference between the FR range overlay and the FL range overlay, and can be mathematically expressed as:In this manner, the overlay marks of the present invention can be used not only to measure the overlay, but can also be used to extract focus information by performing steps 1010 to 1070 of FIG. 23.FIG. 24 is a flow diagram of a method 1500 of using a overlay mark in accordance with some embodiments of the present invention.The method 1500 comprises a step 1510 of measuring a diffraction light intensity using a superposition mark. The overlay mark comprises an upper layer and a lower layer offset with respect to the upper layer.The method 1500 comprises a step 1520 of determining, based on the measured diffraction light intensity, asymmetry information associated with the overlay mark.The method 1500 comprises a step 1530 of calculating, based on the determined asymmetry information, a overlay associated with the overlay mark.The method 1500 includes a step 1540 of performing at least one of the following: extracting, based on the calculated superposition, focus information of an exposure process; or extracting, based on the diffraction light intensity, information about the critical dimension associated with a wafer.In some embodiments, extracting the focus information includes determining an optimal focus range for performing the exposure process. In some embodiments, extracting the critical dimension information includes determining a relationship between a diffraction light intensity and a critical dimension. In some embodiments, steps 1510-1540 are performed on a test wafer, rather than a fabrication wafer.It should be appreciated that additional processes may be performed before, during, and / or after steps 1510- 1540 of method 1540. For example, the method 1500 may include a step of fabricating the overlay mark (or multiple similar overlay marks) on a wafer, such as a test wafer. The overlay mark may be made before the step 1510 of measuring the diffraction light intensity. For simplicity, additional steps will not be discussed in detail herein.FIG. 25 is a flow diagram illustrating a method 1600 of semiconductor fabrication in accordance with aspects of the present invention. The method 1600 comprises a step 1610 of structuring a first overlay mark on a wafer. The first overlay mark comprises: a first component disposed in a region of the first overlay mark, the first component comprising a plurality of gratings extending in a first direction; a second component disposed in a second region of the first overlay mark, the second component comprising a plurality of gratings extending in the first direction; a third component disposed in a third region of the first overlay mark, the third component comprising a plurality of gratings extending in a second direction different from the first direction; and a fourth component disposed in a fourth region of the first overlay mark, the fourth component comprising a plurality of gratings extending in the second direction; wherein: the first region is aligned with the second region; and the third region is aligned with the fourth region. The method 1600 further comprises a step 1620 of performing one or more semiconductor manufacturing processes using the first overlay markIn some embodiments, the first component, the second component, the third component, and the fourth component each include an upper layer in which a first subset of gratings is disposed and a lower layer in which a second subset of gratings is disposed.In some embodiments, for the first component, the first subset of gratings is offset with respect to the second subset of gratings by a distance +d in the second direction; for the second component, the first subset of gratings is offset with respect to the second subset of gratings by a distance -d in the second direction; for the third component, the first subset of gratings is offset with respect to the second subset of gratings by a distance -d in the first direction; and for the fourth component, the first subset of gratings is offset with respect to the second subset of gratings by a distance +d in the first direction.In some embodiments, the first region, the second region, the third region, and the fourth region correspond to four corner regions of a square.In some embodiments, at least a portion of the first overlay mark is disposed adjacent to an edge of an integrated circuit chip or an edge of a test line.In some embodiments, the first overlay mark is part of a device further comprising a structure comprising at least a portion of an integrated circuit chip, wherein the first overlay mark is disposed adjacent a boundary of the structure. In some embodiments, the apparatus further comprises a second overlay mark disposed adjacent to a corner of the structure, wherein the second overlay mark is configured differently than the first overlay mark. In some embodiments, the second overlay mark comprises: a first component disposed in a first region of the second overlay mark, the first component comprising a plurality of gratings extending in the first direction; a second component disposed in a second region of the second overlay mark, the second component comprising a plurality of gratings extending in the first direction, and wherein the first region and the second region are diagonally disposed with respect to each other; a third component and a fourth component collectively disposed in a third region of the second overlay mark and having a common boundary extending in the first direction, the third component and the fourth component each comprising a plurality of gratings extending in the second direction; and a fifth component and a sixth component arranged together in a fourth region of the second overlay mark and having a common boundary extending diagonally in both the first direction and the first direction, wherein the third region and the fourth region are arranged diagonally with respect to each other, and wherein the fifth component and the sixth component each include a plurality of gratings extending in the second direction. In some embodiments, the third component, the fourth component, the fifth component, and the sixth component each include an upper layer in which a first subset of the gratings is disposed and a lower layer in which a second subset of the gratings is disposed; for the third component, the first subset of gratings is offset with respect to the second subset of the gratings by a distance +d in the first direction; for the fourth component, the first subset of gratings is offset with respect to the second subset of the gratings by a distance -d in the first direction; for the fifth component, the first subset of gratings is offset with respect to the second subset of gratings by a distance +d in the first direction; and for the sixth component, the first subset of the gratings is offset with respect to the second subset of the gratings by a distance -d in the first direction.It should be appreciated that additional processes may be performed before, during, and / or after steps 1610- 1620 of method 1600. For simplicity, additional steps will not be discussed in detail herein.FIG. 26 is a flow diagram illustrating a method 1700 of semiconductor fabrication in accordance with aspects of the present invention. The method 1700 includes a step 1710 of patterning a overlay mark on a wafer. The overlay mark comprises: a plurality of first gratings arranged in a first layer of the overlay mark; a plurality of second gratings arranged in a second layer of the overlay mark, one of the first layer and the second layer comprising an upper layer and the other of the first layer and the second layer comprising a lower layer arranged below the upper layer; and a plurality of sub-structures arranged in the first layer but not in the second layer, wherein a size of each of the first gratings is at least an order of magnitude larger than each of the sub-structures. The method 1700 further includes a step 1720 of performing one or more semiconductor manufacturing processes using the overlay markIn some embodiments, the first gratings and the second gratings each extend in a first direction; and the first gratings are offset with respect to the second gratings in a second direction different from the first direction.In some embodiments, the first gratings, the second gratings, and the sub-structures are disposed in a first region of the overlay mark, and the overlay mark includes a second region that is symmetric to the first region. In some embodiments, the overlay mark includes a first component and a second component; the first region and the second region are both received in the first component and the second component; the first region in the first component is oriented perpendicular to the first region in the second component; and the second region in the first component is oriented perpendicular to the second region in the second component. In some embodiments, the first component is configured to measure an X-direction overlap between a first layer and a second layer of a semiconductor device; and the second component is configured to measure a Y-direction overlap between the first layer and a third layer of the semiconductor device. In some embodiments, the sub-structures in the first component are configured differently than the sub-structures in the second component. In some embodiments, the first gratings in the first component and the first gratings in the second component have different widths.In some embodiments, the sub-structures are arranged in a row and a column extending in a same direction as each of the first grids.In some embodiments, the sub-structures include at least a first sub-group of sub-structures and a second sub-group of sub-structures; and the sub-structures in the first sub-group have different plan view profiles than the sub-structures in the second sub-group.It is understood that additional processes may be performed before, during, and / or after steps 1710- 1720 of method 1700. For simplicity, additional steps will not be discussed in detail herein.FIGS. 27-32 show schematic side cross-sectional side views of an apparatus 2000 at various stages of manufacture in accordance with embodiments of the present invention. The apparatus 2000 may include a overlay mark according to the various aspects of the present invention discussed above. Referring to FIG. 27, a wafer 2100 is provided. For example, in some embodiments, wafer 2100 may comprise a silicon substrate, or in other embodiments may comprise another semiconductor or dielectric material. A layer 2110 is formed over wafer 2100. The layer 2110 comprises a material that can be patterned, for example, a dielectric material or a metal material. A patterned layer 2120 is then formed over the layer 2110. In some embodiments, the patterned layer 2120 is a patterned photoresist layer that may be patterned using a first photomask. In other words, the patterned layer 2120 is defined by a first photomask.Referring to FIG. 28, an etching process is performed on the device 2000 using the patterned photoresist layer 2120 as a mask. As a result of the etching process, the layer 2110 is etched to assume the top view structure / shape of the patterned photoresist layer 2120. The patterned layer 2110 can serve as the bottom layer of the various overlay marks of the present invention discussed above.Referring to FIG. 29, a layer 2150 is formed in the openings defined by the patterned layer 2110. A polishing process, such as a chemical mechanical polishing (CMP) process, is then performed to planarize the top surfaces of the patterned layer 2110 and the layer 2150. Layer 2150 comprises a different material than layer 2110.Referring to Figure 30, a layer 2210 is formed over the planarized top surfaces of layers 2110 and 2150. The layer 2210 includes a material that may be patterned, for example, a dielectric material or a metal material. A patterned layer 2220 is then formed over the layer 2210. In some embodiments, the patterned layer 2220 is a patterned photoresist layer that may be patterned using a second photomask different from the first photomask (used to pattern the layer 2110). In other words, the patterned layer 2220 is defined by a second photomask. In some embodiments, the patterned layer 2220 may correspond to the top layer 100A discussed above with reference to FIG. 3. For example, the patterned layer 2220 may be used to measure superposition with the layer 2110, and if the measured superposition is not satisfactory, then the patterned layer 2210 may be removed and replaced with another patterned layer to improve the superposition.Referring to FIG. 31, an etching process is performed on the device 2000 using the patterned resist layer 2220 as a mask. As a result of the etching process, the layer 2210 is etched to assume the top view structure / shape of the patterned resist layer 2220. The patterned layer 2210 may serve as the top layer of the various overlay marks of the present invention discussed above. The patterned layer 2210 and the patterned layer 2110 may also be used for measuring the superposition similarly to the upper and lower layers in FIG. 3.Referring to FIG. 32, a layer 2250 is formed in the openings defined by the patterned layer 2210. A polishing process, such as a CMP process, is then performed to planarize the top surfaces of the patterned layer 2210 and the layer 2250. Layer 2250 comprises a different material than layer 2210. In some embodiments, layers 2150 and 2250 have the same material composition.At this time, a double-layered overlay mark is formed. Again, the top layer of the overlay mark is represented by layer 2210, while the bottom layer of the overlay mark is represented by layer 2110. However, it should be understood that the overlay mark shown in FIG. 32 is simplified for ease of understanding. Layers 2210 and 2110 may each include a plurality of structures arranged in the manner described above with reference to FIGS. 3-21, as well as having a bias voltage (e.g., +d or -d) in a given direction, as discussed above. It will also be appreciated that other functional circuit components (e.g., metal lines or vias) may be patterned in the same layers as in overlay mark layers 2210 and 2110. The overlap measured between layers 2210 and 2110 may indicate a degree of alignment between the functional circuit components.The overlay marks discussed herein may remain even after all of the fabrication processes have been performed and the wafer has been divided and packaged into multiple IC chips. In other words, the overlay marks of the present invention may appear or be detected in an IC chip.In semiconductor fabrication, the overlay marks of the present invention can be used to measure the alignment between different layers. The degree of alignment between the upper and lower layers of the overlay mark represents the alignment between other structures formed in the same layers as the upper and lower layers of the overlay mark, respectively. In some embodiments, the diffraction light intensities of the gratings in a overlay mark may be used to calculate the asymmetry information to calculate the orientation of the overlay, for example, in a similar manner as discussed above with reference to FIG. 3.Although the overlay marks discussed above may be used in EUV lithography processes to measure the alignment between different layers in some embodiments, it should be appreciated that they are not limited to EUV lithography and may be used in non-EUV lithography in other embodiments.Based on the above discussions, it can be appreciated that the present invention provides advantages over conventional methods. It should be understood, however, that other embodiments may provide additional advantages, and not all advantages have necessarily been disclosed herein, and that no particular advantage is required for all embodiments. An advantage is that the overlay marks of the present invention allow more accurate overlay measurements to be taken. For example, the overlay mark configuration discussed above in connection with FIGS. 5-13 may reduce the effects of noise generated as a result of imperfect pattern density uniformity. Another advantage is that the overlay marks of the present invention allow extraction of focus information. For example, sub-patterns (e.g., the sub-patterns shown in FIGS. 15A-15B, 17A-17B, and 18A-18E) are added to overlay marks that result in the sub-lobes discussed above in FIG. 16. The sub-lobes allow focus information to be extracted while not affecting overlay measurements. An optimal focus range may be determined, for example, as discussed above with reference to FIG. 19. Yet another advantage is that the overlay marks of the present invention allow the extraction of critical dimension (CD) information. For example, as discussed above with reference to FIGS. 21A to 21C, the components of the overlay mark are designed to have different grating widths (i.e., critical dimensions of the gratings) to extract critical dimension information. In some embodiments, the extracted critical dimension information may include a relationship between the critical dimension and the diffraction light intensity (or exposure energy). Invention: Invention

Claims

An apparatus comprising: a first overlay mark (200A) comprising: a first component (210) disposed in a first region of the first overlay mark (200A), the first component (210) comprising a plurality of gratings (230) extending in a first direction, a second component (211) disposed in a second region of the first overlay mark (200A), the second component (211) comprising a plurality of gratings (230) extending in the first direction, a third component (220) disposed in a third region of the first overlay mark (200A), the third component (220) comprising a plurality of gratings (231) extending in a second direction different from the first direction, and a fourth component (221), which is arranged in a fourth region of the first overlay mark (200A), wherein the fourth component (221) comprises a plurality of gratings (231) extending in the second direction, wherein: the first region is aligned with the second region and the third region is aligned with the fourth region; wherein at least one portion (240) of the first overlay mark (200A) is arranged adjacent to an edge of an integrated circuit chip or an edge of a test line and has a lower structure density than another portion (250) of the first overlay mark (200A); wherein the first component (210) and the second component (211) each have a boundary arranged in the at least one portion (240).The apparatus of claim 1, wherein the first component (210), the second component (211), the third component (220), and the fourth component (221) each comprise an upper layer (2210) in which a first subset of the grids is disposed and a lower layer (2110) in which a second subset of the grids is disposed.The apparatus of claim 2, wherein: for the first component (210), the first subset of the gratings is offset with respect to the second subset of the gratings by a distance +d in the second direction, for the second component (211), the first subset of the gratings is offset with respect to the second subset of the gratings by a distance -d in the second direction, for the third component (220), the first subset of the gratings is offset with respect to the second subset of the gratings by a distance -d in the first direction, and for the fourth component (221), the first subset of the gratings is offset with respect to the second subset of the gratings by a distance +d in the first direction.The device of any preceding claim, wherein the first region, the second region, the third region, and the fourth region correspond to four corner regions of a square.The apparatus of any preceding claim, further comprising: a structure (405) comprising at least a portion of an integrated circuit chip, wherein the first overlay mark (400A) is disposed adjacent a boundary of the structure, and a second overlay mark (400E) disposed adjacent a corner of the structure (405), wherein the second overlay mark (400E) is configured differently than the first overlay mark (400A).The apparatus of claim 5, wherein the second overlay mark (400E) comprises: a first component (410) disposed in a first region of the second overlay mark (400E), wherein the first component (410) comprises a plurality of gratings extending in the first direction, a second component (411) disposed in a second region of the second overlay mark (400E), wherein the second component (411) comprises a plurality of gratings extending in the first direction, and wherein the first region and the second region are diagonally disposed with respect to each other, a third component (430A) and a fourth component (430B) collectively disposed in a third region of the second overlay mark (400E) and having a common boundary extending in the first direction, wherein the third component (430A) and the fourth component (430B) each include a plurality of gratings extending in the second direction, and a fifth component (470A) and a sixth component (470B) arranged together in a fourth region of the second overlay mark (400E) and having a common boundary extending diagonally in both the first direction and the first direction, wherein the third region and the fourth region are arranged diagonally with respect to each other, and wherein the fifth component (470A) and the sixth component (470B) each include a plurality of gratings extending in the second direction.The apparatus of claim 6, wherein: the third component (430A), the fourth component (430B), the fifth component (470A), and the sixth component (470B) each include an upper layer (2210) in which a first subset of the gratings is disposed and a lower layer (2110) in which a second subset of the gratings is disposed, for the third component (430A), the first subset of the gratings is offset with respect to the second subset of the gratings by a distance +d in the first direction, for the fourth component (403B), the first subset of the gratings is offset with respect to the second subset of the gratings by a distance -d in the first direction, for the fifth component (470A), the first subgroup of grids is offset with respect to the second subgroup of grids by a distance +d in the first direction, and for the sixth component (470B), the first subgroup of grids is offset with respect to the second subgroup of grids by a distance -d in the first direction.A method of manufacturing a semiconductor device, comprising: patterning a overlay mark (500) on a wafer, the overlay mark (500) comprising: a plurality of first gratings (530) arranged in a first layer of the overlay mark (500); a plurality of second gratings (550) arranged in a second layer of the overlay mark (500), one of the first layer and the second layer comprising an upper layer and the other of the first layer and the second layer comprising a lower layer arranged below the upper layer; and a plurality of sub-patterns (540) arranged in the first layer but not in the second layer, wherein a size of each of the first gratings (530) is at least an order of magnitude larger than each of the sub-patterns (540); and performing one or more semiconductor manufacturing processes using the overlay mark (500).The method of claim 8, wherein the first gratings (530) and the second gratings (550) each extend in a first direction, and the first gratings are offset with respect to the second gratings in a second direction different from the first direction.The method of claim 8 or 9, wherein: the first gratings (530), the second gratings (550), and the sub-structures (540) are arranged in a first region (FR) of the overlay mark (500), and the overlay mark (500) comprises a second region (FL) symmetric to the first (FR) region.The method of claim 10, wherein: the overlay mark (500) comprises a first component (510, 511) and a second component (520, 521), the first region and the second region are accommodated in both the first component (510, 511) and the second component (520, 521), the first region in the first component (510, 511) is oriented perpendicular to the first region in the second component (520, 521), and the second region in the first component (510, 511) is oriented perpendicular to the second region in the second component (520, 521).The method of claim 11, wherein: the first component (510, 511) is configured to measure an X-direction overlap between a first layer and a second layer of a semiconductor device, and the second component (520, 521) is configured to measure a Y-direction overlap between the first layer and a third layer of the semiconductor device.The method of claim 12, wherein the sub-structures (540) in the first component (510, 511) are configured differently than the sub-structures (540) in the second component (520, 521).The method of any of the preceding claims 11 to 13, wherein the first gratings in the first component (510, 511) and the first gratings (530) in the second component (520, 521) have different widths.The method of any of the preceding claims 8 to 14, wherein the sub-structures (540) are arranged in a row and a column extending in a same direction as each of the first grids (530).The method of any of the preceding claims 8 to 15, wherein: the sub-structures (540) comprise at least a first sub-group of sub-structures (540) and a second sub-group of sub-structures (540), and the sub-structures (540) in the first sub-group have different plan view profiles than the sub-structures (540) in the second sub-group.A method comprising: measuring a diffraction light intensity using a overlay mark (500), wherein the overlay mark comprises an upper layer and a lower layer offset with respect to the upper layer, wherein the upper layer comprises first gratings (530), and wherein the lower layer comprises second gratings (550), wherein the upper layer, but not the lower layer, or the lower layer, but not the upper layer comprises a plurality of sub-structures (540) having a size at least an order of magnitude smaller than the first gratings (530) and second gratings (550), respectively; determining, based on the measured diffraction light intensity, asymmetry information associated with the overlay mark (100), calculating, based on the determined asymmetry information, an overlay associated with the overlay mark (10), and performing at least one of: extracting, based on the calculated overlay, focus information of an exposure process, or extracting, based on the diffraction light intensity, critical dimension information associated with a wafer.The method of claim 17, wherein extracting the focus information comprises determining an optimal focus range for performing the exposure process.The method according to claim 17 or 18, wherein the extracting of the critical dimension information comprises determining a relationship between a diffraction light intensity and a critical dimension.

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