Generation of a Physically Unclonable Function (PUF)

Abstract

Memory module with: a memory cell matrix (102, 202) with a plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein each of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) is configured to be in a data state; and a PUF generator which features the following: a first read amplifier (204-1) connected to the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein the first read amplifier (204-1) is configured to provide access speeds of a first and a second memory cell of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) during an access to the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299). 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) compares and, based on the comparison, provides a first output signal to generate a PUF signature, and a first control unit (210-1) connected to the plurality of memory cells (e.g. 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein the first control unit (210-1) is configured to output an activation signal to the first read amplifier (204-1) based on a respective first and second signal received by the first and second memory cells, respectively, where the first read amplifier (204-1) has a first input terminal connected to a bit line (BL) of the first memory cell and a second input terminal connected to a bit line (BL) of the second memory cell, and the first control unit (210-1) has a first input terminal connected to the bit line (BL) of the first memory cell and a second input terminal connected to the bit line (BL) of the second memory cell, wherein the first control unit (210-1) is configured to generate the activation signal in response to the respective first and second signals reaching a first defined level on the first and second bit lines respectively.

Description

background

[0001] With the increasing use of electronic devices that utilize integrated circuits to provide various types of information for a wide range of applications, there is a growing demand for adequate protection of sensitive and / or critical information that may be stored on an electronic device. This protection aims to restrict access to this information to only those other devices that have authorization to access it. Examples of such applications include device authentication, the protection of confidential information within a device, and ensuring secure communication between two or more devices.

[0002] A Physically Unclonable Function (PUF) is a physical structure, generally within an integrated circuit, that provides a set of corresponding outputs (e.g., responses) in response to inputs (e.g., prompts / requests) to the PUF. Each PUF provides one or more sets of request-response pairs. These request-response pairs, provided by the PUF, can be used to establish the identity of the integrated circuit. Establishing this identity enables secure communication between devices. The PUF can also be used for existing authentication purposes, replacing the current method of assigning an identity to an electronic device.Since PUF is based on specific properties of a manufacturing process, it has several advantages over conventional authentication methods where an identity is stored on a device that can be more easily imitated and / or analyzed for imitation.

[0003] US 2017 / 0017808A1 discloses methods and devices for creating a physically non-clonable function for SRAM.

[0004] The invention is defined in the claims. Brief description of the drawings

[0005] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 is a block diagram showing an example of a memory chip that incorporates an authentication circuit, according to some embodiments. Fig. 2 is a block diagram showing the exemplary memory module of Fig. Figure 1 shows a schematic representation of an authentication circuit, according to some embodiments. Fig. Figure 3 is a circuit diagram showing an example of two memory cells of the SRAM cell matrix (SRAM: Statistical Random Access Memory) as well as a read amplifier and a control unit of the authentication circuit. Fig. Figure 2 shows, according to some embodiments. Fig. 4A is a circuit diagram showing the reading amplifiers and associated control units of an example authentication circuit of Fig. Figure 2 shows, according to some embodiments. Fig. 4B is a circuit diagram showing the reading amplifier and a control unit of another example of the authentication circuit of Fig. Figure 2 shows, according to some embodiments. Fig. Figure 5 is a circuit diagram showing an example of two memory cells of the SRAM cell matrix and the read amplifier of the authentication circuit. Fig. 2 and shows an example of the control units according to some embodiments. Fig. 6 is a circuit diagram that shows an example of a pulse generator that is in Fig. The control unit shown in section 5 is shown according to some embodiments. Fig. Figure 7 shows examples of waveforms derived from the one in Fig. The pulse generator shown in section 6 can be generated according to some embodiments. Fig. Figure 8 shows examples of waveforms of signals from the circuit of Fig. 5, according to some embodiments. Fig. Figure 9 is a circuit diagram showing another example of two memory cells of the SRAM cell matrix and the read amplifier of the authentication circuit. Fig. 2 and another example of the control unit according to some embodiments is shown. Fig. Figure 10 shows examples of waveforms of signals from the circuit of Fig. 9, according to some embodiments. Fig. Figure 11 is a circuit diagram showing another example of two memory cells of the SRAM cell matrix and the read amplifier of the authentication circuit. Fig. 2 and another example of the control unit according to some embodiments is shown. Fig. Figure 12 shows examples of waveforms of signals from the circuit of Fig. 11, according to some embodiments. Fig. Figure 13 is a circuit diagram showing another example of two memory cells of the SRAM cell matrix and the read amplifier of the authentication circuit. Fig. 2 and another example of the control unit according to some embodiments is shown. Fig. Figure 14 shows examples of waveforms of signals from the circuit of Fig. 13, according to some embodiments. Fig. Figure 15 is a flowchart showing an example of a method for generating a PUF signature according to some embodiments. Detailed description of exemplary embodiments

[0006] Several exemplary embodiments for implementing various features of the provided subject matter are described below. Specific examples of components and arrangements are described to simplify the present invention. For example, it should be clear that when an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or one or more elements may be located between them.

[0007] A Physically Unclonable Function (PUF) is generally used for authentication and key storage without the need for secure electrically erasable and reprogrammable read-only memory (EEPROMs) and / or other expensive hardware (e.g., battery-backed static random-access memory). Instead of storing secrets in digital memory, the PUF derives a secret from the physical properties of an integrated circuit (IC). The PUF is based on the idea that although an identical manufacturing process is used to produce multiple ICs, each IC may be slightly different due to manufacturing variability. PUFs exploit this variability to derive "secret" information specific to each IC (e.g., silicon biometrics). Typically, such secret information is referred to as the IC's "signature."Furthermore, due to the manufacturing variability that defines the signature, it is impossible to produce two identical ICs, even with precise knowledge of the IC design. Various types of IC variability can be used to define this signature, such as gate delays, the power-on states of an SRAM chip (SRAM: static random-access memory), and / or various physical properties of an IC.

[0008] In the example of using the aforementioned turn-on states of an SRAM chip, although an SRAM chip has symmetrical cells (bits), manufacturing variability can still cause each bit of the SRAM chip to tend to be in a high state (i.e., logic one) or a low state (i.e., logic zero) while the SRAM chip is powered on. These initial turn-on states of the bits are randomly distributed across the entire SRAM chip, resulting in variability that can be defined by a PUF to create a specific signature of the SRAM chip. Typically, the generation of a PUF signature using the turn-on states of an SRAM chip is referred to as an "SRAM-based turn-on PUF."Generating a PUF signature using a SRAM-based turn-on PUF typically requires at least one repetition of the SRAM device's power cycle, which can adversely affect power consumption during SRAM operation, and signature generation may take longer (e.g., due to limited throughput). Furthermore, the turn-on state of each bit in an SRAM device is usually subject to various local environmental parameters, such as the bit's operating temperature, supply voltage, and tolerated mechanical stress. Therefore, the turn-on states of two bits located at two different positions can be significantly dependent on the specific local environmental parameters to which those two bits are exposed.Therefore, the PUF signature generated based on the on-states of these two bits may be less reliable. Other types of conventional PUFs that utilize the physical properties of an IC to generate a PUF signature can have similar problems to those described above. Consequently, the conventional PUF has not been entirely satisfactory in every respect.

[0009] Embodiments of the present invention provide various systems and methods for generating at least one bit of a PUF signature for a memory chip by comparing the access speeds (e.g., read speeds) of two memory cells of the memory chip. Since the PUF signature is generated based on the comparison of read speeds in the disclosed systems and methods, there is no need to repeatedly turn the memory chip on and off, thus eliminating the problem of higher energy consumption inherent in conventional SRAM-based turn-on PUF. Furthermore, by comparing the read speeds of two adjacent memory cells of the memory chip (to generate the PUF signature), the PUF signature is less susceptible to the aforementioned environmental parameters and can therefore be more reliable.Furthermore, in certain disclosed embodiments, the comparison of the access speeds of the two memory cells is initiated based on signals received by the memory cells themselves, rather than on the basis of an empirically derived signal, such as a global clock signal, thus enabling a more stable read span for comparing the access speeds.

[0010] Fig. Figure 1 shows a memory module 100 according to various embodiments. In the embodiment of Fig. The memory module 100 comprises the following: a memory cell matrix 102, an authentication circuit 104, a preload / preload circuit (PC / PD circuit) 106, a row decoder 108, an optional column decoder 110, an input / output circuit (I / O circuit) 112, and a control logic 114. As in Fig. As shown in Figure 1, the memory cell matrix 102 also features an embedded voltage regulator 116. Although in Fig. Although not shown in Figure 1, in some embodiments all components (i.e., 102, 104, 106, 108, 110, and 112) can be connected to each other and to the control logic 114, so that they are controlled by the control logic 114. Although in the Fig. In the embodiment shown in Figure 1, for better understanding, each component is depicted as a single block; however, in some other embodiments, some or all of the components shown in Figure 1 may be represented as separate blocks. Fig. The components shown in Figure 1 are combined with one another. For example, the memory cell matrix 102 can have an embedded authentication circuit (e.g., 104).

[0011] Let's stay with Fig. 1. In some embodiments, the memory cell matrix 102 has a plurality of memory cells arranged in a column-row configuration, each column having a bit line (BL) and a bit rail line (BBL), and each row having a word line (WL). Specifically, the BL and BBL of each column are each connected to a plurality of memory cells arranged in that column, and each memory cell in that column is located on a different row and is connected to a respective (different) WL. That is, each memory cell of the memory cell matrix 102 is connected to a BL of a column of the memory cell matrix 102, a BBL of a column of the memory cell matrix 102, and a WL of a row of the memory cell matrix 102. In some embodiments, the BLs and BBLs are arranged vertically parallel, and the WLs are arranged horizontally parallel (i.e., perpendicular to the BLs and BBLs).In some embodiments, the authentication circuit 104 has a plurality of read amplifiers connected to the plurality of memory cells. Each read amplifier of the authentication circuit 104 is configured to compare read speeds (i.e., either a load speed or an unload speed, which will be discussed in more detail later) of two or more memory cells connected to the read amplifier by the BL or BBL of each memory cell, in order to provide an output bit based on the result of the comparison.

[0012] In some embodiments, the authentication circuit 104 may further include a compiler 105 for receiving the output bit of each read amplifier and may use the one or more output bits to generate a PUF signature. The PC / PD circuit 106 is also connected to the plurality of memory cells and is configured to preload and / or preload the BLs and / or BBLs. The row decoder 108 is configured to receive a row address of the memory cell matrix and activate a WL at that row address. In some embodiments, the column decoder 110 may be optional. The column decoder 110 is configured to receive a column address of the memory cell matrix and activate a BL and / or BBL at that column address. The I / O circuit 112 is configured to access a data bit (i.e., a logical one or a logical zero) at each of the memory cells.In some embodiments, a data bit can be written to or read from a memory cell using the I / O circuit 112. As explained above, in some embodiments, the control logic 114 is connected to all components and is configured to control the connected components. The voltage regulator 116 is configured to control (e.g., increase or decrease) a voltage level of a supply voltage applied to each of the memory cells. In some alternative embodiments, the voltage regulator 116 can be implemented as a separate block that is not integrated into the I / O circuit 112. Fig. The memory cell matrix 102 shown in Figure 1 is embedded. An exemplary embodiment of the memory cell matrix 102, the authentication circuit 104, and the I / O circuit 112 is described below with reference to Figure 1. Fig. 2 discussed in more detail.

[0013] In Fig. Figure 2 shows an embodiment of a memory module 200. The memory module 200 can be substantially similar to the memory module 100, and thus a memory cell matrix 202, an authentication circuit 204, a PC / PD circuit 206, a line decoder 208, an I / O circuit 212, a control logic 214 and a voltage regulator 216 can correspond to the respective components 102, 104, 106, 108, 112, 114 and 116 respectively of Fig. 1. They will be essentially similar. Therefore, the functionality of each component of Fig. 2 of the corresponding component of Fig. 1 be essentially similar. In some embodiments, the memory cell matrix 202 can be an SRAM matrix. However, the memory cell matrix 202 can be implemented as one of several different memory cell matrices (e.g., DRAM, MRAM, RRAM, or the like), remaining within the scope of protection of the present invention. For example, the memory cell matrix 102 / 202 can be implemented as a ROM matrix (ROM: solid-state memory), a logic NMOS matrix (NMOS: n-metal oxide semiconductor), a logic PMOS matrix (PMOS: p-metal oxide semiconductor), or a combination thereof, as described in some further embodiments with reference to the Fig. 11, Fig. 12 and Fig. 13 is explained and discussed.

[0014] Let's stay with Fig. 2. As explained above, the SRAM cell matrix 202 comprises a plurality of SRAM memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) arranged in a column-row configuration. For clarity, the SRAM memory cell is referred to below as a “cell”. Although in the Fig. In the embodiment shown in Figure 2, only 16 cells are shown; however, in the embodiment of the memory module 200, any desired number of cells can be used, which is within the scope of protection of the present invention. In particular, the memory cell matrix 202 of Fig. 2. Cells 221 and 229, and all other cells between them, are arranged in column A. Similarly, cells 231 and 239, and all other cells between them, are arranged in column B. Cells 241 and 249, and all other cells between them, are arranged in column C. Cells 251 and 259, and all other cells between them, are arranged in column D. Cells 261 and 269, and all other cells between them, are arranged in column E. Cells 271 and 279, and all other cells between them, are arranged in column F. Cells 281 and 289, and all other cells between them, are arranged in column G. Cells 291 and 299, and all other cells between them, are arranged in column H.Although only 8 columns are shown, any desired number of columns can be placed between columns D and E. Within each column, any desired number of cells can be placed between the cells shown. For example, in column A, one or more cells can be placed between cells 221 and 229. Specifically, in... Fig. 2. The cells in each column are arranged in separate rows, and each row can contain multiple cells, each belonging to a different column. In the Fig. In the embodiment shown in Figure 2, cells 221, 231, 241, 251, 261, 271, 281, and 291, belonging to columns A, B, C, D, E, F, G, and H respectively, are arranged in the same row, which is referred to below as row a. Similarly, cells 229, 239, 249, 259, 269, 279, 289, and 299, belonging to columns A, B, C, D, E, F, G, and H respectively, are arranged in the same row, which is referred to below as row b. Although only two rows are shown, any desired number of rows can be arranged between rows a and b.

[0015] As explained above, each column has a corresponding BL / BBL pair associated with the cells in that column, and each row has a corresponding WL associated with multiple cells, each belonging to multiple columns. As shown in the SRAM cell matrix 202 of Fig. As shown in Figure 2, for example, column A has a BL 222 and a BBL 224, column B has a BL 232 and a BBL 234, column C has a BL 242 and a BBL 244, column D has a BL 252 and a BBL 254, column E has a BL 262 and a BBL 264, column F has a BL 272 and a BBL 274, column G has a BL 282 and a BBL 284, and column H has a BL 292 and a BBL 294. The cells of each column are linked to the column's BL and BBL. Fig. For example, cells 221 and 229 and all cells in between are connected to BL 222 and BBL 224, cells 231 and 239 and all cells in between are connected to BL 232 and BBL 234, cells 241 and 249 and all cells in between are connected to BL 242 and BBL 244, cells 251 and 259 and all cells in between are connected to BL 252 and BBL 254, cells 261 and 269 and all cells in between are connected to BL 262 and BBL 264, cells 271 and 279 and all cells in between are connected to BL 272 and BBL 274, and cells 281 and 289 and all cells in between are connected to BL 282. and BBL 284, and cells 291 and 299 and all cells in between are each connected to BL 292 and BBL 294. Furthermore, in Fig. 2 the cells 221, 231, 241, 251, 261, 271, 281 and up to 291, which are arranged in row a, are each connected to the WL 220 of row a, and the cells 229, 239, 249, 259, 269, 279, 289 and up to 299, which are arranged in row b, are each connected to the WL 240 of row b.

[0016] Let's stay with Fig. 2. The authentication circuit 204 has read amplifiers 204-1, 204-2, 204-3, and 204-4, each read amplifier of the authentication circuit 204 being connected to two BLs, each belonging to two adjacent columns. As in the Fig. As shown in the embodiment 2, for example, the reading amplifier 204-1 is connected to BLs 222 and 232, the reading amplifier 204-2 is connected to BLs 242 and 252, the reading amplifier 204-3 is connected to BLs 262 and 272, and the reading amplifier 204-4 is connected to BLs 282 and 292. Although, as in Fig. As shown in Figure 2, the read amplifiers of the authentication circuit 204 are each connected to two BLs, each belonging to two adjacent columns. In some other embodiments, the read amplifiers of the authentication circuit 204 can each be connected to two BBLs, each belonging to two adjacent columns (e.g., read amplifier 204-1 is connected to BBLs 224 and 234). In some embodiments, the read amplifiers of the authentication circuit 204 are each configured to receive a first and a second input signal via the connected BLs, each belonging to two adjacent columns, and to compare the first and second input signals to provide an output signal.In particular, the first and second input signals of two cells arranged in the same row and belonging to the two adjacent columns are provided while these two cells are being accessed (e.g., while they are being read). For example, one pair consisting of the first and second input signals can be generated for the read amplifier 204-1 while cells 221 and 231 are being accessed, and another pair consisting of the first and second input signals for the read amplifier 204-1 can be generated while cells 229 and 239 are being accessed. In some embodiments, the first and second input signals can each comprise either a discharge rate or a charge rate (i.e., a read rate) of a connected cell.Thus, an output signal is generated based on a comparison of the read speeds, and this output signal can be used by the compiler 205 of the authentication circuit 204 to generate, at least part of, a PUF signature. In one example, the read amplifier 204-1 is configured to receive the first read speed (signal 222-1) from cell 221 along BL 222 and the second read speed (signal 232-1) from cell 231 along BL 232, and compares signals 222-1 and 232-1 to provide an output signal 205-1.

[0017] Let's stay with Fig. 2. The PC / PD circuit 206 is connected to all BLs and BBLs of the SRAM cell matrix 202. In some embodiments, the PC / PD circuit 206 is configured to preload and / or preload the BL and / or BBL connected to a cell of the SRAM cell matrix 202 before a data bit (i.e., a logical one or zero) stored in the cell is read via the connected BL and / or BBL. As a characteristic example, the PC / PD circuit 206 is configured to preload BL 222 and BBL 224, which are connected to cell 221, before reading bit data stored in cell 221. The line decoder 208 is connected to all WLs of the SRAM cell matrix 202.In some embodiments, the line decoder 208 is configured to receive a line address (as described above) and, based on the line address, activates the WL at that line address in order to activate one or more access transistors connected to the WL. The I / O circuit 212 has a further plurality of read amplifiers 212-1, 212-2, 212-3, 212-4, 212-5, 212-6 to 212-8. Unlike the read amplifier of the authentication circuit 204, the read amplifiers of the I / O circuit 212 are each connected to the BL and BBL of only one column.For example, the reading amplifier 212-1 is connected to BL 222 and BBL 224 of column A, the reading amplifier 212-2 is connected to BL 232 and BBL 234 of column B, the reading amplifier 212-3 is connected to BL 242 and BBL 244 of column C, the reading amplifier 212-4 is connected to BL 252 and BBL 254 of column D, the reading amplifier 212-5 is connected to BL 262 and BBL 264 of column E, the reading amplifier 212-6 is connected to BL 272 and BBL 274 of column F, the reading amplifier 212-7 is connected to BL 282 and BBL 284 of column G, and the reading amplifier 212-8 is connected to BL 292 and BBL 294 of column H. These read amplifiers of the I / O circuit 212 are each configured to compare a voltage difference between the BL and the BBL, to which a cell is connected, in order to read the bit data stored in the cell.As a characteristic example, if the bit data stored in cell 221 is a logic one, the read amplifier 212-1 can read a logic one based on the comparison of the voltage difference between the connected BL 222 and BBL 224. Details of the operations of the memory chip 200 and the associated components / signals are described below with reference to [reference missing]. Fig. 3 discussed in more detail.

[0018] Fig. Figure 3 shows an exemplary SRAM circuit, detailing two adjacent cells 221 and 231 and the read amplifier 204-1 of the authentication circuit 204 connected to them, according to various embodiments. The in Fig. The embodiment shown in section 3 is used in conjunction with Fig. 2 discussed. As in Fig. As shown in Figure 3, cells 221 and 231 are each implemented as a 6-transistor SRAM cell (6T SRAM cell), but the cell (e.g., 221, 231, etc.) of the SRAM cell matrix 202 is not limited to being implemented as a 6T SRAM cell. The cell of the SRAM cell matrix 202 can be implemented as one of several different SRAM cells, such as a 2T-2R SRAM cell, a 4T SRAM cell, an 8T SRAM cell, etc.

[0019] Let's stay with Fig. 3. Cell 221 comprises transistors M1, M2, M3, M4, M5, and M6, and cell 231 comprises transistors M11, M12, M13, M14, M15, and M16. In some embodiments, cells 221 and 231 are substantially similar to each other, that is, transistor M1 is substantially similar to transistor M11, transistor M2 is substantially similar to transistor M12, transistor M3 is substantially similar to transistor M13, transistor M4 is substantially similar to transistor M14, transistor M5 is substantially similar to transistor M15, and transistor M6 is substantially similar to transistor M16. For clarity, therefore, the following descriptions and operations of the transistors of cell 231 are directed only to cell 221.

[0020] As in Fig. As shown in Figure 3, transistors M2 and M3 are configured as a first inverter, and transistors M4 and M5 are configured as a second inverter, with the first and second inverters connected together. Specifically, the first and second inverters are each connected between a first voltage reference 301 and a second voltage reference 303, respectively. Typically, the first voltage reference 301 is a voltage level of a supply voltage applied to cell 221. The first voltage reference 301 is usually referred to as "Vdd". The second voltage reference 303 is usually referred to as "ground". In some embodiments, the voltage level Vdd is determined by the control logic 214 and controlled by the voltage regulator 216. The voltage level can be, for example, approximately 30% to approximately 130% of Vdd. Furthermore, the first inverter is connected to transistor M1, and the second inverter is connected to transistor M6.Transistors M1 and M6 are not only connected to the inverters, but they are also both connected to WL 220 and BL 222 and BBL 224, respectively. Transistors M1 and M6 are usually referred to as the access transistors of cell 221. In some embodiments, transistors M1, M3, M5, and M6 each comprise an NMOS transistor, and transistors M2 and M4 each comprise a PMOS transistor. Although the in . Fig. As shown in the 3 illustrated embodiments, where M1 to M6 and M11 to M16 are either NMOS or PMOS transistors, one of several different transistors or components suitable for use in a memory chip can be implemented as at least one of the transistors M1 to M6 and M11 to M16, such as a BJT, HEMT, etc.

[0021] When an SRAM cell stores a data bit, generally a first node of the SRAM cell is configured to be in a first logical state (1 or 0), and a second node of the SRAM cell is configured to be in a second logical state (0 or 1), with the first and second logical states being complementary. In some embodiments, the first logical state at the first node is the data bit stored by the SRAM cell. Fig. The embodiment shown in Figure 3 has, for example, nodes 305 and 307. Node 305 is configured such that it is in logical state 1 when cell 221 stores a data bit (e.g., a logical one), and node 307 is configured such that it is in logical state 0 in this case.

[0022] To cause the authentication circuit 204 to generate a PUF signature, in some embodiments a data bit (e.g., either a logic one or zero) is first written to each of the cells to be read in the SRAM cell matrix 202. In some embodiments, this operation (writing) can be performed by the I / O circuit 212. In particular, the I / O circuit 212 can also include components (e.g., one or more read amplifiers) to perform the write operations. Subsequently, the line decoder 208 receives a line address to set a WL at that line address, and then the WL is activated by the line decoder 208. In some embodiments, this line address can be provided by the control logic 214. In response to the activation of the WL (e.g. 220), the access transistors (e.g. M1, M6, M11 and M16) that are arranged along and connected to the WL are activated (i.e.(switched on). In some embodiments of the present invention, all or some of the BLs and BBLs (e.g., 222, 224, 232, and 234) of the SRAM cell matrix 202 are either pre-charged to Vdd or pre-discharged to ground by the PC / PD circuit 206. Then, the data bit stored (written) in each cell (e.g., 221, etc.) of the row (i.e., along the activated WL) is read by a corresponding read amplifier (e.g., 212-1) of the I / O circuit 212 via the respective BL (e.g., 222) and BBL (e.g., 224) connected to the cell. While the data bits are being read, in some embodiments each of the read amplifiers (e.g. 204-1) of the authentication circuit 204, which are connected to the BLs (or BBLs) of two columns / cells (e.g. 221 and 231) on that row, compares read speeds (i.e.either the charging or discharging rates) of the two adjacent cells along the BLs (or BBLs) connected to them in response to a read amplifier activation signal 351 output by a control unit 210. In some embodiments, the control unit 210 is implemented by the control logic 214.

[0023] The read amplifier of the authentication circuit 204 begins to compare the read speeds (either the unload speed or the load speed) of the two adjacent cells in the same row. In response to the comparison, each of the read amplifiers of the authentication circuit 204 can generate a bit (e.g., 205-1) for a PUF signature. Therefore, for a given row (WL) that is activated, an initial plurality of bits (e.g., 205-1, 205-2, 205-3 ... 205-4) of the PUF signature can be generated (simultaneously) by the read amplifiers of the authentication circuit 204. In some embodiments, each of the remaining rows (WLs) of the memory cell matrix is ​​then activated. Thus, one or more pluralitys of bits of the PUF signature can be generated by the read amplifiers of the authentication circuit 204. If a memory cell matrix N 2comprises cells (N columns x N rows) and each read amplifier of the authentication circuit is connected to two adjacent BLs (i.e., two adjacent columns) of the memory cell matrix, as shown in Fig. As shown in Figure 2, a generated PUF signature of ½ N can thus be obtained. 2 Bits are included, while the logical states (either 1 or 0) of the data bits are read.

[0024] As explained above, the read amplifier 201-4 is configured to receive input signals 222-1 and 232-1 from cell 221 along BL 222 and from cell 231 along BL 232, respectively, to generate the output signal 205-1. In some embodiments, the input signal 222-1 can be a voltage level present on BL 222 at a given time, and the input signal 232-1 can be a voltage level present on BL 232 at that same time.

[0025] Furthermore, in some embodiments, the read amplifiers 204-1, 204-2, 204-3, and 204-4 are configured to receive an activation signal 351 from the control unit 210. If the read speeds of the adjacent memory cells of the memory chip used to generate the PUF signature are very similar, it could be difficult to continuously generate the output signals for the PUF signature as desired. Therefore, in certain disclosed embodiments, the control unit 210 is configured to output the activation signal 351 based on signals received from the first and second memory cells, such as signals 222-1 and 232-1 from BLs 222 and 232 of cells 221 and 231, instead of, for example, a generic clock signal.Furthermore, in some examples, each of the read amplifiers of the authentication circuit 204 is controlled locally by a corresponding control unit 210 in response to the input signals present on the respective bit lines, instead of being controlled globally, which allows for a more stable read span for the BLs.

[0026] Fig. Figure 4A shows such an authentication circuit 204a, in which each of the read amplifiers 204-1, 204-2, 204-3, and 204-4 receives an activation signal from a respective control unit 210-1, 210-2, 210-3, and 210-4. Furthermore, each of the control units 210-1, 210-2, 210-3, and 210-4 outputs an activation signal in response to the BL signals received by the corresponding read amplifier. Thus, control unit 210-1 receives an input signal from a BL 222-1 of memory cell 221 and another input signal from a BL 231-1 of memory cell 231. Likewise, the other control units 210-2, 210-3, and 210-4 shown, which are located in Fig. As shown in Figure 4A, input signals from the same BLs are provided, so that output signals are supplied for the respective reading amplifiers 204-2, 204-3 and 204-4.

[0027] Alternatively, shows Fig. 4B an embodiment in which, as in the example of Fig. 4A The single control unit 210 receives one input signal from BL 222-1 of memory cell 221 and another input signal from BL 231-1 of memory cell 231. However, instead of outputting a global signal generated empirically or a global clock signal, control unit 210 outputs an activation signal to each of the read amplifiers 204-1, 204-2, 204-3, and 204-4 based on the signals received from BL 222-1 of memory cell 221 and BL 231-1 of memory cell 231.

[0028] Thus, each of the read amplifiers 204-1, 204-2, 204-3, and 204-4 of the authentication circuits 204a and 204b is controlled by an activation signal generated in response to signals on local BLs. In this way, BL speed fluctuations, for example due to a process change, are better compensated, and the read span for each I / O signal is stabilized.

[0029] The reading amplifier 204-1 is configured such that, after triggering the activation signal 351 (e.g., after the activation signal 351 has gone from low to high), it begins to compare the input signals 222-1 and 232-1 (i.e., to compare the voltage levels on BLs 222 and 232) over time, which is discussed in more detail below. In some embodiments, the read amplifier 204-1 is configured such that, in response to a voltage level difference between BLs 222 and 232 exceeding a specified threshold (e.g., 50 mV) at a specific time (i.e., when a discharge rate or a charge rate is detected), it generates the output signal 205-1 as a logic one, and that, in response to the voltage level difference between BLs 222 and 232 not exceeding the specified threshold, it generates the output signal 205-1 as a logic zero.Details of how the discharge and charge rates are determined will be discussed later. In some embodiments, the read amplifier 204-1 can continue comparing the voltage levels on BLs 222 and 232 over time until BLs 222 and 232 are completely discharged to ground or completely charged to Vdd, or until the voltage level difference between BLs 222 and 232 exceeds the specified threshold.

[0030] Let's stay with Fig. 3 in conjunction with Fig. 2. In some embodiments, the control logic 214 can decide whether to write either a logic one or a logic zero (via the I / O circuit 212) to each of the plurality of cells (e.g., 221, 231, 234, 251, 261, 271, 281, 291, 229, 239, 249, 259, 269, 279, 289, 299, etc.) of the SRAM cell matrix 202. This written logic one or zero can be stored in each of the cells as a data bit. As explained above, the data bit can be stored in the first node of each cell (e.g., node 302 of cell 221 or node 306 of cell 231), and a complementary data bit (opposite to the logical state of the data bit) can be stored in the second node of the cell (e.g., node 304 of cell 221 or node 308 of cell 231).

[0031] In some embodiments, when the data bit stored (written) in each of the plurality of cells is a logic zero, nodes 302 and 306 of cells 221 and 231 are each in a logic state 0, and nodes 304 and 308 of cells 221 and 231 are each in a logic state 1. The control logic can be configured to cause the PC / PD circuit 106 to "preload" all or a subset of the BLs and BBLs (222, 224, 232, and 234) onto Vdd. Simultaneously with or after preloading, the control logic 214 can cause the line decoder 208 to write a WL of a line (e.g., WL 220 in the example of Fig. 3) to activate (turn on) all access transistors (e.g., M1, M6, M11, and M16). In some embodiments, the voltage level of the voltage reference 301 can be lower than Vdd and can be, for example, about 50% to about 99% of Vdd. Since BLs 222 and 232 are pre-charged to Vdd and nodes 302 and 306 are in logic state 0 (e.g., ground), in response to the turn-on of access transistors M1 and M11, a discharge path 302 can be established from BL 222 via access transistor M1 and transistor M3 in cell 221 to ground, or a discharge path 304 can be established from BL 232 via access transistor M11 and transistor M13 in cell 231 to ground. Due to various manufacturing variations, the individual transistors in the memory cell matrix may not be exactly the same.In other words, each transistor has several individual characteristics, such as an individual threshold voltage, individual carrier mobility, individual on-off ratio, individual below-threshold edge, and the like. Therefore, in some embodiments, the discharge path 302 of cell 221 and the discharge path 304 of cell 231 can each have a discharge rate, and these two discharge rates can be different from each other. For example, the discharge rate of discharge path 302 of cell 221 can be greater or less than the discharge rate of discharge path 304 of cell 231. Using this difference in discharge rates between two adjacent cells, the read amplifier 204-1 can generate a bit (e.g., 205-1) of a PUF signature. For example, the read amplifier 204-1 compares the discharge rates of cells 221 and 231.If, based on the comparison, the difference between these two discharge rates is greater than a defined threshold (e.g., 50 mV / s), the read amplifier 204-1 can provide the output signal 205-1 as a logic one; and if the difference between the two discharge rates is less than the defined threshold, the read amplifier 204-1 can provide the output signal 205-1 as a logic zero. Details of the discharge rate will be discussed later.

[0032] Let's return to... Fig. 2. In some embodiments, one or more output signals (bits) can be provided by other read amplifiers (e.g., 204-2, 204-3, 204-4, etc.) on the same line as the read amplifier 204-1 of the authentication circuit 204, based on a comparison of the discharge rates of the "discharge paths" connected to the respective read amplifier. For example, the read amplifier 204-2 compares the discharge rates of the discharge paths established via the transistor of cells 241 and 251, respectively, and outputs the output bit 205-2 based on this comparison. The read amplifier 204-3 compares the discharge rates of the discharge paths established via the transistor of cells 261 and 271, respectively, and outputs the output bit 205-3 based on this comparison. The reading amplifier 204-4 compares the discharge rates of the discharge paths that pass through the transistor of cells 281 and 282 respectively.291 is generated, and based on the comparison, output bit 205-4 is output. In some embodiments, output bits 205-1, 205-2, 205-3, and 205-4 can generate a PUF signature (e.g., 0100). In other embodiments, output bits 205-1, 205-2, 205-3, and 205-4 can be further processed (e.g., selected or filtered) by compiler 205 to generate a PUF signature. In further embodiments, the output bits 205-1, 205-2, 205-3 and 205-4, which were generated based on the comparison of the discharge rates of two adjacent cells in a first row (e.g., row a), together with the output bits 205-1, 205-2, 205-3 and 205-4, which were generated based on the comparison of the discharge rates of two adjacent cells in a second row (e.g., row b), can be further processed by the compiler 205 to generate a PUF signature.

[0033] Fig. Figure 5 shows the memory cells 221 and 231 and the read amplifier 204-1 associated with them, together with an exemplary control unit 210, which is configured to generate the read amplifier activation signal 351, which is received by the read amplifier 204-1. The in Fig. The control unit 210 shown in Figure 5 has a NOR gate 310, which has a first and a second input terminal connected to BLs 222-1 and 232-1, respectively. Thus, the NOR gate 310 receives the same input signals as the read amplifier 204-1. The output signal of the NOR gate 310 is received by a pulse generator 312, which provides a pulsed activation signal 351 for the read amplifier 204-1. An example of the pulse generator 312 is shown in Figure 5. Fig. Figure 6 shows the pulse generator having an AND gate 314 that receives an input signal 320 from the NOR gate 310 and provides the read amplifier activation signal 351 as an output signal. An XOR gate 316 receives the input signal 320 directly at one input and receives the input signal 320 via a delay element 318 at a second input. As shown in Fig. As shown in Figure 7, when the input signal 320 received by the NOR gate 310 goes into a logic high state, the AND gate 314 receives the logic high input signal 320 at one input and receives a logic high output signal from the XOR gate 316. This defines the rising edge of the pulsed activation signal 351, causing the activation signal 351 to go into a logic high state. The falling edge of the pulse of the activation signal 351 is determined after a delay time 324 has elapsed. When the output signal of the delay element 318 goes into a logic high state, the output signal of the XOR gate 316 goes into a low state, which causes the activation signal 351 at the output of the AND gate 314 to also go into a low state.

[0034] Fig. Figure 8 shows exemplary waveforms 402, 404, 406 and 410 of signals on the WL 220, the discharge path 302, the discharge path 304 and the output signal 205-1 respectively, as well as a waveform 408 of the activation signal 351, according to various embodiments. In particular, during a certain period during the operation of the memory module 200 ( Fig. 2) Waveform 402 can represent the signal over time on WL 220, waveform 404 can represent the signal (the voltage level) over time on the discharge path 302, waveform 406 can represent the signal (the voltage level) over time on the discharge path 304, waveform 408 can represent the activation signal 351 over time, and waveform 410 can represent the output signal 205-1 over time. As in the embodiment of Fig. As shown in Figure 8, BLs 222 and 232 are preloaded onto Vdd at time t0. At time t1, WL 220 is read by the line decoder 208 ( Fig. 2) is activated and therefore begins to transition from a logic low state to a logic high state. When, at time t2, the respective read amplifiers 212-1 and 212-2 of the I / O circuit 212 access (read) cells 221 and 231, the discharge paths 302 and 304 are generated, as described above. This causes the voltage levels of BLs 222 and 232 to ramp down from Vdd. As explained above, each discharge path is formed by one or more transistors that (due to manufacturing variations) differ in themselves and / or externally, so each discharge path can have an individual discharge rate. As described above Fig. As shown in Figure 8, waveforms 404 and 406 each have one flank (i.e., one discharge rate).

[0035] Let's stay with Fig. 8. If at time t3 both voltage levels on BLs 222 and 232 fall below a trigger level 403 of the NOR gate 310 (which is in Fig. (as shown in Figure 5) when the activation signal 351 (i.e., waveform 408) output by pulse generator 312 is triggered from a low state to a high state. After activation signal 351 has been triggered (in response to the signals on both BLs 222 and 232 falling below the NOR trigger point 403), in some embodiments, the read amplifier 204-1 begins detecting the difference between the discharge rates of discharge paths 302 and 304 (via BLs 222 and 232). In particular, after time t3, the read amplifier 204-1 retrieves the voltage levels on the discharge paths 302 and 304 at certain time intervals (e.g. every 100 ps) and calculates the discharge rates of discharge path 302 and 304 respectively by dividing the voltage levels by the time period (100 ps in this example).This allows the discharge rates of discharge paths 302 and 304 to be made available to the read amplifier 204-1. For example, at time "t3 + 100 ps", the voltage level on discharge path 302 is X volts, and at time "t3 + 200 ps", the voltage level on discharge path 302 is Y volts, and the discharge rate of discharge path 302 can be derived from the read amplifier 204-1 as (X - Y) / 10 (V / ps). At time t4, after the delay time 324, the activation signal 351 (waveform 408) goes to a logic low level, and the read amplifier 204-1 can provide the output signal as a logic zero (410-1) or a logic one (410-2).

[0036] Let's move on to... Fig. 3 (in conjunction with Fig. 2) back. If the data bit that is stored (written) in each of the plurality of cells is a logic one, in some embodiments nodes 302 and 306 of cells 221 and 231 are each in a logic 1 (nodes 304 and 308 of cells 221 and 231 are each in a logic 0), and furthermore, the control logic can be configured to cause the PC / PD circuit 106 to "pre-discharge" all BLs and BBLs (222, 224, 232, and 234) to ground. Before, simultaneously with, or after the pre-discharge, the control logic 214 can cause the line decoder 208 to output a WL of a line (WL 220 in the example of Fig. 3) to activate (turn on) all access transistors (e.g., M1, M6, M11, and M16). In some embodiments, the voltage level of the voltage reference 303 can be lower than Vdd and can be, for example, about 50% to about 99% of Vdd. Since BLs 222 and 232 are pre-discharged to ground and nodes 302 and 306 are in logic state 1 (e.g., Vdd), in response to the turn-on of access transistors M1 and M11, a charge path 306 can be created via the supply voltage 301, transistor M2, and access transistor M1 in cell 221, or a charge path 308 can be created via the supply voltage 301, transistor M12, and access transistor M11 in cell 231. Due to manufacturing variations in the transistors that form the charging path, each charging path, similar to the discharging path, can have a different charging speed.Since the charging path is essentially similar to the discharging path, further discussion of the charging path (and charging speed) and the use of the charging speed to provide a PUF signature is omitted for the sake of clarity.

[0037] Fig. Figure 9 shows the memory cells 221 and 231 and the read amplifier 204-1 connected to them, together with another example of a control unit 210' that generates the read amplifier activation signal 351, which is received by the read amplifier 204-1. The in Fig. The control unit 210 shown in Figure 9 has an AND gate 311, which has a first and a second input terminal connected to BLs 222-1 and 232-1. Thus, the AND gate 311 receives the same input signals as the read amplifier 204-1. The output signal of the AND gate 311 is received by the pulse generator 312, which is connected as shown in Figure 9. Fig. The control unit 210' provides the activation signal pulse 351 for the reading amplifier 204-1.

[0038] Fig. Figure 10 shows exemplary waveforms 412, 414, 416 and 418 of signals on the WL 220, the charging path 306, the charging path 308 and the output signal 205-1 respectively, as well as a waveform 420 of the activation signal 351, which is generated by the in Fig. The example shown in 9 can be generated. In particular, during a specific period of time while the memory module is operating, 200 ( Fig. 2) Waveform 412 can represent the signal over time on WL 220, waveform 414 can represent the signal (the voltage level) over time on charging path 306, waveform 416 can represent the signal (the voltage level) over time on charging path 308, waveform 418 can represent the activation signal 351 over time, and waveform 420 can represent the output signal 205-1 over time.

[0039] As in the embodiment of Fig. As shown in Figure 10, BLs 222 and 232 are pre-discharged to ground at time t0. At time t1, WL 220 is discharged by the line decoder 208 ( Fig. 2) activated, and therefore waveform 412 begins to transition from a logic low state to a logic high state. When, at time t2, the respective read amplifiers 212-1 and 212-2 of I / O circuit 212 access (read) cells 221 and 231, charge paths 306 and 308 are generated as described above. This causes the voltage levels of BLs 222 and 232 to ramp upwards from ground. As explained above, each charge path is formed by one or more transistors that (due to manufacturing variations) differ in themselves and / or externally, so each charge path can have an individual charge rate. As described above Fig. As shown in Figure 10, waveforms 414 and 416 each have one flank (i.e., one respective loading rate).

[0040] Let's stay with Fig. 10. If, at time t3, both voltage levels on BLs 222 and 232 (waveforms 414 and 416) have risen above the trigger level 413 of the AND gate 311, the activation signal 351 (i.e., waveform 418) is triggered from a logic low state to a logic high state. After the activation signal 351 has been triggered, the read amplifier 204-1 begins detecting the difference between the charging rates of the charging paths 306 and 308 (via BLs 222 and 232). In particular, after time t3, the read amplifier 204-1 retrieves the voltage levels on charging paths 306 and 308 at specific time intervals (e.g., every 100 ps) and calculates the charging speeds of charging paths 306 and 308, respectively, by dividing the voltage levels by the time interval (100 ps in this example). This makes the charging speeds of charging paths 306 and 308 available to the read amplifier 204-1.For example, at time “t3 + 100 ps”, the voltage level on charging path 306 is X volts, and at time “t3 + 200 ps”, the voltage level on charging path 306 is Y volts, and the charging rate of charging path 306 can be derived from the read amplifier 204-1 as (X - Y) / 10 (V / ps). As explained above, the activation signal 418 is triggered because the respective signals on BLs 222 and 232 fall below the trigger level 413 of the AND gate 311. On the falling edge of the activation signal 351 (waveform 418), which is based on the delay time 324 set by the pulse generator 312, the reading amplifier 204-1 can provide the output signal as a logic zero (420-1) or a logic one (420-2).

[0041] Fig. Figure 11 shows another example of the memory cells 221 and 231 and the read amplifier 204-1' associated with them, together with another example of a control unit 210'' that generates the read amplifier activation signal 351, which is received by the read amplifier 204-1'. In the Fig. In the example shown in Figure 11, the output signal of the reading amplifier 204-1' comprises a Q-signal and a Q-rail (QB) output signal. Similar to the example shown in Fig. The embodiment shown in section 5 features the [features] in Fig. The control unit 210'' shown in Figure 11 has a NOR gate 310' which has a first and a second input terminal connected to BLs 222-1 and 232-1. Thus, the NOR gate 310' receives the same input signals as the read amplifier 204-1. The output signal of the NOR gate 310' is the activation signal 351, which is output to the read amplifier 204-1. The NOR gate 310' also has an activation terminal 326, which receives a NOR activation signal output by an XOR gate 328. The XOR gate 328 receives as its input signals the Q and QB output signals of the read amplifier 204-1'.

[0042] Fig. Figure 12 shows exemplary waveforms 422, 424, 426 and 418 of signals on the WL 220, the charging path 306, the charging path 308 and the output signal 205-1 respectively, as well as a waveform 430 of the activation signal 351, which corresponds to the one in Fig. 11. In particular, during a certain period of time during the operation of the memory module 200 ( Fig. 2) Waveform 422 can represent the signal over time on WL 220, waveform 424 can represent the signal (the voltage level) over time on charging path 306, waveform 426 can represent the signal (the voltage level) over time on charging path 308, waveform 428 can represent the activation signal 351 over time, and waveform 430 can represent the output signal 205-1 over time.

[0043] As in the embodiment of Fig. As shown in Figure 12, BLs 222 and 232 are preloaded onto Vdd at time t0. At time t1, WL 220 is read by the line decoder 208 ( Fig. 2) activated, and it therefore begins to transition from a logic low state to a logic high state. When, at time t2, the respective read amplifiers 212-1 and 212-2 of the I / O circuit 212 access (read) cells 221 and 231, the discharge paths 302 and 304 are generated, as described above. This causes the voltage levels of BLs 222 and 232 to ramp down from Vdd. As explained above, each discharge path is formed by one or more transistors that (due to manufacturing variations) differ in themselves and / or externally, so each discharge path can have an individual discharge rate. As described in Fig. As shown in Figure 12, waveforms 424 and 426 each have one flank (i.e., one respective discharge rate).

[0044] If, as in Fig. As shown in Figure 12, at time t3 both voltage levels on BLs 222 and 232 have fallen below a trigger level 423 of the NOR gate 310', the NOR gate 310' is triggered from a low state to a high state, thus initiating the activation signal 351, which is shown as waveform 428. After the activation signal 351 has been triggered, in some embodiments the read amplifier 204-1 begins to detect the difference between the discharge rates of the discharge paths 302 and 304 (via BLs 222 and 232), so that the Fig. The Q and QB output signals shown in Figure 12 are generated. Time t4 indicates the point at which the Q and QB output signals have been deflected to a point where the Q output signal reaches a logic low and the QB output signal reaches a logic high, whereupon the NOR activation signal goes low and the read amplifier activation signal 351 (waveform 428) goes low. The read amplifier 204-1 can then provide the output signal as a logic zero (430-1) or a logic one (430-2).

[0045] Fig. Figure 13 shows another example of the memory cells 221 and 231 and the read amplifier 204-1' associated with them, together with yet another example of a control unit 210''' that generates the read amplifier activation signal 351, which is received by the read amplifier 204-1'. Similar to the embodiment shown in conjunction with Fig. As described in section 11, it includes the following: Fig. In example 13, the output signal of the reading amplifier 204-1' is a Q and a QB output signal. The in Fig. The control unit 210''' shown in Figure 13 has an AND gate 311' which has a first and a second input terminal connected to BLs 222-1 and 232-1, respectively, so that the AND gate 311' receives the same input signals as the read amplifier 204-1. The output signal of the AND gate 311' is the activation signal 351, which is output to the read amplifier 204-1. The AND gate 311' also has an activation terminal 326, which receives an AND activation signal output by an XOR gate 328. The XOR gate 328 receives as its input signals the Q and QB output signals of the read amplifier 204-1'.

[0046] Fig. Figure 14 shows exemplary waveforms 432, 434, 436 and 438 of signals on the WL 220, the charging path 306, the charging path 308 and the output signal 205-1 respectively, as well as a waveform 440 of the activation signal 351, which is generated by the in Fig. The example shown in point 13 can be generated. In particular, during a specific period of time during the operation of the memory module 200 ( Fig. 2) Waveform 432 can represent the signal over time on WL 220, waveform 434 can represent the signal (the voltage level) over time on charging path 306, waveform 436 can represent the signal (the voltage level) over time on charging path 308, waveform 438 can represent the activation signal 351 over time, and waveform 440 can represent the output signal 205-1 over time.

[0047] As in the embodiment of Fig. As shown in Figure 14, BLs 222 and 232 are pre-discharged to ground at time t0. At time t1, WL 220 is discharged by the line decoder 208 ( Fig. 2) activated, and therefore waveform 432 begins to transition from a logic low state to a logic high state. When, at time t2, the respective read amplifiers 212-1 and 212-2 of the I / O circuit 212 access (read) cells 221 and 231, the charge paths 306 and 308 are generated as described above. This causes the voltage levels of BLs 222 and 232 to ramp upwards from ground. As explained above, each charge path is formed by one or more transistors that (due to manufacturing variations) differ in themselves and / or externally, so each charge path can have an individual charge rate. As described in Fig. As shown in Figure 14, waveforms 434 and 436 each have one flank (i.e., one respective loading rate).

[0048] If, at time t3, both voltage levels on BLs 222 and 232 (waveforms 434 and 436) have risen above a trigger level 433 of the AND gate 311', the activation signal 351, represented by waveform 438, is triggered from a logic low state to a logic high state. After the activation signal 351 has been triggered, the read amplifier 204-1 begins to detect the difference between the charging speeds of the charging paths 306 and 308 (via BLs 222 and 232), so that the Fig. The Q and QB output signals shown in Figure 14 are generated. Time t4 indicates the point at which the Q and QB output signals have been deflected to a point where the Q output signal reaches a logic low and the QB output signal reaches a logic high, whereupon the AND activation signal goes low and the read amplifier activation signal 351 (waveform 438) goes low. The read amplifier 204-1' can then provide the output signal as a logic zero (440-1) or a logic one (440-2).

[0049] Fig. Figure 15 is a flowchart showing an example of a Procedure 500 for generating a PUF signature, such as for the SRAM cell matrix of Fig. 2, according to various embodiments. In some embodiments, the steps of method 500 are carried out using different components of the embodiments described herein.

[0050] For discussion, the following embodiment of method 500 is presented in conjunction with the Fig. 2 to 4B described. The illustrated embodiment of method 500 is merely an example, so that one of the several different steps can be omitted, carried out in a different order and / or added, which is still within the scope of protection of the present invention.

[0051] The process begins with step 510, in which a memory cell matrix, such as the one in Fig. 2 SRAM cell matrix 202 is provided. As explained above, a data bit (either a logic one or a logic zero) can be written into each of the cells of matrix 202. Due to the logical state of the data bit (i.e., either a logic one or a logic zero) written into the cells, the bit lines of the memory cells can be pre-loaded to Vdd or pre-discharged to ground. In step 512, the row decoder activates a WL of the memory cell matrix based on a received row address. In some embodiments, this row address can be provided by the control logic 214. In step 514, when the WL is activated for the received row address, the signals on the bit lines of two memory cells of the memory matrix are, for example, with the one shown in Fig.The control unit 210 shown in section 3 is monitored. As specified in decision block 516, the BL signals are monitored until they reach a specified level. According to some examples described here, the specified level is the trigger level of the NOR or AND gate of the various control units 210 shown here.

[0052] When the BL signals reach the specified level, the read amplifier (e.g., 204-1, 204-2, 204-3, and 204-4) of the authentication circuit 204 begins comparing the read rates (i.e., the discharge or charge rates) of two cells in the enabled row / WL, as specified in step 518. For example, the read amplifier (e.g., 204-1) of the authentication circuit 204 can compare the discharge rates of two substantially adjacent cells (e.g., 221 and 231). If the logical state of the data bits written to the cells is a logical zero, the BLs and BLBs are pre-discharged to ground. This allows the read amplifier (e.g., 204-1) of the authentication circuit 204 to compare the charge rates of these two substantially adjacent cells (e.g., 221 and 231).

[0053] In step 520, the read amplifier of the authentication circuit 204 generates an output bit for a PUF signature based on a comparison of the discharge or charge speeds. In some embodiments, the read amplifiers (e.g., 204-1, 204-2, 204-3, and 204-4) of the authentication circuit 204 can each simultaneously generate an output bit for the PUF signature based on the respective comparison of the discharge or charge speeds in the cells connected to it. Therefore, an initial plurality of output bits for the PUF signature can be generated for an activated row / WL. In some embodiments, the process 500 can return to step 512, in which one or more further WLs are activated to generate further output bits for the PUF signature.

[0054] Among other things, controlling the read amplifiers 204-1, 204-2, 204-3, and 204-4 based on the signals on the respective BLs allows for better tolerance of changes in BL access speed and enables a more stable read span for the BLs. Disclosed embodiments include a memory chip, such as an SRAM memory, which has a memory cell matrix with a plurality of memory cells. Each of the plurality of memory cells is configured to be in a data state. A PUF generator includes a read amplifier connected to the plurality of memory cells. The read amplifier is configured to compare the access speeds for a first and a second memory cell of the plurality of memory cells during an access. Based on this comparison, a first output signal is provided to generate a PUF signature.A control unit is connected to the majority of memory cells and is configured to output an activation signal to the read amplifier based on a respective first and second signal received by the first and second memory cells, respectively.

[0055] Further embodiments include a PUF generator comprising a read amplifier with a first input terminal configured to receive a signal from a first memory cell of a plurality of memory cells, and a second input terminal configured to receive a signal from a second memory cell of the plurality of memory cells. The read amplifier is configured to compare the access speeds of the first and second memory cells of the plurality of memory cells and, based on this comparison, provides a first output signal for generating a PUF signature. A control unit is configured to output an activation signal to the read amplifier.The control unit has a first input terminal configured to receive a signal from a bit line of the first memory cell, and a second input terminal configured to receive a signal from a bit line of the second memory cell.

[0056] Further embodiments include a method for generating a PUF signature. The method comprises providing a memory cell matrix containing a plurality of memory cells, each configured to be in a data state. The memory cell matrix includes at least a first and a second memory cell with a first and a second bit line, respectively. The access speeds of the first and second memory cells are compared in response to the first and second signals reaching a defined level on the first and second bit lines, respectively. Based on the comparison of the access speeds of the first and second memory cells, an output signal is provided for generating a PUF signature.

Claims

[1] Memory module with: a memory cell matrix (102, 202) with a plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein each of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) is configured to be in a data state; and a PUF generator which features the following: a first read amplifier (204-1) connected to the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein the first read amplifier (204-1) is configured to provide access speeds of a first and a second memory cell of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) during an access to the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299). 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) compares and, based on the comparison, provides a first output signal to generate a PUF signature, and a first control unit (210-1) connected to the plurality of memory cells (e.g. 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein the first control unit (210-1) is configured to output an activation signal to the first read amplifier (204-1) based on a respective first and second signal received by the first and second memory cells, respectively, where the first read amplifier (204-1) has a first input terminal connected to a bit line (BL) of the first memory cell and a second input terminal connected to a bit line (BL) of the second memory cell, and the first control unit (210-1) has a first input terminal connected to the bit line (BL) of the first memory cell and a second input terminal connected to the bit line (BL) of the second memory cell, wherein the first control unit (210-1) is configured to generate the activation signal in response to the respective first and second signals reaching a first defined level on the first and second bit lines respectively. [2] Memory module according to claim 1, wherein the first control unit (210-1) is configured to generate the activation signal with a pulse with a rising edge due to the fact that the respective first and second signals on the first and second bit lines respectively reach a first defined level. [3] Memory module according to claim 2, wherein the first control unit (210-1) is configured to generate the activation signal with the pulse with a falling edge due to the fact that the first and second signals each reach a second defined level. [4] Memory module according to claim 2 or 3, wherein the first control unit (210-1) is configured to generate the activation signal with the pulse with a falling edge based on an output signal of the first read amplifier (204-1). [5] Memory module according to any one of claims 1 to 4, wherein the first control unit comprises: a NOR gate (310, 310') with the first and second input terminals of the first control unit (210-1); and a pulse generator (312) which is configured to generate the activation signal in response to an output signal of the NOR gate (310, 310'). [6] Memory module according to any one of claims 1 to 4, wherein the first control unit comprises: an AND gate (311, 311', 314) with the first and second input terminals of the first control unit (210-1); and a pulse generator (312) which is configured to generate the activation signal in response to an output signal of the AND gate (311, 311', 314). [7] Memory module according to any of the preceding claims, wherein the PUF generator further comprises: a second read amplifier (204-2) connected to the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein the second read amplifier (204-2) is configured to provide access speeds of a third and a fourth memory cell of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) during an access to the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299). 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), which are essentially adjacent to each other, and based on the comparison provides a second output signal to generate the first PUF signature; and a second control unit (210-2) connected to the majority of memory cells (e.g. 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein the second control unit (210-2) is configured to output an activation signal to the second read amplifier (204-2) based on a respective first and second signal received by the third and fourth memory cells, respectively. [8] Memory module according to any one of claims 1 to 6, wherein the PUF generator further comprises: a second read amplifier (204-2) connected to the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein the second read amplifier (204-2) is configured to provide access speeds of the third and fourth memory cells of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) during access to the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299). 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), which are essentially adjacent to each other, and based on the comparison provides a second output signal to generate the first PUF signature, wherein the first control unit (210-1) is configured to output the activation signal to the second read amplifier (204-2) based on the respective first and second signals received from the first and second memory cells, respectively. [9] PUF generator (PUF: Physically Unclonable Function) with: a first read amplifier (204-1) having a first input terminal connected to a first bit line and configured to receive a signal from a first memory cell of a plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), and a second input terminal connected to a second bit line and configured to receive a signal from a second memory cell of a plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) receives, a pre-charge circuit (106) configured to pre-charge the first and second bit lines to a predetermined pre-charge level, wherein the first read amplifier (204-1) is configured to compare the access speeds of the first and second memory cells of the majority of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) and, depending on whether the respective first and second signals on the first and second bit lines reach a first fixed level, respectively, provides a first output signal to generate a PUF signature based on the load or unload speeds of the first and second memory cells depending on the comparison of the access speeds of the first and second memory cells; and a first control unit (210-1) configured to output an activation signal to the first read amplifier (204-1), wherein the first control unit (210-1) has a first input terminal configured to receive a signal from a bit line (BL) of the first memory cell and a second input terminal configured to receive a signal from a bit line (BL) of the second memory cell. [10] PUF generator according to claim 9, further comprising: a second read amplifier (204-2) having a first input terminal configured to receive a signal from a third memory cell of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), and a second input terminal configured to receive a signal from a fourth memory cell of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein the second read amplifier (204-2) is configured to compare the access speeds of the third and fourth memory cells of the majority of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) and, based on the comparison, provides a second output signal for generating the PUF signature; and a second control unit (210-2) configured to output an activation signal to the second read amplifier (204-2), wherein the second control unit (210-2) has a first input terminal configured to receive a signal from a bit line (BL) of the third memory cell and a second input terminal configured to receive a signal from a bit line (BL) of the fourth memory cell. [11] PUF generator according to claim 9, further comprising: a second read amplifier (204-2) having a first input terminal configured to receive a signal from a third memory cell of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), and a second input terminal configured to receive a signal from a fourth memory cell of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein the second read amplifier (204-2) is set up in such a way that it provides access speeds of the third and fourth memory cells of the majority of memory cells (e.g.221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) compares and, based on the comparison, provides a second output signal to generate the PUF signature, wherein the first control unit (210-1) is configured to output the activation signal to the second reading amplifier (204-2). [12] PUF generator according to any one of claims 9 to 11, wherein the first control unit (210-1) is configured to generate the activation signal in response to the respective first and second signals reaching a first fixed level on the first and second bit lines, respectively, and the second control unit (210-2) is configured to generate the activation signal in response to the respective third and fourth signals on the third and fourth bit lines respectively reaching the first specified level. [13] PUF generator according to any one of claims 9 to 11, wherein the first control unit (210-1) is configured to generate the activation signal in response to the respective first and second signals reaching a first fixed level on the first and second bit lines, respectively, and the second control unit (210-2) is configured to generate the activation signal in response to the respective first and second signals on the first and second bit lines respectively reaching the first specified level. [14] Method for generating a PUF signature (PUF: Physically Unclonable Function) using the following steps: Providing a memory cell matrix (102, 202) comprising a plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299), wherein each of the plurality of memory cells (e.g., 221, 229, 231, 239, 241, 249, 251, 259, 261, 269, 271, 279, 281, 289, 291, 299) is configured to be in a data state, wherein the memory cell matrix (102, 202) comprises a first and a second memory cell with a first and a has a second bit line; Preload the first and second bit lines to a predetermined preload level; Comparing the access speeds of the first and second memory cells in response to a respective first and second signal reaching a defined level on the first and second bit lines, respectively; and Providing an initial output signal to generate a PUF signature based on the loading or unloading speeds of the first and second memory cells, depending on the comparison of the access speeds of the first and second memory cells. [15] Method according to claim 14, wherein the memory cell matrix (102, 202) has a third and a fourth memory cell with a third and a fourth bit line respectively, wherein the method further comprises: Comparing the access speeds of the third and fourth memory cells in response to the respective third and fourth signals reaching the specified level on the third and fourth bit lines, respectively; and Providing a second output signal to generate the PUF signature based on a comparison of the access speeds of the third and fourth memory cells. [16] Method according to claim 14, wherein the memory cell matrix (102, 202) has a third and a fourth memory cell with a third and a fourth bit line respectively, wherein the method further comprises: Comparing the access speeds of the third and fourth memory cells in response to the first and second signals on the first and second bit lines, respectively, reaching the specified level; and Providing a second output signal to generate the PUF signature based on a comparison of the access speeds of the third and fourth memory cells. [17] Method according to any one of claims 14 to 16, further comprising preloading the first and second bit lines to a specified preload level before comparing the access speeds. [18] Method according to any one of claims 14 to 16, further comprising pre-discharging the first and second bit lines to a specified pre-discharge level before comparing the access speeds.

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