Memory cells of novel resistive random access memory components and methods for their production

Abstract

Memory cell comprising: a first electrode (212) comprising an upper interface (212A) and a side wall (212B), a layer of resistive material (218) disposed over the first electrode (212) and comprising at least a first portion (218-1) and a second portion (218-2, 218-3) coupled to a first end of the first portion (218-1), a second electrode (234) disposed over the layer of resistive material (218), a first cover layer (208) extending along an upper interface (212A) of the first electrode (212), a lower surface of the first electrode (212) and the side wall (212B) of the first electrode (212), and a first electrode layer (216) extending along the upper interface (212A) and the side wall (212B) of the first electrode (212), wherein the first portion (218-1) of the layer of resistive material (218) extends along the upper interface (212A) of the first electrode (212) and the second portion (218-2, 218-3) of the layer of resistive material (218) extends along the side wall (212B) of the first electrode (212), wherein the first cover layer (208) and the first electrode layer (216) are arranged between the first electrode (212) and the layer of resistive material (218).

Description

GENERAL STATE OF THE ART

[0001] In recent years, unconventional non-volatile memory (NVM) devices such as ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), and resistive random access memory (RRAM) have been developed. In particular, RRAM devices that switch between a high-resistance state and a low-resistance state offer several advantages over conventional NVM devices. These advantages include manufacturing steps compatible with current CMOS (complementary metal oxide semiconductor) technologies, low-cost manufacturing, compact size, flexible scalability, fast switching, high integration density, and more.

[0002] Integrated circuits (ICs) containing such RRAM components are becoming increasingly more powerful, so the aim is to increase the number of RRAM components in the integrated circuit accordingly. An RRAM component generally comprises a top electrode (e.g., an anode) and a bottom electrode (e.g., a cathode), with a layer of variable resistance material arranged therebetween. In particular, an active region of the layer of variable resistance material runs parallel to the top or bottom electrode. Forming the RRAM component in such a stacked configuration, so that each layer can only extend two-dimensionally, may entail a compromise between maximizing the number of RRAM components in the integrated circuit and maintaining optimal performance of the RRAM component.For example, the number of RRAM devices is typically proportional to the number of active areas of the variable resistance material layers. Increasing the number of RRAM devices in a particular region of the integrated circuit itself reduces the active area of ​​each RRAM device, which can negatively impact the performance of each RRAM device due to weaker signal coupling between the respective top and bottom electrodes.

[0003] Therefore, existing RRAM components and methods for their manufacture are not entirely satisfactory.

[0004] US 7,667,221 B2 relates to a phase-change memory device with an insulating interlayer on a substrate. A phase-change pattern is arranged on the insulating interlayer to cover the upper surface and the side surface of a protruding part of a heater plug. US 6,211,005 B1 discloses ferroelectric memory devices with integrated circuits, which include an integrated circuit substrate comprising a cell region and a peripheral region. A plurality of ferroelectric memory cells, including a plurality of ferroelectric capacitors, are formed in the cell region. DE 10 2015 104 684 A1 relates to an integrated circuit device with an ohmic random access memory (RRAM) cell or an MIM capacitor cell with a dielectric layer, an upper conductive layer, and a lower conductive layer.US 2014 / 0 264 229 A1 discloses a resistive RRAM cell and methods for its fabrication. The RRAM cell comprises a transistor and an RRAM structure. US 2015 / 0 048 298 A1 relates to the fabrication of a first electrode having a top surface and a side surface, a variable resistance film over the first electrode, and a second electrode over the variable resistance film. US 2015 / 0 069 316 A1 discloses a semiconductor structure comprising a conductive layer and a resistance-configurable structure over the conductive layer.

[0005] The task is to improve corresponding RRAM components and reduce the problems mentioned.

[0006] The object is achieved by the memory cells according to patent claims 1 and 9, as well as by the method according to patent claim 17.

[0007] Further details emerge from the dependent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure can best be understood by studying the following detailed description in conjunction with the accompanying figures. It should be noted that various structural elements are not necessarily drawn to scale. Rather, the dimensions and geometries of the various structural elements may be exaggerated or reduced as desired for ease of explanation. The Fig. 1A and Fig. 1B illustrates a flow diagram for an example method of forming a semiconductor device according to some embodiments. Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2 years, Fig. 2K, Fig. 2L, Fig. 2M, Fig. 2N, Fig. 2O and Fig. 2P illustrate cross-sectional views of an exemplary semiconductor device during various manufacturing stages in the process Fig. 1 according to some embodiments. DETAILED DESCRIPTION OF EMBODIMENTS

[0009] The following disclosure describes various embodiments for implementing various features of the subject invention. Certain example components and arrangements are described below to simplify the present disclosure. In the following description, for example, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. In addition, reference numbers and / or reference symbols may be repeated throughout the various examples in the present disclosure.This repetition is for simplicity and clarity and does not in itself prescribe any relationship between the various embodiments and / or configurations explained.

[0010] Spatially relatable terms such as "beneath," "under," "lower," "above," "above," "above," "upper," and the like may also be used herein for convenience in describing the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relatable terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relatable descriptors used herein may also be interpreted accordingly.

[0011] The present disclosure provides various embodiments of a novel RRAM device and methods of forming the same. In some embodiments, the disclosed RRAM device comprises an RRAM resistor having an inverted U-shaped layer of variable resistance material having a first interface (e.g., a concave, lower interface) coupled to a lower electrode and a second interface (e.g., a convex, upper interface) coupled to an upper electrode, respectively. In particular, the first interface of the inverted U-shaped layer of variable resistance material may surround at least an upper portion of the lower electrode, while the second interface of the inverted U-shaped layer of variable resistance material may be coupled to a lower interface of the upper electrode.Forming such an inverted U-shaped layer of variable resistance material in the RRAM resistor can provide various advantages. For example, compared to the above-mentioned conventional RRAM device, forming the layer of variable resistance material in the inverted U-shaped profile in a specific region can significantly increase the active area of ​​the layer of variable resistance material that can be coupled to the upper and lower electrodes. In other words, the above-mentioned trade-off between performance and the number of integrable RRAM devices can be advantageously eliminated when multiple disclosed RRAM devices are integrated into an integrated circuit.

[0012] The Fig. 1A and Fig. 1B illustrate a flow diagram for a method 100 of forming a semiconductor device according to one or more embodiments of the present disclosure. It should be noted that the method 100 is merely an example and is not intended to limit the present disclosure. In some embodiments, the semiconductor device is at least part of an RRAM device. In the context of the present disclosure, the RRAM device refers to any device having a layer of variable resistance material. It should be noted that the method 100 in the Fig. 1A and Fig. 1B, no finished RRAM device is produced. A finished RRAM device may be manufactured using CMOS (Complementary Metal Oxide Semiconductor) processing. Accordingly, it is understood that before, during, and after the process 100, Fig. 1A and Fig. 1B, additional operations may be provided, and some other operations may only be briefly described here. In some other embodiments, the method may be used to form various non-volatile memory (NVM) devices, such as ferroelectric random access memory (FRAM) devices, phase change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, etc., while still being within the scope of the present disclosure.

[0013] In some embodiments, the method 100 begins in Fig. 1A with operation 102 in which a substrate with a transistor is provided. The method 100 proceeds to operation 104 in which a first dielectric layer is formed on the substrate. In some embodiments, the first dielectric layer is formed on the transistor. In some embodiments, the first dielectric layer may be an inter-metal dielectric layer formed over the substrate with one or more such inter-metal dielectric layers disposed therebetween, as will be explained in more detail below. The method 100 proceeds to operation 106 in which an opening extending through the first dielectric layer is formed. In some embodiments, the opening may expose a portion of at least one conductive feature (e.g., drain, source, gate, etc.) of the transistor.In other words, the opening may be connected to the at least one conductive feature of the transistor. The method 100 proceeds to operation 108, in which a first capping layer is formed on the first dielectric layer. In some embodiments, the first capping layer lines the opening through the first dielectric layer and extends along an upper interface of the first dielectric layer. The method 100 proceeds to operation 110, in which a metal layer is formed on the first capping layer. In some embodiments, the metal layer covers the upper interface of the first capping layer and fills the opening.

[0014] Next, the method 100 proceeds to operation 112, where a first electrode is formed. In some embodiments, the first electrode is formed from the metal layer filling the opening, as explained below. The method 100 proceeds to operation 114, where an upper portion of the first dielectric layer is recessed. In other words, a new upper interface of the first dielectric layer is formed, exposing an upper portion of the first electrode and an upper portion of the first cap layer extending along an upper sidewall of the first electrode. The method 100 proceeds to operation 116, where a lower cap layer is formed.In some embodiments, such a lower cap layer, which may be formed from a substantially identical material as the first cap layer, may cover the new upper interface of the first dielectric layer and an exposed upper interface of the first electrode. In addition to covering the new upper interface of the first dielectric layer, the first and lower cap layers, which are integrally formed, may intrinsically line the first electrode, as will be explained below. The method 100 proceeds to operation 118, in which a first electrode layer is formed on the first cap layer.

[0015] In Fig. 1B, the method 100 then proceeds to operation 120, in which a layer of variable resistance material is formed on the first electrode layer. The method 100 proceeds to operation 122, in which a second electrode layer is formed on the layer of variable resistance material. The method 100 proceeds to operation 124, in which a second cap layer is formed on the second electrode layer. In some embodiments, the first cap layer, the first electrode layer, the layer of variable resistance material, the second electrode layer, and the second cap layer are each substantially conformal and thin. The first cap layer, the first electrode layer, the layer of variable resistance material, the second electrode layer, and the second cap layer may intrinsically follow a profile of the exposed upper portion of the first electrode (i.e.,each form an inverted U-shaped profile), which is explained in more detail below. The method 100 proceeds to operation 126 in which the first cap layer, the first electrode layer, the layer of variable resistance material, the second electrode layer, and the second cap layer are patterned. In some embodiments, the respective inverted U-shaped profiles of the first cap layer, the first electrode layer, the layer of variable resistance material, the second electrode layer, and the second cap layer may remain unchanged after patterning. The method 100 proceeds to operation 128 in which spacers are formed. In some embodiments, the spacers are disposed on respective sides of the patterned first electrode layer, layer of variable resistance material, second electrode layer, and second cap layer.The method 100 proceeds to operation 130, in which a second dielectric layer is formed on the first dielectric layer. In some embodiments, the first and second dielectric layers may be formed from substantially the same material, so they are also referred to as one step. The method 100 proceeds to operation 132, in which a second electrode is formed. In some embodiments, the second electrode is formed to extend through the second dielectric layer and couple the variable resistance material layer via the second cap and second electrode layers.

[0016] In some embodiments, operations of the method 100 may be linked to cross-sectional views of a semiconductor device 200 at various manufacturing stages, as shown in the Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2 years, Fig. 2K, Fig. 2L, Fig. 2M, Fig. 2N, Fig. 2O and 2P, respectively. In some embodiments, the semiconductor device 200 may be an RRAM device. The RRAM device 200 may be part of a microprocessor, a memory cell, and / or another integrated circuit (IC). Fig. 2A through 2P are also simplified to better understand the concepts of the present disclosure. For example, while the figures illustrate the RRAM device 200, it should be understood that the integrated circuit in which the RRAM device 200 is formed may include a number of other components, including resistors, capacitors, inductors, fuses, etc., and are not shown in the figures for clarity. Fig. 2A to 2P are not shown.

[0017] According to step 102 in Fig. 1A is Fig. 2A shows a cross-sectional view of the RRAM device 200 including a substrate 202 with a transistor 204 provided in one of the various manufacturing stages, according to some embodiments. The RRAM device 200 in the Fig. 2A has only one transistor 204, it is understood that the embodiment shown in Fig. 2A and the subsequent figures are intended for illustrative purposes only. Therefore, RRAM device 200 may include any desired number of transistors while still falling within the scope of the present disclosure.

[0018] In some embodiments, substrate 202 includes a semiconductor material substrate, for example, silicon. Alternatively, substrate 202 may include other elemental semiconductor material, such as germanium. Substrate 202 may also include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. Substrate 202 may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenophosphide, and gallium indium phosphide. In one embodiment, substrate 202 includes an epitaxial layer. For example, the substrate may include an epitaxial layer covering a bulk semiconductor. Furthermore, substrate 202 may have a semiconductor-on-insulator (SOI) construction.For example, the substrate may have a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or another suitable technique such as wafer bonding and grinding.

[0019] In some embodiments, transistor 204 includes a gate electrode 204-1, a gate dielectric layer 204-2, and source / drain features 204-3 and 204-4. Source / drain features 204-3 and 204-4 may be formed using doping processes such as ion implantation. Gate dielectric layer 204-2 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, and / or combinations thereof, which may be formed using deposition processes such as atomic layer deposition (ALD). Gate electrode 204-1 may include a conductive material such as polysilicon or a metal, which may be formed using deposition processes such as chemical vapor deposition (CVD).As explained in more detail below, transistor 204 may function as an access transistor for RRAM device 200, controlling access to a data storage component (e.g., an RRAM resistor) of RRAM device 200 during read / write operations.

[0020] According to step 104 in Fig. 1A is Fig. 2B shows a cross-sectional view of the RRAM device 200 with a first dielectric layer 206 formed in one of the various manufacturing stages, according to some embodiments. The first dielectric layer 206 is formed, as shown, on the transistor 204 and a major surface of the substrate 202. The first dielectric layer may be part of an IMD (Inter-Metal Dielectric) layer, as mentioned above. Although the first dielectric layer 206 covers Fig. 2B (and subsequent figures), the first dielectric layer 206 directly contacts the substrate 202 and the transistor 204. However, it should be noted that one or more such IMD layers may be located between the first dielectric layer 206 and the substrate 202. In other words, the first dielectric layer 206 may be formed in a back end of line (BEOL) process. For clarity, one or more such IMD layers are not shown in the figures of the present disclosure.

[0021] In some embodiments, the first dielectric layer 206 is formed from a dielectric material. Such a dielectric material may be silicon oxide, a low-k material, another suitable dielectric material, or / and a combination thereof. The low-k material may include fluorinated silicate glass (FSG), phosphosilicate glass (PSG), boron-phosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), strontium oxide (SrO), Black Diamond® (Applied Materials of Santa Clara, Calif., USA), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB (bisbenzocyclobutene), SiLK™ (Dow Chemical, Midland, Mich., USA), polyimide and / or other low-k dielectric materials yet to be developed.

[0022] According to step 106 in Fig. 1A is Fig. 2C illustrates a cross-sectional view of RRAM device 200 having an opening 207 extending through first dielectric layer 206, formed during one of various manufacturing stages, according to some embodiments. Opening 207, as shown, exposes source / drain feature 204-3 (i.e., opening 207 is connected to source / drain feature 204-3), enabling coupling of a later-formed RRAM resistor to transistor 204 via source / drain feature 204-3. As mentioned above, one or more IMD layers (not shown) may be formed between first dielectric layer 206 and substrate 202, such that opening 207 may be indirectly connected to source / drain feature 204-3 via respective conductive features disposed in the one or more IMD layers.

[0023] In some embodiments, the opening 207 may be formed by performing at least some of the following processes: optionally forming an anti-reflective coating (ARC) on the first dielectric layer 206, forming a patternable layer (e.g., a photoresist layer) having a recess that coincides with a desired area for forming the opening 207, performing one or more dry etching processes to etch a portion of the first dielectric layer 206 not covered by the patternable layer using the patternable layer as a mask, and removing the patternable layer.

[0024] According to step 108 in Fig. 1A is Fig. 2D shows a cross-sectional view of RRAM device 200 with a first capping layer 208 formed in one of the various manufacturing stages, according to some embodiments. As shown, the first capping layer 208 covers a top interface 206A of the first dielectric layer 206 and lines the opening 207, i.e., it covers a bottom interface and sidewalls of the opening 207.

[0025] In some embodiments, the first capping layer 208 may be formed from materials such as gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium-tin oxide (ITO), or any alloy, oxide, nitride, fluoride, SiLK™ boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. The first capping layer 208 is in the Fig. 2D (and subsequent figures), it should be noted that it may include multiple layers in the form of a stack, with each of the multiple layers formed from one of the materials described above, e.g., TaN, TiN, etc. In some embodiments, the first cap layer 208 is formed using chemical vapor deposition (CVD), plasma-enhanced (PE) CVD, high-density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin-coating, and / or other suitable techniques for depositing the at least one of the materials described above onto the first dielectric layer 206.

[0026] According to step 110 in Fig. 1A is Fig. 2E shows a cross-sectional view of RRAM device 200 with a metal layer 210 formed during one of the various manufacturing stages, according to some embodiments. As shown, metal layer 210 is formed to cover first cap layer 208 and, accordingly, fill opening 207.

[0027] In some embodiments, the metal layer 210 may include a conductive material such as copper (Cu), aluminum (Al), tungsten (W), etc. In some embodiments, the metal layer 210 may be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, and / or other suitable techniques for depositing the conductive material described above on the first cap layer 208.

[0028] According to step 112 in Fig. 1A is Fig. 2F shows a cross-sectional view of the RRAM device 200 with a first electrode 212 formed in one of the various manufacturing stages, according to some embodiments. In some embodiments, the first electrode 212 is formed by depositing a layer of silicon oxide on the metal layer 210 ( Fig. 2E) a polishing process (e.g., a chemical mechanical polishing (CMP) process) is performed until the upper interface 206A of the first dielectric layer 206 is exposed again. It is therefore understood that when performing such a polishing process, a portion of the first cap layer 208 covering the upper interface 206A is removed. This exposes an upper interface 212A of the first electrode 212 and, furthermore, an upper interface 208A of a portion of the first cap layer 208 extending along a sidewall 212B of the first electrode 212.

[0029] According to step 114 in Fig. 1A is Fig. 2G shows a cross-sectional view of the RRAM device 200 in which an upper portion of the first dielectric layer 206 is recessed in one of the various manufacturing stages, according to some embodiments. After recessing the upper portion of the first dielectric layer 206, a new upper interface 206B of the first dielectric layer 206 is exposed, as shown, and further, a sidewall 208B of the portion of the first cap layer 208 that runs along the sidewall 212B of the first electrode 212 is also exposed. In other words, the first electrode 212 has an upper portion protruding from the new upper interface 206B and a lower portion that is still embedded in the first dielectric layer 206. Furthermore, in some embodiments, a corner (i.e.,an L-shaped profile) 213, and furthermore, the upper interfaces 212A / 208A and the side walls 208B together may form an inverted U-shaped profile.

[0030] In some embodiments, the recess of the upper portion of the first dielectric layer 206 may be formed by performing at least some of the following processes: optionally forming an anti-reflective coating (ARC) on the first dielectric layer 206, forming a patternable layer (e.g., a photoresist layer) covering the first electrode 212 (and the portion of the first cap layer 208 that runs along a sidewall 212B of the first electrode 212), performing one or more dry etching processes to etch the upper portion of the first dielectric layer 206 not covered by the patternable layer using the patternable layer as a mask, and removing the patternable layer.

[0031] According to step 116 in Fig. 1A is Fig. 2H illustrates a cross-sectional view of RRAM device 200 in which a lower cap layer 208' is formed during one of the various manufacturing stages, according to some embodiments. Since the lower cap layer 208' is formed as substantially the same material as the first cap layer 208 in some embodiments, the lower first cap layer 208' and the first cap layer 208 may be integrally formed as a single layer (i.e., the interface between two such layers is not visible), which will be referred to herein as the first cap layer 208 in the following discussion.

[0032] In some embodiments, the lower cap layer 208' is substantially conformal and thin (e.g., about 10.0 to 30.0 nm thick) such that at least a portion of the first cap layer 208 may also follow an inverted U-shaped profile 215 defined by the upper interface 212A and an upper portion of the sidewall 212B. In some embodiments, the first cover layer 208 per se comprises at least one horizontally extending (transverse) section 208-1 running along the upper interface 212A of the first electrode 212, and two vertically extending (longitudinal) sections 208-2 and 208-3 running along the sidewalls 212B of the first electrode 212, wherein the two vertically extending sections 208-2 and 208-3 are each coupled to two ends of the horizontally extending section 208-1.The first cap layer 208 further includes two horizontally extending or “leg” portions 208-4 and 208-5, each extending along the upper interface 206B of the first dielectric layer 206, with the leg portion 208-4 being coupled to the vertically extending portion 208-2 at one end of the vertically extending portion 208-2 opposite the other end to which the horizontally extending portion 208-1 is coupled, and the leg portion 208-5 being coupled to the vertically extending portion 208-3 at one end of the vertically extending portion 208-3 opposite the other end to which the horizontally extending portion 208-1 is coupled. It should be noted that the term "vertical section" as used herein does not necessarily mean that a surface of such a vertical section and a surface intersecting it form an absolute right angle.For example, each of the vertically extending portions 208-2 and 208-3 and the horizontally extending portion 208-1 may form an acute or obtuse angle while still being within the scope of the present disclosure.

[0033] According to step 118 in Fig. 1A is Fig. 2I illustrates a cross-sectional view of RRAM device 200 including a first electrode layer 216 formed during one of the various manufacturing stages, according to some embodiments. The first electrode layer 216 overlies the first capping layer 208, as shown. Like the first capping layer 208, the first electrode layer 216 is substantially conformal and thin (e.g., about 10.0 to 30.0 nm thick) so that at least a portion of the first electrode layer 216 can also follow the inverted U-shaped profile 215.In some embodiments, the first electrode layer 216 includes at least one horizontally extending portion 216-1 extending along the upper interface 212A of the first electrode 212, and two vertically extending portions 216-2 and 216-3 extending along the sidewalls 212B of the first electrode 212, respectively, wherein the two vertically extending portions 216-2 and 216-3 are each coupled to two ends of the horizontally extending portion 216-1.The first electrode layer 216 further includes two horizontally extending or leg portions 216-4 and 216-5, each extending along the upper interface 206B of the first dielectric layer 206, wherein the leg portion 216-4 is coupled to the vertically extending portion 216-2 at one end of the vertically extending portion 216-2 opposite the other end to which the horizontally extending portion 216-1 is coupled, and the leg portion 216-5 is coupled to the vertically extending portion 216-3 at one end of the vertically extending portion 216-3 opposite the other end to which the horizontally extending portion 216-1 is coupled.

[0034] In some embodiments, the first electrode layer 216 may be formed from materials such as gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium-tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. The first electrode layer 216 is in the Fig. 2I (and subsequent figures) is shown as a single layer, it should be noted that it may include multiple layers in the form of a stack, with each of the multiple layers formed from one of the materials described above, e.g., TaN, TiN, etc. In some embodiments, the first electrode layer 216 is formed using chemical vapor deposition (CVD), plasma-enhanced (PE) CVD, high-density plasma (HDP) CVD, inductively-coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin-coating, and / or other suitable techniques for depositing the at least one of the materials described above onto the first cap layer 208.

[0035] According to step 120 in Fig. 1B is Fig. 2J illustrates a cross-sectional view of RRAM device 200 including a variable resistance material layer 218 formed during one of various manufacturing stages, according to some embodiments. The variable resistance material layer 218 overlies the first electrode layer 206 as shown. The variable resistance material layer 218, like the first cap layer 216 and the first electrode layer 208, is substantially conformal and thin (e.g., about 1.0 to 10.0 nm thick) so that at least a portion of the variable resistance material layer 218 can also follow the inverted U-shaped profile 215.In some embodiments, the layer 218 of variable resistance material includes at least one horizontally extending portion 218-1 extending along the upper interface 212A of the first electrode 212 and two vertically extending portions 218-2 and 218-3 extending along the sidewalls 212B of the first electrode 212, respectively, wherein the two vertically extending portions 218-2 and 218-3 are each coupled to two ends of the horizontally extending portion 218-1.The variable resistance material layer 218 further includes two horizontally extending or leg portions 218-4 and 218-5, each extending along the upper interface 206B of the first dielectric layer 206, with the leg portion 218-4 being coupled to the vertically extending portion 218-2 at one end of the vertically extending portion 218-2 opposite the other end to which the horizontally extending portion 218-1 is coupled, and the leg portion 218-5 being coupled to the vertically extending portion 218-3 at one end of the vertically extending portion 218-3 opposite the other end to which the horizontally extending portion 218-1 is coupled.

[0036] In some embodiments, the variable resistance material layer 218 is a layer with a resistance conversion characteristic (e.g., variable resistance). In other words, the variable resistance material layer 218 includes material characterized by exhibiting a reversible resistance variance according to a polarity and / or an amplitude of an applied electrical pulse. The variable resistance material layer 218 includes a dielectric layer. The variable resistance material layer 218 can be converted into a conductor or an insulator based on the polarity and / or the strength of the electrical signal.

[0037] In one embodiment, the variable resistance layer 218 may include a transition metal oxide. The transition metal oxide may be M x O ywhere M is a transition metal, O is oxygen, x is the nature of the transition metal, and y is the nature of the oxygen. In one embodiment, the variable resistance material layer 218 comprises ZrO2. Examples of other materials suitable for the variable resistance material layer 218 include: NiO, TiO2, HfO, ZrO, ZnO, WO3, CoO, Nb2O5, Fe2O3, CuO, CrO2, SrZrO3 (Nb-doped), and / or other materials known in the art. In another embodiment, the variable resistance layer 218 may comprise a colossal magnetoresistance (CMR)-based material such as Pr 0.7 Ca 0.3 , MnO3, etc.

[0038] In yet another embodiment, the variable resistance layer 218 may include a polymer material such as polyvinylidene fluoride and poly(vinylidene fluoride-co-trifluoroethylene) (P(VDF / TrFE)). In yet another embodiment, the variable resistance layer 218 may include a conductive bridging random access memory (CBRAM) material such as Ag in GeSe. According to some embodiments, the variable resistance material layer 218 may include multiple layers having resistance conversion material properties. A set and / or reset voltage of the variable resistance material layer 218 may be determined by the nature of the variable resistance material layer 218' (including the "x" and "y" values), its thickness, and / or other factors known in the art.

[0039] In some embodiments, the variable resistance material layer 218 may be formed using an atomic layer deposition (ALD) technique with a precursor containing a metal and oxygen. In some embodiments, other chemical vapor deposition (CVD) techniques may be used. In some embodiments, the variable resistance material layer 218 may be formed using a physical vapor deposition (PVD) technique, such as a sputtering process with a metal target and with oxygen and optionally nitrogen supplied to the PVD chamber. In some embodiments, the variable resistance material layer 218 may be formed using an electron beam deposition process.

[0040] According to step 122 in Fig. 1B is Fig. 2K shows a cross-sectional view of RRAM device 200 with a second electrode layer 220 formed during one of the various manufacturing stages, according to some embodiments. The second electrode layer 220 overlies the variable resistance material layer 218, as shown. The second electrode layer 220 is also substantially conformal and thin (e.g., about 10.0 to 30.0 nm thick) so that at least a portion of the second electrode layer 220 can also follow the inverted U-shaped profile 215.In some embodiments, the second electrode layer 220 includes at least one horizontally extending portion 220-1 extending along the upper interface 212A of the first electrode 212, and two vertically extending portions 220-2 and 220-3 extending along the sidewalls 212B of the first electrode 212, respectively, wherein the two vertically extending portions 220-2 and 220-3 are each coupled to two ends of the horizontally extending portion 220-1.The second electrode layer 220 further includes two horizontally extending or leg portions 220-4 and 220-5, each extending along the upper interface 206B of the first dielectric layer 206, wherein the leg portion 220-4 is coupled to the vertically extending portion 220-2 at one end of the vertically extending portion 220-2 opposite the other end to which the horizontally extending portion 220-1 is coupled, and the leg portion 220-5 is coupled to the vertically extending portion 220-3 at one end of the vertically extending portion 220-3 opposite the other end to which the horizontally extending portion 220-1 is coupled.

[0041] In some embodiments, the second electrode layer 220 may be formed from materials such as gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium-tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. The second electrode layer 220 is in the Fig. 2K (and subsequent figures) is shown as a single layer, it should be noted that it may include multiple layers in the form of a stack, with each of the multiple layers formed from one of the materials described above, e.g., TaN, TiN, etc. In some embodiments, the second electrode layer 220 is formed using chemical vapor deposition (CVD), plasma-enhanced (PE) CVD, high-density plasma (HDP) CVD, inductively-coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin-coating, and / or other suitable techniques for depositing the at least one of the materials described above onto the variable resistance material layer 218.

[0042] According to step 124 in Fig. 1B is Fig. 2L illustrates a cross-sectional view of RRAM device 200 including a second capping layer 222 formed during one of the various manufacturing stages, according to some embodiments. The second capping layer 222 overlies the second electrode layer 220 as shown. The second capping layer 222 is also substantially conformal and thin (e.g., about 10.0 to 30.0 nm thick) such that at least a portion of the second capping layer 222 can also follow the inverted U-shaped profile 215. In some embodiments, the second cover layer 222 includes at least one horizontally extending portion 222-1 extending along the upper interface 212A of the first electrode 212, and two vertically extending portions 222-2 and 222-3 extending along the sidewalls 212B of the first electrode 212, respectively, wherein the two vertically extending portions 222-2 and 222-3 are each coupled to two ends of the horizontally extending portion 222-1.The second cap layer 222 further includes two horizontally extending or leg portions 222-4 and 222-5, each extending along the upper interface 206B of the first dielectric layer 206, wherein the leg portion 222-4 is coupled to the vertically extending portion 222-2 at one end of the vertically extending portion 222-2 opposite the other end to which the horizontally extending portion 222-1 is coupled, and the horizontally extending portion 222-5 is coupled to the vertically extending portion 222-3 at one end of the vertically extending portion 222-3 opposite the other end to which the horizontally extending portion 222-1 is coupled.

[0043] In some embodiments, the second capping layer 222 may be formed from materials such as gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium-tin oxide (ITO), or any alloy, oxide, nitride, fluoride, carbide, boride, or silicide thereof, such as TaN, TiN, TiAlN, TiW, or a combination thereof. The second capping layer 222 is in the Fig. 2L (and subsequent figures), it should be noted that the second capping layer 222 may comprise a single layer in the form of a stack, wherein each of the multiple layers is formed from one of the materials described above, e.g., TaN, TiN, etc. In some embodiments, the second capping layer 222 is formed using chemical vapor deposition (CVD), plasma-enhanced (PE) CVD, high-density plasma (HDP) CVD, inductively coupled plasma (ICP) CVD, physical vapor deposition (PVD), spin-coating, and / or other suitable techniques for depositing the at least one of the materials described above onto the second electrode layer 220.

[0044] According to step 126 in Fig. 1B is Fig. 2M illustrates a cross-sectional view of the RRAM device 200 in which the first electrode layer 208, the first capping layer 216, the variable resistance material layer 218, the second electrode layer 220, and the second capping layer 222 are patterned in one of the various manufacturing stages, according to some embodiments. Following such a patterning process, as shown, respective "leg" portions of the first electrode layer 208, the first capping layer 216, the variable resistance material layer 218, the second electrode layer 220, and the second capping layer 222 that run along the upper interface 206B are partially removed (e.g., etched). Furthermore, such removed leg portions may not be directly connected to respective vertically running portions (e.g.,208-2 / 208-3, 216-2 / 216-3, 218-2 / 218-3, 220-2 / 220-3 and 222-2 / 222-3) are coupled so that the respective horizontal sections 208-1, 216-1, 218-1, 220-1 and 222-1 and vertical sections 208-2 / 208-3, 216-2 / 216-3, 218-2 / 218-3, 220-2 / 220-3 and 222-2 / 222-3 can remain intact. The structured first electrode layer 208, first cover layer 216, layer 218 of variable resistance material, second electrode layer 220 and second cover layer 222 may nevertheless each follow the inverted U-shaped profile.

[0045] In some embodiments, the patterned first electrode layer 208, the first cap layer 216, the variable resistance material layer 218, the second electrode layer 220, and the second cap layer 222 may be formed by performing at least some of the following processes: Forming a patternable layer (e.g.,a photoresist layer) covering the respective horizontally extending sections 208-1, 216-1, 218-1, 220-1 and 222-1, vertically extending sections 208-2 / 208-3, 216-2 / 216-3, 218-2 / 218-3, 220-2 / 220-3 and 222-2 / 222-3 and portions of the leg sections 208-4 / 208-5, 216-4 / 216-5, 218-4 / 218-5, 220-4 / 220-5 and 222-4 / 222-5, performing one or more dry etching processes to etch portions of the leg sections 208-4 / 208-5, 216-4 / 216-5, 218-4 / 218-5, 220-4 / 220-5 and 222-4 / 222-5 not covered by the patternable layer, using the patternable layer as a mask and removing the patternable layer.

[0046] According to step 128 in Fig. 1B is Fig. 2N illustrates a cross-sectional view of RRAM device 200 including spacers 230 formed during one of various manufacturing stages, according to some embodiments. As shown, spacers 230 are formed to respectively cover sides of patterned first electrode layer 208, first cap layer 216, variable resistance material layer 218, second electrode layer 220, and second cap layer 222, while at least partially exposing an upper interface 222-1A of horizontally extending portion 222-1 of patterned second cap layer 222. In particular, the spacers 230 can each cover the vertically extending sections 222-2 / 222-3 and remaining leg sections 222-4 / 222-5 and side walls of the remaining leg sections 222-4 / 222-5 (and 208-4 / 208-5, 216-4 / 216-5, 218-4 / 218-5, 220-4 / 220-5), which are collectively referred to as side walls 231.

[0047] In some embodiments, the spacers 230 may be formed by performing at least some of the following processes: forming a dummy dielectric layer (e.g., silicon nitride (SiN), silicon carbide (SiC), or the like) on the first dielectric layer 206 and the patterned first electrode layer 208, first cap layer 216, variable resistance material layer 218, second electrode layer 220, and second cap layer 222; and performing one or more dry etching processes to etch the dummy dielectric layer until the upper interface 222-1A of the horizontally extending portion 222-1 of the patterned second cap layer 222 and the upper interface 206B of the first dielectric layer 206 are exposed again.

[0048] According to step 130 in Fig. 1B is Fig. 2O shows a cross-sectional view of RRAM device 200 including a second dielectric layer 232 formed during one of various manufacturing stages, according to some embodiments. As shown, second dielectric layer 232 is formed to overlie first dielectric layer 206, patterned first electrode layer 208, first cap layer 216, variable resistance material layer 218, second electrode layer 220, second cap layer 222, and spacers 230. First dielectric layer 206 may be part of an IMD (Inter-Metal Dielectric) layer, as mentioned above, and in some embodiments, second dielectric layer 232 is formed of substantially the same material as first dielectric layer 206. Therefore, the first and second dielectric layers 206 / 232 may be referred to as a stage, according to some embodiments.

[0049] In some embodiments, the second dielectric layer 232 is formed from a dielectric material. Such a dielectric material may be silicon oxide, a low-k material, another suitable dielectric material, or / and a combination thereof. The low-k material may include fluorinated silicate glass (FSG), phosphosilicate glass (PSG), boron-phosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), strontium oxide (SrO), Black Diamond® Xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB (bisbenzocyclobutene), SiLK, polyimide and / or other low-k dielectric materials yet to be developed.

[0050] According to step 132 in Fig. 1B is Fig. 2P illustrates a cross-sectional view of RRAM device 200 including a second electrode 234 formed during one of the various manufacturing stages, according to some embodiments. As shown, second electrode 234 is coupled to at least a portion of the upper interface 222-1A of the horizontally extending portion of second cap layer 222.

[0051] In some embodiments, the second electrode 234 is formed by performing a series of processes substantially similar to the processes for forming the first electrode 212. For example, the second electrode 231 may be formed by performing at least some of the following processes: forming an opening through the second dielectric layer 232 to expose at least a portion of the upper interface 222-1A of the horizontally extending portion of the second cap layer 222, forming a metal layer (e.g., Cu) on the second dielectric layer 232 to refill the opening with the metal layer, and performing a CMP process to re-expose an upper interface of the second dielectric layer 232.

[0052] In some embodiments, the first electrode 212, the first cap layer 208, the first electrode layer 216, the variable resistance material layer 218, the second electrode layer 220, the second cap layer 222, and the second electrode 234 may form an RRAM resistor, with the first electrode 212 serving as the bottom electrode and the second electrode 234 serving as the top electrode of the RRAM resistor, respectively. In some embodiments, such an RRAM resistor is coupled to the transistor 204 to form a 1T1R RRAM bit cell (1T1R - 1 transistor 1 resistor), with the RRAM resistor serving as the data storage device and the transistor 204 serving as the access transistor for the 1T1R RRAM bit cell.In some other embodiments, the RRAM resistor may be coupled to the transistor 204 via respective conductive structures disposed in the one or more IMD layers (not shown) between the substrate 202 and the first dielectric layer 206, as explained above. It should be noted that the respective active area of ​​the RRAM resistor of the disclosed RRAM device 200 increases significantly while the occupied horizontal area remains the same. For example, the active area of ​​the RRAM resistor of the disclosed RRAM device 200 increases by adding respective vertically extending portions (218-2 and 218-3 in FIG. Fig.2J) of the layer 218 of variable resistance material for coupling at least the bottom electrode 212, while maintaining substantially the same horizontal area (or pitch). In a particular region of the disclosed RRAM device 200, the number of RRAM resistors that can be integrated into the RRAM device 200 can be substantially increased without affecting the performance of the individual RRAM resistors (since the respective active area is not reduced).

[0053] In one embodiment, a memory cell comprises: a first electrode having an upper interface and a sidewall, a layer of resistive material disposed over the first electrode and comprising at least a first portion and a second portion coupled to a first end of the first portion, and a second electrode disposed over the layer of resistive material, wherein the first portion of the layer of resistive material extends along the upper interface of the first electrode and the second portion of the layer of resistive material extends along an upper portion of the sidewall of the first electrode.

[0054] In another embodiment, a memory device comprises: a first electrode partially embedded in a first dielectric layer, a layer of resistive material conformally disposed on the protruding portion of the first electrode and a top surface of the first dielectric layer, and a second electrode disposed over the layer of resistive material, the layer of resistive material having a first portion disposed between the first and second electrodes.

[0055] In yet another embodiment, a method comprises forming a first electrode having a top interface and top sidewalls extending over a top interface of a first dielectric layer, forming a layer of resistive material comprising a first portion extending along the top sidewalls, a second portion coupled to one end of the first portion, and a third portion coupled to the other end of the first portion, and forming a second electrode extending through a second dielectric layer overlying the first dielectric layer, the second portion of the layer of resistive material being disposed between the first and second electrodes.

Claims

[1] Memory cell comprising: a first electrode (212) comprising an upper interface (212A) and a side wall (212B), a layer of resistive material (218) disposed over the first electrode (212) and comprising at least a first portion (218-1) and a second portion (218-2, 218-3) coupled to a first end of the first portion (218-1), a second electrode (234) disposed over the layer of resistive material (218), a first cover layer (208) extending along an upper interface (212A) of the first electrode (212), a lower surface of the first electrode (212) and the side wall (212B) of the first electrode (212), and a first electrode layer (216) extending along the upper interface (212A) and the side wall (212B) of the first electrode (212), wherein the first portion (218-1) of the layer of resistive material (218) extends along the upper interface (212A) of the first electrode (212) and the second portion (218-2, 218-3) of the layer of resistive material (218) extends along the side wall (212B) of the first electrode (212), wherein the first cover layer (208) and the first electrode layer (216) are arranged between the first electrode (212) and the layer of resistive material (218). [2] The memory cell of claim 1, wherein the layer of resistive material (218) provides a variable resistance value. [3] The memory cell of claim 1 or 2, wherein the first portion (218-1) of the layer of resistive material (218) is coupled between a lower interface of the second electrode (234) and the upper interface (212A) of the first electrode (212). [4] A memory cell according to any one of the preceding claims, wherein the first electrode (212) and the second electrode (234) each comprise a via structure. [5] A memory cell according to any one of the preceding claims, wherein a first dielectric layer (206) and a second dielectric layer (232) are formed of a substantially same material. [6] A memory cell according to any one of the preceding claims, further comprising: a second cover layer (222) extending along the upper interface (212A) and the side wall (212B) of the first electrode (212), and a second electrode layer (220) extending along the upper interface (212A) and the side wall (212B) of the first electrode (212), wherein the second cover layer (222) and the second electrode layer (220) are arranged between the layer of resistive material (218) and the second electrode (234). [7] A memory cell according to any one of the preceding claims, wherein the layer of resistive material (218) comprises at least a third portion (218-4, 218-5) coupled to a second end of the second portion (218-2, 218-3) opposite a first end of the second portion (218-2, 218-3) to which the first portion (218-1) is coupled and extending away from the sidewall (212B) of the first electrode (212). [8] The memory cell of claim 7, wherein the third portion (218-4, 218-5) is parallel to the first portion (218-1). [9] Memory cell comprising: a first electrode (212) having an upper portion protruding from a first dielectric layer (206), a layer of resistive material (218) conformally disposed on the protruding portion of the first electrode (212) and a top surface (206B) of the first dielectric layer (206), a second electrode (234) disposed over the layer of resistive material (218), a first cover layer (208) extending along an upper interface (212A) and side walls (212B) of the first electrode (212), and a first electrode layer (216) extending along the upper interface (212A) and the side walls (212B) of the first electrode (212), wherein the first cover layer (208) and the first electrode layer (216) are arranged between the first electrode (212) and the layer of resistive material (218), wherein the layer of resistive material (218) has a first portion (218-1) disposed between the first electrode (212) and the second electrode (234). [10] The memory cell of claim 9, wherein the layer of resistive material (218) provides a variable resistance value. [11] The memory cell of claim 9 or 10, wherein the layer of resistive material (218) further comprises a second portion (218-2) and a third portion (218-3) each extending along sidewalls of the projecting portion of the first electrode (212). [12] A memory cell according to any one of claims 9 to 11, further comprising: a spacer (230) disposed along a sidewall of the protruding portion of the first electrode (212) and on the top surface (206B) of the first dielectric layer (206). [13] A memory cell according to any one of claims 9 to 12, further comprising: a second dielectric layer (232) disposed over the first dielectric layer (206), wherein the second electrode extends through the second dielectric layer (232). [14] The memory cell of claim 13, wherein the first dielectric layer (206) and the second dielectric layer (232) are formed of a substantially same material. [15] The memory cell of any one of claims 9 to 14, wherein the first electrode (212) and the second electrode (234) each comprise a via structure. [16] A memory cell according to any one of claims 9 to 15, further comprising: a second cover layer (222) extending along the upper interface (212A) and the side walls (212B) of the first electrode (212), and a second electrode layer (220) extending along the upper interface (212A) and the side walls (212B) of the first electrode (212), wherein the second cover layer (222) and the second electrode layer (220) are arranged between the layer of resistive material (218) and the second electrode (234). [17] Procedure (100) comprising: Forming (112) a first electrode (212) comprising an upper interface (212A) and upper sidewalls extending over an upper interface (206B) of a first dielectric layer (206), Forming (116) a first cover layer (208) extending along an upper interface (212A) and side walls (212B) of the first electrode (212), Forming (118) a first electrode layer (216) extending along the upper interface (212A) and the side walls (212B) of the first electrode (212), Forming (120) a layer of resistive material (218) comprising a second portion (218-2, 218-3) extending along the upper side walls, a first portion (218-1) coupled to one end of the second portion (218-2, 218-3), and a third portion (218-4, 218-5) coupled to the other end of the second portion (218-2, 218-3), and Forming (132) a second electrode (234) extending through a second dielectric layer (232) covering the first dielectric layer (206), wherein the first portion (218-1) of the layer of resistive material (218) is disposed between the first electrode (212) and the second electrode (234), wherein the first cover layer (208) and the first electrode layer (216) are arranged between the first electrode (212) and the layer of resistive material (218). [18] The method of claim 17, wherein the first portion (218-1) of the layer of resistive material (218) extends along the upper interface (212A) of the first electrode (212) and the third portion (218-4, 218-5) of the layer of resistive material (218) extends along the upper interface (206B) of the first dielectric layer (206).

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