Manufacturing method for a semiconductor device and semiconductor processing system

Abstract

A method of manufacturing a semiconductor device (20), comprising: Forming a photoresist layer (203) on a substrate (200) in a lithography tool (300); Exposing the photoresist layer (203) in the lithography tool (300) to form an exposed photoresist layer (206); Developing the exposed photoresist layer (206) in the lithography tool (300) using a developer (208) from a developer supply unit (305b) to form a patterned photoresist layer (207); and Removing an ammonia gas by-product (2081) of the developer (208) from the lithography tool (300) via a gas outlet (308d) of the developer supply unit (305b) into a treatment tool (310) outside the chamber of the lithography tool (300).

Description

BACKGROUNDSemiconductor devices are used in a variety of electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Lithography is one of the most important technologies commonly used in the manufacture of semiconductor devices. During lithography processes, byproducts may be generated after the formation of photoresist materials and the removal of the photoresist materials.DE 698 16 277 T2 discloses a detection system for detecting a base impurity at low concentrations in gas, characterized in that the detection system is configured to assay amines in gas, wherein the detection system comprises an amine remover, at least two channels through which the gas samples to be tested pass, a first converter converting the amines into NO, a detector for generating signals representative of the NO concentration in gas passed through, wherein the amine concentration is determined based on the difference between the detected NO concentration in a converted gas sample connected to the amine remover and the detected NO concentration in a converted gas sample passing through the second converter.US 2002 / 0036760 A1 discloses a chemical filter which removes chemical pollutants from gas and limits temperature fluctuations of the gas before and after passing through the filter to a predetermined range, and which is disposed in a portion of a ventilation path which extends from a machine chamber in which at least a part of an air conditioner is located to a main body chamber in which a main body of an exposure apparatus is located.US 2015 / 0099228 A1 discloses a resist composition comprising a metal compound obtained by reacting a starting metal compound of the formula (A-1) or a (partial) hydrolyzate or condensate or (partial) hydrolytic condensate with a di- or trivalent alcohol of the formula (A-2).BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read with the accompanying drawings. It should be noted that, according to the usual industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be increased or decreased as desired for clarity of description. FIG. 1 is a flow chart showing the process steps of a manufacturing method for manufacturing a semiconductor device according to some embodiments of the present disclosure.FIGS. 2A-2F are schematic cross-sectional views illustrating a semiconductor device at various stages of a manufacturing method for manufacturing the semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a schematic diagram illustrating a semiconductor processing system according to some embodiments of the present disclosure. FIG. 4 is a diagram showing the relationship between processing time and a concentration of an ammonia gas byproduct in a lithography tool of a semiconductor processing system according to some embodiments of the present disclosure.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples to implement various features of the subject matter recited. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.Further, spatially relative terms such as "bottom," "below," "lower," "above," "upper," and the like, may be used herein for convenience of description to describe the relationship of an element or feature with one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative terms used herein may also be interpreted accordingly.FIG. 1 is a flow chart showing the process steps of a manufacturing method 100 for manufacturing a semiconductor device according to some embodiments of the present disclosure. The method 100 includes performing the process step 102 of forming a photoresist layer on a substrate in a lithography tool. In some embodiments, the material of the photoresist layer is a positive resist. In some embodiments, the material of the photoresist layer comprises poly(4-t-butoxycarbonyloxystyrene), polymethyl methacrylate (PMMA), tetrafluoroethylene (TFE), or other suitable photoresist materials. In process step 104, the photoresist layer is exposed in the lithography tool to form an exposed photoresist layer. In process step 106, the exposed photoresist layer is developed using a developer in the lithography tool to form a patterned photoresist layer. In some embodiments, the developer comprises an alkaline-based developer. In some embodiments, the developer comprises an ammonium-containing developer. In some embodiments, the developer comprises an aqueous solution of tetramethylammonium hydroxide (TMAH). In process step 108, an ammonia gas byproduct is removed from the lithography tool. In some embodiments, the act of removing the ammonia gas byproduct of the developer from the lithography tool (step 108) may be performed after the act of developing the exposed photoresist layer (step 106). The method 100 may further include monitoring a concentration of the ammonia gas byproduct in the lithography tool using an ammonia gas monitor, as shown in process step 110. In some embodiments, the act of removing the ammonia gas byproduct of the developer from the lithography tool (step 108) and the act of monitoring a concentration of the ammonia gas byproduct in the lithography tool using an ammonia gas monitor (step 110) may be performed simultaneously. In alternative embodiments, process step 108 and process step 110 may be performed sequentially. The method 100 of manufacturing the semiconductor device described in accordance with embodiments of the present disclosure may be part of the semiconductor manufacturing processes for manufacturing a semiconductor device, and the method 100 may be used to pattern photosensitive material layers, masking layers, or layers of any suitable material over a semiconductor substrate or semiconductor wafer. The details of the method 100 are further shown in FIGS. 2A-2F and FIG. 3, which are described in the following sections.FIGS. 2A-2F are schematic cross-sectional views illustrating a semiconductor device at various stages of a manufacturing method for manufacturing the semiconductor device according to some embodiments of the present disclosure. FIG. 3 is a schematic diagram illustrating a semiconductor processing system 30 according to some embodiments of the present disclosure. The semiconductor processing system 30 of FIG. 3 may be used at certain stages during the performance of the fabrication method for fabricating the semiconductor device of FIGS. 2A-2F. The semiconductor processing system 30 of FIG. 3 may be referred to for illustrative purposes when describing the fabrication method shown in FIGS. 2A-2F. It should be appreciated that the process steps described herein may cover a portion of the fabrication processes used to fabricate a semiconductor device.FIG. 2A is a schematic cross-sectional view of the semiconductor device 20 at one of various stages of the manufacturing method, and FIG. 3 is a schematic diagram showing the semiconductor processing system 30 used for the manufacturing method of FIG. 2A. Referring to FIG. 2A, a substrate 200 is provided. In some embodiments, the substrate 200 includes a crystalline silicon substrate. In some embodiments, the substrate 200 is part of a bulk silicon wafer. The bulk silicon wafer may include interconnect structures (not shown) formed with patterned dielectric layers and patterned conductive layers stacked on top of each other. In some embodiments, the substrate 200 may include other features, such as various doped regions, a buried layer, and / or an epitaxial layer. In certain embodiments, the doped regions are doped with p- and / or n-type dopants depending on design requirements (e.g., a p-substrate or an n-substrate). In some alternative embodiments, the substrate 200 is made of another suitable elementary semiconductor, such as germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.In process step 102, and as shown in FIG. 2, a photoresist layer 203 is formed on substrate 200. In some embodiments, the photoresist layer 203 is formed on the substrate 200 in a coating unit 302 of a lithography tool 300 in the semiconductor processing system 30. That is, the coating unit 302 is configured to coat the photoresist layer 203 on the substrate 200. In some embodiments, the photoresist layer 203 is formed by performing a spin coating process, a spray coating process, a dip coating process, or a roll coating process. In certain embodiments, after forming the photoresist layer 203, for example, by spin coating in the coating unit 302, the photoresist layer 203 is heated by performing a pre-bake process in a baking unit 303 of the lithography tool 300. At this point, the baking unit 303, which may include a heater board, is configured to dry out the photoresist layer 203 and thereby remove excess solvent from the photoresist layer 203. In some embodiments, the material of the photoresist layer 203 is a positive resist material. The exposed portion of the positive resist layer becomes soluble for the later deposited developer, while the unexposed areas of the positive resist layer remain on the substrate. In some embodiments, the photoresist layer 203 is a positive resist layer and the portion of the photoresist layer 203 exposed to radiation is removed by a developer. In some embodiments, the material of the positive resist comprises poly(4-t-butoxycarbonyloxystyrene), polymethyl methacrylate (PMMA), or tetrafluoroethylene (TFE). In some embodiments, the material of the positive resist comprises a mixture of diazonaphthoquinone (DNQ) and novolak resin.In some embodiments, a dielectric layer 201 and a gate material layer 202 are sequentially formed on the substrate 200 before forming the photoresist layer 203 on the substrate 200. That is, the photoresist layer 203 is disposed over the gate material layer 202. In some embodiments, dielectric layer 201 includes SiO 2, SiO x, SiN, other dielectrics, or combinations thereof, or multilayers thereof. In some embodiments, the dielectric layer 201 is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other methods. In some embodiments, the material of the gate material layer 202 comprises polysilicon or doped silicon. In some embodiments, the material of the gate material layer 202 comprises a metal-containing material such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, or a combination thereof. In some embodiments, the gate material layer 202 is formed by PVD, CVD, sputtering, plating, or other suitable methods. In some embodiments, the thickness or structure of the dielectric layer 201 and / or the gate material layer 202 may be modified based on the function or desired characteristics of the desired semiconductor device 20.FIGS. 2B-2C are schematic cross-sectional views of the semiconductor device 20 at various stages of the fabrication process. For illustrative purposes, reference may be made to the semiconductor processing system 30 of FIG. 3. Referring to FIGS. 2B and 2C, the photoresist layer 203 is exposed to a radiation beam 204 in the process step 104 to form an exposed photoresist layer 206. The process of exposing the photoresist layer 203 is performed in an exposure unit 304 of the lithography tool 300 in the semiconductor processing system 30. That is, the exposure unit 304 is configured to apply a radiation beam 204 and perform an exposure process on the photoresist layer 203, so that the photoresist layer 203 is converted into an exposed photoresist layer 206. As shown in FIG. 2B, after providing a photomask 205 over the photoresist layer 203, the radiation beam 204 is applied to the photoresist layer 203, with the photomask 205 being located between the radiation beam 204 and the photoresist layer 203. In some embodiments, the radiation beam 204 includes an electron beam, an ion beam, an x-ray beam, extreme ultraviolet light, deep ultraviolet light, a KrF excimer laser (248 nm), an ArF excimer laser (193 nm), and / or an F2 excimer laser (157 nm). In some embodiments, the photomask 205 includes a transparent substrate 205 aand a radiation absorption layer 205 bdisposed on the transparent substrate 205 a. That is, the region of the transparent substrate 205 aon which the radiation absorption layer 205 bis disposed is a shading region S, and the region of the transparent substrate 205 aon which the radiation absorption layer 205 bis not disposed is a transparent region T. In one embodiment, the material of the transparent substrate 205 aincludes fused silica, calcium fluoride, or another suitable material. In an embodiment, the radiation absorbing layer 205 bis formed by depositing a metal film such as a film of chromium and iron oxide on the transparent substrate 205 a. In one embodiment, the radiation beam 204 passes through the transparent region T of the transparent substrate 205 aand reaches the underlying photoresist layer 203. In alternative embodiments, photomask 205 includes a binary mask, a phase shift mask (PSM), or an optical short range correction (OPC) mask. As shown in FIG. 2B, a portion of the photoresist layer 203 on the substrate 200 is exposed to the radiation beam 204 passing through the transparent region T of the photomask 205. In some embodiments, the process of exposing the photoresist layer 203 is implemented using a stepper by a step and repeat method or using a scanner by a step and scan method. In some embodiments, a pattern according to the predefined pattern of the photomask 205 may be transferred to the photoresist layer 203. However, the present disclosure is not limited thereto. In alternative embodiments, the process of exposing the photoresist layer 203 may include other technologies, such as a mask-free exposure process.As shown in FIG. 2C, after exposing the photoresist layer 203 by the exposure process, the exposed photoresist layer 206 includes an exposed portion 206 aand an unexposed portion 206 b. As previously mentioned, the exposed portion 206a of the exposed photoresist layer 206 becomes soluble for the subsequently applied developer. In some embodiments, after the exposure process and obtaining the exposed photoresist layer 206, the exposed photoresist layer 206 is further heated and baked by performing a baking process in the baking unit 303 of the lithography tool 300.FIG. 2D is a schematic cross-sectional view of the semiconductor device 20 at one of various stages of the fabrication process. Referring to FIGS. 2D and 3, in process step 106, the exposed photoresist layer 206 is developed using a developer 208 and a patterned photoresist layer 207 is formed. In FIG. 2D, the patterned photoresist layer 207 is formed on the gate material layer 202 by removing the exposed portions 206 aof the exposed photoresist layer 206 and retaining the unexposed portion 206 b(FIG. 2C ). The process of developing the exposed photoresist layer 206 is performed in a developing unit 305 of the lithography tool 300 of the semiconductor processing system 30. That is, the developing unit 305 is configured to perform a developing process on the exposed photoresist layer 206 to form the patterned photoresist layer 207. In some embodiments, the developer 208 comprises an aqueous alkaline solution. In some embodiments, the developer 208 comprises an aqueous ammonium-containing solution. In some embodiments, the developer 208 comprises an aqueous solution of tetramethylammonium hydroxide (TMAH).As shown in FIG. 3, the developing unit 305 includes a process tank 305 aand a developer supply unit 305 bfor supplying the developer 208 into the process tank 305 a. In some embodiments, the process of developing the exposed photoresist layer 206 is performed in the process tank 305 aof the developing unit 305, and the developer 208 used for developing the exposed photoresist layer 206 is supplied from the developer supplying unit 305 b. In some embodiments, the developer supply unit 305 bincludes a housing 306 and a storage container 307 located in the housing 306. In some embodiments, the developer supply unit 305 bfurther includes a pump 307P for driving the gas and flowing the developer 208. More specifically, the storage container 307 has a developer inlet 308a and a developer outlet 308b provided or installed on the storage container 307, while the housing 306 has a gas inlet 308c and a gas outlet 308d installed on the housing 306.In some embodiments, the storage container 307 is configured to hold or store the developer 208 therein. In some embodiments, during the developing process, nitrogen gas is pumped and blown into the developer supply unit 305 bthrough the gas inlet 308 c, and the developer 208 stored in the reservoir 307 is discharged into the process tank 305 athrough the developer outlet 308 b, driven by the pump 307 p. As mentioned above, when the developer 208 includes an ammonium-containing developer or an aqueous ammonium-containing solution, an ammonia gas byproduct 2081 may be generated from the developer 208 stored in the storage container 307. In some embodiments, the ammonia gas byproduct 2081 comprises ammonia gas. In some embodiments, the material of the storage container 307 comprises polytetrafluoroethylene (PTFE) such that the storage container 307 is gas permeable. During or after the process of supplying the developer 208, the ammonia gas by-product 2081 enters the developer supply unit 305 bfrom the storage container 307. Without further treatment, the ammonia gas byproduct 2081 may be discharged into the chamber C of the lithography tool 300, which may trigger foaming of the photoresist material and degrade development resolution.In some embodiments, in FIG. 2D, after the patterned photoresist layer 207 is formed, the patterned photoresist layer 207 is heated and baked by performing a post-bake process in the baking unit 303 of the lithography tool 300. At this point, the post-bake process helps to cure the patterned photoresist layer 207 to resist harsh reaction conditions that occur in the subsequent processes, such as an etch process or an implant process. It is noted that, as shown in FIGS. 2A to 2D, the formation of the patterned photoresist layer 207, i.e., the formation, development, and patterning of the photoresist layer, is performed using the lithography tool 300.Following the process of developing the exposed photoresist layer 206, the fabrication method 100 of the semiconductor device 20 continues with the process of removing the ammonia gas byproduct 2081 from the lithography tool 300 in the process step 108. As shown in FIG. 3, a treatment tool 310 is used to remove the ammonia gas byproduct 2081 in the developer supply unit 305 b. In some embodiments, when the storage container 307 is replenished with the developer 208 driven by the pump 307P, the gas in the developer supply unit 305 bis purged out of the developer supply unit 305 bthrough the gas outlet 308 dand further purged into the treatment tool 310. Further, in some embodiments, the ammonia gas byproduct 2081 discharged into the treatment tool 310 is retained in the treatment tool 310. That is, the ammonia gas byproduct 2081 in the developer supply unit 305 bis removed by purging the ammonia gas byproduct 2081 from the developer supply unit 305 bof the lithography tool 300 into the treatment tool 310, and then the ammonia gas byproduct 2081 is retained in the treatment tool 310. In some embodiments, the treatment tool 310 includes an adsorptive material therein, and thereby the ammonia gas byproduct 2081 is adsorbed from the adsorptive material by chemisorption or physisorption in the treatment tool 310. In some embodiments, the adsorptive material is an inorganic adsorptive material and the inorganic adsorptive material comprises alumina, silica or activated carbon. In some embodiments, the adsorptive material is an organic adsorptive material and the organic adsorptive material comprises organic polymeric materials such as tenax, poropak, or chromosorb. In alternative embodiments, the treatment tool 310 includes a filter to filter out the ammonia gas byproduct 2081.As shown in FIG. 3, the ammonia gas by-product 2081 is discharged from the gas outlet 308 dof the developer supply unit 305 binto the treatment tool 310 through an exhaust tool 320 connected therebetween. The exhaust tool 320 spatially communicates with and connects the processing tool 310 and the developer supply unit 305 bof the lithography tool 300. In some embodiments, the exhaust tool 320 includes an exhaust pipe as the passage for the flow of the gas or ammonia gas byproduct 2081. The exhaust tool 320 connects the gas outlet 308 don the housing 306 of the developer supply unit 305 bto the treatment tool 310. The treatment tool 310 is located outside the lithography tool 300. That is, the ammonia gas byproduct 2081 is discharged from the developer supply unit 305 bof the lithography tool 300 to an environment outside the lithography tool 300 and is removed from the lithography tool 300.In some embodiments, the manufacturing method 100 of the semiconductor device 20 includes the operation of monitoring the concentration of the byproduct ammonia gas 2081 in the lithography tool 300 using an ammonia gas monitor 330, as shown in the process step 110. Although the ammonia gas byproduct 2081 is discharged into the processing tool 310 and then retained therein, the concentration of the ammonia gas byproduct 2081 in the lithography tool 300 is monitored. In some embodiments, as a precautionary measure in the event that the byproduct ammonia gas 2081 unexpectedly exits into the chamber C of the lithography tool 300 or into the environment within the lithography tool 300 so as to interfere with certain processes performed in the lithography tool 300, the concentration of the byproduct ammonia gas 2081 in the lithography tool 300 is monitored using an ammonia gas monitor 330. More specifically, removal of the ammonia gas byproduct 2081 may prevent the byproduct from reacting with the exposed portion 206 aof the exposed photoresist layer 206 before the development process is implemented. In this way, foaming and incomplete reaction between the exposed portion 206 aand the developer 208 are prevented due to the presence of the ammonia gas by-product 2081, resulting in higher product yield and better development resolution and pattern fidelity.In certain embodiments, the ammonia gas monitor 330 is a real-time ammonia gas monitor. More specifically, the ammonia gas monitor 330 is used to monitor, in real time, whether the concentration of the ammonia gas byproduct 2081 in the lithography tool 300 remains below a concentration threshold. That is, the ammonia gas monitor 330 is used to determine whether the concentration of the ammonia gas byproduct 2081 in the lithography tool 300 is lower than such a concentration threshold. When the ammonia gas monitor 330 determines that the concentration of the ammonia gas byproduct 2081 in the lithography tool 300 is lower than such a concentration threshold, the method 100 executes the process step 102 again. When the ammonia gas monitor 330 determines that the concentration of the ammonia gas byproduct 2081 in the lithography tool 300 is higher (i.e., not lower) than such a concentration threshold, the ammonia gas monitor 330 connected to the control module 309 sends an alarm signal to the control module 309 of the lithography tool 300. In some embodiments, upon receiving the alert signal, the control module 309 may control the lithography tool 300 to enter a pause mode, thereby stopping operation of the coating unit 302, the baking unit 303, the exposure unit 304, and / or the developing unit 305 of the lithography tool 300. While the control module 309 controls the lithography tool 300 to enter a pause mode, in some embodiments, the ammonia gas monitor 330 still monitors the concentration of the ammonia gas byproduct 2081 in the lithography tool 300. In certain embodiments, for lithography tool 300 in the pause mode, the act of removing ammonia gas byproduct 2081 from lithography tool 300 continues to decrease the concentration of the ammonia gas. In some embodiments, a gas removal tool (not shown) disposed in the chamber C of the lithography tool 300 may additionally be used to remove the ammonia gas byproduct 2081 from the lithography tool 300. In some embodiments, the method 100 resumes when the ammonia gas monitor 330 has determined that the concentration of the byproduct ammonia gas 2081 in the lithography tool 300 is again lower than such a concentration threshold. In one embodiment, the concentration threshold of the byproduct ammonia gas 2081 is about 2 parts per billion (ppb). In some embodiments, the ammonia gas monitor 330 is disposed proximate to the gas outlet 308 dconnected to the exhaust tool 320.FIG. 4 is a diagram showing the relationship between the processing time and a concentration of an ammonia gas byproduct in a lithography tool of the semiconductor processing system 30 according to some embodiments of the present disclosure. In certain embodiments, in the state in which the ammonia gas byproduct 2081 in the developer supply unit 305 bof the lithography tool 300 is removed by the treatment tool 310, the concentration of the ammonia gas byproduct 2081 in the lithography tool 300 is further lowered until the concentration threshold is reached. With respect to the manufacturing method and the semiconductor processing system described in the above embodiments, it has been shown that the concentration of the ammonia gas byproduct detected by the ammonia gas monitor further decreases from an initial concentration of about 9.4 ppb to a concentration of less than 2.0 ppb (even not more than about 1.0 ppb) over a certain period of time. That is, in the above-described semiconductor processing system for implementing the lithography process over several months, the concentration of the ammonia gas byproduct in the lithography tool detected by the ammonia gas monitor can be significantly reduced to a value even lower than the concentration threshold. On the other hand, if the ammonia gas byproduct is no longer treated and is purged to the environment within the lithography tool, the determined concentration of the ammonia gas byproduct in the lithography tool may be relatively high (e.g., greater than 10.8 ppb).In some embodiments, subsequent to the process step shown in FIG. 2D, the patterned photoresist layer 207 is used as an etch mask and the gate material layer 202 and the dielectric layer 201 are etched by performing an etch process to form a gate dielectric layer 210 and a gate 211 in FIG. 2E. In some embodiments, the etching process includes a dry etching process. Further, in some embodiments, after the gate dielectric layer 210 and the gate 211 are formed, the patterned photoresist layer 207 is removed by performing a wet photoresist etch process or a dry photoresist etch process.Continuing to refer to FIG. 2E, a spacer material layer 212 is formed over the substrate 200, wherein the spacer material layer 212 covers the gate dielectric 210 and the gate 211. In some embodiments, spacer material layer 212 includes SiO 2, SiO x, SiN, other dielectrics, combinations thereof, or multilayers thereof. In some embodiments, spacer material layer 212 is formed by CVD or other methods. In alternative embodiments, spacer material layer 212 may comprise other materials and may be formed using other methods.Referring to FIGS. 2E and 2F, the spacers 214 are formed on the sidewalls of the gate dielectric layer 210 and the gate 211 by performing an etch back process to partially remove the spacer material layer 212. In some embodiments, the etch back process includes an anisotropic etching process. Referring further to FIG. 2F, source and drain regions 216 aand 216 bare formed in the substrate 200 by performing an implantation process. In some embodiments, the implantation process includes performing an ion implantation process. In some embodiments, the implantation process includes implanting dopant ions into the substrate 200 adjacent to the spacers 214 and on both sides of the stack of the gate dielectric layer 210 and the gate 211. In some embodiments, the dopant ions are p-type dopant ions, such as boron, BF 2+ and / or a combination thereof. In some alternative embodiments, the dopant ions are n-type dopant ions, such as phosphorus, arsenic, and / or a combination thereof.Herein, the example manufacturing method for forming the semiconductor device 20 on the substrate 200 will be described. In some embodiments, the semiconductor device 20 is a p-channel metal oxide semiconductor (PMOS) device. In some alternative embodiments, semiconductor device 20 is an n-channel MOS (NMOS) device. As mentioned previously, the semiconductor processing system 30 may be used in the manufacturing method of the semiconductor device 20 for implementing the lithography process.Referring to FIG. 3, the semiconductor processing system 30 including the lithography tool 300 and the treatment tool 310 is shown. In some embodiments, lithography tool 300 includes housing H, coating unit 302, baking unit 303, exposure unit 304, development unit 305, and control module 309, and coating unit 302, baking unit 303, exposure unit 304, and development unit 305 are located within chamber C defined by housing H. In some embodiments, control module 309 is located within chamber C of lithography tool 300. However, the control module 309 may be located outside the chamber C of the lithography tool 300 depending on the design of the system. In some embodiments in FIG. 3, the developing unit 305 includes the process tank 305 aand the developer supplying unit 305 bconnected to the process tank 305 a. In some embodiments, the coating unit 302, the baking unit 303, the exposure unit 304, and the process tank 305 aof the developing unit 305 are installed in a process station 301. In some embodiments, the processing station 301 is connected to the control module 309, and processing and transfer of the substrate or wafer between different units, i.e., the coating unit 302, the baking unit 303, the exposure unit 304, and the process tank 305 aof the developing unit 305 of the processing station 301 may be controlled by the control module 309. In some embodiments, the coating unit 302, the baking unit 303, the exposure unit 304, and the process tank 305 aof the developing unit 305 are connected to each other so that substrates to be processed can be transferred and processed therebetween.In some embodiments, the developer supply unit 305 bis located outside the process station 301. In some embodiments, the developer supply unit 305 bincludes a housing 306, a storage container 307, a developer inlet 308 a, a developer outlet 308 b, a gas inlet 308 c, and a gas outlet 308 d. The treatment tool 310 is located outside the chamber C of the lithography tool 300. The semiconductor processing system 30 further includes the exhaust tool 320 disposed between the developer supply unit 305 bof the lithography tool 300 and the treatment tool 310 so as to connect the developer supply unit 305 bto the treatment tool 310. In one embodiment, the exhaust tool 320 includes an exhaust pipe and is connected to the gas outlet 308 dvia a connector. In another embodiment, the exhaust tool 320 is integrally formed with the gas outlet 308 dof the developer supply unit 305 b.The semiconductor processing system 30 further includes the ammonia gas monitor 330. The ammonia gas monitor 330 is located in the chamber C of the lithography tool 300 and is connected to the control module 309 of the lithography tool 300. As mentioned above, in some embodiments, the ammonia gas monitor 330 is configured to monitor the concentration of the ammonia gas byproduct in the chamber C of the lithography tool 300. In certain embodiments, the ammonia gas monitor 330 is a real-time ammonia gas monitor and is disposed proximate the gas outlet 308 dor proximate the exhaust tool 320.In the above embodiments, for the manufacturing method of the semiconductor device 20 using the semiconductor processing system 30, the ammonia gas byproduct 2081 of the developer 208 generated by the developing unit 305 is removed by discharging the ammonia gas byproduct 2081 from the developing unit 305 of the lithography tool 300 and then held in the treatment tool 310. As a result of the removal of the ammonia gas byproduct 2081 of the developer 208 from the lithography tool 300, the risk of foaming due to the reaction of the ammonia gas byproduct 2081 with the exposed portion 206 ais reduced. Accordingly, the pattern transfer fidelity and product yield of the semiconductor device 20 are improved.According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device is as follows. In a lithography tool, a photoresist layer is formed on a substrate. The photoresist layer is exposed in the lithography tool to form an exposed photoresist layer. The exposed photoresist layer is developed using a developer in the lithography tool to form a patterned photoresist layer. An ammonia gas by-product of the developer is removed from the lithography tool.According to alternative embodiments of the present disclosure, a method of manufacturing a semiconductor device is as follows. A lithography tool having a coating unit, an exposure unit and a developing unit is provided. A photoresist layer is formed on a substrate in the coating unit. The photoresist layer is exposed in the exposure unit to form an exposed photoresist layer. The exposed photoresist layer is developed in the developing unit using a developer to form a patterned photoresist layer. An ammonia gas by-product of the developer is discharged from the developing unit into a processing tool. The ammonia gas byproduct is retained in the treatment tool. A concentration of the ammonia gas byproduct in the lithography tool is monitored.According to still some other alternative embodiments of the present disclosure, a semiconductor processing system includes a lithography tool, a treatment tool, an exhaust tool, and an ammonia gas monitor. The lithography tool comprises a coating unit, an exposure unit and a development unit, which are located in a chamber of the lithography tool. The treatment tool is arranged outside the chamber of the lithography tool. The exhaust tool is arranged between the lithography tool and the treatment tool such that it connects the lithography tool to the treatment tool. The ammonia gas monitor is located in the chamber of the lithography tool and is connected to the lithography tool.

Claims

A method of manufacturing a semiconductor device (20), comprising: forming a photoresist layer (203) on a substrate (200) in a lithography tool (300); exposing the photoresist layer (203) in the lithography tool (300) to form an exposed photoresist layer (206); developing the exposed photoresist layer (206) in the lithography tool (300) using a developer (208) from a developer supply unit (305b) to form a patterned photoresist layer (207); and removing an ammonia gas byproduct (2081) of the developer (208) from the lithography tool (300) via a gas outlet (308d) of the developer supply unit (305b) into a treatment tool (310) outside the chamber of the lithography tool (300).The method of claim 1, wherein a material of the photoresist layer (203) comprises a positive resist material.The method of claim 2, wherein the positive resist material comprises poly(4-t-butoxycarbonyloxystyrene), polymethyl methacrylate (PMMA), or tetrafluoroethylene (TFE).The method of any preceding claim, wherein the developer comprises an aqueous solution of tetramethylammonium hydroxide (TMAH).The method of any preceding claim, further comprising: real-time monitoring a concentration of the ammonia gas byproduct (2081) in the lithography tool (300).The method of claim 5, wherein the removing of the ammonia gas byproduct of the developer from the lithography tool and the monitoring of the concentration of the ammonia gas byproduct in the lithography tool are performed simultaneously.The method of any preceding claim, wherein removing the ammonia gas byproduct (2081) of the developer (208) from the lithography tool (300) comprises: retaining the ammonia gas byproduct (2081) in the treatment tool (310).A method of manufacturing a semiconductor device (20), comprising: providing a lithography tool (300) having a coating unit (302), an exposure unit (304), a developing unit (305) having a developer supplying unit; forming a photoresist layer (203) on a substrate (200) in the coating unit (302); exposing the photoresist layer (203) in the exposure unit (304) to form an exposed photoresist layer (206); developing the exposed photoresist layer (206) using a developer (208) in the developing unit (305) to form a patterned photoresist layer (207); discharging an ammonia gas byproduct (2081) of the developer (208) from the developing unit (305) into a processing tool (310) outside the chamber of the lithography tool (300) via a gas outlet (308d) of the developer supplying unit (305b); retaining the ammonia gas byproduct (2081) in the processing tool (310); and monitoring a concentration of the ammonia gas byproduct (2081) in the lithography tool (300).The method of claim 8, wherein forming a photoresist layer (203) comprises forming a positive resist layer.The method of claim 8 or 9, wherein a material of the photoresist layer (203) comprises poly(4-t-butoxycarbonyloxystyrene), polymethyl methacrylate (PMMA), or tetrafluoroethylene (TFE).The method of any one of claims 8 to 10, wherein the developer comprises an aqueous solution of tetramethylammonium hydroxide (TMAH).The method of any one of claims 8 to 11, wherein the ammonia gas byproduct (2081) is discharged by an exhaust tool (320) into the treatment tool (310) located outside the lithography tool (300).The method of any of claims 8 to 12, wherein retaining the ammonia gas byproduct (2081) comprises providing an adsorptive material in the treatment tool (310) to adsorb the ammonia gas byproduct (2081).The method of any of claims 8 to 13, wherein monitoring a concentration of the ammonia gas byproduct (2081) comprises real-time monitoring the ammonia gas byproduct (2081) using a real-time ammonia gas monitor.A semiconductor processing system comprising: a lithography tool (300), the lithography tool (300) having a coating unit (302), an exposure unit (304), and a developing unit (305) located in a chamber of the lithography tool (300); a processing tool (310) disposed outside the chamber of the lithography tool (300); an exhaust tool (320) disposed between the lithography tool (300) and the processing tool (310) to connect the lithography tool (300) and the processing tool (310); and an ammonia gas monitor (330) located inside the chamber of the lithography tool (300) and connected to the lithography tool (300), wherein the developing unit (305) comprises a developer supply unit (305b), and the developer supply unit (305b) comprises a gas outlet (308d).The semiconductor processing system of claim 15, wherein the exhaust tool (320) comprises an exhaust pipe connecting the gas outlet (308d) to the treatment tool (310).The semiconductor processing system of claim 15 or 16, wherein the ammonia gas monitor (330) is disposed proximate the gas outlet (308d).The semiconductor processing system of any of claims 15 to 17, wherein the ammonia gas monitor (330) is a real-time gas monitor.The semiconductor processing system according to any one of claims 15 to 18, wherein the treatment tool (310) comprises an adsorptive material for adsorbing ammonia gas.

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