Chip-on-film and display device comprising the same

Abstract

Chip-on-film (300-1, ..., 300-k), comprising: Data input pads (332) and gate input pads (334, 336) connected to an integrated IC driver circuit (310) and arranged in a first pad region (330) of a circuit film (320, 320'); and Output contact points (342, 344, 346) of a first to a third group, which are connected to the data driver IC (310) and are arranged in a second contact point region (340) of the circuit film (320, 320'), wherein the data driver IC (310) comprises output buffers (B) of the first to third groups, a first switchable output unit (312) configured to selectively supply a plurality of gate transfer signals (GS) received from the gate input pads (334, 336) and an output from output buffers (B) of the first group to output pads (342) of the first group, and a second switchable output unit (314) configured to selectively supply the plurality of gate transfer signals (GS) and an output from output buffers (B) of the third group to output pads (346) of the third group; and wherein an output from output buffers (B) of the second group is provided to output pads (344) of the second group disposed between output pads (342, 346) of the first and third groups.

Description

BACKGROUNDTechnical field

[0001] The present disclosure relates to a chip-on-film and a display device having the same for selectively outputting gate transfer signals and data outputs to reduce the number of output pads in a data driver integrated circuit (IC). Description of the state of the art

[0002] Recently, representative examples of a display device for displaying an image using digital data include a liquid crystal display (LCD) using a liquid crystal, an organic light-emitting diode (OLED) display using an OLED, and an electrophoretic display (EPD) using electrophoretic particles.

[0003] A gate-in-panel (GIP) driver installed in a panel was used as a gate driver to drive the panel's gate lines. The GIP gate driver receives the required GIP drive signals from a printed circuit board (PCB) via GIP transmission lines onto a chip-on-film (COF) with a data driver integrated circuit (IC) mounted thereon.

[0004] The COF including the gate transmission lines has N gate output pads positioned on a first side, e.g., a left side, of a circuit film, and N gate output pads positioned on a second side, e.g., a right side, of the circuit film to ensure compatibility. Depending on a connection position of a COF, only N gate output pads positioned on one side of the left and right sides are connected to a panel, and N gate output pads positioned on the other side are unused dummy pads.

[0005] US 2014 / 0 132 873 A1 describes a display device connected to a circuit applied to a flexible substrate. It shows a first contact area and a second contact area for output, with the output contact areas comprising a first to third group. A switchable output unit is also shown.

[0006] US 2019 / 0 049 805 A1 shows a data driver IC which is implemented as a chip-on-film and provides gate transfer signals and an output from output buffers at output pads.

[0007] US 2010 / 0 002 180 A1 shows a display device with a chip-on-film driver circuit, data input pads, and gate input pads. The output pads are arranged in three groups.

[0008] However, as the number of gate transfer signals increases, as in an OLED display device, the number of gate output pads formed in each COF also increases, resulting in a problem that the output pad pitch of a COF becomes narrower. This problem is especially prevalent when the size of the COF does not increase.

[0009] When the number of output pads of a COF is increased, a misalignment error may occur during a bonding process of the COF, and therefore, a horizontal width of the COF is increased, but there is a problem that the manufacturing cost increases when a horizontal width of the COF is increased.

[0010] A method of additionally dividing each of the two source PCBs into two parts is proposed to overcome the misalignment error during the connection process, but the additionally divided source PCBs need to be connected to each other via a connector and a flexible cable, and therefore there is a problem that the number of operations in a connection and assembly process is increased, thereby increasing a tact time and manufacturing cost. SUMMARY

[0011] The above objects are achieved by the independent claims. Advantageous embodiments can be derived from the corresponding dependent claims. In various embodiments, the present disclosure provides a chip-on-film (COF) and a display device comprising the same for selectively outputting gate transfer signals and data outputs to reduce the number of output pads in a data driver integrated circuit (IC).

[0012] Additional advantages, objects, and features of the disclosure will be set forth in part in the description which follows, and in part will become apparent to those of ordinary skill in the art upon examination of the following, or may be learned from practice of the disclosure. The objects and other advantages of the disclosure may be realized and attained by the structure particularly pointed out in the written description and claims, as well as the accompanying drawings.

[0013] To achieve these goals and other advantages, and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a chip-on-film comprises data input pads and gate input pads connected to a data driver integrated circuit (IC) and arranged in a first pad region of a circuit film, and output pads of a first to third group connected to the data driver IC and arranged in a second pad region of the circuit film, the data driver IC having output buffers of a first to a third group, a first switchable output unit configured to selectively supply a plurality of gate transfer signals received from the gate input pads and an output from output buffers of a first group to output pads of the first group, and a second switchable output unit configuredselectively supplying a plurality of gate transfer signals and an output from output buffers of a third group to output pads of the third group; and wherein an output from output buffers of the second group is supplied to output pads of a second group arranged between output pads of the first and third groups.

[0014] The first switchable output unit may comprise multiplexers (MUXs) of a first group configured to select the plurality of gate transfer signals or the output of the output buffers of the first group in response to an enable signal, and to deliver the selected signal or the output to the output pads of the first group. The second switchable output unit may comprise MUXs of a second group configured to select the plurality of gate transfer signals or the output of the output buffers of the third group in response to an inverted enable signal obtained by inverting the enable signal, and to deliver the selected signals or the output to the output pads of the third group.

[0015] When the first switchable output unit selects the plurality of gate transfer signals and supplies the selected signals to the output pads of the first group, the second switchable output unit may select the output of the output buffers of the third group and the output buffers of the second group, and the third group outputs data via the output pads of the second group and the third group.

[0016] When the second switchable output unit selects the plurality of gate transfer signals and supplies the selected signals to the output pads of the third group, the first switchable output unit may select the output of the output buffers of the first group and the output buffers of the first group, and the second group outputs data through the output pads of the first group and the second group.

[0017] The data driver IC may include digital-to-analog converters (DACs) of the first to third groups connected to the output buffers of the first to third groups for respective channels, latches of the first to third groups connected to the DACs of the first to third groups for respective channels, and a shift register having stages of a first to a third group connected to the latches of the first to third groups for respective channels to provide a strobe signal, and wherein the shift register may further include a first demultiplexer (DEMUX) configured to supply a latch start pulse to a first stage of the first group or a first stage of the second group in response to the enable signal, and a second DEMUX configured to output a strobe signal of a last stage from the second group to a next-end data driver IC as a transfer output.or supplying the scanning signal to a first stage of the third group in response to the reversed enable signal.

[0018] When the first switchable output unit provides the plurality of gate transfer signals to the output pads of the first group, the stages of the second group and the third group may perform a shift operation according to a control of the first and second DEMUX to latch pixel data in the latches of the second group and the third group, and supply the latched pixel data to the output pads of the second and third groups via DACs and the output buffers of the second and third groups.

[0019] When the second switchable output unit provides the plurality of gate transfer signals to the output pads of the third group, stages of the first and second groups may perform a shift operation according to a control of the first and second DEMUXes to latch pixel data in the latches of the first and second groups, and provide the latched pixel data to the output pads of the first and second groups via DACs and output buffers of the first and second groups.

[0020] The gate input pads may include at least any group of gate input pads of a first group positioned outside one side of the data input pads and gate input pads of the second group positioned outside the other side, and the first switchable output unit may be connected to the gate input pads of the first group, and the second switchable output unit is connected to the gate input pads of the second group, or the first and second switchable output units are commonly connected to the gate input pads of any group of the first and second groups via an input terminal of the data driver IC.

[0021] In another aspect of the present disclosure, a display device includes a panel having a pixel array, first and second gate drivers connected to opposite sides of the panel for driving gate lines of the pixel array, and a plurality of chips-on-film in which a plurality of data driver ICs for driving data lines of the pixel array are installed on a plurality of circuit films, respectively, and connected between the panel and a printed circuit board (PCB), wherein a first chip-on-film connected to the first gate driver of the plurality of chips-on-film and a second chip-on-film connected to the second gate driver can transmit a plurality of gate transmission signals using the aforementioned chips-on-film. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain the principle of the disclosure. In the drawings: Fig. 1 is a schematic block diagram showing a configuration of a display device according to an embodiment of the present disclosure; Fig. 2 is a schematic diagram showing a configuration of a COF according to an embodiment of the present disclosure; Fig. 3 is a diagram illustrating an output setting of a switchable output applied to a first COF, according to an embodiment of the present disclosure; Fig. 4 is a diagram illustrating an output setting of a switchable output applied to a final COF, according to an embodiment of the present disclosure; Fig. 5 is a schematic diagram showing a configuration of a COF according to another embodiment of the present disclosure; Fig. 6 is a circuit block showing an internal configuration of data driver ICs according to an embodiment of the present disclosure; and Fig. 7 is a schematic system configuration diagram showing a configuration of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to the preferred embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.

[0024] Fig. 1 is a schematic block diagram showing a configuration of a display device according to an embodiment of the present disclosure.

[0025] Referring to Fig. 1, the display device may include a panel 100, gate-in-panel (GIP) type drivers 200 and 210, a data driver, source printed circuit boards (PCBs) 500 and 510, and so on.

[0026] The panel 100 can display an image through a pixel array PA in which subpixels are arranged in a matrix. A basic pixel can have at least three subpixels capable of representing white using a color mixture of white W, red R, green G, and blue B subpixels. For example, the basic pixel can have subpixels of an R / G / B combination or subpixels of a W / R / G / B combination. The basic pixel can have subpixels of an R / G / B combination, subpixels of a W / R / G combination, subpixels of a B / W / R combination, and subpixels of a G / B / W combination.

[0027] The panel 100 may be of various display panels, such as a liquid crystal display (LCD) panel and an organic light-emitting diode (OLED) panel, and it may be a touch panel having both a touch sensing function and a display function.

[0028] The panel 100 may have first and second GIP gate drivers 200 and 210 installed therein. The first and second gate drivers 200 and 210 may be positioned in first and second non-active regions of the panel 100, respectively, to drive gate lines included in the pixel array PA. The first and second gate drivers 200 and 210 may simultaneously provide gate signals to opposite ends of each gate line to reduce the delay of the gate signals. Therefore, the first gate driver 200 may be positioned in a first non-active region of the panel 100, positioned adjacent to a first side, e.g., a left side, of the pixel array PA, while the second gate driver 210 may be positioned in a second non-active region of the panel 100, located adjacent to a second side, e.g., a right side, of the pixel array PA. This way the first side can be opposite the second side.

[0029] The data driver may include multiple chips-on-film (COFs) 300 in which multiple data driver integrated circuits (ICs) 310 are separately installed on multiple circuit films 320.

[0030] The plurality of COFs 300 may be connected between the first and second source PCBs 500 and 510 and the panel 100. A first pad region of each of the plurality of COFs 300 may include a plurality of input pads bonded and connected to pad regions of the first and second source PCBs 500 and 510 by an anisotropic conductive film (ACF) using automated tape bonding (TAB). A second pad region of each of the plurality of COFs 300 may include a plurality of output pads bonded and connected to the pad regions of the panel 100 by an ACF using a TAB process.

[0031] The first and second source PCBs 500 and 510 may be connected to a control PCB 400 through first and second flat flexible cables (FFCs) 410 and 420. A timing controller for generating a plurality of data control signals and outputting the data control signals with image data, a level shifter for generating and outputting a plurality of GIP drive signals under the control of the timing controller, and drive circuits, such as a power management circuit for generating and outputting a plurality of drive voltages required for a display device, may be installed on the control PCB 400. The level shifter may be installed on the first and second source PCBs 500 and 510.

[0032] The plurality of data driver ICs 310 can receive a plurality of data control signals and image data from the control PCB 400 through the FFCs 410 and 420 and the source PCBs 500 and 510, convert the received image data into an analog data signal, and supply the analog data signal to the data lines of the panel 100.

[0033] If the panel 100 is an organic light-emitting diode (OLED), the plurality of data driver ICs 310 may include a detection unit for detecting the pixel current indicating the electrical characteristics (threshold voltage and mobility of a driving TFT, and a threshold voltage of an OLED device) of each subpixel as a current or voltage under the control of the timing controller, converting the pixel current into digital detection data, and supplying the digital detection data to the timing controller. The timing controller may update a compensation value of each subpixel using the detection data of each subpixel received from the plurality of data driver ICs 310. The timing controller may compensate image data corresponding to each subpixel with a corresponding compensation value to compensate for brightness unevenness caused by a characteristic difference between subpixels.

[0034] Gate transfer signals generated by the level shifter of the control PCB 400 may be transmitted through the first FFC 410 and the first source PCB 500 to a first COF 300-1 positioned at one end of one side, and may be transmitted through the second FFC 420 and the second source PCB 510 to a last COF 300-K

[0035] For example, the gate transfer signals may include a plurality of scan clocks used as a start pulse, a reset pulse, an alternating current (AC) drive voltage for an odd frame, an AC drive voltage for an even frame, and a scan signal for driving the gate lines, and may further include a plurality of carrier clocks for controlling a shift operation of the gate drivers 200 and 210. If the panel 100 is an OLED panel, the gate transfer signals may further include a plurality of sense clocks used as a sense signal for driving sense gate lines, a row signal used for selecting gate lines for sense, and so on.

[0036] The first and last COFs 300-1 and 300-K of the plurality of COFs 300 may further include a gate transfer path including the circuit films 320 and the data driver ICs 310 to transfer a plurality of gate transfer signals received from the source PCBs 500 and 510 through the gate transfer path to the first and second gate drivers 200 and 210 of the panel 100.

[0037] In particular, the first and last COFs 300-1 and 300-K can selectively output N gate transmission signals and N data outputs from opposing output units through the data driver IC 310 to remove N redundant gate dummy output pads. Accordingly, in the first and last COFs 300-1 and 300-K according to an embodiment of the present disclosure, the number of gate output pads can be reduced from 2N according to the prior art to N to reduce the total number of output pads from M+2N according to the prior art to M+N (M is the number of data outputs).

[0038] The Fig. 2 to 4 are schematic diagrams showing a COF structure according to an embodiment of the present disclosure.

[0039] Referring to the Fig. 2 to 4, the COFs 300-1 and 300-K, each having a gate transfer path according to an embodiment of the present disclosure, may include a first pad region 330 of the circuit films 320 bonded and connected to a pad region of the source PCBs 500 and 510, and a second pad region 340 of the circuit films 320 bonded and connected to a pad region of the panel 100. The COFs 300-1 and 300-K may further include first connecting lines 350 for separately connecting contact pads 332, 334, and 336 of the first contact pad region 330 to terminals of the data driver ICs 310 and second connecting lines 360 for separately connecting terminals of the data driver IC 310 to contact pads 342, 344, and 346 of the second contact pad region 340.

[0040] The first pad region 330 of the circuit films 320 may include data input pads 332 and gate input pads 334 and 336 connected to the source PCB 500 or 510. The gate input pads 334 and 336 may include N gate input pads 334 of a first group and N gate input pads 336 of a second group for transmitting N gate transfer signals. Depending on a connection position of the COFs 300-1 and 300-K, only any one group of the gate input pads 334 and 336 of the first and second groups may be connected to the source PCB 500 or 510, and the other group may be a dummy input pad. The N gate input pads 334 of the first group may be arranged on one side (e.g., the left side) of the first pad region 330, the N gate input pads 336 of the second group may be arranged on the other side (e.g.,The gate input pads 332 may be arranged on the right side (the right side), and the data input pads 332 may be arranged between the first and second groups 334 and 336. One side may be opposite the other side. Other arrangements of gate input pads are not excluded. IC output pads (not shown) for transmitting output signals of the data driver IC 310 to the source PCB 500 or 510 may also be arranged in the first pad area 330.

[0041] The first connecting lines 350 arranged between the first contact pad region 330 and the data driver IC 310 can separately connect the input contact pads 332, 334 and 336 of the first contact pad region 330 and the input contact terminals of the data driver IC 310.

[0042] The second connecting lines 360, which are arranged between the data driver IC 310 and the second contact pad region 340, can separately connect the output terminals of the data driver IC 310 to the output contact pads 342, 344 and 346 of the second contact pad region 340.

[0043] The second pad region 340 of the circuit film 320 may include the first to third group output pads 342, 344, and 346 connected to the panel 100. (MN) output pads 344 of the second group, positioned in a central portion of the second pad region 340, may receive (MN) data outputs from the data driver ICs 310 and transmit the data outputs to the panel 100. N output pads 342 of the first group and N output pads 346 of the third group, positioned on opposite sides of the second pad region 340, may receive N gate transfer signals or N data outputs from each of the first and second switchable output units 312 and 314 installed in the data driver IC 310, and supply the received signals or outputs to the panel 100.

[0044] If the first switchable output unit 312 and the output pads 342 of the first group provide N gate transfer signals to the panel 100, the second switchable output unit 314 and the output pads 346 of the third group, together with the output pads 344 of the second group, can provide M data outputs to the panel 100.

[0045] On the other hand, if the second switchable output unit 314 and the output pads 346 of the third group provide N gate transfer signals to the panel 100, the first switchable output unit 312 and the output pads 342 of the first group, together with the output pads 344 of the second group, provide M data outputs to the panel 100.

[0046] Referring to the Fig. 3 and Fig. 4, each of the first and second switchable output units 312 and 314 installed in the data driver IC 310 may include multiplexers (MUXs) 313 and 315 for respective output channels for selectively outputting a gate transfer signal GS and a data output of an output buffer B. The first switchable output unit 312 may be controlled by an enable signal EN, and the second switchable output unit 314 may be controlled by an inverted enable signal / EN obtained by inverting the enable signal EN, and therefore the first and second switchable output units 312 and 314 may select and output opposite inputs.

[0047] The first switchable output unit 312 may include N first MUXs 313 controlled by the enable signal EN to select N gate transfer signals GSs received by the gate input pads 334 of the first group and output the N gate transfer signals GSs to the output pads 342 of the first group, or to select N data outputs received by N output buffers Bs and output the N data outputs to the output pads 342 of the first group.

[0048] The second switchable output unit 314 may include N second MUXs controlled by the inverted enable signal / EN to select N gate transfer signals GSs received via the gate input pads 336 of the second group and output the N gate transfer signals GSs to the output pads 346 of the third group, or to select N data outputs received from N output buffers Bs and output the N data outputs to the output pads 346 of the third group.

[0049] Referring to the Fig. 1 and Fig. 3, the first COF 300-1, bonded to a side portion of the pad area of ​​the panel 100 in the X-axis direction, can select N data outputs via the first switchable output unit 312 and output the N data outputs to the output pads 342 of the first group, and can select N gate transfer signals GSs and output the N gate transfer signals GSs via the second switchable output unit 314 to the output pads 346 of the third group. Accordingly, the first COF 300-1 can supply M data outputs to the panel 100 via the M output pads 342 and 344 of the first and second groups, and supply N gate transfer signals to the first gate driver 200 of the panel 100 via the N output pads 346 of the third group.

[0050] Referring to the Fig. 1 and Fig. 4, the last COF 300-K bonded to the other side portion of the pad area of ​​the panel 100 in the X-axis direction can select N gate transfer signals GSs and output the N gate transfer signals GSs to the output pads 342 of the first group via the first switchable output unit 312, and can select N data outputs and output the N data outputs to the output pads 346 of the third group via the second switchable output unit 314. Accordingly, the last COF 300-K can supply M data outputs to the panel 100 via the M output pads 346 and 344 of the third group and the second group, and supply N gate transfer signals to the second gate driver 210 of the panel 100 via the N output pads 342 of the first group.

[0051] Thus, according to an embodiment of the present disclosure, the first and last COFs 300-1 and 300-K can selectively output N gate transmission signals and N data outputs via the first and second switchable output units 312 and 314 installed in the data driver IC 310 to remove N gate dummy output pads compared to the prior art, and therefore, a total number of output pads can be reduced from M+2N according to the prior art to M+N.

[0052] Fig. 5 is a schematic diagram showing a configuration of a COF according to another embodiment of the present disclosure.

[0053] Referring to Fig. 5, the COF structure is configured such that gate transmission lines 352 and 354, which are connected to the N gate input pads 334 of the first group via the first connection lines 350 and are positioned in a data driver IC 310', branch into the data driver IC 310'. Accordingly, the first switchable output unit 312 may be connected to the input pads 334 of the first group via the N gate transmission lines 352 of the first group, and the second switchable output unit 314 may be connected to the input pads 334 of the first group through the N gate transmission lines 354 of the second group branching from the first group 352.

[0054] Accordingly, compared to Fig. 2, the N gate input pads 336 of the Fig. 2 shown second group continues to be influenced by the Fig. 5, and therefore the number of gate input pads 334 can also be reduced from 2N to N.

[0055] Fig. 6 is a circuit block showing an internal configuration of the data driver IC 310 having a gate transfer path installed therein according to an embodiment of the present disclosure.

[0056] Referring to Fig. 6, the data driver IC 310 having a gate transfer path installed therein may include a shift register 10, a first latch array 20, a second latch array 30, a digital-to-analog converter (hereinafter referred to as DAC) array 40, an output buffer array 50, and the first and second switchable output units 312 and 314.

[0057] The shift register 10 may have (M+N) stages ST1 to ST(M+N), may input a source start pulse SSP or a transfer output EIO1 received from a data driver IC of the previous end as a latch start pulse, and may sequentially output M sampling signals while shifting the latch start pulse according to a source shift clock SSC.

[0058] In order to select M channels of the (M+N) stages STs, the shift register 10 may further comprise a first demultiplexer (hereinafter referred to as DEMUX) 12 controlled by an enable signal EN and a second DEMUX 14 controlled by the inverse enable signal / EN.

[0059] The first DEMUX 12 can supply the latch start pulse SSP or EIO1 to the first stage ST1 of the first group G1 or the (N+1)th stage ST(N+1) of the second group G2 in response to the enable signal EN. The second DEMUX 14 can output a strobe signal of the M-th stage ST(M) of the second group G2 as a transfer output EIO2 for latch start of a next-end data IC in response to the reverse enable signal / EN, or can supply the strobe signal to the (M+1)th stage ST(M+1) of the third group G3. Accordingly, a stage with M channels from the first stage ST1 to the M-th stage ST(M) of the first and second groups G1 and G2 can perform a shift operation through the first and second DEMUXs 12 and 14, or a stage with M channels from the (N+1)-th stage ST(N+1) to the (M+N)-th stage ST(M+N) of the second and third groups G2 and G3 can perform a shift operation to sequentially output M sampling signals.

[0060] The first latch array 20 may include first latches LH1 of (M+N) channels, and the second latch array 30 may include second latches LH2 of (M+N) channels. The first latches LH1 of the first and second groups G1 and G2, which receive M sampling signals from the first and second groups G1 and G2 of the shift register 10, can sequentially sample and latch M pixel data, and then can simultaneously output the M pixel data through the second latches LH2 of M channels of the first and second groups G1 and G2. The first latches LH1 of the second and third groups G2 and G3, which receive M sampling signals from the second and third groups G2 and G3 of the shift register 10, can sequentially sample and latch M pixel data, and then can simultaneously store the M pixel data through the second latches LH2 of the M channels of the second and third groups G2 and G3.

[0061] The DAC array 40 may include DACs of (M+N) channels, and the output buffer array 50 may include output buffers of (M+N) channels. The DAC array 40 may convert pixel data of M channels received from the second latch array 30 into analog data voltages using grayscale voltages obtained by dividing reference gamma voltages, and output the analog data voltages through the output buffers Bs of M channels. DACs of the first and second groups G1 and G2 may convert pixel data received from the second latches LH2 of the first and second groups G1 and G2 into analog data voltages, and output the analog data voltages to the output buffers Bs of the first and second groups G1 and G2.DACs of the second and third groups G2 and G3 can convert pixel data received from the second latches LH2 of the second and third groups G2 and G3 into analog data voltages, and output the analog data voltages to output buffers Bs of the second and third groups G2 and G3.

[0062] The first switchable output unit 312 may include the first MUX 313 controlled by the enable signal EN to select the N gate transfer signals GS-1 to GS-N received from the source PCB 500 or 510 and output the N gate transfer signals GS-1 to GS-N to the output pads 342 of the first group, or to select N data outputs of the first group received from N output buffers Bs of the first group G1 and output the N data outputs to the output pads 342 of the first group.

[0063] The second switchable output unit 314 may include the N second MUXes 315 controlled by the reverse enable signal / EN to select N gate transfer signals GSs received from the source PCB 500 or 510 and output the N gate transfer signals GSs to the third group output pads 346, or to select N third group data outputs received from the N third group output buffers Bs and output the N data outputs to the third group output pads 346.

[0064] (MN) Output buffers of the second group G2, arranged between the first and third groups, can output (MN) data outputs of the second group to the output pads 344 of the second group.

[0065] For example, when the enable signal EN is high and the converse enable signal / EN is low, the first switchable output unit 312 can select and output the N gate transfer signals GS-1 to GS-N, and therefore the output pads 342 of the first group can output the N gate transfer signals GS-1 to GS-N to the panel 100.The stages ST(N+1) to ST(M+N) of the (N+1)th to (M+N)th channels of the second and third groups G2 and G3 can output M sampling signals according to the control of the first and second DEMUXes 12 and 14, and therefore, through the latches LH1 and LH2 and DACs of the (N+1)th to (M+N)th channels and the output buffers Bs of the second and third groups G2 and G3, M pixel data can be output, and in addition, the second switchable output unit 314 can select and output N pixel data output from the N output buffers Bs of the third group G3, and therefore the output pads 344 and 346 of the second and third groups can output M pixel data to the panel 100.

[0066] When the enable signal EN is low and the converse enable signal / EN is high, the second switchable output unit 314 can select and output the N gate transfer signals GS-1 to GS-N, and therefore the output pads 346 of the third group can output the N gate transfer signals GS-1 to GS-N to the panel 100.The stages ST1 to ST(M) of the first to M-th channels of the first and second groups G1 and G2 can output M sampling signals according to the control of the first and second DEMUXes 12 and 14, and therefore, through the latches LH1 and LH2 and the DAC of the first to M-th channels and the output buffers Bs of the first and second groups G1 and G2, M pixel data can be output, and in addition, the first switchable output unit 312 can select and output N pixel data output from N output buffers B of the first group G1, and therefore the output pads 342 and 344 of the first and second groups can output M pixel data to the panel 100.

[0067] Fig. 7 is a schematic system configuration diagram showing a configuration of a display device according to another embodiment of the present disclosure.

[0068] The Fig. The display device shown in Figure 7 differs from that shown in Fig. 1 only in that the gate drivers 200 and 210 have the plurality of gate ICs 220, and therefore, a description of the repeated components of Fig. 7 omitted.

[0069] A plurality of gate COFs 250 in which the plurality of gate ICs 220 are installed on the plurality of circuit films 240 may be bonded and connected via ACF to opposite sides or a single-sided portion of the panel 100.

[0070] Gate transfer signals generated by a timing controller of the control PCB 400 may be transmitted through the first FFC 410 and the first source PCB 500 to the first COF 300-1 positioned at one end of one side, and may be transmitted through the second FFC 420 and the second source PCB 510 to the last COF 300-K positioned at one end of another side.

[0071] As above with reference to the Fig. 2 to 6, the first and last COFs 300-1 and 300-K may each further include a gate transmission path including the circuit film 320 and the data driver IC 310, and may transmit a plurality of gate transmission signals received from the source PCB 500 or 510 to the panel 100 through a gate transmission path. The panel 100 may transmit a plurality of gate transmission signals to the gate IC 220 on the gate COF 250 via a transmission path.

[0072] As in the Fig.As shown in FIGS. 2 to 6, the first and last COFs 300-1 and 300-K can each selectively output N gate transmission signals and N data outputs from opposing output units through the data driver IC 310 to remove N redundant gate dummy output pads. Accordingly, the first and last COFs 300-1 and 300-K can each reduce the number of gate output pads from 2N according to the prior art to N to reduce the total number of output pads from M+2N according to the prior art to M+N (M is the number of data outputs).

[0073] Thus, a COF according to an embodiment of the present disclosure can selectively output gate transfer signals and data outputs using a switchable output unit in a driver IC to remove a gate dummy pad, thereby reducing the number of output pads.

[0074] Accordingly, even if a horizontal width of a COF is not increased, a pitch of an input pad can be stably ensured, and therefore, a misalignment error during the bonding process of a COF and a printed circuit board can be minimized, and manufacturing costs can be reduced.

[0075] To overcome a misalignment error of a COF and a source PCB, it is not necessary to divide each of two source PCBs into multiple pieces, and therefore connection and assembly processes are performed in a simple manner, reducing the fixing time and manufacturing cost.

[0076] A COF according to an embodiment of the present disclosure can be applied to any display device such as an OLED display device and an LCD.

[0077] It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the scope of the disclosure. Therefore, it is intended that the present disclosure cover the modifications and variations of this disclosure, provided they fall within the scope of the appended claims and their equivalents.

[0078] The various embodiments described above may be combined to provide further embodiments. These and other changes may be made to the embodiments in light of the above detailed description.

Claims

[1] Chip-on-film (300-1, ..., 300-k), comprising: Data input pads (332) and gate input pads (334, 336) connected to an integrated IC driver circuit (310) and arranged in a first pad region (330) of a circuit film (320, 320'); and Output contact points (342, 344, 346) of a first to a third group, which are connected to the data driver IC (310) and are arranged in a second contact point region (340) of the circuit film (320, 320'), wherein the data driver IC (310) comprises output buffers (B) of the first to third groups, a first switchable output unit (312) configured to selectively supply a plurality of gate transfer signals (GS) received from the gate input pads (334, 336) and an output from output buffers (B) of the first group to output pads (342) of the first group, and a second switchable output unit (314) configured to selectively supply the plurality of gate transfer signals (GS) and an output from output buffers (B) of the third group to output pads (346) of the third group; and wherein an output from output buffers (B) of the second group is provided to output pads (344) of the second group disposed between output pads (342, 346) of the first and third groups. [2] The chip-on-film according to claim 1, wherein the first switchable output unit (312) comprises multiplexer MUXs (313) of a first group configured to select the plurality of gate transfer signals (GS) or select the output of the output buffers (B) of the first group in response to an enable signal (EN), and supply the selected signal or output to the output pads (342) of the first group; and wherein the second switchable output unit (314) comprises MUXs (315) of a second group configured to select the plurality of gate transfer signals (GS) or select the output of the output buffers (B) of the third group in response to an inverted enable signal ( / EN) obtained by inverting the enable signal (EN), and output the selected signals or output to the output pads (346) of the third group. [3] The chip-on-film according to claim 2, wherein, when the first switchable output unit (312) selects the plurality of gate transfer signals (GS) and supplies the selected signals to the output pads (342) of the first group, the second switchable output unit (314) selects the output of the output buffers (B) of the third group, and the output buffers (B) of the second group and the third group output data via the output pads (344, 346) of the second group and the third group, respectively, or, when the second switchable output unit (314) selects the plurality of gate transfer signals (GS) and supplies the selected signals to the output pads (346) of the third group, the first switchable output unit (312) selects the output of the output buffers (B) of the first group, and the output buffers (B) of the first group and the second group output data via the output pads (342, 344) of the first group or the second group output data. [4] Chip-on-film according to claim 2 or 3, wherein the data driver IC (310) comprises: Digital-to-analog converters DACs (40) of the first to third groups connected to the output buffers (B) of the first to third groups for respective channels; Latches (20, 30) of the first to third groups connected to the DACs (40) of the first to third groups for respective channels; and a shift register (10) comprising stages (ST) of the first to third groups connected to the latches (20, 30) of the first to third groups for respective channels to provide a sampling signal; and wherein the shift register (10) further comprises: a first demultiplexer DEMUX (12) configured to supply a first latch start pulse to a first stage of stages of the first group or a first stage of stages of the second group in response to the enable signal (EN); and a second DEMUX (14) configured to output, in response to the reversed enable signal ( / EN), a strobe signal of a last stage of the stages of the second group to a data drive IC (310) at the next end as a transmission output, or to supply the strobe signal to a first stage of the stages of the third group. [5] The chip-on-film of claim 4, wherein, when the first switchable output unit (312) supplies the plurality of gate transfer signals (GS) to the output pads (342) of the first group, stages (ST) of the second group and the third group perform a shift operation according to a control of the first and second DEMUX (12, 14) to latch pixel data in the latches (20, 30) of the second group and the third group and supply the latched pixel data via DACs (40) to the output pads (344, 346) of the second and the third group and output the output buffers (B) of the second and third groups, respectively. [6] A chip-on-film according to claim 4 or 5, wherein, when the second switchable output unit (314) supplies the plurality of gate transfer signals (GS) to the output pads (346) of the third group, stages (ST) of the first and second groups perform a shift operation under the control of the first and second DEMUX (12, 14) to latch pixel data in the latches (20, 30) of the first and second groups and supply the latched pixel data via DACs to the output pads (342, 344) of the first and second groups and output the output buffers (B) of the first and second groups, respectively. [7] The chip-on-film of any one of claims 3 to 6, wherein the gate input pads (334, 336) comprise at least any group of gate input pads (334) of a first group positioned outside one side of the data input pads (332) and gate input pads (336) of a second group positioned outside the other side of the data input pads (332); and wherein the first switchable output unit (312) is connected to the gate input contact points (334) of the first group and the second switchable output unit (314) is connected to the gate input contact points (336) of the second group, or the first and second switchable output units (312, 314) are jointly connected via an input terminal of the data driver IC (310) to the gate input contact points (334, 336) of any one of the first and second groups. [8] Display device comprising: a panel (100) comprising a pixel array (PA); a first and a second gate driver (200, 210) connected to opposite sides of the panel (100) for driving gate lines of the pixel array (PA); and a plurality of chips-on-film (300) in which a plurality of integrated ICs (310) for driving data lines of the pixel array are installed on a plurality of circuit films (320) respectively, and which are connected between the panel (100) and a printed circuit board (500, 510), wherein a first chip-on-film (300-1, ..., 300-k) connected to the first gate driver (200) of the plurality of chips-on-films (300) and a second chip-on-film (300-1, ..., 300-k) connected to the second gate driver (210) of the plurality of chips-on-films (300) are chips-on-films according to any one of claims 1 to 7. [9] The display device according to claim 8, wherein each of the first and second chip-on-films is connected to the PCB (500, 510) through the first pad region and is connected to the panel (100) through the second pad region; and wherein the first and second gate drivers (200, 210) are installed in the panel (100) or are configured to be connected to the panel (100) with a plurality of gate chips-on-films having a plurality of gate driver ICs separately installed thereon.

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