Read amplifier with negative threshold detection for non-volatile memory

Abstract

Device comprising: a transistor (1115, 1215); a first switch (1111, 1211) and a second switch (1113, 1213) connected in series between a selected memory cell (1101, 1201) and the transistor, wherein a control gate of the transistor is connected to a node (BLI) between the first switch and the second switch, wherein the first switch (1111, 1211) and the second switch (1113, 1213) are configured to discharge the selected memory cell through the transistor (1115, 1215) when they are simultaneously switched on, and are configured to set the control gate of the transistor (1115, 1215) to float at a voltage level at the node between the first switch (1111, 1211) and the second switch (1113, 1213) when the first switch and the second switch are simultaneously switched off; and a third switch (1121, 1221) connected between a read node (SEN) and the transistor (1115, 1215), wherein the third switch (1121, 1221) is configured to discharge the read node through the transistor, wherein the control gate of the transistor is set to float on the voltage level at the node between the first switch (1111, 1211) and the second switch (1113, 1213).

Description

BACKGROUND

[0001] Semiconductor memory is widely used in various electronic devices such as mobile phones, digital cameras, PDAs, medical electronics, portable computing devices, servers, solid-state drives, stationary computing devices, and other equipment. Semiconductor memory can be either non-volatile or volatile. Non-volatile memory allows information to be stored and retained even when the memory is not connected to a power source (such as a battery).

[0002] US 2006 / 0 104 112 A1 relates to an electrically erasable programmable read-only memory (EEPROM), wherein, in particular, a data reprogramming / recovery circuit is provided that temporarily stores data to be programmed or data to be recovered for a cache function or a multi-level logic function. US 2008 / 0 253 195 A1 relates to a semiconductor memory device with a MOS transistor having a charge accumulation layer and a control gate, and an associated data readout method. US 2011 / 0 188 317 A1 relates to a non-volatile memory with fast binary programming and reduced power consumption. US 2014 / 0269094A1 relates to a semiconductor memory device in which a read module is provided for each bit line, wherein each read module contains a read transistor configured to turn on and off to indicate whether data is stored in a memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Elements with the same numbers refer to common components in the different figures. Fig. 1A is a functional block diagram of a storage device. Fig. 1B is a block diagram that illustrates an example of a storage structure. Fig. Figure 2 is a block diagram that represents one embodiment of a storage system. Fig. Figure 3 is a perspective view of a section of an embodiment of a monolithic three-dimensional storage structure. Fig. Figure 4 is a schematic representation of a plurality of NAND strings. Fig. Figure 5 shows different embodiments of a section of a three-dimensional storage array with a vertical intersection structure. Fig. Figure 6 shows threshold voltage distributions in a three-bit-per-cell implementation form. Fig. 7A is a flowchart that describes one embodiment of a process for programming / writing. Fig. 7B is a flowchart that describes one embodiment of a process for programming / writing data into memory cells connected by a common word line. Fig. 7C represents a word line voltage during programming / writing and verification operations. Fig. Figure 8 is a flowchart that describes one embodiment of a process for reading data from non-volatile memory cells. Fig. 9A and Fig. 9B represents a window of thresholds to which memory cells can be programmed, including negative thresholds. Fig. 10A-10C represent different techniques for reading memory cells with negative threshold voltage values. Fig. 11 presents some elements of an embodiment of a read amplifier that can be used to perform a read operation using the in Fig. 10C illustrated techniques to be carried out. Fig. Figure 12 is a more detailed representation of an embodiment for the reading amplifier of Fig. 11. Fig. 13 presents an embodiment for some of the control waveforms for a read operation using the embodiment of Fig. 12 dar. Fig. 14 is a flowchart that shows an embodiment of a process for a read operation for the read amplifier of Fig. 12 using the waveforms of Fig. 13 describes. DETAILED DESCRIPTION

[0004] According to the invention, a device and a method with the features of the independent claims are provided; dependent claims relate to preferred embodiments.

[0005] To increase the amount of data stored in a non-volatile storage device, data can be stored in a multi-level cell (MLC) format, where a single memory cell can be programmed to multiple different states, allowing each cell to hold more than one bit of data. In memory cells where different data states correspond to different threshold voltage (Vt) values, this involves splitting the range or window of available Vt values ​​into a number of ranges corresponding to the different data states. To store more states per cell, the Vt range associated with each state must be made smaller, the window size increased, or both. The Vt window size can be increased by extending the window further into negative Vt values, thus allowing for multiple states with negative or non-positive Vt values.However, for this to be useful, the storage device must be able to distinguish between different non-positive Vt states.

[0006] Reading negative Vt states using most standard measurement techniques and read amplifier structures has several limitations. In a typical measurement setup, the control gate of a memory cell is biased by a read voltage, and a bit line connected to a read amplifier discharges through the memory cell to a source line, the discharge amount depending on the value of the read voltage relative to the memory cell's Vt. Under this common setup, reading negative Vt states uses negative read voltages; however, negative voltages are typically not available on a memory chip, and introducing them presents complications. Alternatively, negative Vt states can be read by raising the source voltage, but this approach is usually limited to a relatively shallow negative Vt range.To enable reading further down in the negative Vt range, read amplifier structures and techniques are introduced below, in which the source is discharged through a selected memory cell into the bit line and the read amplifier, and the usual direction of current flow through the selected memory cell is reversed in a read operation.

[0007] Specifically, a read amplifier structure and measurement techniques are described in which, in a first phase, the source line is discharged through a selected memory cell to the corresponding bit line and then into the read amplifier. The amount of current discharged in this phase depends on the conductivity of the memory cell, which in turn depends on the word line voltage applied to the control gate of the selected memory cell relative to its threshold voltage. In the case of a discharge transistor, its control gate is connected to the discharge path of the memory cell during the first phase, so that the conductivity of the discharge transistor reflects the conductivity of the selected memory cell. The control gate of the discharge transistor is then set to float at this level.In a second phase, a read node is discharged by the discharge transistor: since the conductivity of the discharge transistor reflects the conductivity of the selected memory cell, the rate at which the read node discharges reflects the conductivity of the memory cell. After the read node has discharged during a read period, the level on the read node is temporarily stored for the read result.

[0008] To improve the accuracy of the read operation, elements can be included in the read amplifier to reduce noise levels. To reduce noise in the control gate of the discharge transistor during phase transitions, a decoupling capacitor can be connected to the control gate. The capacitor can also be biased to adapt to operating conditions, such as temperature, and variations in device processing. To reduce noise in the source node of the discharge transistor, an auxiliary holding current can be applied through the discharge transistor during phase transitions and further into the read node discharge phase.

[0009] Fig. 1A-5 describe examples of storage systems that can be used to implement the technology proposed herein. Fig. 1A is a functional block diagram of an exemplary memory system 100. In one embodiment, the in Fig. The components shown in Figure 1A are electrical circuits. The memory system 100 includes one or more memory chips 108. The one or more memory chips 108 can be complete memory chips or partial memory chips. In one embodiment, each memory chip 108 includes a memory structure 126, a control circuit 110, and read / write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The row decoder 124 can include the drivers and other elements to pre-bias the word lines for the various memory operations. The read / write circuits 128 include several read blocks 150, including SB1, SB2,..., SBp (read circuits), and allow one side of memory cells to be read or programmed in parallel, with one side being a unit in which data is written and / or read.A physical page is the physical unit of a number of cells into which data can be written and / or read simultaneously, and a logical page is a corresponding logical unit of data written into a physical page. Further details of read amplifier circuits that can be used in the 150 read blocks, including SB1, SB2,..., SBp, are given below in relation to [reference to relevant section]. Fig. 11-14 given.

[0010] In some systems, a controller 122 is included in the same package (e.g., a removable memory card) as the one or more memory chips 108. However, in other systems, the controller may be separate from the memory chip 108. In some embodiments, the controller is located on a different chip than the memory chip 108. In some embodiments, a controller 122 communicates with multiple memory chips 108. In other embodiments, each memory chip 108 has its own controller. Commands and data are transmitted between a host 140 and the controller 122 via a data bus 120 and between the controller 122 and the one or more memory chips 108 via lines 118. In one embodiment, the memory chip 108 includes a set of input and / or output (I / O) pins connected to lines 118.

[0011] The control circuit 110 interacts with the read / write circuits 128 to perform memory operations (e.g., writing, reading, and others) on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control circuit 116. The state machine 112 provides chip-level control of memory operations. In one embodiment, the state machine 112 is software-programmable. In other embodiments, the state machine 112 does not use software and is implemented entirely in hardware (e.g., electrical circuits). In other embodiments, the state machine 112 can be replaced by a programmable microcontroller. In one embodiment, the control circuit 110 includes buffer memories, such as registers, ROM fuses, and other storage devices for storing default values, such as base voltages and other parameters.

[0012] The on-chip address decoder 114 provides an address interface between addresses used by a host 140 or a controller 122 and the hardware address used by decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. The power control module 116 may include charge pumps for generating voltages. The read blocks include bit line drivers.

[0013] The state machine 112 and / or the controller 122 (or equivalently functioning circuits) in combination with all or a subset of the other circuits that are in Fig. The components shown in Figure 2 can be considered a control circuit that performs the functions described herein. The control circuit may consist of hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FGA, ASIC, integrated circuit, or other type of circuit.

[0014] The controller 122 (on-chip or off-chip) (which in one embodiment is an electrical circuit) may comprise one or more processors 122c, ROM 122a, RAM 122b, a memory interface (MI) 122d, and a host interface (HI) 122e, all interconnected. The memory devices (ROM 122a, RAM 122b) store code (software), such as a set of instructions (including firmware), and one or more processors 122c are operable to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, one or more processors 122c may access code from a memory device in the memory structure, such as a reserved area of ​​memory cells connected to one or more word lines. RAM 122b may be used to store data for the controller 122, including caching program data (discussed below).The memory interface 122d, in conjunction with ROM 122a, RAM 122b, and processor 122c, is an electrical circuit that provides an electrical interface between the controller 122 and one or more memory chips 108. For example, the memory interface 122d can modify the format or timing of signals, provide a buffer, isolate against voltage surges, buffer I / O, etc. One or more processors 122c can issue commands to the control circuit 110 (or another component of the memory chip 108) via the memory interface 122d. The host interface 122e provides an electrical interface with the data bus 120 of the host 140 to receive commands, addresses, and / or data from the host 140 and to provide data and / or status information to the host 140.

[0015] In one embodiment, the memory structure 126 comprises a three-dimensional memory array of non-volatile memory cells, on which multiple memory layers are formed over a single substrate, such as a wafer. The memory structure can incorporate any type of non-volatile memory monolithically formed in one or more physical layers of arrays of memory cells, each having an active region arranged over a silicon (or other type) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material as described, for example, in U.S. Patent US 9,721,662 B1.

[0016] In another embodiment, the memory structure 126 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells using floating gates of the type described, for example, in US patent US 9,082,502 B2. Other types of memory cells (e.g., NOR-type flash memory) can also be used.

[0017] The exact type of memory array architecture or memory cell contained in memory structure 126 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 126. No specific non-volatile memory technology is required for the purposes of the new claimed embodiments proposed here. Other examples of suitable technologies for memory cells of memory structure 126 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), phase-change memory (e.g., PCM), and the like. Examples of suitable technologies for the memory cell architectures of memory structure 126 include two-dimensional arrays, three-dimensional arrays, crosspoint arrays, stacked two-dimensional arrays, vertical bitline arrays, and the like.

[0018] An example of a ReRAM or PCMRAM crosspoint memory includes reversible resistive switching elements arranged in crosspoint arrays, accessed via X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element can be used as a state-change element based on the physical displacement of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes.As the temperature increases, the mobility of the ions also increases, which causes the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element can exhibit a wide range of programming thresholds across a temperature range.

[0019] A magnetoresistive memory (MRAM) stores data using magnetic storage elements. These elements consist of two ferromagnetic plates, each of which can contain a magnetization separated by a thin insulating layer. One of the plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match that of an external field for storing the data. A memory device is constructed from a grid of such memory cells. In one programming embodiment, each memory cell is sandwiched between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below it. When current is passed through these lines, an induced magnetic field is generated.

[0020] Phase-change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve non-thermal phase changes by simply altering the coordination state of the germanium atoms with a laser pulse (or light pulse from another source). Therefore, the programming doses are laser pulses. The memory cells can be blocked by shielding them from receiving the light. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but rather involves a (continuous or non-continuous) vibration or a pulse of sound, current, voltage light, or any other wave.

[0021] A person skilled in the art will recognize that the technology described herein is not limited to a single specific storage structure, but covers many relevant storage structures in accordance with the spirit and scope of the technology as described herein and as known to a person skilled in the art.

[0022] Fig. Figure 1B shows an example of memory structure 126. In one embodiment, an array of memory cells is divided into several levels. In the example of Fig. In 1B, the memory structure 126 is divided into two levels: level 141 and level 142. In other embodiments, more or fewer than two levels may be used. In some embodiments, each level is subdivided into a number of erase blocks (e.g., blocks 0-1023 or another set). In certain memory technologies (e.g., 2D / 3D NAND and other types of flash memory), an erase block is the smallest unit of memory cells for an erase operation. That is, each erase block contains the minimum number of memory cells that are erased together in a single erase operation. Other erase units may also be used. In other memory technologies (e.g., MRAM, PCM, etc.) used in other embodiments implementing the solution claimed herein, memory cells can be overwritten without an erase operation, and thus erase blocks may not exist.

[0023] Each memory erase block contains numerous memory cells. The construction, size, and organization of a memory erase block depend on the architecture and design for memory structure 126. As used here, a memory erase block is a contiguous set of memory cells that share word lines and bit lines; for example, erase block i of Fig. 1B memory cells that share word lines WL0_i, WL1_i, WL2_i and WL3_i and bit lines BL0-BL69.623.

[0024] In one embodiment, a memory erase block (see block i) contains a set of NAND strings which are accessed via bit lines (e.g., bit lines BL0 - BL69.623) and word lines (WL0, WL1, WL2, WL3). Fig. Figure 1B shows four memory cells connected in series to form a NAND string. Although it is shown that four cells are contained in each NAND string, more or fewer than four can be used (e.g., 16, 32, 64, 128, 256, or any other number of memory cells can be found on a NAND string). One endpoint of the NAND string is connected to a corresponding bit line via a drain select gate, and another endpoint is connected to the source line via a source select gate. Fig. Although 1B shows 69,624 bit lines, a different number of bit lines can also be used.

[0025] Each memory erase block and / or storage unit is typically divided into a number of pages. In one embodiment, a page is a programming / writing unit and a reading unit. Other programming units may also be used. One or more pages of data are typically stored in a set of memory cells. For example, one or more pages of data may be stored in memory cells connected by a common word line. A page contains user data and overhead data (also called system data). Overhead data typically includes header information and error correction codes (ECCs) calculated from the sector's user data. The controller (or another component) calculates the ECC when data is written to the array and also checks it when data is read from the array.In one embodiment, a page contains data that is stored in all memory cells connected by a common word line.

[0026] In the example discussed above, the unit for erasing is a memory erase block, and the unit for programming and reading is a page. Other programming units can also be used. Data can be stored / written / programmed, read, or erased byte-wise, 1 KB-wise, 512 KB-wise, and so on. No special operating unit is required for the claimed solutions described herein. In some examples, the system programs, erases, and reads in the same operating unit. In other embodiments, the system programs, erases, and reads in different operating units. In some examples, the system programs / writes and erases, while in other examples, the system only needs to program / write without needing to erase, since the system can program / write zeros and ones (or other data values) and thus overwrite previously stored information.

[0027] As used herein, a storage unit is the set of memory cells that constitutes the smallest operational storage unit for the storage technology for storing / writing / programming data into the memory structure 126. For example, in one embodiment, the storage unit is a page sized to hold 4 KB of data. In certain embodiments, a complete storage unit is sized to correspond to the number of physical memory cells across a row of the memory structure 126. In one embodiment, an incomplete storage unit has fewer physical memory cells than a complete storage unit.

[0028] Fig. Figure 2 is a block diagram of an exemplary storage system 100, showing more details of an embodiment of the controller 122. As used here, the flash memory controller is a device that manages data stored on the flash memory and communicates with a host, such as a computer or electronic device. A flash memory controller can have various functionalities in addition to the specific functionality described herein. For example, the flash memory controller can format the flash memory to ensure that the memory is functioning properly, to exclude bad flash memory cells, and to allocate spare memory cells to replace future faulty cells. Some portions of the spare cells can be used to hold firmware to operate the flash memory controller and implement other features.During operation, when a host needs to read data from or write data to flash memory, the host communicates with the flash memory controller. If the host provides a logical address to which data should be read / written, the flash memory controller can translate the logical address received from the host into a physical address within the flash memory controller. (Alternatively, the host can provide the physical address.) The flash memory controller can also perform various memory management functions, such as, but not limited to, wear balancing (distributing write operations to avoid wear and tear on specific memory blocks that would otherwise be repeatedly written to) and garbage collection (once a block is full, moving only the valid data pages to a new block so that the full block can be erased and reused).

[0029] The interface between the controller 122 and the non-volatile memory chip 108 can be any suitable flash interface, such as toggle mode 200, 400, or 800. In one embodiment, the storage system 100 can be a card-based system, such as a secure digital (SD) or secure digital micro card (microSD). In an alternative embodiment, the storage system 100 can be part of an embedded storage system. For example, the flash memory can be embedded in the host. In another example, the storage system 100 can be in the form of a solid-state drive (SSD).

[0030] In some embodiments, the non-volatile memory system 100 includes a single channel between the controller 122 and the non-volatile memory chip 108, the subject matter described herein being not limited to a single memory channel. For example, in some memory systems, there may be 2, 4, 8, or more channels between the controller and the memory chip, depending on the capabilities of the controller. In each of the embodiments described herein, more than a single channel may be present between the controller and the memory chip, even if a single channel is shown in the drawings.

[0031] As in Fig. As shown in Figure 2, the controller 122 includes a front-end module 208 which has an interface with a host, a back-end module 210 which has an interface with one or more non-volatile memory chips 108, and various other modules that perform functions which will now be described in detail.

[0032] The components of the control unit 122, which are in Fig. The components shown in Figure 2 can take the form of a packed functional hardware unit (e.g., an electrical circuit) designed for use with other components, a section of program code (e.g., software or firmware) executable by a (micro)processor or processing circuit that typically performs a specific function among related functions, or a self-contained hardware or software component that interfaces with, for example, a larger system. For instance, each module can include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof.Alternatively or additionally, each module may contain software stored in a processor-readable device (e.g., memory) to program a processor for the controller 122 to perform the functions described herein. The in . Fig. The architecture shown in section 2 is an exemplary implementation that incorporates the components of the [unclear text]. Fig. 1A can use (or cannot use) the control 122 shown (i.e., RAM, ROM, processor, interface).

[0033] Referring again to modules of the controller 122, a buffer manager / bus controller 214 manages buffer memory in the random access memory (RAM) 216 and controls the internal bus arbitration of the controller 122. A read-only memory (ROM) 218 ​​stores the system's boot code. Although they are in Fig. In other embodiments, where RAM 216 or ROM 218 are shown as being arranged separately from the controller 122, one or both may be arranged within the controller. In still other embodiments, sections of RAM and ROM may be located both inside and outside the controller 122. Furthermore, in some implementations, the controller 122, RAM 216, and ROM 218 may be arranged on separate semiconductor chips.

[0034] Additionally, the front-end module 208 can have a host interface 220 and a physical layer (PHY) interface 222, which provide the electrical interface with the host or controller of the next storage layer. The choice of host interface 220 type can depend on the type of storage used. Examples of host interfaces 220 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 can typically allow the transmission of data, control signals, and clock signals.

[0035] The backend module 210 includes an error correction code (ECC) machine 224, which encodes the data bytes received from the host and decodes the data bytes read from the non-volatile memory, correcting errors. An instruction sequencer 226 generates instruction sequences, such as program and erase instruction sequences, to be transferred to the non-volatile memory chip 108. A RAID (redundant array of independent dies) module 228 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for the data written to the non-volatile storage system 100. In some cases, the RAID module 228 can be a component of the ECC machine 224.It should be noted that RAID parity can be added as an additional chip or chips, as implied by the common name, but that it can also be added within the existing chip, e.g., as an additional layer, or an additional block, or additional WLs within a block. A memory interface 230 provides the command sequences to the non-volatile memory chip 108 and receives status information from the non-volatile memory chip 108. In one embodiment, the memory interface 230 can be a double data rate (DDR) interface, such as a toggle-mode 200, 400, 800, or higher interface. A flash control layer 232 controls the overall operation of the backend module 210.

[0036] One embodiment includes a read / write manager 236, which can be used (in conjunction with the circuitry on the memory chip) to manage the writing and reading of memory cells. In some embodiments, the read / write manager 236 performs the processes shown in the flowcharts described below.

[0037] Additional components of System 100, which is in Fig. The system 100, as shown in Figure 2, includes the media management layer 238, which performs wear compensation of the memory cells of the non-volatile memory chip 108. The system 100 also includes other discrete components 240, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may be connected to the controller 122. In alternative embodiments, one or more of the interface to the physical layer 222, the RAID module 228, the media management layer 238, and the buffer manager / bus controller 214 are optional components that are not required in the controller 122.

[0038] The flash translation layer (FTL) or media management layer (MML) 238 can be integrated as part of the flash management system, which can handle flash errors and interact with the host. Specifically, the MML can be a module within a flash management system and be responsible for the internals of NAND management. In particular, the MML 238 can contain an algorithm in the memory device's firmware that translates write operations from the host into write operations to the memory structure 126 of the chip 108. The MML 238 may be necessary because: 1) the memory may have a limited lifespan; 2) the memory structure 126 can only be written to in multiples of pages; and / or 3) the memory structure 126 cannot be written to unless it is erased as a block. The MML 238 understands these potential limitations of the memory structure 126, which may not be visible to the host.Accordingly, the MML 238 attempts to translate write operations from the host into writes to the memory structure 126. As described below, bad bits can be identified and recorded using the MML 238. This recording of bad bits can be used to assess the health of blocks and / or word lines (the memory cells on the word lines).

[0039] The controller 122 can have an interface with one or more memory chips 108. In one embodiment, the controller 122 and several memory chips (which together constitute the non-volatile memory system 100) implement a solid-state drive (SSD) that can emulate, replace, or be used instead of a hard disk drive in a host, such as a NAS device, laptop, tablet, server, etc. Furthermore, the SSD does not need to be designed to function as a hard disk drive.

[0040] Some embodiments of a non-volatile memory system include a memory chip 108 connected to a controller 122. However, other embodiments may include multiple memory chips 108 connected to one or more controllers 122. In one example, the multiple memory chips may be grouped into a set of memory packages. Each memory package includes one or more memory chips connected to the controller 122. In one embodiment, a memory package includes a printed circuit board (or similar structure) on which one or more memory chips are mounted. In some embodiments, a memory package may include molding compound to encapsulate the memory chips of the memory package. In some embodiments, the controller 122 is physically separate from each of the memory packages.

[0041] Fig. Figure 3 is a perspective view of a section of an exemplary embodiment of a monolithic three-dimensional storage structure 126, which includes a plurality of storage cells. For example, Figure 3 shows... Fig. 3. A section of a memory block. The structure shown includes a set of bit lines BL positioned over a stack of alternating dielectric and conductive layers. For example, one of the dielectric layers is labeled D and one of the conductive layers (also called word line layers) is labeled W. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 10⁸ and 216 alternating dielectric and conductive layers, for example, 96 data word line layers, 8 selection layers, 4 dummy word line layers, and 10⁸ dielectric layers. More or fewer than 10⁸ to 216 layers can also be used.As explained below, the alternating dielectric layers and the conductive layers are divided into four "fingers" by local intermediate connections LI (insulating regions). Fig. Figure 3 shows only two fingers and two local intermediate connections LI. Below the alternating dielectric and conduction layers is a source conduction layer SL. Memory holes are formed in the stack of alternating dielectric and conducting layers. For example, one of the memory holes is labeled MH. It should be noted that in Fig. 3 the dielectric layers are shown transparently so that the reader can see the memory holes positioned in the stack of alternating dielectric and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials that enclose a charge-capturing layer to create a vertical column of memory cells. Each memory cell can store one or more data bits. More details of the three-dimensional monolithic memory structure 126 are given in reference to Fig. 4 provided.

[0042] Fig. Figure 4 shows an example 3D NAND structure and illustrates the physical word lines WLL0–WLL47 that run across the entire block. The structure of Fig. 4 can be a section of one of the blocks from Fig. This corresponds to 1B, including bit lines 311, 312, 313, 314, ..., 319. Within the block, each bit line is connected to four NAND strings. Drain-side select lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings is connected to the corresponding bit line. The block can also be viewed as being divided into four subblocks SB0, SB1, SB2, and SB3. Subblock SB0 corresponds to those vertical NAND strings controlled by SGD0 and SGS0, subblock SB1 corresponds to those vertical NAND strings controlled by SGD1 and SGS1, subblock SB2 corresponds to those vertical NAND strings controlled by SGD2 and SGS2, and subblock SB3 corresponds to those vertical NAND strings controlled by SGD3 and SGS3.

[0043] Fig. 5 represents a different storage structure, which is used for structure 126 of Fig. 1A can be used. Fig. Figure 5 represents a three-dimensional vertical intersection structure, with the word lines still running horizontally and the bit lines oriented to run in a vertical direction.

[0044] Fig. Figure 5 shows an embodiment of a section of a monolithic three-dimensional storage array structure 126, which includes a first storage layer 412 positioned below a second storage layer 410. As shown, the local bit lines LBL are 11 -LBL 33 arranged in a first direction (i.e., a vertical direction), and the word lines WL 10 -WL 23are arranged in a second direction perpendicular to the first direction. This arrangement of vertical bit lines in a monolithic three-dimensional memory array is one embodiment of a vertical bit line memory array. As shown, a specific memory cell is arranged between the intersection of each local bit line and each word line (e.g., memory cell M). 111 between the local bit line LBL 11 and the word lead WL 10arranged). This structure can be used with a number of different memory cell structures. In one example, the specific memory cell may contain a floating-gate device or a charge-trap device (e.g., using a silicon nitride material). In another example, the specific memory cell may contain a reversible resistance switching material, a metal oxide, a phase-change memory (PCM) material, or a ReRAM material. The global bit lines GBL1-GBL3 are arranged in a third direction, perpendicular to both the first and second directions. A set of bit line selectors (e.g., Q) 11 -Q 31 ), such as a vertical thin-film transistor (VTFT), can be used to select a set of local bit lines (e.g., LBL). 11 -LBL 31 ) are used. As shown, bit line selection devices Q are used. 11 -Q 31for selecting the local bit lines LBL 11 -LBL 31 and to connect the local bit lines LBL 11 -LBL 31 with the global bit lines GBL1-GBL3 using a line selector line SG1. Similarly, bit line selectors Q 12 -Q 32 for selectively connecting the local bit lines LBL 12 -LBL 32 with the global bit lines GBL1-GBL3 using a line selector line SG2, and the bit line selectors Q 13 -Q 33 are used for selectively connecting the local bit lines LBL 13 -LBL 33 used with the global bit lines GBL1-GBL3 using a row selection line SG3.

[0045] Referring to Fig. 5. Since only a single bit line selection device is used per local bit line, only the voltage of a given global bit line can be applied to a corresponding local bit line. Therefore, if a first set of local bit lines (e.g., LBL) is used, 11 -LBL 31 ) is biased on the global bit lines GBL1-GBL3, the other local bit lines (e.g. LBL 12 -LBL 32 and LBL 13 -LBL 33) are either driven on the same global bit lines GBL1-GBL3 or are floating. In one embodiment, during a memory operation, all local bit lines within the memory array are first biased to the voltage of an unselected bit line by connecting each of the global bit lines to one or more of the local bit lines. After the local bit lines have been biased to the voltage of the unselected bit line, only a first set of local bit lines (LBL) is subsequently used. 11 -LBL 31 biased on the voltages of one or more selected bit lines via the global bit lines GBL1-GBL3, while the other local bit lines (e.g. LBL) 12 -LBL 32 and LBL 13 -LBL 33) are floating. The voltages of one or more selected bit lines can, for example, correspond to one or more read voltages during a read operation or to one or more programming voltages during a programming operation.

[0046] The memory systems discussed above can be erased, programmed / written, and read. At the end of a successful programming process, the threshold voltages of the memory cells should lie within one or more distributions of threshold voltages for programmed memory cells, or, if applicable, within a distribution of threshold voltages (Vts) for erased memory cells. Fig. Figure 6 presents exemplary threshold voltage distributions for the memory cell array when each memory cell stores more than one bit of data in a multi-level cell (MLC) format, in this case three bits of data. However, other embodiments may use different data capacities per memory cell (such as one, two, four, or five bits of data per memory cell). Fig. Figure 6 shows eight threshold voltage distributions corresponding to eight data states. The first threshold voltage distribution (data state), S0, represents memory cells that are erased. The other seven threshold voltage distributions (data states), S1 through S7, represent memory cells that are programmed and are therefore also called programmed states. Each threshold voltage distribution (data state) corresponds to predetermined values ​​for the set of data bits. The specific relationship between the data programmed into the memory cell and the cell's threshold voltage levels depends on the data encoding scheme used for the cells. In one embodiment, data values ​​are assigned to the threshold voltage ranges using a Gray code assignment, so that if the threshold voltage of a memory cell mistakenly shifts into its adjacent physical state, only one bit is affected.

[0047] Fig. Figure 6 also shows seven read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 for reading data from memory cells. By testing (e.g., performing read operations) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine the data state (i.e., S0, S1, S2, S3, ...) of a memory cell.

[0048] Fig. Figure 6 also shows seven test reference voltages: Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7. When memory cells are programmed to data state S1, the system checks whether these memory cells have a threshold voltage greater than or equal to Vv1. When memory cells are programmed to data state S2, the system checks whether these memory cells have a threshold voltage greater than or equal to Vv2. When memory cells are programmed to data state S3, the system determines whether the memory cells have a threshold voltage greater than or equal to Vv3. When memory cells are programmed to data state S4, the system checks whether these memory cells have a threshold voltage greater than or equal to Vv4. When memory cells are programmed to data state S5, the system checks whether these memory cells have a threshold voltage greater than or equal to Vv5.When memory cells are programmed to data state S6, the system checks whether these memory cells have a threshold voltage greater than or equal to Vv6. When memory cells are programmed to data state S7, the system checks whether these memory cells have a threshold voltage greater than or equal to Vv7.

[0049] In one embodiment known as full-sequence programming, memory cells can be directly programmed from the erased data state S0 to one of the programmed data states S1 through S7. For example, a population of memory cells to be programmed can first be erased so that all memory cells in the population are in the erased data state S0. Then, a programming process is used to directly program memory cells to data states S1, S2, S3, S4, S5, S6, and / or S7. While, for example, some memory cells are programmed from data state S0 to data state S1, other memory cells are programmed from data state S0 to data state S2 and / or from data state S0 to data state S3, and so on. The arrows of Fig. Section 6 represents the complete sequence programming. The technology described herein can also be used with other programming methods in addition to full sequence programming (including, but not limited to, multi-stage / phase programming). In some embodiments, the data states S1 to S7 may overlap, with the controller 122 relying on the ECC to identify the correct data to be stored.

[0050] Fig. Figure 7A is a flowchart describing one embodiment of a programming process performed by the controller 122. In some embodiments, the host can perform the functions of the controller instead of having a dedicated controller. In step 702, the controller 122 sends instructions to one or more memory chips 108 to program data. In step 704, the controller 122 sends one or more addresses to one or more memory chips 108. The one or more addresses indicate where the data is to be programmed. In step 706, the controller 122 sends the data to be programmed to one or more memory chips 108. In step 708, the controller 122 receives a result of the programming from one or more memory chips 108.Exemplary results include that the data was successfully programmed, an indication that the programming operation failed, an indication that the data was programmed but in a different location, or another result. In step 710, in response to the result received in step 708, the controller 122 updates the system information it maintains. In one embodiment, the system maintains tables of data that display status information for each block. This information may include a mapping of logical addresses to physical addresses, which blocks / word lines are open / closed (or partially open / closed), which blocks / word lines are bad, and so on.

[0051] In some embodiments, the controller 122 would receive host data and a programming instruction from the host prior to step 702, and the controller would run the ECC machine 224 to generate codewords from the host data, as is known in the prior art and described in more detail below. These codewords are the data transferred in step 706. The controller 122 (e.g., the read / write manager 236) can also encrypt the data before programming it into memory.

[0052] Fig. 7B is a flowchart that describes one implementation of a programming process. The process of Fig. 7B is activated by the memory chip in response to the steps of Fig. 7A (i.e., in response to instructions, data, and addresses from controller 122). In an exemplary embodiment, the process is carried out by Fig. 7B on memory chip 108 executed on instruction from state machine 112 using one or more of the control circuits discussed above (see Fig. 1) The process of Fig. 7B can also be used to implement the full sequence programming discussed above. The process of Fig. 7B can also be used to implement each phase of a multi-phase programming process.

[0053] Typically, the programming voltage applied to the control gates (via a selected word line) during a programming operation is applied as a series of programming pulses. A set of check pulses is inserted between programming pulses to perform a verification. In many implementations, the size of the programming pulses is increased with each successive pulse by a predetermined step size. In step 770 of Fig. In step 7B, the programming voltage (Vpgm) is initialized to the starting value (e.g., ~12-16 V or another suitable level), and a program counter PC, which is controlled by the state machine 112, is initialized at 1. In step 772, a programming pulse of the program signal Vpgm is applied to the selected word line (the word line chosen for programming). In one embodiment, all memory cells of the group of memory cells being programmed simultaneously are connected to the same word line (the selected word line). The unselected word lines receive one or more gain voltages (e.g., ~7 to 11 volts) to implement gain schemes known in the art. If a memory cell is to be programmed, the corresponding bit line is grounded.If, on the other hand, the memory cell should remain at its current threshold voltage, then the corresponding bit line is connected to Vdd to prevent programming. In step 772, the programming pulse is applied simultaneously to all memory cells connected to the selected word line, so that all memory cells connected to the selected word line are programmed at the same time. That is, they are programmed at the same time or during overlapping times (both of which are considered simultaneous). In this way, all memory cells connected to the selected word line change their threshold voltage simultaneously, unless they have been excluded from programming.

[0054] In step 774, the relevant memory cells are verified using the appropriate set of test reference voltages to perform one or more verification operations. In one embodiment, the verification process is performed by applying the test to determine whether the threshold voltages of the memory cells selected for programming have reached the appropriate test reference voltage.

[0055] Step 776 determines whether all memory cells have reached their target threshold voltages (pass). If so, the programming process is complete and successful because all selected memory cells have been programmed to their target states and verified. Step 778 reports a "PASS" status. If step 776 determines that not all memory cells have reached their target threshold voltages (fail), the programming process continues with step 780.

[0056] In step 780, the system counts the number of memory cells that have not yet reached their respective target threshold voltage distribution. That is, the system counts the number of memory cells that have not yet passed the verification process. This counting can be performed by the state machine, the controller, or other logic. In one implementation, each read block stores the status (pass / fail) of its respective cells. In one embodiment, there is a total count value that represents the total number of currently programmed memory cells that have failed the last verification step. In another embodiment, separate count values ​​are determined for each data state.

[0057] Step 782 determines whether the count from step 780 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by ECC during a read operation for the page of memory cells. If the number of faulty memory cells is less than or equal to the predetermined limit, the programming process can stop, and step 778 reports a "PASS" status. In this situation, enough memory cells have been correctly programmed that the few remaining memory cells that have not been fully programmed can be corrected using ECC during the read operation. In some embodiments, step 780 counts the number of failed cells for each sector, target data state, or other unit, and these counts are compared individually or collectively to a threshold in step 782.

[0058] In another embodiment, the predetermined limit can be smaller than the number of bits that can be corrected by ECC during a read process to account for future errors. If fewer than all memory cells for a page are programmed, or if a count is compared for only one data state (or fewer than all states), the predetermined limit can be a proportion (pro rata or non-pro rata) of the number of bits that can be corrected by ECC during a read process for that page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors already counted for the page, the number of program / erase cycles performed, or other criteria.

[0059] If the number of faulty memory cells is not less than the predetermined limit, the programming process proceeds to step 784, and the program counter PC is checked against the program limit (PL). Examples of program limits include 12, 20, and 30; however, other values ​​can be used. If the program counter PC is not less than the program limit PL, the program process is considered to have failed, and the status FAILED is reported in step 788. This is an example of a program error. If the program counter PC is less than the program limit PL, the process proceeds to step 786, during which the program counter PC is incremented by 1, and the programming voltage Vpgm is increased to the next size. For example, the next pulse will have a size that is one step size larger (e.g., a step size of 0.1 to 0.5 volts) than the previous pulse.After step 786, the process returns to step 772 and another programming pulse is applied to the selected word line, so that another iteration (steps 772-786) of the programming process of . Fig. 7B is carried out.

[0060] In general, the selected word line is connected to a voltage (an example of a reference signal) during test and read operations, the level of which is set for each read operation (see, for example, read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6 and Vr7 of Fig. 6) or test procedure (see e.g. test reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6 and Vv7 of Fig. 6) is specified to determine whether a threshold voltage of the memory cell in question has reached such a level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell is switched on (current conducting) in response to the voltage applied to the word line. If the conduction current, according to measurements, is greater than a specified value, then it is assumed that the memory cell is switched on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current, according to measurements, is not greater than the specified value, then it is assumed that the memory cell is not switched on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell.During a read or verification process, the unselected memory cells are supplied with one or more read pass voltages at their control gates, so that these memory cells act as pass gates (e.g., conducting current regardless of whether they are programmed or erased).

[0061] There are many ways to measure the conduction current of a memory cell during a read or test operation. In one example, the conduction current of a memory cell is measured by the rate at which it discharges or charges a dedicated capacitor in the read amplifier. In another example, the conduction current of the selected memory cell enables (or prevents) the NAND string encompassing the memory cell from discharging a corresponding bit line. The voltage on the bit line is measured after a period of time to determine whether it has discharged. It should be noted that the technology described herein can be used with various methods known in the prior art for test / reading. Other read and test techniques known in the prior art can also be employed.

[0062] In some embodiments, the controller 122 receives a request from the host (or a client, user, etc.) to program host data (data received from the host) into the storage system. In some embodiments, the controller 122 arranges the host data to be programmed into data units. For example, the controller 122 can arrange the host data into pages, sub-pages (a subset of a page), word line units, blocks, jumbo blocks, or other units.

[0063] Step 772 of Fig. Step 7B involves applying a programming voltage pulse to the selected word line. Step 774 of Fig. Step 7B includes a test which, in some embodiments, involves applying the test reference voltages to the selected word line. Since steps 772 and 774 are part of an iterative loop, the programming voltage is applied as a series of voltage pulses whose magnitude increases stepwise. Test reference voltages are applied between voltage pulses. This is described in Fig. Figure 7C shows the programming voltage pulses 792, 794, and 796, which are applied during three consecutive iterations of step 772. Between programming voltage pulses 792, 794, and 796, the system tests the memory cells to determine, by applying the test reference voltages as test pulses, whether the threshold voltages of the memory cells are greater than the respective test reference voltages.

[0064] Fig. Figure 8 is a flowchart of a read operation performed to retrieve data from the memory cells. In step 800, a pass voltage is applied to unselected word lines, causing unselected memory cells on a NAND string to conduct. This allows the system to check if the selected memory cell conducts in response to the read reference voltage. This pass voltage is often referred to as Vread. In step 802, the appropriate read reference voltage, also known as Vcgr, is applied to the selected word line. In an example of a system storing one bit per memory cell, Vcgr is equal to 0V, or a small voltage close to 0V. In step 804, all bit lines are preloaded.In one exemplary embodiment, the bit lines are precharged by charging a capacitor in the read amplifier and then connecting the bit line to the charged capacitor, thus charging the bit line. In step 806, the bit line is discharged, for example, by discharging the capacitor. After a predetermined time period, called the "integration time" or strobe time, the capacitor voltage is sampled to see if the respective memory cell(s) conducted in step 810. If the memory cell conducts in response to Vcgr, then the threshold voltage of the memory cell is less than Vcgr. If Vcgr = 0V and the memory cell turns on, then the memory cell is in the erased state and the stored data is 1. If Vcgr = 0V and the memory cell does not turn on, then the memory cell is in the programmed state and the stored data is 0.

[0065] The storage density of a memory circuit, such as in Fig. 1B, Fig. 3, Fig. 4 or Fig. 5 can be increased by storing multiple data states in each of the cells. For example, shows Fig. Figure 6 shows an example with 3 bits per cell, where each memory cell can store one of 8 different data states. Storing 8 or even more states per cell presents a number of difficulties, as either the different state distributions must be stored closer together, a larger range of threshold voltages (or "Vt windows") must be used, or both. However, programming memory cell states closer together becomes increasingly complicated, as maintaining sufficiently dense, well-separated distributions can significantly reduce performance; and accurate data retention is more difficult, since even a small amount of threshold voltage drift can make reading the data difficult or even impossible.Regarding the widening of the Vt window, switching to higher threshold voltages allows for the addition of more states at the high Vt end, but at the cost of increased operating voltages, increased power consumption, and potentially a shorter device lifetime. Alternatively, the Vt window can be widened by extending it further into negative threshold voltages.

[0066] In the example of Fig. Only the distribution of the lowest or deleted data state of S0 has a threshold voltage below 0V. Storing more states with negative thresholds can widen the Vt window. This is in the Fig. 9A and Fig. 9B is shown.

[0067] Fig. 9A is Fig. Figure 6 is similar, but only shows the lowest threshold state S0 and the highest threshold state SN. The effective Vt window in this example ranges from approximately -1V, or a few tenths of a volt less, on the low side to a few volts on the high side (for example, in the 4-6V range, such as 5V), with the other state distributions falling between these two values. If S0 is the only state whose Vt is less than 0V, this can be read by checking the memory cell control gate in step 802 of the flowchart. Fig. 8 is placed on mass. Fig. 9B represents lowering the lower end of the Vt window deeper into negative Vt values. In this example, the S0 distribution lies at or below Vt = 2.5 V to 1.5 V (e.g., approximately 2 V), adding about 1 V to the Vt window and providing additional headroom for more data states, as illustrated by S1. However, distinguishing between different data states with negative thresholds has always been difficult. Therefore, Fig. 10A-10C presents some techniques for reading negative Vt values.

[0068] Fig. Figures 10A-10C are simplified representations showing a NAND string with only one memory cell connected in series between a source-side select gate (SGS) and a drain-side select gate (SGD). To simplify the figures, other unselected memory cells of the NAND string are not shown, but would be biased to a read pass voltage, allowing them to conduct for any stored data state. The NAND string is connected on the source side to a source line (SRC) and on the drain side to a bit line, which in turn is connected to a read amplifier.

[0069] Fig. 10A represents a read operation for the memory cell using a negative word line voltage CGRV to read a negative threshold. In addition to the negative word line voltage, the NAND string is biased as is usual for reading positive threshold voltage values. The drain and source select gates are turned on by applying a sufficiently high voltage along the control lines to their gates, SGD=H and SGD=H, respectively, and the source line voltage VSRC is set to ground, VSRC=0 V, or another low voltage. The bit line is biased to a positive voltage higher than VSRC; for example, VBL might be in the range of 0.2–1.0 V, such as 0.5 V or slightly lower. The bit line is then discharged by the current Icell, with the discharge rate based on the memory cell's threshold voltage and the word line voltage CGRV at its control gate.After an integration time, the result is temporarily stored by the read amplifier connected to the bit line. Although this approach can be used for negative Vt states, it requires the use of negative voltages, such as the one in [reference missing]. Fig. The CGRV shown for 10A is -1.5V. However, negative voltages are not typically used in a storage device because they require additional circuitry for generation and are often difficult to maintain. Furthermore, negative voltage levels near or below -1.5V are difficult to produce, which limits how far the Vt window can be extended downwards.

[0070] Another approach to reading negative Vt states, but without negative voltages, is in Fig. 10B is shown. Fig. In step 10B, the bias voltage of the NAND string is changed to allow a non-negative voltage, such as CGRV=0V, to be used to read negative Vt states. The select gates (and any unselected memory cells) of the NAND string are biased again to be turned on, but now the source line is raised above ground; for example, VSRC can be in the range of 0.8–1.5V, such as 1V or slightly higher. This places the source of the selected memory cell at VSRC, allowing a negative Vt to be read with a non-negative word line voltage. To discharge the bit line through Icell by the selected memory cell, the bit line is then biased to a level above the source line; for example, VBL can be in the range of 1.2–1.8V, such as approximately 1.5V, placing it a few tenths of a volt above VSRC.After the bit line is discharged for a read interval, the result is then temporarily stored by the corresponding read amplifier. Although this technique allows reading a negative Vt without negative voltages, it cannot go much deeper into negative Vt values ​​than approximately -1.1V.

[0071] Fig. 10C presents a different approach that can extend reading to deeper negative Vt values ​​while using only non-negative voltages. In the reading setup of Fig. At 10C, the source line is raised to a voltage level above the bit line voltage level VSRC>VBL>0V. Instead of determining whether a selected memory cell is conducting by discharging the bit line through the memory cell into the source line, the source line is now discharged through the memory cell into the bit line and the read amplifier. Fig. 10C represents this by having the current Icell flow upwards towards the bit line, instead of downwards towards the source line, as in Fig. 10A and Fig. 10B. For example, the source line can be set in the range VSRC=2.0-2.5V, such as slightly below 2V, and the bit line voltage VBL can be set a few tenths (e.g., 0.2-0.4V) of a volt less. With CGRV=0V, this allows reading a Vt down to approximately, for example, -1.8V or even further, depending on the VSRC and VBL levels. The approach of Fig. 10C is used in the following read amplifier implementations, which can be used for reading a deep negative threshold voltage and techniques for reducing the noise that may occur during such read operations.

[0072] Fig. Figure 11 represents an embodiment of a read amplifier 1110 which can be used to perform a read operation using the approach of Fig. 10C to be carried out. The reading amplifier 1110 can be used in one of the reading blocks SB1, SB2,..., SBp 150 in Fig. 1A corresponds to this. A selected memory cell 1101 is connected between a source line SRC 1103 and a bit line BL 1105. Other memory cells (e.g., of the same NAND string) are also connected between the source line SRC 1103 and the bit line BL 1105; however, these other memory cells are in Fig. 11 not shown. The read amplifier 1110 can typically be selectively connected to multiple bit lines via a Fig. The selected bit line BL 1105 can be connected to the column decoding circuit (not shown) via the path labeled "BL path" through the series-connected switches BLC2 1111 and BLC 1113 to the discharge transistor DT 1115, and then further through the discharge transistor DT 1115 to the discharge node SRCGND. The control gate of the discharge transistor DT 1115 is connected in a diode-like arrangement to the internal bit line node BLI (for the read amplifier) ​​between BLC2 1111 and BLC 1113. When both BLC2 1111 and BLC 1113 are switched on, the current flowing from memory cell 1101 to bit line BL 1105 can discharge along the BL path to the discharge node SRCGND. and when both BLC2 1111 and BLC 1113 are switched off, the discharge BL path is interrupted and the control gate of DT 1115 remains floating at the level at node BLI between BLC2 1111 and BLC 1113.

[0073] Right in Fig. Section 11 provides a second discharge path, labeled "SEN path," allowing the SEN read node to also be discharged to the discharge transistor DT 1115 via the XXL 1121 switch. When XXL 1121 is switched on, any charge stored on the Csen 1123 capacitor is discharged at a rate determined by the control gate voltage at the discharge transistor DT 1115. After discharging over a read period, a read result, based on the level at the SEN node, can then be placed in the latch 1125 and transmitted via the DBUS data bus. The SEN node can be pre-charged via the latch 1125.

[0074] The voltage levels and timing for the switches in Fig. 11 are controlled by the elements on the memory array, such as the read / write circuits 128 and the read blocks SB1, SB2,..., SBp 150 in Fig. 1A, represented here by the biasing circuit of control block 1131. A read operation, such as a read or verification, is performed in two stages. After the initial biasing of the source line SRC, the bit line BL, the selected memory, and other elements (such as selection gates and unselected memory cells in a NAND implementation), switches BLC2 1111 and BLC 1113 are turned on, and the bit line is discharged along the BL path through the discharge transistor. The degree of discharge, or whether any current is discharged at all, depends on the word line voltage CGRV at the control gate of the selected memory cell and the threshold voltage Vt of the selected memory cell. Consequently, the voltage at node BLI depends on the data state of the memory cell and how closely this data state corresponds to the read level CGRV that biases the selected memory cell.Once the voltage level at node BLI is sufficiently stable, switches BLC2 1111 and BLC 1113 are switched off, so that node BLI and consequently the control gate of the discharge transistor DT 1115 remain floating at the level set during the bit line discharge phase.

[0075] Once switches BLC2 1111 and BLC 1113 are switched off and the gate of discharge transistor DT 1115 floats at the level set during the bit-line discharge phase, the conductance of transistor DT 1115 is based on the conductance of the selected memory cell. During the read-node discharge phase, switch XXL 1121 is switched on, allowing the previously charged read node SEN and read-node capacitor Csen 1123 to discharge through discharge transistor DT 1115 along the SEN path. After a discharge period, the value at the SEN node can then be read by latch 1125. Since the discharge rate along the SEN path depends on the gate voltage at discharge transistor DT 1115, which in turn depends on the state of the selected memory cell, the buffered value corresponds to the data state. For a memory cell configured as in Fig. When 10C is pre-loaded, VCGR=0V is used to read the lowest (i.e., most negative) data state, with the VCGR value being increased to read higher Vg states, both less negative Vt states and positive Vt states.

[0076] A number of variations in Fig. 11 is possible. For example, instead of having switches BLC2 1111 and BLC 1113 connected in series between the bit line BL 1105 and the central SCOM node, as shown, one of them can be moved between node BLI and the gate of the discharge transistor DT 1115. This arrangement also allows the level at the control gate of the discharge transistor DT 1115 to be set by the voltage level at the BLI node when both switches are turned on; and the BL path is closed and the control gate at the discharge transistor DT 1115 remains floating when both are turned off. In another variation, the BL path and the SEN path could discharge through different transistors, but with the gates of both connected together. These and other variations can be incorporated into the embodiment of Fig. 11 and other embodiments described below.

[0077] To read data values ​​more accurately, noise during the read process should be minimized to the practically feasible level, especially when a large number of states are to be stored within the available Vt window. Several techniques can be used for this purpose, as detailed in Fig. The 11 illustrated read amplifier designs are applied to provide improved product reliability and performance. Two noise sources concern the discharge transistor DT 1115. Fig. 11, where noise either at the gate of the transistor or corresponding to the BLI node and noise along the current paths through the transistor can disrupt the reading process.

[0078] To reduce noise on the current path through the discharge transistor DT 1115, a clamping device and an auxiliary current source, or "holding current," can be introduced into the read amplifier circuit to clamp the drain voltage of the discharge transistor DT 1115 during the read operation. This can help block any potential noise through the discharge transistor DT 1115 and provide current flow through the discharge transistor DT 1115 to the SRCGND node. The SRCGND node is typically a node on a common regulated SRCGND line to which the read amplifier and other read amplifiers are connected, allowing all connected read amplifiers to discharge current into the SRCGND line during a read operation. Introducing the auxiliary holding current helps eliminate critical noise at the SRCGND node during the read operation.

[0079] To reduce noise in the control gate of the discharge transistor DT 1115, a decoupling capacitor can be introduced to compensate for and correct any coupling that may occur when switches BLC2 1111 and BLC 1113 turn off to prepare for the discharge of the read node. This solution helps correct potentially unwanted coupling to the gate of the discharge transistor DT 1115 and provides a more accurate read result. The decoupling capacitor can monitor operating conditions, such as temperature, and device corners to obtain more accurate read results. This can be useful for providing accurate read results in cases of temperature dependence and device corners, as the degree to which a voltage (Vt) can be read negatively can depend on the temperature and the device corners.

[0080] Fig. 12 includes the previously described elements for reducing noise, as well as other elements that can be incorporated into various embodiments of a read amplifier circuit, such as those found in the read blocks SB1, SB2,..., SBp 150 of Fig. They can be installed in 1A. Fig. 12 will be the elements of Fig. 11 together with a decoupling capacitor Cdecop 1212, which is connected to the BLI node and an additional current source NLO 1218 to help stabilize the SRCGND node during the transition to the read phase.

[0081] More precisely, it Fig. Figure 12 represents a memory cell 1201, which is connected between a source line SRC 1203 and a bit line BL 1205. The memory cell 1201 can be part of a NAND string of charge-storing memory cells, such as those related to the Fig. 3 and Fig. 4 described, a memory cell based on a phase-change memory material (PCM), such as the one described above in relation to Fig. 5 described, or another storage technology. The bit line BL 1205 is connected to the read amplifier via the decoding circuit, represented here by the bit line selector (BLS) switch 1206. (In this paper, switches are generally named according to their control signals from the bias control circuit, so, for example, the control signal BLS for switch 1206 is also used for its name.)

[0082] After the bit line selector switch BLS 1206, the bit line BL 1205 is connected to the internal bit line BLI via the switch BLC2 1211, and then via the switch BLC 1213 to the central comment read node SCOM. The node SCOM is connected via the discharge transistor DT 1215 to allow the node SCOM to discharge to SRCGND. Analogous to Fig. Section 11 provides the discharge path, labeled BL path, from SRC 1203 through the selected cell 1201 to the selected bit line, then through the series-connected switches BLC2 1211 and BLC 1213 to the discharge transistor DT 1215, and finally to SRCGND. The control gate of DT 1215 is again connected to the node at BLI, so that when switches BLC2 1211 and BLC 1213 are switched off, the control gate of DT 1215 remains floating at the level at BLI.

[0083] Right in Fig. 12. The SEN node is connected to the capacitor Csen 1223 via the switch XXL 1221 to the SCOM node and then further to the discharge transistor DT 1215 to provide the second discharge path (SEN path) from the SEN node to SRCGND for the second read operation. The SEN node is also connected to the latch 1225 to temporarily store the result of the read operation, which in turn is connected to the data bus DBUS. Depending on the embodiment, the latch 1225 can contain a number of individual latches for use in multi-state read and write operations or for other data operations. The elements described so far of Fig. 12 are largely as above with regard to Fig. 11 described, with the exception that, for the sake of simplicity, Fig. 12 of the preload control block (1131 of Fig. 11) for providing the control signals for the various switches is not shown (but is intended to be included in the device). Some of the waveforms that the elements in Fig. 12 are provided, are in Fig. 13, as described below.

[0084] Fig. 12 explicitly shows a number of elements that are in Fig. Figure 11 are not shown, but can be added in various embodiments. A switch NLO2 1207 is connected between SRCGND and a node between BLS 1206 and BLC2 1211, allowing BL 1205 or BLI to be precharged or set to different voltage levels from SRCGND. A switch INV 1216 is connected between the discharge transistor DT 1215, allowing the read amplifier to be selectively isolated from SRCGND, since the SRCGND node may be connected to a line commonly shared by a large number of other read amplifiers. A switch GRS 1217 is connected in parallel to DT 1215, which allows DT 1215 to be bypassed if, for example, the level at BLI is low, so that DT 1215 is off, and the read amplifier has to discharge the DCOM node to SRCGND via DT 1215.These and various other switches can be added to the reading amplifier circuit to improve operation and versatility.

[0085] The embodiment of Fig. Section 12 also includes some additional elements that are not directly involved in the main read operations described herein, but which can also contribute to their versatility. A switch BIAS 1204 can connect the bit line to a BLBIAS level, which can be used when biasing a selected bit line for various storage operations. Another path to the central SCOM node is also provided through a switch BLX 1241 (and possibly additional switches) to a high read amplifier voltage VHSA. Although it is not used in the main read operations described herein (where all data states are read into the read amplifier by discharging the SRC line 1203 through the memory cell 1201), more standard read operations, such as those described in Section 1204, could be used. Fig. As shown in diagram 10A (where the read amplifier / bit line discharges through memory cell 1201 into SRC 1203), use switch BLX 1241. For example, instead of showing all states as in Fig. To read 10C by successively increasing CGRV from 0V through the various read values, the approach of Fig. 10C can be used for negative Vt states and then applied to the approach of Fig. 10A for non-negative Vt states, which occur when using the approach of Fig. 10A does not require a negative CGRV value, it can be switched.

[0086] As above in relation to Fig. As described in section 11, the reading amplifier arrangement can be used by Fig. 12 are used to perform a read operation on a selected memory cell by means of a first phase using the first of the discharge path "BL path" to discharge the source line 1203 through the selected memory cell 1201 and further through the discharge transistor DT 1215 to SRCGND. This sets the node at BLI and the control gate at DT 1215 to a voltage level that depends on the data state of the memory relative to the voltage level CGRV at the corresponding word line. Once the level at the BLI node is stabilized, switches BLC2 1211 and BLC 1213 are turned off, which leaves the control gate of DT 1215 floating, with the conductance of DT 1215 being determined by the conductance of the selected memory cell 1201.In the second phase, switch XXL 1221 is activated to discharge the pre-charged node SEN through DT 1215 to SRCGND at a rate based on the conductivity of DT 1215, which in turn is based on the conductivity of memory cell 1201. After a discharge period, the level at SEN is detected by latch 1225 to obtain the read result.

[0087] To reduce noise in the BLI node and the gate of the discharge transistor DT 1215 when switches BLC2 1211 and BLC 1213 are turned off during the transition, the decoupling capacitor Cdecop 1212 is included. This capacitor helps to compensate for and correct potentially unwanted coupling to the gate of the discharge transistor DT 1215, providing a more accurate reading. The lower plate of Cdecop 1212 is connected to the BLI node, and the upper plate is connected to a BLI_BST level, which allows the decoupling capacitor Cdecop 1212 to monitor operating conditions, such as temperature, and device parameters to obtain a more accurate reading. In some embodiments, the Cdecop 1212 can be implemented as a transistor, of which both its source and drain are connected to the BLI node and its control gate is connected to the BLI_BST level.

[0088] Another noise source during the phase transition and subsequent discharge of the SEN node can originate from noise at the SRCGND level, where the SRCGND line is typically shared by a large number of read amplifiers simultaneously supplying current to the SRCGND line. An additional current source through the switch NLO 1218 is connected to a read amplifier voltage LVSA to provide a holding current through the discharge transistor 1215. A clamping device DCL 1219 clamps the drain voltage (at node DCOM) of the discharge transistor DT 1215 during the read operation. These devices help block any potential noise through the discharge transistor DT 1215 and supply a constant current to the jointly controlled SRCGND node. This can help eliminate the detrimental noise at the SRCGND node during the read operation.

[0089] Fig. 13 presents waveforms for the control signals from the bias circuit for some of the control signals for Fig. Figure 12 represents an embodiment for a read operation. The waveforms are marked at times t0 - t10, where t0 - t3 is a preparatory period; t3 - t6 is the first phase, during which the source line SRC 1203 is discharged into the read amplifier and the level at the control gate of the discharge transistor DT 1215 is set; t6 - t8 is the transition between phases; t8 - t9 is the second phase, when the SEN node is discharged along the second discharge or SEN path; and t9 - t10 is the strobe period, when the value is buffered on the SEN node.

[0090] The control signals for some of the devices in Fig. 12 are not in the waveforms of Fig. 13 included. INV 1216 is switched on, and GRS 1217 is switched off for the entire period shown. The bit line selector switch BLS 1206 is switched on for the entire period, or at least until the first phase ends at t6. As discussed above, switches BIAS 1204 and BXL 1241 are switched off with respect to Fig. The described read operation 13 is not active and both would be switched off. DCL 1219 acts as a voltage terminal for the DCOM node and has configured its gate for this purpose.

[0091] Starting at t0 for Fig. At t0 and t1, BL 1205, nodes BLI, SCOM, SEN, and SRCGND are all low, as are the control signals at NLO2 1207, BLC2 1211, BLC 1213, XXL 1221, the CLK signal to the disk of Csen 1223, and NLO. Between t0 and t1, the array is biased. This may involve setting the SRC line 1203, the selected and unselected word lines, selection gates, or other levels required to bias a selected memory cell 1201, depending on the array architecture.

[0092] Between t1 and t2, the initial levels for the read amplifier are set. The SRCGND line is raised to an initial high value, and NLO2 1207 is switched on, as is BLC2 1211. This sets the values ​​at BL 1205 and the node at BLI to high. Once the bit line and the internal bit line between t2 and t3 are set, NLO2 is switched off, and SRCGND is lowered to the level used during the subsequent discharge phases.

[0093] The first unloading phase along the first, in Fig. 11 and Fig. The discharge path labeled BL path 12, when the source line SRC 1203 discharges through the selected memory cell 1201 into the read amplifier, begins at t3 when BLC 1213 is switched on, thus connecting the central common read node SCOM to BLI. The bit line BL 1205 and BLI begin to discharge between t3 and t4 while the SCOM is charging. The level on all three of these upper traces depends on the conductivity of the selected memory cell, where HC is a highly conductive cell, MC is a cell of medium conductivity, and NC is a non-conductive cell. As shown, BL, BLI, and SCOM stabilize at t4 with the highly conductive cell at its highest, the non-conductive cell at its lowest, and the intermediate state in the middle.To prepare for the next phase, the SEN node is pre-charged at t4, which can be done by Latch 1225, followed by raising the CLK signal at Csen 1223 at t5, which further increases the level at SEN. By t6, the level at BLI (and the control gate of DT 1215) is stabilized at a level based on the conductivity of the selected memory cell, and the SEN node is pre-charged, thus establishing the conditions for the second discharge phase.

[0094] At t6, BLC2 1211 and BLC 1213 are switched off, isolating the BLI node so that from t7 onwards, BLI is floating (represented by the dashed lines) at a level based on the conductance of the memory cell. This disconnects the discharge path from the source line SRC 1203 and causes the bit line 1205 to go high, where it remains for the rest of the process, and SCOM discharges through the discharge transistor DT 1215, jumping around. This also introduces coupling noise in BLI and the gate of DT 1215, as shown in Fig. Figure 13 is represented by the jagged contour of the BLI levels between t6 and t8. The decoupling capacitor Cdecop 1212 is used to help correct this noise, with the BLI_BST level on the top plate of the Cdecop 1212 able to track temperature and device corners to provide a more accurate reading.

[0095] The fluctuations at the SCOM and BLI nodes also introduce noise onto SRCGND, which can be very sensitive to noise, as illustrated by the jagged outline of SRCGNE between t6 and t7. To help eliminate this noise, the additional current from NLO 1218 and the DCL 1219 terminal for holding the level at DCOM assists in stabilizing the SRCGND and SCOM nodes. As shown in the lower line, NLO 1218 is switched on to provide the additional holding current at t7.

[0096] At t6, the SEN node is pre-charged, and the control gates of DT 1215 and SRCGND have stabilized. XXL 1221 is then switched on to discharge the SEN node. The transition to XXL 1221 can again introduce noise into SRCGND, the stabilization of which will also be supported by the holding current of NLO 1218. When XXL 1221 switches on at t8, SCOM and SEN begin to discharge at a rate determined by the gate voltage at DT 1215, which in turn is determined by the conductivity of the memory cell. As shown, between t8 and t9, the HC state discharges fastest, the NC state shows almost no discharge, while the MC state drops in the middle range. At t9-t10, the level at SEN is buffered, after which the read operation is complete.

[0097] Fig. 14 is a flowchart that shows an embodiment of a process for a read operation for the read amplifier of Fig. 12 using the waveforms of Fig. Section 13 describes this. Starting in step 1401, the selected memory cell 1201, source line 1203, and all other array elements (selection gates, unselected memory cells on the same NAND string, etc.) are pre-loaded in preparation for the read operation. This corresponds to section t0 - t1 of Fig. 13. In step 1403, the bit line BL 1205 and internal bit line BLI are charged, corresponding to the period from t1 - t3 of Fig. 13 corresponds to this. The first discharge phase then begins in step 1405.

[0098] In step 1405, switch BLC 1213 is turned on, and source SRC 1203 begins the first discharge phase through the selected memory cell 1201 along the first discharge path (B1 path), eventually stabilizing at a level dependent on the conductivity of the selected cell 1201. The level at BLI during this process is also the level at the control gate of the discharge transistor DT 1215, which corresponds to step 1407. Steps 1405 and 1407 take place during the period t3 - t6 of Fig. 13 instead.

[0099] The SEN node is preloaded in step 1409. In the embodiment of Fig. 13 This occurs during the period t4 - t6 during the first discharge phase along the BL path. Other embodiments may include this step earlier or later, as long as the SEN node is prepared for a subsequent discharge along the SEN path in step 1415.

[0100] Steps 1411 and 1413 are part of the transition between the two phases, corresponding to period t6 - t8 in the embodiment of Fig. 13. In step 1411, the BL path is interrupted for discharge, and the control gate of DT 1215 is set to float at the level of BLI by turning off switches BLC2 1211 and BLC 1213. The capacitor Cdecop 1212 helps to reduce noise in BLI, and connecting the upper plate to the BLI_BST level can be helpful in case of variations due to operating conditions or process corners. In step 1413, the auxiliary holding current of NLO 1218 is applied, which helps to stabilize SRCGND.

[0101] The second discharge phase for the second discharge path, the SEN path, which corresponds to the period t8, t9, begins in step 1415. The switch XXL 1221 is turned on and the SEN node discharges through DT 1215, whose control gate was set in step 1407 based on the conductivity of the selected memory cell 1201. For the embodiment of Fig. In step 13, the holding current is allowed to run during this period to keep the SRCGND noise low. In step 1417, the level at SEN is buffered to provide the read result and complete the read operation.

[0102] According to a first set of aspects, a device includes a discharge transistor, a first discharge path, a second discharge path, and a bias circuit. The first discharge path is configured to connect a selected bit line to the discharge transistor, and the second discharge path is configured to connect a read node to the discharge transistor. The bias circuit is configured to read a memory cell connected to the selected bit line by setting a gate voltage at the discharge transistor through a voltage level on the first discharge path, followed by the first discharge path being opened while the gate voltage at the discharge transistor remains floating at the voltage level, and the read node being discharged through the second discharge path by the discharge transistor.

[0103] According to other aspects, a device includes a transistor and a first, a second, and a third switch. The first and second switches are connected in series between a selected memory cell and the transistor, with a control gate of the transistor connected to a node between the first and second switches. The first and second switches are configured to discharge the selected memory cell through the transistor when they are simultaneously turned on, and to adjust the transistor's control gate so that it floats at a voltage level across the node between the first and second switches when the first and second switches are simultaneously turned off.The third switch is connected between a read node and the transistor and is configured to discharge the read node through the transistor, with the control gate of the transistor set to float on the voltage level at the node between the first switch and the second switch.

[0104] Other aspects include a method that involves discharging a selected memory cell through a first discharge path by a read amplifier and setting a voltage at a control gate of a discharge transistor to a voltage level along the first discharge path, the voltage level depending on a data state of the selected memory cell. Subsequently, an additional current is supplied through the discharge transistor, and while the additional current is supplied by the discharge transistor, a read node is discharged through the discharge transistor, the control gate of the discharge transistor being set to the voltage level that depends on the data state of the selected memory cell.

[0105] Further aspects include a system comprising a first transistor, a first switch, a second switch, and a power source. The first switch is connected between a selected memory cell and the gate of the first transistor and is configured to set a voltage level at the gate of the first transistor corresponding to a data state of the selected memory cell. The second switch is connected between a read node and the first transistor and is configured to discharge the read node through the first transistor, with the gate of the first transistor set to the voltage level corresponding to the data state of the selected memory cell.The power source is set up to supply an additional current through the first transistor after the voltage level at the gate of the first transistor has been set according to the data state of the selected memory cell and before the first transistor has discharged the read node.

[0106] According to further aspects, a read amplifier circuit includes a transistor connected to a discharge node; means for discharging a selected memory cell through a discharge path of the read amplifier circuit; means for setting a control gate of the transistor to a voltage level that depends on a data state of the selected memory cell at a node of the discharge path while the selected memory cell is being discharged; and means for discharging a read node through the transistor while the control gate of the transistor is set to the voltage level that depends on the data state of the selected memory cell.

[0107] Embodiments of the means for discharging a selected memory cell may include the elements required to bias the selected element of a memory array, including the memory cell, source, and bit lines, so that when the memory cell is conducting, it discharges from its source line into its bit line and further into the read amplifiers. This can be used to drive the various drivers and decode elements of blocks 124, 128, and 132, as required for the array structures such as those in the Fig. Figures 1B and 3-5 illustrate. Within the read amplifier, the means for discharging a selected memory cell may include the switches and bias control circuitry for those switches to provide the discharge path for a selected bit line, including those shown in the Fig. 11 and Fig. The topologies shown in Figure 12 for the path shape of the bit line BL are examples such as BLC2 1111 / 1211, BLC 1113 / 1213, and DT 1115 / 1215, but other topologies and arrangements of switches and transistors can be used. Embodiments for the means of setting a control gate of the transistor to a voltage level may involve connecting the gate of the transistor to a level that reflects the conductivity of the memory cell, such as connecting the gate of DT 1115 / 1215, as shown in Figure 12. Fig. 11 and Fig.12, or with another point on the path through which the cell is discharged, or with another level based on the state of the memory cell, such as the gate of another transistor used to discharge the memory cell. Embodiments for the means of discharging a read node may include switches, such as XXL 1121 / 1221, connecting the read node to the discharge transistor, and means of pre-charging a holding charge onto the read node, such as capacitor Csen 1123 / 1223.

[0108] For the purposes of this document, reference in the description to “one embodiment”, “some embodiments” or “another embodiment” may be used to describe different embodiments or the same embodiment.

[0109] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is described as connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intermediate elements. When an element is described as directly connected to another element, there are no intermediate elements between the element and the other element. Two devices are "in communication link" if they are connected, directly or indirectly, such that they can exchange electronic signals.

[0110] For the purposes of this document, the term “based on” may be read as “at least partially based on”.

[0111] For the purposes of this document, without additional context, the use of numerical expressions such as a "first" object, a "second" object, and a "third" object may not imply a sorting of objects, but may instead be used for identification purposes to distinguish between different objects.

[0112] For the purposes of this document, the term “set” of objects can refer to a “set” of one or more of the objects.

Claims

[1] comprising a device: a transistor (1115, 1215); a first switch (1111, 1211) and a second switch (1113, 1213) connected in series between a selected memory cell (1101, 1201) and the transistor, wherein a control gate of the transistor is connected to a node (BLI) between the first switch and the second switch, wherein the first switch (1111, 1211) and the second switch (1113, 1213) are configured to discharge the selected memory cell through the transistor (1115, 1215) when they are simultaneously switched on, and are configured to set the control gate of the transistor (1115, 1215) to float at a voltage level at the node between the first switch (1111, 1211) and the second switch (1113, 1213) when the first switch and the second switch are simultaneously switched off; and a third switch (1121, 1221) connected between a read node (SEN) and the transistor (1115, 1215), wherein the third switch (1121, 1221) is configured to discharge the read node through the transistor, wherein the control gate of the transistor is set to float on the voltage level at the node between the first switch (1111, 1211) and the second switch (1113, 1213). [2] Device according to claim 1, further comprising: an additional current source (1218) which is set up to provide an additional current through the transistor (1115, 1215) after the first and second switches (1111, 1211; 1113, 1213) are switched off and before the third switch (1121, 1221) is switched on. [3] Device according to claim 1, further comprising: a decoupling capacitor (1212) with a first plate connected to the control gate of the transistor (1115, 1215). [4] Device according to claim 3, further comprising: a bias circuit which is set up to apply a voltage level dependent on operating conditions to a second plate of the decoupling capacitor (1212) after the first and second switches (1111, 1211; 1113, 1213) are switched off and before the third switch (1121, 1221) is switched on. [5] Device according to claim 1, further comprising: a bit line (1105, 1205) through which the selected memory cell (1101, 1201) is connected to the first and second switches; a source line (1103, 1203), wherein the selected memory cell (1101, 1201) is connected between the source line and the bit line (1105, 1205); and a bias circuit that is set up to set the source line (1103, 1203) to a higher voltage than the bit line (1105, 1205) during a read operation. [6] Device according to claim 5, further comprising: a word line connected to a control gate of the selected memory cell (1101, 1201), wherein the bias circuit is set up to perform a read operation for a negative threshold voltage state by applying a non-negative voltage to the word line. [7] Device according to claim 6, wherein the bias circuit is further configured to perform a read operation for a positive threshold voltage state by discharging the bit line (1105, 1205) through the memory cell (1101, 1201) to the source line. [8] Device according to claim 1, wherein the device comprises a storage array of a monolithic three-dimensional semiconductor storage device in which memory cells, including the selected memory cell (1101, 1201), are arranged in several physical planes over a silicon substrate and comprise a charge storage medium. [9] Methods, exhibiting: Discharge (1405) of a selected memory cell (1101, 1201) through a first discharge path by a read amplifier; Setting (1407) a voltage at a control gate of a discharge transistor (1115, 1215) to a voltage level along the first discharge path, wherein the voltage level depends on a data state of the selected memory cell (1101, 1201); subsequent provision (1413) of an additional current through the discharge transistor (1115, 1215); and while the additional current is provided by the discharge transistor (1115, 1215), discharge (1415) of a read node (SEN) by the discharge transistor, wherein the control gate of the discharge transistor is set to the voltage level which depends on the data state of the selected memory cell (1101, 1201). [10] The method of claim 9, further comprising: Providing the additional current to the discharge transistor (1115, 1215) via a clamping transistor, through which the read node is discharged; and Biasing of the clamping transistor to maintain a constant voltage level at a node between the clamping transistor and the discharge transistor.

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