Power semiconductor devices and methods for their manufacture

Abstract

Power semiconductor device (1) comprising: - a semiconductor body (10) with a front face (10-1) coupled to a first load terminal structure (11), a rear face (10-2) coupled to a second load terminal structure (12), and a lateral chip edge (109); - an active region (16) configured in a conducting state of the power semiconductor device (1) to conduct a load current between the first load terminal structure (11) and the second load terminal structure (12); - an edge termination region (17) separating the active region (16) from the lateral chip edge (109);- an insulating layer (15) arranged on the front face (10-1), wherein a lateral edge (151) of the insulating layer (15) defines at least one contact hole (H), the contact hole (H) being filled with a metal and / or polysilicon layer (111) in contact with a doped semiconductor region (1711) of the semiconductor body (10); and - a hard passivation layer (18) arranged on the front face (10-1) in at least a part of the edge termination region (17) such that the hard passivation layer (18) does not extend above the lateral edge (151) of the insulating layer (15), the hard passivation layer (18) at least partially covering the metal and / or polysilicon layer (111).

Description

TECHNICAL FIELDThis description relates to embodiments of a power semiconductor device. In particular, this description relates to embodiments of a power semiconductor device having a hard passivation layer arranged at least in a part of an edge termination region.BACKGROUNDMany functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving an electric motor or electric machine, depend on power semiconductor devices. Insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name just a few, have been used for a variety of applications, including, but not limited to, switches in power supplies and power converters, e.g., in traction applications.A power semiconductor device usually comprises a semiconductor body configured to conduct a load current along a load current path between two load terminals of the device. Further, if the power semiconductor device has a transistor configuration, the load current path may be controlled by means of an insulated electrode, often referred to as a gate electrode. For example, upon receiving a corresponding control signal, e.g. from a driver unit, the control electrode may put the power semiconductor device in a conducting state or a blocking state.Further, the power semiconductor device for conducting the load current may comprise one or more power cells, which may be arranged in a so-called active region of the power semiconductor device. The power semiconductor device may be laterally bounded by an edge. Between the lateral edge and the active region comprising the one or more power cells, an edge termination region, which may comprise an edge termination structure, may be arranged. Such an edge termination structure may serve the purpose of influencing the course of an electric field within the semiconductor body, e.g. to ensure a reliable blocking capability of the power semiconductor device. The termination structure may include one or more components arranged within the semiconductor body and also one or more components arranged above a surface of the semiconductor body.A common example of such edge termination concepts is a combination of p-doped polysilicon field rings with field plates, wherein the field plates may be configured to provide effective shielding of external charges. For example, the field plates may comprise a metal, such as aluminum. Alternatively, such field plates may be formed of polysilicon, e.g., to make the edge termination structure less susceptible to corrosion when exposed to moisture and electrical fields. For example, in an edge termination structure combining p-doped field rings with n-doped polysilicon field plates, there may still be metallic layers present to provide electrical contact between a field plate and a field ring, reducing the influence of an electric field on the outer edges of the metallic layers.Usually, one or more passivation layers such as a hard passivation layer comprising an oxide and a nitride are provided in the edge termination region. For example, such a passivation layer may be arranged above an edge termination structure, so as to protect the semiconductor surface including the edge termination structure from electrical and chemical contaminants, such as ions.It is generally desirable to provide edge termination and passivation concepts that are reliable even under harsh environmental conditions encountered, for example, in traction applications. For this purpose, it may be desirable to make edge termination structures less susceptible to corrosion under the combined influence of moisture and electric fields. Device performances under such conditions are usually tested by heavily accelerated reliability tests such as, for example, HV-H3TRB or H 2 S.US 2015 / 0048450A1 shows, in FIG. 1A there, a section of an edge region of a power semiconductor component which has an IGBT structure and a protection diode connected between collector and gate of the IGBT. An edge termination region adjoins an active region. In the edge termination region, a horizontally extending polysilicon layer is arranged on the front side of a LOCOS oxide layer.US2018 / 0047652A1 shows an edge region of a power semiconductor device in FIG. 12. A so-called PSG (phosphosilicate glass) layer is provided there.US 2016 / 0204192A1 discloses a power semiconductor device having a so-called super junction structure.SummaryAccording to an example, a power semiconductor device has a power semiconductor transistor configuration and comprises: a semiconductor body having a front side coupled to a first load terminal structure, a rear side coupled to a second load terminal structure, and a lateral chip edge; an active region configured in a conductive state of the power semiconductor device for conducting a load current between the first load terminal structure and the second load terminal structure; and an edge termination region separating the active region from the lateral chip edge. On the front side, the edge termination region comprises a protection region that does not comprise any metallic structures, unless the metallic structure is electrically shielded from below by a polysilicon layer extending a lateral distance of at least 20 μm further to the lateral chip edge than the metallic structure. In a blocking state of the power semiconductor device, the protection region is configured to accommodate a voltage change of at least 90% of a blocking voltage within the semiconductor body in a lateral direction from the active region towards the lateral chip edge.According to an example, a power semiconductor device has a power semiconductor transistor configuration and comprises: a semiconductor body having a front side coupled to a first load terminal structure, a rear side coupled to a second load terminal structure, and a lateral chip edge; an active region configured in a conductive state of the power semiconductor device for conducting a load current between the first load terminal structure and the second load terminal structure; and an edge termination region separating the active region from the lateral chip edge. On the front side, the edge termination region comprises a protection region that does not comprise any metallic structures, unless the metallic structure is electrically shielded from below by a polysilicon layer extending a lateral distance of at least 20 μm further to the lateral chip edge than the metallic structure. In a vertical cross-section, the protection region extends from a starting point along the lateral direction to the lateral chip edge, wherein the starting point is at a distance of at most 30 μm from an outermost point, where a doped semiconductor region is in contact with a metal layer electrically connected to the first load terminal structure.According to another embodiment, a power semiconductor device comprises: a semiconductor body having a front side coupled to a first load terminal structure, a back side coupled to a second load terminal structure, and a lateral chip edge; an active region configured in a conductive state of the power semiconductor device for conducting a load current between the first load terminal structure and the second load terminal structure; an edge termination region separating the active region from the lateral chip edge; an insulation layer arranged on the front side, wherein a lateral edge of the insulation layer defines at least one contact hole, wherein the contact hole is filled with a metal layer that is in contact with a doped semiconductor region of the semiconductor body; and a hard passivation layer disposed on the front side in at least a part of the edge termination region in such a manner that the hard passivation layer does not extend above the lateral edge of the insulation layer. The hard passivation layer at least partially covers the metal and / or polysilicon layer.According to a further embodiment, a power semiconductor device comprises: a semiconductor body having a front side coupled to a first load terminal structure, a rear side coupled to a second load terminal structure, and a lateral chip edge; an active region configured in a conductive state of the power semiconductor device for conducting a load current between the first load terminal structure and the second load terminal structure; an edge termination region separating the active region from the lateral chip edge; a hard passivation layer arranged on the front side in at least a part of the edge termination region, wherein the hard passivation layer comprises an oxide layer having an oxide layer thickness; and a metal layer arranged on the front side in at least a part of the edge termination region and having a lateral edge; An insulation layer arranged at least in a part of the edge termination region at the front side, wherein a lateral edge of the insulation layer is covered by the metal layer, in a cross section along a vertical direction pointing from the front side to the back side, wherein the cross section is perpendicular to the lateral edge, a common lateral extension area of the hard passivation layer and the metal layer is at most 10 times the oxide layer thickness. The common extension region does not extend over a single lateral edge of the insulation layer within the edge termination region.According to an example, a method of processing a power semiconductor device comprises the steps of: providing a semiconductor body having a front side, a back side and a lateral chip edge; and generating an active region configured in a conductive state of the power semiconductor device for conducting a load current between a first load terminal structure arranged on the front side and a second load terminal structure arranged on the back side; and generating an edge termination region separating the active region from the lateral chip edge, wherein the edge termination region on the front side comprises a protection region that does not comprise any metallic structures except the metallic structure is electrically shielded from below by a polysilicon layer extending a lateral distance of at least 20 μm further to the lateral chip edge than the metallic structure; and wherein the protection region in a blocking state of the power semiconductor device is configured to accommodate a voltage change of at least 90% of a blocking voltage within the semiconductor body in a lateral direction from the active region towards the lateral chip edge.According to an example, a method of processing a power semiconductor device comprises the steps of: providing a semiconductor body having a front side, a back side and a lateral chip edge; and generating an active region configured in a conductive state of the power semiconductor device for conducting a load current between a first load terminal structure arranged on the front side and a second load terminal structure arranged on the back side; and generating an edge termination region separating the active region from the lateral chip edge, wherein the edge termination region on the front side comprises a protection region that does not comprise any metallic structures, unless the metallic structure is electrically shielded from below by a polysilicon layer extending a lateral distance of at least 20 μm further to the lateral chip edge than the metallic structure. In a vertical cross-section, the protection region extends from a starting point along the lateral direction to the lateral chip edge, wherein the starting point is at a distance of at most 30 μm from an outermost point, where a doped semiconductor region is in contact with a metal layer electrically connected to the first load terminal structure.According to a further embodiment, a method for processing a power semiconductor device comprises the following steps: providing a semiconductor body having a front side, a rear side and a lateral chip edge; and generating an active region configured in a conductive state of the power semiconductor device for conducting a load current between a first load terminal structure arranged on the front side and a second load terminal structure arranged on the rear side; generating an edge terminal region separating the active region from the lateral chip edge; generating an insulation layer on the front side such that a lateral edge of the insulation layer defines at least one contact hole; filling the contact hole with a metal layer such that a contact is made with a doped semiconductor region of the semiconductor body; and creating a hard passivation layer on the front side in at least a part of the edge termination region in such a way that the hard passivation layer does not extend above the lateral edge of the insulation layer. The hard passivation layer at least partially covers the metal layer.According to another embodiment, a method for processing a power semiconductor device comprises the steps of: providing a semiconductor body having a front side, a back side and a lateral chip edge; and generating an active region configured in a conductive state of the power semiconductor device for conducting a load current between a first load terminal structure arranged on the front side and a second load terminal structure arranged on the back side; generating an edge termination region separating the active region from the lateral chip edge; generating a hard passivation layer on the front side in at least a part of the edge termination region, wherein the hard passivation layer comprises an oxide layer having an oxide layer thickness; and generating a metal layer on the front side in at least a part of the edge termination region, wherein the metal layer has a lateral edge; and generating an insulation layer arranged at least in a part of the edge termination region at the front side, wherein a lateral edge of the insulation layer is covered by the metal layer. In a cross section along a vertical direction pointing from the front side to the back side, wherein the cross section is perpendicular to the lateral edge, a common lateral extension area of the hard passivation layer and the metal layer is at most 10 times the oxide layer thickness. The common extension region does not extend over a single lateral edge of the insulation layer within the edge termination region.Additional features and advantages will become apparent to those skilled in the art upon reading the following detailed description and upon consideration of the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGSThe parts in the figures are not necessarily drawn to scale, emphasis instead being placed upon illustrating principles of the invention. In addition, like reference numerals designate corresponding parts in the figures. In the drawings, the following applies: FIGS. 1A-C each schematically and exemplarily illustrate a portion of a vertical projection of a power semiconductor device according to one or more embodiments; FIG. 2 schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; FIG. 3 schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; FIG. 4 schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; FIG. 5 schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; and FIG. 6 is an enlarged view of a portion of FIG. 5.DETAILED DESCRIPTIONIn the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.In this regard, directional terminology such as "top," "bottom," "below," "front," "behind," "back," "leading," "pendant," "below," "above," etc. is used with reference to the orientation of the described figures. Because portions of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation and is not intended to limit the invention. For example, features illustrated or described as part of one embodiment may be applied to or combined with other embodiments to obtain yet another embodiment. The present invention is intended to include such modifications and variations. The examples are described using a specific language, which is not to be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements or fabrication steps have been designated by the same reference numerals throughout the several drawings, unless otherwise indicated.The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may be, for example, the surface of a semiconductor wafer or a die. Each of the below-mentioned first lateral direction X and the below-mentioned second lateral direction Y may be horizontal directions, for example, and the first lateral direction X and the second lateral direction Y may be perpendicular to each other.The term "vertical" as used in this specification is intended to describe an orientation oriented substantially perpendicular to the horizontal surface, i.e., parallel to the normal of the surface of the semiconductor wafer. The below-mentioned vertical direction Z may be, for example, a vertical direction perpendicular to both the first lateral direction X and the second lateral direction Y.In this specification, n-doped is referred to as a "first conductivity type", whereas p-doped is referred to as a "second conductivity type". Alternatively, reverse doping relationships may be employed such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.Further, the term "dopant concentration" in this specification may refer to an average dopant concentration or to an average dopant concentration or to a surface charge carrier concentration of a particular semiconductor region or region. Thus, for example, a statement that a particular semiconductor region has a particular dopant concentration that is higher or lower compared to a dopant concentration of another semiconductor region may indicate that the respective average dopant concentrations of the semiconductor regions are different from each other.In the context of the present specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe that there is a low ohmic electrical connection or current path between two regions, portions, zones, portions or parts of a semiconductor device or between different terminals of one or more devices or between a terminal or metallization or electrode and a portion or part of a semiconductor device. Further, the term "in contact" in the context of the present description is intended to describe that there is a direct physical connection between two elements of the corresponding semiconductor device; e.g., a transition between two elements in contact with each other may not include a further intermediate element or the like.Additionally, in the context of the present specification, the term "electrical isolation" is used in the context of its generally valid understanding, unless otherwise indicated, and is thus intended to describe that two or more components are positioned separately from each other and that there is no ohmic connection connecting these components. However, components that are electrically insulated from each other may nevertheless be coupled to each other, for example mechanically coupled and / or capacitively coupled and / or inductively coupled. To cite an example, two electrodes of a capacitor may be electrically insulated from each other and may simultaneously be mechanically and capacitively coupled to each other, e.g. by means of an insulation, e.g. a dielectric.Specific embodiments described in this specification relate to, but are not limited to, a power semiconductor device having a strip cell or pin cell configuration, such as a power semiconductor transistor that may be used within a power converter or power supply. Accordingly, in one embodiment, the semiconductor device is configured to carry a load current to be supplied to a load and / or which is each provided by a power source. For example, the semiconductor device may comprise one or more active power unit cells, such as a monolithically integrated diode cell and / or a monolithically integrated transistor cell and / or a monolithically integrated IGBT cell and / or a monolithically integrated RC-IGBT cell and / or a monolithically integrated MOS gated diode (MGD) cell and / or a monolithically integrated MOSFET cell and / or derivatives thereof. Such a diode cell and / or such transistor cells may be integrated in a power semiconductor module. A plurality of such cells may represent a cell array arranged with an active region of the power semiconductor device.The term "power semiconductor device" as used in this specification is intended to describe a single-chip semiconductor device having high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor device is intended for a high current, typically in the Ampere range, e.g. of up to several tens or hundreds of Ampere or even up to several kA, and / or for high voltages, typically above 100 V, more typically 500 V and above, e.g. up to at least 1 kV, up to at least 6 kV. For example, the semiconductor device described below may be a semiconductor device having a strip cell configuration or a pin cell configuration and which may be configured to be employed as a power component in a low, medium and / or high voltage application.For example, the term "power semiconductor device" as used in this specification does not refer to logic semiconductor devices used, e.g., for storing data, computing data, and / or other types of semiconductor-based data processing.FIGS. 1A to 1C each schematically and exemplarily illustrate a portion of a vertical projection of a power semiconductor device 1 according to some embodiments. The illustrated vertical projection is in each case parallel to a plane defined by a first lateral direction X and a second lateral direction Y and orthogonal to a vertical direction Z. The power semiconductor device 1 comprises a semiconductor body 10 having a lateral chip edge 109. Further, the power semiconductor device 1 comprises an active region 16 configured to conduct a load current (e.g. substantially along the vertical direction Z) and an edge termination region 17 laterally arranged between the chip edge 109 and the active region 16. As can be seen in each of FIGS. 1A to 1C, the active region 16 may be laterally surrounded by the edge termination region 17.For example, the active region 16 comprises one or more power cells 14 each extending at least partially into the semiconductor body 10. The present specification is not limited to a specific type of configuration of the one or more power cells 14. Rather, the power cells 14 may have any configuration common to a power semiconductor device, e.g., a diode configuration, a thyristor configuration, a MOS gated diode (MGD) configuration, a transistor configuration such as an IGBT configuration, a reverse conducting (RC) IGBT configuration, a MOSFET configuration, and / or any configuration derived therefrom. One skilled in the art is familiar with these types of configurations. Accordingly, in FIGS. 1A-C, the power cells 14 are only schematically illustrated because the exact configuration is not a major subject matter of this description.For example, the configuration shown in FIG. 1A may correspond to a power diode configuration that includes a single power cell 14. In contrast, the configurations illustrated in FIGS. 1B and 1C represent, for example, semiconductor switch configurations (such as, e.g., a MOSFET and / or IGBT configuration), wherein the power cells 14 may be configured to control a load current by switching the power semiconductor device 1 into a conduction state or a blocking state. Such power cells 14 may comprise, for example, a control structure, such as a MOS control structure. As exemplarily illustrated in FIG. 1B, the power cells 14 may have a stripe configuration extending, e.g., throughout the active region 16 along the second lateral direction Y. In another embodiment, as illustrated in FIG. 1C, the power cells 14 may have a cellular configuration, e.g., with a horizontal cross-section having a square shape, a rectangular shape, a rectangular shape with rounded corners, a circular shape, or an ellipsoidal shape.The one or more power cells 14 which may be included in the active region 16 of the power semiconductor device 1 may be configured to selectively conduct a load current and block a load voltage depending on, e.g., a switching state of the power semiconductor device 1 and / or a direction in which a current and / or a voltage is supplied or applied to the power semiconductor device 1.For example, the power semiconductor device 1 may be configured by means of the at least one power cell 14 to support a blocking voltage of at least 300 V, of at least 500 V, of at least 600 V, of at least 1000 V, of at least 1500 V or of at least 3000 V or of even more than 6000 V. Furthermore, the at least one power cell 14 may have a compensation structure, also referred to as a "superjunction" structure.For example, to control the one or more power cells 14, a control terminal (not illustrated) may be provided that may be configured to pass a control signal to a control electrode structure of the one or more power cells 14. For example, the control terminal may be a gate terminal. Thereby, the power semiconductor device 1 can be set to the conduction state or the blocking state. In an embodiment, such a control signal may be provided by applying a voltage between the control terminal and a first load terminal (not shown in FIGS. 1A-C ).Between the chip edge 109, which may be formed e.g. by means of wafer dicing, and the active region 16, an edge termination structure 171 (not shown in FIGS. 1A-C, see FIGS. 2 to 5 ) may be arranged. In other words, an edge termination structure 171 may be arranged in the edge termination region 17. For example, the edge termination structure 171 may completely surround the active region 16. The edge termination structure 171 is not configured to conduct a load current according to an embodiment, but instead is configured to ensure a reliable blocking capability of the power semiconductor device 1. For example, the edge termination structure 171 comprises a field ring / field plate termination structure. Additionally or alternatively, the edge termination structure may comprise a junction termination extension (JTE) structure and a variation of lateral doping (VLD) structure. One skilled in the art is familiar with these types of edge termination structures.FIGS. 2 to 6 each schematically and exemplarily illustrate a portion of a vertical cross section of the power semiconductor device 1 according to some embodiments. The illustrated cross-sections are parallel to a plane defined by the first lateral direction X and the vertical direction Z, wherein each of the illustrated components may also extend along the second lateral direction Y. FIG. 6 is an enlarged view of a portion of FIG. 5.The portions of the vertical cross-sections shown in FIGS. 2 to 6 are in each case located near the lateral chip edge 109 of the semiconductor body 10 and include a vertical cross-section of at least a part of the edge termination region 17.The semiconductor body 10 is coupled to both a first load terminal structure 11 and a second load terminal structure 12 of the power semiconductor device 1. The first load terminal structure 11 may be (depending on the type of the power semiconductor device) an anode terminal, an emitter terminal or a source terminal arranged on a front side 10- 1 of the semiconductor body 10, for example. Accordingly, the second load terminal 12 may be, for example, a cathode terminal, a collector terminal or a drain terminal arranged on a back side 10- 2 of the semiconductor body 10. For example, the first load terminal 11 and / or the second load terminal 12 may comprise respective front side or back side metallizations.The semiconductor body 10 includes a drift region 100 of a first conductivity type (e.g. n-type). In an embodiment, the drift region 100 is an n -- doped region. As illustrated in FIGS. 2 to 5, the drift region 100 may extend into both the active region 16 and the edge termination region 17 of the power semiconductor device 1. Each of the one or more power cells 14 that may be included in the active region 16 of the power semiconductor device 1 may include a part of the drift region 100. Further, each of the one or more power cells 14 may be configured to conduct a load current across the drift region 100 between the load terminal structures 11 and 12 and to block a blocking voltage applied between the load terminal structures 11 and 12.For example, in some embodiments according to each of FIGS. 1B to 6, the power semiconductor device 1 may be a switching device such as an IGBT or a MOSFET, for example. In this case, the active region 16 comprises a plurality of power cells 14, wherein each power cell 14 may comprise e.g. a trench gate structure as schematically illustrated in FIGS. 2 to 5, which in each case show an outermost power cell 14 of the active region 16. For example, the trench gate structure may be arranged in a stripe configuration as illustrated in FIG. 1B or a cellular configuration (e.g., having a square or rectangular shape in a horizontal cross section) as exemplarily illustrated in FIG. 1C. For example, each of the power cells 14 may include a control electrode (not illustrated in the figures) disposed within a trench 141, wherein the control electrode may be configured to receive a control signal such as a gate voltage from a control terminal (not illustrated) of the power semiconductor device 1. For example, within each power cell 14, the control electrode may be electrically isolated from the first load terminal by an isolation structure, such as an oxide structure, as is well known to one of ordinary skill in the art.Further, each of the cells 14 may include a body region 142 of the second conductivity type (e.g. p-type) and at least one source region 143 of the first conductivity type, the source region 143 being arranged in contact with the first load terminal 11, the body region 142 isolating the at least one source region 143 from the drift region 100. As shown in each of FIGS. 2 to 5, a junction between the body region 102 and the drift region 100 may form a pn junction 103 configured to block a reverse voltage applied in the forward direction between the first load terminal 11 and the second load terminal 12. Within each power cell 14, the respective control electrode may be electrically insulated from each of the source region 143, the body region 142, and the drift region 100 by an isolation structure (indicated schematically by a thick line in FIGS. 2-6 ) such as a gate oxide. For example, the control electrode may be configured to induce a transport channel, such as e.g. an n-channel, in the body region 142 between the source region 143 and the drift region 100, depending on the control signal, thereby enabling the conduction state of the power semiconductor device 1. Instead of such trench cells 14, the semiconductor device 1 may be equipped with so-called planar power switching cells, wherein the gate electrode is located vertically above the semiconductor body 10 (not shown in the figures). One skilled in the art is familiar with the principles and variations of configurations of such trench-based or planar power switching cells 14, and therefore will not be explained in detail.As is also well known to a person skilled in the art, if the power semiconductor device has an IGBT configuration, the semiconductor body 10 may further comprise a back side emitter region 108 of the second conductivity type (e.g. p-type) arranged on the back side 10- 2 in contact with the second load terminal 12. In another variant, in which the power semiconductor device 1 is configured as a MOSFET, for example, such a back side emitter region 108 may be absent and may be replaced by a heavily doped region (drain) of the first conductivity type.It should be noted that the transistor power cell 14 illustrated in each of FIGS. 2 through 5 is only an example implementation of a power cell in the active region 16. For example, in an alternative embodiment of FIG. 1A, a single large power cell 14 may be provided, which may be configured as a power diode cell. For example, the power diode cell 14 comprises an anode region of a second conductivity type (e.g. p-type), wherein the anode region is arranged in contact with the first load terminal 11. Further, a junction between the anode region and the drift region 100 forms a pn junction configured to block a blocking voltage between the first load terminal 11 and the second load terminal 12. Accordingly, although the cross-sections illustrated in FIGS. 2 to 5 in each case illustrate an active region 16 comprising a power cell 14 having a trench gate structure as an example, aspects regarding the configuration of the edge termination region 17 discussed below may also refer to embodiments of the power semiconductor device 1 having a diode configuration, e.g., in the form of a single large power cell 14 within the active region 16.Turning now to the edge termination region 17 according to all embodiments illustrated in FIGS. 1A to 7, the edge termination region 17 may include an edge termination structure 171 not configured to conduct a load current but rather configured to ensure a reliable blocking capability of the power semiconductor device 1. The edge termination structure 171 may be configured to laterally terminate an electric field present in the semiconductor body 10 in a blocking state of the power semiconductor device 1. For example, such an edge termination structure 171 may comprise a junction termination extension (JTE) structure, a field ring / field plate termination structure, a lateral doping variation (VLD) structure and / or a combined VLD-DLC edge termination structure. A person skilled in the art is familiar with these types of edge termination structures as such.In the exemplary embodiments illustrated in FIGS. 2 to 5, the edge termination structure 171 comprises a doped semiconductor region 1711of the second conductivity type. For example, the doped semiconductor region 1711may have a variation of lateral doping (VLD). Further, in the embodiments of FIGS. 2 to 5, the edge termination structure 171 may include an electrically active semi-insulating layer 1712 arranged above a part of the doped semiconductor region 1711. For example, the semi-insulating layer 1712 is electrically insulated from the doped semiconductor region 1711 by at least one insulation layer 15, such as an oxide. The semi-insulating layer 1712 may include, for example, at least one of amorphous silicon (a-Si), semi-insulating polycrystalline silicon (SIPOS), and an electroactive material such as diamond-like carbon (DLC) or hydrogen-containing amorphous carbon (a-C:H). For example, such an electrically active semi-insulating layer may have a specific electrical resistance in a range from 1E07Ωcm to 1E15Ωcm. It may accordingly be configured to ensure a relatively high electrical blocking capability. At the same time, the electric resistivity may be low enough to prevent the accumulation of electric charges, e.g., in a region of the semiconductor body 10 near the hard passivation layer 18.In an embodiment according to each of FIGS. 2 to 6, a hard passivation layer 18 is arranged on the front side 10- 1 within the edge termination region 17. The hard passivation layer 18 may extend at least above a part of an edge termination structure 171, as illustrated in the figures. For example, in an embodiment according to FIGS. 2 and 3, the hard passivation layer 18 may cover the entire edge termination region 17 and may optionally also extend further into the active region 16, as exemplarily illustrated in FIG. 2. In another embodiment, the hard passivation layer 18 may include, for example, some non-contiguous portions.In one embodiment, the hard passivation layer 18 includes an oxide layer 181. For example, the oxide layer 181 may have an oxide layer thickness d 2. The oxide layer thickness d 2 may be, for example, in the range of 50 nm to 5000 nm, e.g., 2700 nm. Additionally, in one embodiment, the hard passivation layer 18 may include a nitride layer 182. For example, nitride layer 182 may be disposed over oxide layer 181, such as on oxide layer 181. Such a nitride layer 182 may have a nitride layer thickness d 3 that is at least 100 nm, such as at least 400 nm or even at least 800 nm.Further, in an embodiment, the edge termination region 17 comprises a protection region 172. The protection region 172 is arranged on the front side 10- 1 of the semiconductor body 10 and does not comprise any metallic structure. This is illustrated by way of example in FIGS. 2 and 3. Note that in this connection, a structure made of polysilicon is not to be understood as a metallic structure. Furthermore, the statement that the protection region 172 does not comprise any metallic structure means, in the present context, that no metallic structure which was produced at the wafer level, e.g. a gate runner electrode or a metal-filled contact hole, is present within the protection region 172. In other words, a metallic structure that may have been arranged, for example, as part of a housing of the power semiconductor device 1 in a later assembly step (e.g. bonding wires) is not to be understood as "metallic structures" in the context of this specification.In another embodiment, a protection region 172 may be provided in the edge termination region 17, wherein the protection region 172 does not comprise any such metallic structures, except the metallic structure is electrically shielded from below by a polysilicon layer 178. This is illustrated by way of example in FIG. 4. In the embodiment shown in FIG. 4, a gate runner electrode GR is arranged on the front side 10- 1 within the edge termination region 17. Such a gate runner electrode GR may be provided for distributing a control signal, which may originate from e.g. a gate driver, to the control electrodes of a plurality of transistor cells 14, which may be arranged in different regions of the active region 16. The function and configuration of such gate runner electrodes is well known to those skilled in the art and will therefore not be described in more detail. As exemplarily illustrated in FIG. 4, a polysilicon layer 178 extends below the gate runner electrode GR. The polysilicon layer 178 may be configured to shield the gate runner electrode GR from below. That is, the polysilicon layer 178 shields the gate runner electrode GR from an electric field that is present in the semiconductor body 10 in the vicinity of the front surface 10- 1, for example, in the blocking state of the power semiconductor device 1. For example, the polysilicon layer 178 may be embedded in an isolation structure, which may be formed by, e.g., oxide layers 1715, 15, as exemplarily illustrated in FIG. 4.In an embodiment variant, such a polysilicon layer 178 shielding a metallic structure within the edge termination region 17 extends by a lateral distance d 5 of at least 15 μm, such as at least 20 μm or even at least 50 μm, further towards the lateral chip edge 109 than the metallic structure. This is exemplarily illustrated in FIG. 4, wherein the metallic structure is a gate runner electrode GR as described above.According to the embodiments illustrated in each of FIGS. 2 to 6, it may be provided that the protection region 172 in a blocking state of the power semiconductor device 1 is configured to accommodate a voltage change of at least 90% of a blocking voltage within the semiconductor body in a lateral direction from the active region 16 towards the lateral chip edge 109. For example, the voltage along the lateral direction X may change within the protection region 172 by at least 90%. For example, such a lateral voltage change may be achieved on the front side 10- 1 of the semiconductor body 10 by means of an edge termination structure 171, as described above, wherein the edge termination structure 171 may be at least partially arranged within the protection region 172.In an embodiment, the protection region 172 extends in a vertical cross section, as exemplarily illustrated in each of FIGS. 2 to 6, from a starting point SP along the lateral direction X to the lateral chip edge 109. The starting point SP may be located at a distance dspof at most 5 μm, such as at most 10 μm or at most 30 μm, from an outermost point P where a doped semiconductor region 1711is in contact with a metal and / or polysilicon layer 111 electrically connected to the first load terminal structure 11. For example, in this context, "outermost" is to be understood as being located near the lateral chip edge 109 (compared to all other points in the vertical cross section where a doped semiconductor region is in contact with a metal layer electrically connected to the first load terminal structure). The doped semiconductor region 1711 may be of the second conductivity type. For example, the doped semiconductor region 1711may form a part of an edge termination structure 171, as exemplarily illustrated in FIGS. 2 to 4. In the embodiments of FIGS. 2 to 4, the portion of the doped semiconductor region 1711 that is in contact with the metal and / or polysilicon layer 111 forms a portion of a drain cell D configured for draining holes from the semiconductor body 10 in certain operating states of the power semiconductor device 1. In other embodiments (not illustrated), the doped semiconductor region in contact with the metal layer may be, e.g., a body region of an outermost power cell of the active region 16. For example, the metal and / or polysilicon layer 111 may form a part of the first load terminal structure 11.In an embodiment, the hard passivation layer 18 does not extend further towards the active region 16 than the protection region 172 (not illustrated). More generally, if the hard passivation layer 18 comprises an oxide layer 181 with an oxide layer thickness d 2, it may be provided that the hard passivation layer 18 extends further towards the active region 16 than the protection region 172 by at most a lateral distance of 10 times the oxide layer thickness d 2. Such a situation is schematically and exemplarily illustrated in FIG. 3.Further, in an embodiment according to each of Figs. 2 to 6, a soft passivation layer 13 may be disposed above at least a part of the hard passivation layer 18. For example, the soft passivation layer 13 includes an organic material such as polyimide and / or an epoxy compound. It is understood that the term "soft passivation layer" in the context of this specification is intended to refer to a dielectric layer that is or has been produced at the wafer level, such as by deposition on a semiconductor wafer. In other words, material layers that may have been arranged, for example, as part of a housing of the power semiconductor device 1 in a later assembly step (e.g. a potting compound) are not to be understood as a "soft passivation layer".In an embodiment, the soft passivation layer 13 may cover the entire edge termination region 17 (see e.g. FIG. 2 ). Further, in an embodiment, the soft passivation layer 13 may also be arranged above the front side 10- 1 in a considerable portion of the active region 16.In another embodiment, as exemplarily illustrated in FIG. 3, the soft passivation layer 13 does not extend further towards the active region 16 than the protection region 172. For example, in this case, the hard passivation layer 18 may extend laterally further towards the active region 16 than the soft passivation layer 13.In an embodiment according to any of FIGS. 2 to 6, the power semiconductor device 1 may comprise an insulation layer 15 arranged on the front side 10- 1, wherein a lateral edge 151 of the insulation layer 15 defines at least one contact hole H. The contact hole H may be filled with a metal and / or polysilicon layer 111. For example, the metal and / or polysilicon layer 111 is in contact with a doped semiconductor region 1711 of the semiconductor body 10. It should be noted that the contact hole H may also be extended in a lateral direction (e.g. along the second lateral direction Y) so as to form an elongated contact notch. For example, the lateral edge 151 of the isolation layer 15 may form a pronounced step topography on the front side 10- 1 of the semiconductor body 10.As illustrated in more detail in FIG. 6, which provides an enlarged view of a portion of FIG. 5, the hard passivation layer 18 may be arranged at least in a part of the edge termination region 17 on the front side 10- 1 in such a manner that the hard passivation layer 18 laterally does not extend beyond a vertical projection V of the lateral edge 151 of the insulation layer 15. In other words, the hard passivation layer 18 may be arranged in such a way that it does not extend into an area extending above the lateral edge 151 of the insulation layer 15. For example, if the hard passivation layer 18 comprises an oxide layer 181 having an oxide layer thickness d 2 as described above, it may be provided that the hard passivation layer 18 laterally ends at a minimum distance d 4 of at least 1 time, such as at least 5 times or even at least 10 times, the oxide layer thickness d 2 away from the vertical projection V of the lateral edge 151 of the insulation layer 15. In a further development, it may be provided that the hard passivation layer 18 ends laterally at a minimum distance d 4 of at least 1 μm from the lateral edge 151 of the insulation layer 15 if the oxide layer thickness d 2 is equal to or less than 1 μm.In an embodiment, the metal and / or polysilicon layer 111 filling the contact hole H may be at least partially covered by a soft passivation layer 13, such as e.g. a polyimide layer 13, as described above. This is schematically illustrated in FIG. 6, where the dashed-dotted line is intended to indicate that the soft passivation layer 13 may optionally extend further towards the active region 16, thereby covering the metal and / or polysilicon layer 111 in the contact hole H.Further, as illustrated in FIG. 6, the power semiconductor device 1 may include one or more layers 111, 174 arranged on the front side 10- 1 at least in a part of the edge termination region 17. For example, such a metal layer 111 establishes an electrical connection between a discharge cell D and the first load terminal 11, as has been described above. Additionally or alternatively, a metal layer 174 may form at least a portion of a gate runner electrode GR, as also described above.The metal layer 111, 174 in each case has at least one lateral edge 111- 1, 174- 1. For example, the lateral edge 111- 1, 174- 1 defines a step topography. As mentioned above, the hard passivation layer 18, which may include an oxide layer 181 having an oxide layer thickness d 2, extends at least in a part of the edge termination region 17.In an embodiment according to FIG. 6, it can be provided that in a cross section along a vertical direction Z, which points from the front side 10- 1 to the rear side 10- 2, wherein the cross section is perpendicular to the respective lateral edge 111- 1, 174- 1, a respective common lateral extension region LX 1, LX 2, LX 3 of the hard passivation layer 18 and the respective metal layer 111, 174 is at most 10 times the oxide layer thickness d 2. For example, the respective common lateral extension region LX 1, LX 2, LX 3 may begin at the respective lateral edge 111- 1, 174- 1. Additionally or alternatively, it may be provided that the common lateral extension region LX 1, LX 2, LX 3 is at least 10 times a metal layer thickness d 6, d 7 of the respective metal layer 111, 174 as measured at the respective lateral edge 111- 1, 174- 1.In one embodiment variant, it can be provided that the common lateral extension range of the hard passivation layer 18 and the respective metal layer at any such lateral edge of a metal layer, which may be present within the edge termination region 17, is at most 10 times the oxide layer thickness and / or at most 10 times a metal layer thickness of the respective metal layer at the respective lateral edge of the metal layer.Further, a soft passivation layer 13 (e.g., comprising a polyimide) may be disposed above at least a portion of the hard passivation layer 18, such as on the hard passivation layer 18 as described above. The soft passivation layer 13 can also extend above a part of the respective metal layer 111, 174 or above the entirety of the metal layer 111, 174. This is schematically illustrated in each of FIGS. 6 and 7, where the dashed-dotted line is intended to indicate that the soft passivation layer 13 may optionally extend further towards the active region 16, thereby covering the metal layer 111, 174.Embodiments of a method for processing a power semiconductor device correspond to the embodiments of the power semiconductor as described above with reference to the figures. Therefore, for example, the features of the embodiments of the power semiconductor device described above with reference to the figures may be achieved by performing respective processing method steps. Embodiments of a method for processing a power semiconductor device may accordingly comprise providing a semiconductor body 10 and forming the respective structures arranged in / on the semiconductor body 10, e.g. by processes such as masked implants of dopants and deposition of semiconductor and / or oxide layers.The embodiments described above include the recognition that the reliability of a power semiconductor device, such as its robustness under a high voltage and high humidity operating condition, may be significantly improved by considering certain design rules with respect to the arrangement of metallic structures and / or passivation layers in an edge termination region of the power semiconductor device.According to one or more embodiments, a protection region may be provided within an edge termination region on the front side of a power semiconductor device, wherein the protection region does not comprise any metallic structure unless the metallic structure is electrically shielded from below by a polysilicon layer extending a lateral distance of at least 20 μm further to a lateral chip edge than the metallic structure, and wherein the protection region is configured, in a blocking state of the power semiconductor device, to accommodate a voltage change of at least 90% of a blocking voltage within the semiconductor body in a lateral direction from the active region towards the lateral chip edge. For example, by providing such a protection region, it may be avoided that the beginning of these metallic structures, which may be covered by a hard passivation layer, is exposed to high electric field strengths during operation of the power semiconductor device.Furthermore, according to one or more embodiments, an insulation layer is arranged on the front side of the power semiconductor device, wherein a lateral edge of the insulation layer defines at least one contact hole, wherein the contact hole is filled with a metal layer which is in contact with a doped semiconductor region of the semiconductor body. A hard passivation layer is arranged on the front side in at least a part of the edge termination region in such a way that the hard passivation layer does not extend above the lateral edge of the insulation layer.Further, according to one or more embodiments, a metal layer and a hard passivation layer comprising an oxide layer are arranged on the front side of a power semiconductor device at least in a part of an edge termination region. The metal layer has a lateral edge. In a cross section along a vertical direction pointing from the front side to the back side of the power semiconductor device, wherein the cross section is perpendicular to the lateral edge, a common lateral extension area of the hard passivation layer and the metal layer is at most 10 times the oxide layer thickness.For example, by keeping the lateral edges of contact holes free of a hard passivation layer and / or by avoiding tight encapsulation of a metal layer edge by a hard passivation layer, an exchange of ions with the environment may still be possible, thereby mitigating or preventing fission corrosion of the metal layer. For example, instead of being subjected to fission corrosion, the metal layer may be subject to moderate self-limiting corrosion, which may not be detrimental to the reliability of the edge termination.Features of further embodiments are defined in the dependent claims. The features of other embodiments and the features of the above-described embodiments may be combined with each other to form additional embodiments, as long as the features are not expressly described as alternative to each other.Previously, embodiments related to a power semiconductor device such as a diode, a MOSFET, or an IGBT and respective processing methods have been explained. These devices are based on silicon (Si), for example. Accordingly, a monocrystalline(s) semiconductor region or layer, e.g. the semiconductor body 10 and its regions / zones, such as the regions 100, 108, 142, 143, 103 and 1711, may be a monocrystalline(s) Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon may be used.However, it is understood that the semiconductor body 10 and its doped regions / zones may be made of any semiconductor material suitable for manufacturing a semiconductor device. Examples of such materials include, but are not limited to, elementary semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AllnN), indium gallium nitride (InGaN), Aluminum gallium indium nitride (AlGaInN) or Indiumgalliumarsenidphosphid (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) to name few. The aforementioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, Aluminiumgalliumnitrid(AlGaN)-Aluminiumgalliumindiumnitrid(AlGaInN ), Indiumgalliumnitrid(InGaN)-Aluminiumgalliumindiumnitrid(AlGalnN ), indium gallium nitride (InGaN ) gallium nitride (GaN ), aluminum gallium nitride (AlGaN ) gallium nitride (GaN ), Indiumgalliumnitrid(InGaN)-Aluminiumgalliumnitrid(AlGaN ), silicon-silicon carbide (Si x C 1-x) and silicon-SiGe heterojunction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs and GaN materials are mainly used at present.Spatially relative terms such as "below," "below," "above," "lower," "above," "upper," and the like are used for convenience of description to explain the positioning of an element relative to a second element. These terms are intended to include different orientations of the corresponding device in addition to those depicted in the figures. Further, terms such as "first", "second", and the like are also used to describe various elements, regions, portions, etc., and are also not intended to be limiting. Throughout the specification, like terms refer to like elements.As used herein, the terms "comprising", "including", "including", "comprising", "presenting", and the like are open ended terms that indicate the presence of the stated elements or features, but do not exclude additional elements or features.List of Reference Numerals1 Power semiconductor device 10 semiconductor body 10- 1 front side 10- 2 back side 100 drift region 109 chip edge 11 first load terminal structure 111 metal and / or polysilicon layer 111- 1 lateral edge 12 second load terminal structure 13 soft passivation layer 14 power cell(s) 141 trench 142 body region 143 source region 15 isolation layer 151 lateral edge of isolation layer 16 active region 17 edge termination region 171 edge termination structure 1711 doped semiconductor region 1712 semi-insulating layer 1715 oxide layer 172 protective layer 174 metal layer 174- 1 lateral edge 178 polysilicon layer 18 hard passivation layer 181 oxide layer 182 nitride layer D drain cell d 2 oxide layer thickness d 3 nitride layer thickness d 4 minimum distance d 5 lateral distance d 6 metal layer thickness d 7 metal layer thickness GR Gate runner electrode H Contact hole LX 1 Lateral extension region LX 2 Lateral extension region LX 3 Lateral extension region X First lateral direction Y Second lateral direction Z Vertical direction

Claims

A power semiconductor device (1) comprising: - a semiconductor body (10) having a front side (10-1) coupled to a first load terminal structure (11), a back side (10-2) coupled to a second load terminal structure (12), and a lateral chip edge (109); - an active region (16) configured in a conductive state of the power semiconductor device (1) for conducting a load current between the first load terminal structure (11) and the second load terminal structure (12); - an edge termination region (17) separating the active region (16) from the lateral chip edge (109); an insulation layer (15) arranged on the front side (10-1), a lateral edge (151) of the insulation layer (15) defining at least one contact hole (H), the contact hole (H) being filled with a metal and / or polysilicon layer (111) which is in contact with a doped semiconductor region (1711) of the semiconductor body (10); and a hard passivation layer (18) arranged on the front side (10-1) in at least a part of the edge termination region (17) in such a way that the hard passivation layer (18) does not extend above the lateral edge (151) of the insulation layer (15), the hard passivation layer (18) at least partially covering the metal and / or polysilicon layer (111).The power semiconductor device (1) according to claim 1, wherein the hard passivation layer (18) comprises an oxide layer (181) having an oxide layer thickness (d2), and wherein the hard passivation layer (18) laterally ends at a minimum distance (d4) of at least once the oxide layer thickness (d2) away from a vertical projection (V) of the lateral edge (151) of the insulation layer (15).The power semiconductor device (1) according to claim 2, wherein the hard passivation layer (18) laterally ends at a minimum distance (d4) of at least 1 μm from the lateral edge of the insulation layer if the oxide layer thickness (d2) is equal to or less than 1 μm.The power semiconductor device (1) according to any one of the preceding claims, wherein the metal layer (111) is electrically connected to the first load terminal structure (11).The power semiconductor device (1) according to any one of the preceding claims, wherein the polysilicon and / or metal layer (111) filling the contact hole (H) is at least partially covered by a soft passivation layer (13).A power semiconductor device (1) comprising: - a semiconductor body (10) having a front side (10-1) coupled to a first load terminal structure (11), a back side (10-2) coupled to a second load terminal structure (12), and a lateral chip edge (109); - an active region (16) configured in a conductive state of the power semiconductor device (1) for conducting a load current between the first load terminal structure (11) and the second load terminal structure (12); - an edge termination region (17) separating the active region (16) from the lateral chip edge (109); a hard passivation layer (18) arranged on the front side (10-1) in at least a part of the edge termination region (17), wherein the hard passivation layer (18) comprises an oxide layer (181) with an oxide layer thickness (d2); and a metal layer (174, 111) arranged on the front side (10-1) in at least a part of the edge termination region (17) and having a lateral edge (174-1, 111-1); an insulation layer (15) arranged at least in a part of the edge termination region (17) at the front side (10-1), wherein a lateral edge (151) of the insulation layer (15) is covered by the metal layer (174, 111), wherein in a cross section along a vertical direction (Z) pointing from the front side (10-1) to the back side (10-2), wherein the cross section is perpendicular to the lateral edge (111-1, 174-1), a common lateral extension region (LX1, LX2, LX3) of the hard passivation layer (18) and the metal layer (174, 111) is at most 10 times the oxide layer thickness (d2), and wherein the common extension region (LX1, LX2, LX3) within the edge termination region (17) does not extend over a single lateral edge of the insulation layer (15).The power semiconductor device (1) according to claim 6, wherein at any such lateral edge of a metal layer (111, 174) in the edge termination region (17), the common lateral extension region (LX1, LX2, LX3) of the hard passivation layer (18) and the metal layer in a vertical cross section perpendicular to the lateral edge (111-1, 174-1) is at most 10 times the oxide layer thickness (d2).The power semiconductor device (1) according to claim 6 or 7, wherein the common lateral extension region (LX1, LX2, LX3) is at most 10 times a metal layer thickness (d6, d7) of the metal layer (111, 174) at the lateral edge (111-1, 174-1).The power semiconductor device (1) according to any one of claims 6 to 8, wherein the metal layer (174) forms at least a part of a gate runner electrode (GR).The power semiconductor device (1) according to any one of claims 6 to 8, wherein the metal layer (111) establishes an electrical connection between a drain cell (D) and the first load terminal (11).The power semiconductor device (1) according to any one of the preceding claims, wherein the hard passivation layer (18) comprises a nitride layer (182).The power semiconductor device (1) according to any one of the preceding claims, comprising a soft passivation layer (13) disposed above at least a part of the hard passivation layer (18).The power semiconductor device (1) according to any of the preceding claims, comprising an edge termination structure (171), wherein the edge termination structure (171) is arranged on the front side (10-1) and is configured to laterally terminate an electric field present in the semiconductor body (10) in a blocking state of the power semiconductor device (1), wherein the hard passivation layer (18) is arranged above at least a part of the edge termination structure (171).The power semiconductor device (1) according to claim 13, wherein the edge termination structure (171) comprises: a junction termination extension structure, a lateral doping variation structure, a field plate termination structure and / or a field ring / field plate termination structure.The power semiconductor device (1) according to any one of the preceding claims, wherein the power semiconductor device (1) is an IGBT or comprises an IGBT.A method for processing a power semiconductor device (1) comprising the steps of: - providing a semiconductor body (10) having a front side (10-1), a back side (10-2) and a lateral chip edge (109); - creating an active region (16) configured in a conductive state of the power semiconductor device (1) for conducting a load current between a first load terminal structure (11) arranged on the front side (10-1) and a second load terminal structure (12) arranged on the back side (10-2); - creating an edge termination region (17) separating the active region (16) from the lateral chip edge (109); - creating an insulation layer (15) on the front side (10-1) such that a lateral edge (151) of the insulation layer defines at least one contact hole (H); filling the contact hole (H) with a metal and / or polysilicon layer (111) so as to make contact with a doped semiconductor region (1711) of the semiconductor body (10); and creating a hard passivation layer (18) on the front side (10-1) in at least a part of the edge termination region (17) in such a way that the hard passivation layer (18) does not extend above the lateral edge (151) of the insulation layer (15), wherein the hard passivation layer (18) at least partially covers the metal and / or polysilicon layer (111).Method for processing a power semiconductor device (1), comprising the steps of: - providing a semiconductor body (10) having a front side (10-1), a back side (10-2) and a lateral chip edge (109); - generating an active region (16) configured in a conductive state of the power semiconductor device (1) for conducting a load current between a first load terminal structure (11) arranged on the front side (10-1) and a second load terminal structure (12) arranged on the back side (10-2); - generating an edge termination region (17) separating the active region (16) from the lateral chip edge (109); - creating a hard passivation layer (18) on the front side (10-1) in at least a part of the edge termination region (17), wherein the hard passivation layer (18) comprises an oxide layer (181) with an oxide layer thickness (d2); and - creating a metal layer (111, 174) on the front side (10-1) at least in a part of the edge termination region (17), wherein the metal layer (111, 174) has a lateral edge (111-1, 174-1); - creating an insulation layer (15) which is arranged at least in a part of the edge termination region (17) on the front side (10-1), wherein a lateral edge (151) of the insulation layer (15) is covered by the metal layer (174, 111), wherein in a cross section along a vertical direction (Z) pointing from the front side (10-1) to the rear side (10-2), wherein the cross section perpendicular to the lateral edge (111-1, 174-1), a common lateral extension region (LX1, LX2, LX3, LX4) of the hard passivation layer (18) and the metal layer (111, 174) is at most 10 times the oxide layer thickness (d2), and wherein the common extension region (LX1, LX2, LX3) within the edge termination region (17) does not extend over a single lateral edge of the insulation layer (15).

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