Timestamping technologies with error correction

Abstract

Computing device (100) for timestamping data packets, the computing device comprising the following: a processor (102); a memory (104); and a network interface controller (110) to perform the following: Receiving data from another component of the computing device (302); Inserting one or more alignment markers into the data (304); Identifying a trigger pattern in the data after the insertion of one or more alignment markers (310); Triggering a timestamp according to the detection of the trigger pattern (312); and Sending the data to a remote computing device (330).

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority under 35 USC § 119(e) over provisional US patent application No. 62 / 619,689, entitled “TECHNOLOGIES FOR TIME STAMPING WITH ERROR CORRECTION”, which was filed on January 19, 2018. BACKGROUND

[0002] Timestamping of packets sent or received over a network is important for several applications. Determining the time of transmission and arrival of a packet can be used to synchronize a clock between the sending and receiving computing devices, which may be necessary for time-critical applications such as certain wireless communication protocols.

[0003] A timestamp for sending or receiving a packet can have several sources of inaccuracy. For example, a packet might be encrypted, requiring decryption before a timestamp pattern can be established, or the packet might be transmitted between domains with asynchronous clocks compared to the clock used for timestamps, both of which can contribute to timestamp inaccuracies when a packet actually arrives at a device.

[0004] Document EP 3 113 502 A1 discloses flexible Ethernet systems and methods for switching, OAM, multi-service, chip-to-chip interface, time transmission and encryption. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The concepts described here are illustrated in the accompanying figures as examples and are not exhaustive. For the sake of simplicity and clarity, the elements depicted in the figures are not necessarily to scale. Where deemed appropriate, reference marks have been repeated below the figures to indicate corresponding or analogous elements. Fig. Figure 1 is a simplified block diagram of at least one embodiment of a computing device for timestamping data packets; Fig. 2 is a block diagram of at least one embodiment of an environment defined by the computing device of Fig. 1 can be set up; Fig. 3 and Fig. Figure 4 presents a simplified flowchart of at least one embodiment of a method for performing error-correcting timestamps for data received from a network interface controller of the computing device of Fig. 1 will be sent; and Fig. 5 and Fig. Figure 6 presents a simplified flowchart of at least one embodiment of a method for performing error-correcting timestamps for data received by the network interface controller of the computing device. Fig. 1 will be received. DETAILED DESCRIPTION OF THE DRAWINGS

[0006] While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are described in detail here. It should be understood, however, that the intention is not to limit the concepts of the present disclosure to the specific forms disclosed, but rather to cover all modifications, correspondences, and alternatives that are consistent with the present disclosure and the appended claims.

[0007] References in the specification to "an embodiment," "a form of embodiment," "an exemplary embodiment," etc., indicate that the described embodiment may include a specific feature, structure, or property, but this does not necessarily mean that every embodiment must include this specific feature, structure, or property. Furthermore, such expressions do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or property is described in connection with an embodiment, it is implied that it is within the knowledge of a person skilled in the art to recognize such a feature, structure, or property in connection with other embodiments, regardless of whether an explicit description is provided.Furthermore, it should be noted that items listed as "at least one of A, B and C" can mean (A); (B); (C): (A and B); (B and C); (A and C); or (A, B and C). Similarly, items listed as "at least one of A, B or C" can mean (A); (B); (C): (A and B); (B and C); (A and C); or (A, B and C).

[0008] The disclosed embodiments can, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments can also be implemented as instructions that are transported or stored on one or more volatile or non-volatile machine-readable (e.g., computer-readable) storage media that can be read and executed by one or more processors. A machine-readable storage medium can be any storage device, mechanism, or other physical structure for storing or transferring data in a form readable by a machine (e.g., volatile or non-volatile memory, a media disc, or other media device).

[0009] In the drawings, some structural or process features may be shown in specific arrangements and / or orders. However, it is understood that such specific arrangements and / or orders may not be necessary. Rather, in some embodiments, such features may be arranged in a different manner and / or sequence than those shown in the exemplary figures. Furthermore, the inclusion of a structural or process feature in a specific figure does not mean that such a feature is required in all embodiments and may be omitted or combined with other features in some embodiments.

[0010] Now on Fig. 1. Referring to this, an exemplary computing device 100 is designed to perform timestamping of data packets either sent or received by a network interface controller 110 of the computing device 100. When data is received by the network interface controller 110 from another component of the computing device 100, the network interface controller 110 performs several steps as part of processing the data before it is transmitted over the network. For example, in an exemplary embodiment, the data is received on a 32-bit bus using an elastic memory phased first-in, first-out (FIFO) encoder. The phased FIFO encoder can periodically insert alignment markers and clear other data, such as idle control characters.It should be noted that the insertion of alignment markers and / or the deletion of other data, such as idle control characters, can affect control when the data is transmitted over the network and could result in a less precise timestamp. After the phase FIFO, the data on the 32-bit bus is converted to a 64-bit bus. Then, each block of 64 bits is encoded and encrypted to 66 bits. As part of the encoding of the 64 bits to 66 bits, the Network Interface Controller 110 monitors for a trigger pattern, such as the beginning of an Ethernet packet frame delimiter, and triggers a timestamp when the frame delimiter is detected.It should be noted that, since the timestamping is performed after the alignment markers have been inserted and / or other data, such as sleep control characters, has been deleted, the timestamping will not be affected by this insertion or deletion. Subsequently, a set of four 66-bit blocks (264 bits total) is transcoded to a 257-bit block. Several 257-bit blocks are then encoded using a forward error correction algorithm, such as Reed-Solomon. The encoded blocks are then transmitted to the network, for example, over an electrical or optical cable.

[0011] The computing device 100 can be configured as any type of computing device capable of managing data packets and performing the functions described herein. For example, the computing device 100 can be configured as, but is not limited to, a server computer, an integrated computer system, a system-on-a-chip (SoC), a multiprocessor system, a processor-based system, a consumer electronics device, a smartphone, a mobile phone, a desktop computer, a tablet computer, a notebook computer, a laptop computer, a network device, a router, a switch, a networked computer, a portable computer, a handset, a notification device, a camera device, and / or any other computing device.The exemplary computing device 100 includes the processor 102, a memory 104, an input / output (I / O) subsystem 106, a system clock 108, a network interface controller 110, and data storage 112. In some embodiments, one or more of the exemplary components of the computing device 100 may be integrated into another component or otherwise form part of it. For example, in some embodiments, the memory 104, or parts thereof, may be integrated into the processor 102.

[0012] The processor 102 can be any type of processor capable of performing the functions described herein. For example, the processor 102 can be a single-core or multi-core processor, a single-socket or multi-socket processor, a digital signal processor, a graphics processor, a microcontroller, or any other processor or processing / control circuit. Likewise, the memory 104 can be any type of volatile or non-volatile memory or data storage capable of performing the functions described herein. During operation, the memory 104 can store various data and software used during the operation of the computing device 100, such as operating systems, applications, programs, libraries, and drivers.Memory 104 is communicatively coupled to processor 102 via I / O subsystem 106, which is configured as circuitry and / or components to facilitate input / output operations with processor 102, memory 104, and other components of computing device 100. For example, I / O subsystem 106 can be configured as memory controller hubs, input / output control hubs, firmware devices, communication links (i.e., point-to-point connections, bus connections, wires, cables, optical fibers, PCB traces, etc.), and / or other components and subsystems, or otherwise incorporated to facilitate input / output operations. In some embodiments, I / O subsystem 106 can form part of a system-on-a-chip (SoC) and be integrated on a single integrated circuit chip along with processor 102, memory 104, and other components of computing device 100.

[0013] The system clock 108 can be configured as any type of device, circuit, and / or collection of devices and circuits capable of generating a clock signal usable by other components of the computing device 100. For example, the system clock 108 can be configured as a circuit based on a crystal oscillator or otherwise incorporated. The clock signal can be used by various components of the computing device 100 to synchronize the timing of communications. For example, the processor 102 and the memory 104 can each be synchronized to the system clock 108. The clock signal can be any type of clock signal, such as a square wave or a sine wave. The frequency of the clock signal generated by the system clock 108 can be any suitable frequency, such as 100, 200, or 500 megahertz (MHz).

[0014] The network interface controller 110 can be configured as any type of interface capable of connecting the computing device 100 to other computing devices, for example, via a network. In some embodiments, the network interface controller 110 can be designated as a host fabric interface (HFI). The network interface controller 110 can be capable of establishing a connection using any suitable cable type, such as an electrical cable or an optical cable, and / or can be capable of establishing a connection using a radio signal, for example, through one or more antennas. The network interface controller 110 can be configured to use one or more communication technologies and their associated protocols (e.g., Ethernet, Bluetooth®, Wi-Fi®, WiMAX, Near Field Communication (NFC), etc.).The network interface controller 110 can be located separately from the processor 102 on silicon, or the network interface controller 110 can be included in a multi-chip package with the processor 102, or even on the same chip as the processor 102. The network interface controller 110 can be configured as one or more expansion cards, daughter cards, network interface cards, controller chips, chipsets, specialized components such as a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC), or other devices that can be used by the computing device 100 to establish a connection with another computing device.In some embodiments, the network interface controller 110 can be configured as part of a system-on-a-chip (SoC) containing one or more processors, or be included in a multi-chip package that also contains one or more processors. In some embodiments, the network interface controller 110 can include a local processor (not shown) and / or local memory (not shown), both of which are local to the network interface controller 110. In such embodiments, the local processor of the network interface controller 110 can be capable of performing one or more of the functions of the processor 102 described herein. Additionally or alternatively, in such embodiments, the local memory of the network interface controller 110 can be integrated into one or more components of the computing device 100 at the board level, socket level, chip level, and / or other levels.

[0015] The exemplary network interface controller 110 includes one or more network interface controller clocks (NIC clocks) 114. In the exemplary embodiment, one of the NIC clocks 114 is used to transmit a signal to another computing device. The NIC clock 114 used for transmission may be similar to the system clock 108, the description of which is not repeated for clarity. In the exemplary embodiment, another of the NIC clocks 114 is used to receive a signal from another computing device. The NIC clock 114 used for receiving may operate differently from the system clock 108, for example, by recovering a clock signal from the signal received by the network interface controller 110.It should be noted that the NIC clock 114 may operate at a different frequency than the system clock 108, and that the NIC clock 114 and the system clock 108 may be free-running (i.e., operating independently without a fixed timing relationship between them). It should also be noted that different components of the network interface controller 110 may operate with different clocks, including the NIC clock 114 and the system clock 108.

[0016] The data storage device 112 can be configured as any type of device or devices designed for short-term or long-term data storage. For example, the data storage device 112 can include one or more storage devices and circuits, memory cards, hard disk drives, solid-state drives, or other data storage devices.

[0017] In some embodiments, the computing device 100 may include other or additional components, such as those commonly found in a computing device. For example, the computing device 100 may also include a display 116 and / or peripheral devices 118. The peripheral devices 118 may include a keyboard, a mouse, etc. The display 116 may be any type of display on which information can be shown to a user of the computing device 100, such as a touchscreen display, a liquid crystal display (LCD), a light-emitting diode (LED) display, a cathode ray tube (CRT) display, a plasma display, an image projector (e.g., 2D or 3D), a laser projector, a heads-up display, and / or other display technology.

[0018] Now on Fig. 2 With reference to this, in an exemplary embodiment, the computing device 100 establishes an environment 200 during operation. The exemplary environment 200 includes a network interface manager 202. The various modules of the environment 200 can be configured as hardware, software, firmware, or a combination thereof. For example, the various modules, logic, and other components of the environment 200 can form part of the processor 102 or other hardware components of the computing device 100, such as the network interface controller 110, or be otherwise configured as such. Therefore, in some embodiments, one or more of the modules of the environment 200 can be configured as a circuit or collection of electrical devices (e.g., a network interface manager circuit 202, etc.). It should be noted that in such embodiments, one or more of the circuits (e.g.,The network interface manager circuit 202, etc., may form part of one or more of the processor 102, the memory 104, the I / O subsystem 106, the network interface controller 110, the data storage 112, and / or other components of the computing device 100. Additionally, in some embodiments, one or more of the exemplary modules may form part of another module, and / or one or more of the exemplary modules may be independent of each other. Furthermore, in some embodiments, one or more of the environment 200 modules may be configured as virtualized hardware components or an emulated architecture that can be set up and managed by the processor 102 or other components of the computing device 100.It should be noted that some of the functionality of one or more modules of Environment 200 may require a hardware implementation, so embodiments of the modules that implement such functionality will be at least partially designed as hardware.

[0019] The network interface manager 202, which can be implemented as hardware, firmware, software, virtualized hardware, emulated architecture, and / or a combination thereof, as discussed above, is designed to control the network interface controller 110, including the interaction of the network interface controller 110 with the physical medium to which it is connected and the processing of incoming and outgoing signals received and sent by the network interface controller 110. The network interface manager 202 includes a physical medium attachment (PMA) sublayer 204, one or more gearboxes 206, a physical coding sublayer (PCS) 208, a forward error correction (FEC) encoder / decoder 210, and a data packet timestamp 212.

[0020] The PMA sublayer 204 is designed to sample an incoming signal from the physical medium to which it is connected and provide a signal that can be used by other components of the Network Interface Controller 110, such as a serial electrical signal at standardized voltage levels. The PMA sublayer 204 can operate at any suitable rate or bandwidth, such as 10 gigabits per second (Gbps), 25 Gbps, 40 Gbps, 100 Gbps, or higher or lower than these rates. The PMA sublayer 204 is also designed to send outgoing signals received by other components of the Network Interface Controller 110 back to the physical medium to which it is connected.In the exemplary embodiment, the PMA sublayer 204 synchronizes a NIC clock 114 with the incoming signal, which is used by the PMA sublayer 204 and other components of the network interface controller 110 to process the incoming signal. The exemplary PMA sublayer 204 also uses a NIC clock 114, which is free-running relative to other clocks, to transmit a signal over the physical medium and to process the signal before it is transmitted over the physical medium.

[0021] The exemplary physical medium attachment (PMA) includes a serializer / deserializer (SerDes) 214. The SerDes 214 is designed to convert a serial signal to a parallel signal and a parallel signal to a serial signal. In the exemplary embodiment, the physical medium is serially sampled or driven, and the SerDes 214 deserializes incoming signals from the physical medium to a bus for use by the PMA sublayer 204, and serializes signals from the PMA sublayer 204 for transmission on the physical medium. The SerDes 214 can transfer between a serial interface and a parallel interface of any suitable bus size, such as 16 or 40 bits.In some embodiments, the signal from the physical medium may not be transmitted as a single serial signal, but may be transmitted as a parallel signal or as several separate serial signals.

[0022] The gearbox 206 is designed to transfer data between a first-width parallel bus and a second-width parallel bus. For example, the gearbox 206 can be used to transfer data between a 257-bit parallel bus at the FEC encoder / decoder 210 and a 40-bit parallel bus at the PMA sublayer 204.

[0023] The physical coding sublayer 208 is designed to perform coding on the incoming and outgoing signals. In the exemplary embodiment, the physical coding sublayer 208 performs 64b / 66b coding to decode 66 bits to 64 bits or encode 64 bits to 66 bits, using the 64b / 66b coding algorithm described in IEEE Std 802.3-2015, approved on September 3, 2015, by the IEEE-SA Standards Board. To accomplish this, in the exemplary embodiment, the physical coding sublayer 208 takes 64 bits of outgoing data, adds 2 bits as a synchronization header, and then encodes the 64 bits. For incoming data, the exemplary physical coding sublayer 208 takes 66 bits of data, removes the first two bits of the synchronization head, and decodes the remaining two bits.The two bits in the exemplary synchronization head are only valid if they are "01" or "10", and they perform two functions in the exemplary embodiment. First, they act as an indicator of the beginning of 66-bit blocks, because every 66 bits should always have a transition from zero to one or from one to zero. Second, they indicate whether the bits in the following 64-bit block are control bits or data bits. In other embodiments, the physical coding sublayer 208 can perform additional or alternative encoding / decoding, such as 4b / 5b encoding / decoding or 8b / 10b encoding / decoding. It should be noted that in the exemplary embodiment, the incoming signal may not be processed until the physical coding sublayer 208 has decoded the signal.For example, the trigger pattern that is recognized as the trigger for timestamps may only be recognizable after the decoding is complete.

[0024] The exemplary physical coding sublayer 208 may delete data, such as idle control characters, from the outgoing data. In the exemplary embodiment, idle control characters can be deleted from an interpacket gap period. The physical coding sublayer 208 may periodically insert one or more alignment markers, for example, after every 16,383 64-bit blocks or after every 81,916 64-bit blocks. In some embodiments, alignment markers may be inserted into each of several data tracks. For incoming data, the exemplary physical coding sublayer 208 may use the alignment markers to synchronize the data between different data tracks when there are multiple data tracks. Additionally or alternatively, in some embodiments, the alignment markers may be used as codeword markers.As used here, an alignment marker refers to a marker that can be used to align multiple data tracks or a marker that can be used to identify codewords. The exemplary physical coding sublayer 208 removes the alignment markers (regardless of whether one or more tracks are present) and inserts idle control characters into the interpacket gap period. It is understood that the insertion of alignment markers and / or the deletion of other data, such as idle control characters, can affect control when the data is transmitted over the network and could result in a less precise timestamp if no correction is made. In some embodiments, the physical coding sublayer 208 can receive data using an elastic storage / phase first-in-first-out buffer.The use of such a buffer can allow the physical coding sublayer 208 to insert alignment markers and delete data, such as sleep control characters, in a manner that is less disruptive to the data flow through the components of the NIC 110.

[0025] The FEC encoder / decoder 210 is designed to perform forward error correction by encoding an outgoing bitstream and decoding an incoming bitstream. As part of the encoding process, the FEC encoder / decoder 210 can transcode four 66-bit blocks of outgoing data into a single 257-bit block. In the exemplary embodiment, the FEC encoder / decoder 210 can remove alignment markers, reassign them, and insert them into the bitstream as codeword markers without encoding. The reassigned alignment markers may have shifted or modified bits compared to the alignment markers before the reassignment. In the exemplary embodiment, four 66-bit alignment markers are reassigned to 256 bits each, plus a 1-bit pad, for a total of 257 bits.In the exemplary embodiment, the alignment markers can be used to identify the starting position of codewords in the FEC algorithm, which can be used to decode the encoded data. For this reason, the alignment markers also function as codeword markers. It should be noted that, as part of the decoding process, the FEC encoder / decoder 210 can reinsert the alignment markers at the same position from which they were removed, which would not cause any variable delay in timestamping based on the detection of a trigger pattern. In the exemplary embodiment, the FEC encoder / decoder uses a 10-bit Reed-Solomon error correction algorithm by encoding 20 257-bit blocks (i.e., 5140 bits) with 140 parity bits. The resulting 5280 bits constitute a codeword of the FEC algorithm.It should be noted that the newly assigned alignment markers can also serve as codeword markers, indicating the boundaries between codewords. In some implementations, different approaches to FEC encoding can be applied, for example, by using different encoding algorithms, different numbers of blocks, or different numbers of parity bits.

[0026] The FEC encoder / decoder 210 is designed to decode incoming data in a similar way to how it encodes outgoing data. The FEC encoder / decoder 210 can capture alignment markers (which also act as codeword markers) to mark the boundaries between codewords. Each codeword is decoded, and then the alignment markers are removed. The 257-bit blocks are transcoded to 66-bit blocks in a manner complementary to the process described above. Likewise, the alignment markers are remapped to 66-bit blocks in a manner complementary to the process described above. The alignment markers are then reinserted into the data at the same position from which they were removed.

[0027] The trigger pattern timestamp 212 is designed to trigger a timestamp when a trigger pattern is sent or received. The trigger pattern timestamp 212 includes a trigger pattern detector 216 and a trigger pattern reporter 218. The trigger pattern detector 216 is designed to detect specific trigger patterns, such as the beginning of a data packet or frame in the incoming or outgoing signal. Upon detection of a trigger pattern by the trigger pattern detector 216, the trigger pattern reporter 218 is designed to report the presence of a specific trigger pattern in the incoming or outgoing data by sending a corresponding trigger signal to the trigger pattern timestamp 212.The trigger pattern reporter 218 is designed to send the trigger at a fixed time relative to the detection of the relevant trigger pattern, so that no variable latency is introduced by the trigger pattern detector 216 or the trigger pattern reporter 218. In the exemplary embodiment, the trigger pattern for which the trigger pattern detector 216 and the trigger pattern reporter 218 are configured to trigger is a frame beginning delimiter in an Ethernet frame. In other embodiments, the trigger pattern detector 216 and / or the trigger pattern reporter 218 can be configured to trigger on different trigger patterns, such as the beginning of a packet or frame from various other protocols, the end of a packet or frame from various protocols, etc.In the exemplary embodiment, the trigger pattern timestamp 212 checks for the presence of a trigger pattern in outgoing data, including the alignment markers that will be present in the outgoing data, for example, immediately before the 64b / 66b encoding is performed, and checks for the presence of a trigger pattern in incoming data, including the received alignment markers, for example, immediately after the 64b / 66b decoding is performed. In the exemplary embodiment, the alignment markers can be removed, remapped, and reinserted before the presence of a trigger pattern is checked, which is acceptable because the remapping does not introduce variable latency into the position of the trigger pattern.

[0028] Now on Fig. 3 With reference to this, the computing device 100 can execute a procedure 300 for performing error-correcting timestamps during use. In block 302, the network interface controller (NIC) 110 receives data from another component of the computing device 100, for example, from the processor 102, the memory 104, the I / O subsystem 106, etc.

[0029] In block 304, the NIC 110 inserts alignment markers into the data to be transmitted. In the exemplary embodiment, the alignment markers can be inserted at regular intervals, for example, after every 16,383 64-bit blocks. In some multi-track embodiments, the NIC 110 can insert alignment markers into each of the multiple tracks in block 306. The NIC 110 can also delete other data, such as idle control characters, from an interpacket gap period in block 308. It should be noted that the idle control characters can be deleted to compensate for the insertion of the alignment markers, but the alignment markers do not necessarily appear in the same position as the idle control characters. In some embodiments, the NIC 110 can insert alignment markers and delete data, such as sleep control characters, because data is routed through an elastic storage / phase-first-in-first-out buffer.The use of such a buffer can allow the NIC 110 to insert alignment markers and delete data, such as sleep control characters, in a manner that is less disruptive to the data flow through the components of the NIC 110.

[0030] In block 310, the NIC 110 checks for the presence of a trigger pattern in the data. In the exemplary embodiment, the trigger pattern is a frame beginning delimiter in an Ethernet frame. In other embodiments, the trigger pattern can be different, such as the beginning of a packet or frame from various other protocols, the end of a packet or frame from various protocols, and so on. If the NIC 110 detects a trigger pattern, method 300 proceeds to block 312, in which the NIC 110 triggers a timestamp based on the detection of the trigger pattern. The NIC 110 can record the timestamp corresponding to the detected trigger pattern and can use the timestamp to perform various functions, such as time synchronization with a remote computing device.

[0031] Referring back to block 310, if the NIC 110 does not detect a trigger pattern in the data, procedure 300 jumps to block 314, where the NIC 110 encodes the data. In the exemplary embodiment, the NIC 110 encodes the data by encoding 64 bits to 66 bits using the 64b / 66b encoding algorithm described in IEEE Std 802.3-2015, approved on September 3, 2015, by the IEEE-SA Standards Board. To accomplish this, in the exemplary embodiment, the NIC 110 adds two bits as a synchronization header before the 64-bit block in block 314. The NIC 110 then encodes the 64-bit block and prepends the two synchronization bits to the encoded 64 bits in block 318.It should be noted that in the exemplary embodiment, the NIC 110 does not encrypt the alignment markers, although the NIC 110 can still prepend the two synchronization head bits to create a 66-bit alignment marker from a 64-bit alignment marker. The two bits in the exemplary synchronization head are only valid if they are "01" or "10". The synchronization head bits indicate whether the bits in the following 64-bit block are control bits or data bits. In other embodiments, the physical encoding sublayer 208 can perform additional or alternative encoding / decoding, such as 4b / 5b encoding / decoding or 8b / 10b encoding / decoding. It should be noted that in the exemplary embodiment, the outgoing data may not be processable after the data has been encrypted.For example, in the exemplary embodiment, the trigger pattern might not be detected if it is encrypted. However, certain other operations can take place before checking for the presence of the trigger pattern, such as adding the 2-bit synchronization header.

[0032] Procedure 300 runs with block 320 in Fig. 4 continues, in which the NIC 110 removes the alignment markers in block 320. The NIC 110 then performs a remapping of the alignment markers in block 322. The remapplied alignment markers may have shifted or changed bits compared to the alignment markers before the remapping. In the exemplary embodiment, 4 alignment markers of 66 bits each are remapplied to 256 bits plus a 1-bit pad for a total of 257 bits.

[0033] The NIC 110 then transcodes the 66-bit blocks of synchronization heads and data by transcoding four 66-bit blocks into a 257-bit block in block 324. The NIC 110 then reinserts the newly allocated alignment markers into the data in block 326. In this exemplary embodiment, the alignment markers can be used to identify the starting position of codewords in the FEC algorithm, which can be used to decode the encoded data. For this reason, the alignment markers also function as codeword markers. It should be noted that the NIC 110 can reinsert the alignment markers at the same position from which they were removed, which would not cause any variable timestamping delay based on the detection of a trigger pattern.

[0034] In block 328, the NIC 110 performs forward error correction (FEC) encoding on the data. In this exemplary embodiment, the FEC encoder / decoder uses a 10-bit Reed-Solomon error correction algorithm by encoding 20 257-bit blocks (i.e., 5140 bits) with 140 parity bits. The resulting 5280 bits form a codeword of the FEC algorithm. In some embodiments, different approaches to FEC encoding can be used, for example, by employing different encoding algorithms, different numbers of blocks, or different numbers of parity bits.

[0035] In block 330, the NIC 110 transmits the encoded data over a network. In some embodiments, the NIC 110 may transmit the encoded data directly to a destination computing device via a physical medium, or the data may otherwise not be transmitted to a network of computing devices.

[0036] Now on Fig. With reference to Section 5, the computing device 100 can, during operation, execute a procedure 500 for performing error-correcting timestamping. Procedure 500 is used to timestamp data arriving at the NIC 110 from a network or another computing device. Procedure 500 is complementary to procedure 300, which is a procedure used to timestamp data originating from the NIC 110 to a network or another computing device. Since many of the details are identical between the two procedures, some details are omitted in the description of procedure 500 for the sake of clarity.

[0037] In block 502, the NIC 110 received data from a network. In some embodiments, the NIC 110 can receive the data directly from a source computing device via a physical medium, or the data may otherwise not be received from a network of computing devices.

[0038] In block 504, the NIC 110 performs forward error correction decoding. As part of performing error correction decoding, the NIC 110 can detect alignment markers (which can function as codeword markers) to determine the beginning of the codewords to be decoded. The forward error correction decoding can be complementary to the coding performed in block 328 of procedure 300.

[0039] In block 506, the NIC 110 removes the alignment markers from the data. In block 508, the NIC 110 remaps the alignment markers. The remapped alignment markers may have shifted or changed bits compared to the alignment markers before the remap. In the exemplary embodiment, four alignment markers in a 257-bit block are remapped to four 66-bit alignment markers.

[0040] In block 510, the NIC 110 transcodes the decoded data blocks. In the exemplary embodiment, the NIC 110 transcodes a 257-bit block into four 66-bit blocks. In block 512, the newly assigned alignment marker is reinserted into the data. It should be noted that the NIC 110 can reinsert the alignment markers at the same position from which they were removed, which would not cause any variable delay in timestamping based on the detection of a trigger pattern.

[0041] Procedure 500 is running with block 514 in Fig. 6 continues, in which the NIC 110 performs a further stage of decoding. In the exemplary embodiment, the NIC 110 performs 66b / 64b decoding. The 66b / 64b decoding can be complementary to the 66b / 64b encoding performed in block 314 of method 300. The NIC 110 removes a synchronization head from each 66-bit block in block 516. In block 518, the NIC 110 decodes each 64-bit block except for the 64-bit blocks corresponding to the alignment marks.

[0042] In block 520, the NIC 110 checks for the presence of a trigger pattern in the data. In the exemplary embodiment, the trigger pattern is a frame beginning delimiter in an Ethernet frame. In other embodiments, the trigger pattern can be different, such as the beginning of a packet or frame from various other protocols, the end of a packet or frame from various protocols, and so on. If the NIC 110 detects a trigger pattern, method 500 proceeds to block 522, in which the NIC 110 triggers a timestamp based on the detection of the trigger pattern. The NIC 110 can record the timestamp corresponding to the detected trigger pattern and can use the timestamp to perform various functions, such as time synchronization with a remote computing device.

[0043] Referring back to block 520, if the NIC 110 does not detect a trigger pattern in the data, method 500 jumps to block 524, where the NIC 110 removes the alignment markers from the data. In some multi-track embodiments, the NIC 110 can remove alignment markers in each of the multiple tracks in block 526. The NIC 110 can also insert other data, such as idle control characters, into an interpacket gap period in block 528. It should be noted that the idle control characters can be inserted to compensate for the deletion of the alignment markers, but the alignment markers do not necessarily appear in the same location as the idle control characters. In some embodiments, the NIC 110 can delete the alignment markers and insert other data, such as idle control characters, because data is routed through an elastic storage / phase-first-in-first-out buffer.The use of such a buffer allows the NIC 110 to clear alignment markers and insert other data, such as sleep control characters, in a manner that is less disruptive to the data flow through the components of the NIC 110. In block 520, the NIC 110 routes the data to another component of the computing device 100, for example, from the processor 102, the memory 104, the I / O subsystem 106, etc.

[0044] It should be noted that in some embodiments, the computing device can perform accurate timestamping while also applying error correction in a different manner. For example, in some embodiments, the physical coding sublayer 208 may not insert alignment markers or delete idle characters or other data to compensate for the alignment markers. Instead, in such embodiments, the FEC encoder / decoder 210 may insert alignment (or codeword) markers into outgoing data and delete idle characters and / or other data to compensate for the insertion of the alignment markers. To accomplish this, the FEC encoder / decoder 210 may decode the outgoing data using 66b / 64b decoding to detect idle control characters. After this decoding, the FEC encoder / decoder 210 can insert the alignment marks.After the insertion of the alignment marks and before the re-encoding of the outgoing data with a 66b / 64b encoding, the FEC encoder / decoder 210 can determine whether the outgoing data contains a trigger pattern, such as a frame beginning delimiter, in a manner similar to the physical encoding sublayer 208 described above. The FEC encoder / decoder 210 can then trigger a timestamp based on the detection of the trigger function. It should be noted that, in such embodiments, the detection of the trigger function in the FEC encoder / decoder 210 after the insertion of the alignment marks offers the same advantages of avoiding the variable latency of the alignment mark insertion as described above. Fig. The embodiments described in sections 3-6 are included. For outgoing data, the FEC encoder / decoder 210 can perform complementary actions to those described above in a similar manner to those described in the Fig. 5 and Fig. The 6 actions described are complementary to those described in the Fig. 3 and Fig. The 4 described actions are. EXAMPLES

[0045] The following are illustrative examples of the devices, systems, and methods disclosed herein. An embodiment of the devices, systems, and methods may include any one or more, and any combination of, the examples described below.

[0046] Example 1 includes a computing device for timestamping data packets, wherein the computing device comprises a processor, a memory, and a network interface controller to receive data from another component of the computing device, insert one or more alignment markers into the data, detect a trigger pattern in the data after the insertion of the one or more alignment markers, trigger a timestamp corresponding to the detection of the trigger pattern, and send the data to a remote computing device.

[0047] Example 2 includes the subject of Example 1, wherein the network interface controller further has the task of removing the one or more alignment markers from the data, reassigning the one or more alignment markers, encoding the data using a forward error correction algorithm, and inserting the one or more alignment markers into the data as codeword markers.

[0048] Example 3 includes the subject of one of Examples 1 and 2, where the trigger pattern is a frame beginning limiter.

[0049] Example 4 includes the subject of one of Examples 1-3, wherein the network interface controller further has the task of adding synchronization heads to each of the plurality of 64-bit blocks and encrypting each of the plurality of 64-bit blocks, wherein the detection of the trigger pattern in the data includes the detection of the trigger pattern in the plurality of 64-bit blocks after the addition of the synchronization heads and before the encryption of the plurality of 64-bit blocks.

[0050] Example 5 includes the subject of one of Examples 1-4, wherein the data comprises a plurality of 64-bit blocks, and wherein the network interface controller is further tasked with encrypting each of the plurality of 64-bit blocks after the insertion of the alignment markers, without encrypting the alignment markers themselves.

[0051] Example 6 includes the subject of one of Examples 1-5, wherein the network interface controller further has the task of removing part of a packet gap from the data to compensate for the insertion of the alignment markers.

[0052] Example 7 includes the subject matter of one of Examples 1-6, wherein the network interface controller further has the task of receiving additional data from the remote computing device, detecting the trigger pattern in the additional data, triggering a timestamp according to the detection of the trigger pattern in the additional data, and removing one or more alignment markers in the additional data after the detection of the trigger pattern in the additional data.

[0053] Example 8 includes the subject matter of any of Examples 1-7, wherein sending the data to the remote computing device includes sending the data to the remote computing device at a rate of at least 25 gigabits per second.

[0054] Example 9 includes a method for timestamping data packets by a network interface controller of a computing device, wherein the method includes receiving, by the network interface controller, data from another component of the computing device, inserting, by the network interface controller, one or more alignment markers into the data, detecting, by the network interface controller, a trigger pattern in the data after the insertion of the one or more alignment markers, triggering, by the network interface controller, a timestamp according to the detection of the trigger pattern, and sending, by the network interface controller, data to a remote computing device.

[0055] Example 10 includes the subject of Example 9 and furthermore removal, by the network interface controller, of one or more alignment markers from the data; reassignment, by the network interface controller, of one or more alignment markers; encoding, by the network interface controller, of data using a forward error correction algorithm; and insertion, by the network interface controller, of one or more alignment markers as codeword markers into the data.

[0056] Example 11 includes the subject of one of Examples 9 and 10, where the trigger pattern is a frame beginning limiter.

[0057] Example 12 includes the subject of one of Examples 9-11 and further adding, by the network interface controller, synchronization heads to each of the plurality of 64-bit blocks, and encrypting, by the network interface controller, each of the plurality of 64-bit blocks, wherein the detection of the trigger pattern in the data includes the detection of the trigger pattern in the plurality of 64-bit blocks after the addition of the synchronization heads and before the encryption of the plurality of 64-bit blocks.

[0058] Example 13 includes the subject of one of Examples 9-12, wherein the data comprises a plurality of 64-bit blocks, and further includes the encryption, by the network interface controller, of each of the plurality of 64-bit blocks after the insertion of the alignment markers, without encrypting the alignment markers.

[0059] Example 14 includes the subject of one of Examples 9-13 and further includes the removal, by the network interface controller, of part of a packet space from the data to compensate for the insertion of the alignment markers.

[0060] Example 15 includes the subject matter of any of Examples 9-14 and further includes receiving, by the network interface controller, additional data from the remote computing device, detecting, by the network interface controller, the triggering pattern in the additional data, triggering, by the network interface controller, a timestamp corresponding to the detection of the triggering pattern in the additional data, and removing, by the network interface controller, one or more alignment markers in the additional data after the detection of the triggering pattern in the additional data.

[0061] Example 16 includes one or more machine-readable media containing a variety of stored instructions which, when executed, cause a computing device to receive data from another component of the computing device, insert one or more alignment markers into the data, detect a trigger pattern in the data after the insertion of the one or more alignment markers, trigger a timestamp according to the detection of the trigger pattern, and send the data to a remote computing device.

[0062] Example 17 includes the subject matter of Example 16, wherein the plurality of instructions further causes the computing device to remove the one or more alignment markers from the data, to reassign the one or more alignment markers, to encode the data using a forward error correction algorithm, and to insert the one or more alignment markers into the data as codeword markers.

[0063] Example 18 includes the subject of one of Examples 16 and 17, where the trigger pattern is a frame beginning limiter.

[0064] Example 19 includes the subject matter of one of Examples 16-18, wherein the plurality of instructions further causes the computing device to add synchronization heads to each of the plurality of 64-bit blocks and to encrypt each of the plurality of 64-bit blocks, wherein the detection of the trigger pattern in the data includes the detection of the trigger pattern in the plurality of 64-bit blocks after the addition of the synchronization heads and before the encryption of the plurality of 64-bit blocks.

[0065] Example 20 includes the subject of one of Examples 16-19, wherein the data comprises a plurality of 64-bit blocks, wherein the plurality of instructions further causes the computing device to encrypt each of the plurality of 64-bit blocks after the insertion of the alignment markers, without encrypting the alignment markers.

[0066] Example 21 includes the subject of one of Examples 16-20, wherein the plurality of instructions further causes the computing device to remove part of a packet space from the data to compensate for the insertion of the alignment marks.

[0067] Example 22 includes the subject matter of one of Examples 16-21, wherein the plurality of instructions further causes the computing device to receive additional data from the remote computing device, to detect the trigger pattern in the additional data, to trigger a timestamp in accordance with the detection of the trigger pattern in the additional data, and to remove one or more alignment markers in the additional data after the detection of the trigger pattern in the additional data.

[0068] Example 23 includes a computing device for timestamping data packets, wherein the computing device comprises circuits for receiving, by the network interface controller, data from another component of the computing device; means for inserting, by the network interface controller, one or more alignment markers into the data; means for detecting, by the network interface controller, a trigger pattern in the data after the insertion of the one or more alignment markers; means for triggering, by the network interface controller, a timestamp according to the detection of the trigger pattern; and circuits for sending, by the network interface controller, data to a remote computing device.

[0069] Example 24 includes the subject matter of Example 23, and further includes means of removal, by the network interface controller, of one or more alignment markers from the data; means of reassignment, by the network interface controller, of one or more alignment markers; means of encoding, by the network interface controller, of data using a forward error correction algorithm; and means of insertion, by the network interface controller, of one or more alignment markers as codeword markers into the data.

[0070] Example 25 includes the subject matter of one of Examples 23 and 24, and further includes means for receiving, by the network interface controller, additional data from the remote computing device, means for detecting, by the network interface controller, the triggering pattern in the additional data, means for triggering, by the network interface controller, a timestamp corresponding to the detection of the triggering pattern in the additional data, and means for removing, by the network interface controller, one or more alignment markers in the additional data after the detection of the triggering pattern in the additional data.

Claims

[1] Computing device (100) for timestamping data packets, the computing device comprising: a processor (102); a memory (104); and a network interface controller (110) to perform the following: Receiving data from another component of the computing device (302); Inserting one or more alignment markers into the data (304); Identifying a trigger pattern in the data after the insertion of one or more alignment markers (310); Triggering a timestamp according to the detection of the trigger pattern (312); and Sending the data to a remote computing device (330). [2] Computing device (100) according to claim 1, wherein the network interface controller further performs the following functions: Removing one or more alignment marks from the data (320); Reordering one or more alignment markers (322); Encoding the data using a forward error correction algorithm (328); and Inserting one or more alignment markers as codeword markers into the data (326). [3] Computing device (100) according to claim 1, wherein the trigger pattern is a frame start limiter. [4] Computing device (100) according to claim 1, wherein the data comprise a plurality of 64-bit blocks, and the network interface controller further performs the following functions: Adding synchronization heads to each of the multitude of 64-bit blocks (314); and Encrypting each of the multitude of 64-bit blocks (318), where the detection of the trigger pattern in the data includes the detection of the trigger pattern in the multitude of 64-bit blocks after the addition of the synchronization heads and before the encryption of the multitude of 64-bit blocks. [5] Computing device (100) according to claim 1, wherein the data comprise a plurality of 64-bit blocks, wherein the network interface controller further has the task of encrypting each of the plurality of 64-bit blocks after the insertion of the alignment marks, without encrypting the alignment marks (318). [6] Computing device (100) according to claim 1, wherein the network interface controller further has the task of removing part of a packet gap from the data in order to compensate for the insertion of the alignment marks. [7] Computing device (100) according to claim 1, wherein the network interface controller further performs the following functions: Receiving additional data from the remote computing device (502); Identifying the trigger pattern in the additional data (520); Triggering a timestamp according to the detection of the trigger pattern in the additional data (522); and Removal of one or more alignment markers in the additional data after detection of the trigger pattern in the additional data, (524). [8] Computing device (100) according to claim 1, wherein sending the data to the remote computing device comprises sending the data to the remote computing device at a rate of at least 25 gigabits per second. [9] Method (300) for timestamping data packets by a network interface controller (110) of a computing device (100), the method comprising: Receiving, through the network interface controller, data from another component of the computing device (302); Insert, by the network interface controller, one or more alignment markers into the data (304); Detect, by the network interface controller, a trigger pattern in the data after the insertion of one or more alignment markers (310); Triggering, by the network interface controller, a timestamp according to the detection of the trigger pattern (312); and Sending, through the network interface controller, data to a remote computing device (330). [10] Method (300) according to claim 9, further comprising: Remove, by the network interface controller, one or more alignment marks from the data, (320); To reassign, by the network interface controller, which has one or more alignment markers, (322); Encoding, by the network interface controller, which processes data using a forward error correction algorithm, (328); and Insertion, by the network interface controller, which inserts one or more alignment markers as codeword markers into the data, (326). [11] Method (300) according to claim 9, wherein the trigger pattern is a frame beginning limiter. [12] Method (300) according to claim 9, wherein the data comprise a plurality of 64-bit blocks, and the method further comprises: Adding, through the network interface controller, synchronization heads to each of the multitude of 64-bit blocks, (314); and Encrypting, by the network interface controller, each of the multitude of 64-bit blocks, (318), where the detection of the trigger pattern in the data includes the detection of the trigger pattern in the multitude of 64-bit blocks after the addition of the synchronization heads and before the encryption of the multitude of 64-bit blocks. [13] Method (300) according to claim 9, wherein the data comprise a plurality of 64-bit blocks and the method further comprises encrypting, by the network interface controller, each of the plurality of 64-bit blocks after the insertion of the alignment marks, without encrypting the alignment marks, (318). [14] Method (300) according to claim 9, further comprising removing, by the network interface controller, a portion of a packet space from the data to compensate for the insertion of the alignment marks. [15] Method (300) according to claim 9, further comprising: Received, by the network interface controller, additional data from the remote computing device, (502); Detect, by the network interface controller, the triggering pattern in the additional data, (520); Triggering, by the network interface controller, a timestamp corresponding to the detection of the trigger pattern in the additional data, (522); and Remove, by the network interface controller, one or more alignment markers in the additional data after detection of the trigger pattern in the additional data, (524). [16] Method (300) according to claim 9, wherein sending the data to the remote computing device comprises sending the data to the remote computing device at a rate of at least 25 gigabits per second. [17] One or more machine-readable media (104, 112) containing a plurality of instructions stored thereon which, when executed, cause a computing device (100) to carry out the method according to any one of claims 9-16. [18] Computing device (100) for timestamping data packets, wherein the computing device comprises means for carrying out the method (300) according to any one of claims 9-16.

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