Structures from the middle section of the production line and manufacturing processes for them

Abstract

A structure with: a plurality of gate structures (150) with source and drain regions (115); Contacts (200) connected to the source and drain regions (115), wherein the contacts (200) have regions along an X-axis direction and a Y-axis direction that are covered by a dielectric cover (130), and the contacts (200) further have regions that are not covered by the dielectric cover (130) such that a step is formed along the Y-axis direction; Contacts (205) connected to the gate structures (150) and offset from the contacts (200) connected to the source and drain regions (115), at least along the X-axis direction, wherein the areas of the contacts (200) connected to the source and drain regions (115) covered by the dielectric cover (130) have a reduced height compared to the contacts (205) connected to the gate structures (150); and Interconnection structures (220, 225) which are in electrical contact with the contacts (205) connected to the gate structures (150) and the contacts (200) connected to the source and drain regions (115), wherein the contacts (205) connected to the gate structures (150) and the covered and uncovered areas of the contacts (200) connected to the source and drain regions (115) are constructed from a coating (120) and a similar filling material (195).

Description

Field of the InventionThe present disclosure relates generally to semiconductor structures, and more particularly to structures and fabrication methods used in the middle portion of the manufacturing line.BackgroundWith the continuous scaling of semiconductor processes, for example, size reduction, the desired distances between structural elements (i.e., the sum of line distance and line width) also become smaller. To do so, the smaller technology nodes will increase difficulty in fabricating metallization structures at the end of the manufacturing line (BEOL) and midway in the middle of the manufacturing line (MOL), such as interconnects, due to the scaling of critical dimensions (CD) and process characteristics, as well as due to materials used to fabricate such structures.For example, in the fabrication of interconnection structures for source and drain contacts, it is necessary to remove dielectric material disposed adjacent to the gate structures. The removal of the dielectric material is accomplished by an etching process that also tends to attack the spacer material of the gate structure. That is, the low dielectric constant dielectric material used for the spacer or sidewalls of the gate structure may be eroded in the subsequent etching processes used to form the openings for the source and drain contacts. This loss of material exposes the metal material of the gate structure, resulting in a short circuit between the metal material of the gate structure and the metal material used to make the contact itself.US 5 924 010 A describes a conventional process technique according to which a metal silicide and a self-aligning barrier are simultaneously produced for contacting drain and source regions and gate electrode structures.U.S. Pat. No. 6,429,493 B1 describes a process in which contacts to drain and source are produced, wherein the gate electrode structures are covered by an interlayer dielectric material and a cover material.DE 102 58 761 A1 describes a process technique for forming contact openings, wherein an opening is formed after depositing an interlayer dielectric material between two adjacent gate lines such that corresponding regions of the adjacent gate electrode structures and the corresponding drain / source region lying between these adjacent gate lines are simultaneously contacted.US 2016 / 0 359 009 A1 describes a structure in which metal silicide is applied to drain and source regions, whereas the actual contact connections are provided in such a way that they are connected only to a part of the metal silicide.In current structures, there must be a minimum distance between the gate structures to avoid short circuit between the gate contacts and the source and drain contacts. As device size reduction continues, it becomes increasingly difficult to meet the minimum pitch and other design rules in these conventional structures.OverviewIn one aspect of the disclosure, a solution to the aforementioned problems is provided by the features of claim 1.In a further aspect of the disclosure, a solution to the aforementioned problems is provided by the features of claim 10.In a further aspect of the disclosure, a solution to the aforementioned problems is provided by a method having the features of claim 13.Further advantageous embodiments of the aforementioned aspects are described in the dependent claims.Brief Description of the DrawingsThe present disclosure is set forth in the following detailed description with reference to the plurality of drawings given in terms of non-limiting examples of illustrative embodiments of the present disclosure. FIGS. 1A-1C show, among other features, gate structures, and corresponding fabrication processes, in accordance with aspects of the present disclosure. FIGS. 2A and 2B show, among other features, shallow trench isolation regions and corresponding fabrication processes, in accordance with aspects of the present disclosure. FIGS. 3A-3G illustrate, among other features, shallow trench isolation structures and corresponding fabrication processes, in accordance with aspects of the present disclosure. FIGS. 4A-4C show, among other features, amorphous silicon exposed structures and corresponding fabrication processes, in accordance with aspects of the present disclosure. FIGS. 5A-5C show structures with exposed source and drain regions and corresponding fabrication processes, among other features, in accordance with aspects of the present disclosure. FIGS. 6A-6C show, among other features, place holder fill materials, and corresponding fabrication processes, in accordance with aspects of the present disclosure. FIGS. 7A-7D show, among other features, gate contacts and source and drain contacts and corresponding fabrication processes, in accordance with aspects of the present disclosure. FIGS. 8A-8D show, among other structural elements, interconnect structures, and corresponding fabrication processes, in accordance with aspects of the present disclosure.Detailed DescriptionThe present disclosure relates generally to semiconductor structures, and more particularly to structures and fabrication methods from the center of the manufacturing line. In embodiments, the processes and structures provided herein enable the gate contacts and the source and drain contacts to be offset from each other. Further, the processes and structures provided herein enable the gate contacts and the source and drain contacts to have different heights from each other. Advantageously, by offsetting contacts at different heights, short circuits may be avoided during the manufacturing processes between the metallization features of the gate structures and the metallization features of the source and drain regions, i.e. during the formation of the interconnection structures for the gate contacts and the source and drain contacts. In this way, the structures and processes described herein provide interconnection structures for both the gate contacts and the source and drain contacts without the issues of short circuits.The structures of the present disclosure may be manufactured in many ways using a number of different equipment. Generally, however, the methods and apparatus are used to produce structures having dimensions on the order of micrometers and nanometers. The methods, i.e., the technologies used to fabricate the structure of the present disclosure are taken from integrated circuit (IC) technology. For example, the structures are produced on wafers and are realized in layers of material which are structured on the top side of a wafer by photolithographic processes. In particular, three basic building blocks are used in the fabrication of the structures: (i) depositing thin layers of material on a substrate, (ii) applying a patterned mask on top of the layers by photolithographic imaging, and (iii) etching the layers selectively to the mask.FIGS. 1A-1C show an initial structure and corresponding fabrication processes, in accordance with aspects of the present disclosure. More specifically, FIG. 1A shows a top view of a structure 100, while FIG. 1B shows a cross-sectional view in an X-axis direction, and FIG. 1C shows a cross-sectional view in a Y-axis direction. The structure 100 comprises an active region 110 serving to form a device, for example a transistor. The structure 100 further comprises a substrate 105 constructed from a suitable semiconductor material. For example, the substrate 105 may be composed of any suitable material, such as, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and the like. In embodiments, the substrate 105 may represent a fin structure or a planar structure element.In embodiments, a ridge structure may be fabricated using a sidewall image transfer (SIT) technique. In an example of a SIT technique, a centering material, for example SiO 2, is deposited on the substrate 105 using conventional CVD processes. A resist material is formed on the centering material and exposed to light to form a pattern (openings). A reactive ion etch is performed through the openings to form the centering. In embodiments, the centering elements may have different widths and / or spacings depending on the desired dimensions of the web structures. Spacers are made on the side walls of the centring elements, preferably made of material different from that of the centring elements, and these are made using conventional deposition processes known to those skilled in the art. The spacers can have a width which corresponds, for example, to the dimensions of the narrow web structures or fin structures. The centering elements are removed or stripped using a conventional etching process, selective to the centering material. An etching process is then performed within the space of the spacers to form sublithographic features. The sidewall spacers may then be removed.Gate structures 150 are formed on the substrate 105. It should be noted that the gate structures 150 may be planar gate structures or fin FET gate structures. In any case, the gate structures 150 may be formed using any known gate fabrication processes, such as replacement gate fabrication processes known in the art. Therefore, the gate structures 150 may be replacement gate structures. In embodiments, the gate fabrication process begins with dummy gate materials, for example, polysilicon (poly-Si) to form dummy gate structures. Source and drain (S / D) regions 115 are formed at the sides of the dummy gate structures in the substrate 105, using, for example, a conventional method. For example, the S / D regions 115 may be formed by an ion implantation process, a doping process, or a diffusion process, as known to those skilled in the art, and thus no further explanation is required to understand the present disclosure. In further embodiments, the S / D regions 115 may be raised S / D regions formed by epitaxial growth on the surfaces of the substrate 105 between the dummy gate structures. In this way, the plurality of gate structures 150 include the S / D regions 115.Sidewall spacers 140, for example, in the form of a low dielectric constant dielectric, may be deposited on the sidewalls of the dummy gate materials. The sidewall spacers 140 may be deposited by conventional CVD processes with a subsequent patterning process, such as an anisotropic etching process, removing material from horizontal surfaces of the structure. A coating 120 is deposited on sidewalls of the spacers 140 of the dummy gate structures and over the S / D regions 115. In embodiments, the coating 120 may be deposited by chemical vapor deposition (CVD) processes. The coating 120 may be constructed of any suitable material, for example, SiN.FIGS. 1B and 1C show an amorphous silicon (α-Si) material 125 deposited over the coating 120. In this way, the α-Si material 125 overlies the S / D regions 115. The α-Si material 125 may be deposited by conventional deposition processes, for example CVD processes, followed by an etching process. The α-Si material 125 is etched using reactive ion etching (RIE) with chemistries selective to the α-Si material 125. In embodiments, the α-Si material 125 is recessed to a height of, for example, in a range of about 10 nm-50 nm. An interlayer dielectric (ILD) 130 is deposited in the recesses over the α-Si material 125. The ILD layer 130 may be constructed of any suitable dielectric material, for example oxide, deposited by a CVD process. The deposition of the ILD layer 130 is followed by a chemical mechanical polishing (CMP) process. In this manner, an ILD layer is created with a dual layer material: an underlying sacrificial layer, i.e., the α-Si material 125, and an upper dielectric cap, i.e., the ILD layer 130. In particular, an ILD layer includes a sacrificial layer and a dielectric cap over the source and drain regions 115 of the gate structures 150.The dummy gate materials, for example poly-Si, are removed, thereby forming trenches and exposing the substrate 105. The dummy gate materials as centering elements are removed or stripped using a conventional etching process that is selective to the dummy gate materials. The gate structures 150 are formed in the trenches on the substrate 105. In embodiments, the gate structures 150 include gate dielectric materials and metallization structures. The gate dielectric materials may be, for example, a gate dielectric material having a high dielectric constant, for example, dielectrics based on hafnium. In further embodiments, the high dielectric constant dielectric materials may include, but are not limited to, Al 2 O 3, Ta 2 O 3, TiO 2, La 2 O 3, SrTiO 3, LaAlO 3, ZrO 2, Y2O3, Gd2O3, and combinations including multilayers thereof. The metallization features, i.e., gate material 135, may include a metal for the work function or a combination of metals depending on the particular application and design parameters. For example, in embodiments, the gate material 135 may be a tungsten (W) material from various examples.In embodiments, the gate material 135 is etched to form recesses in the gate structures 150. In this way, the gate structures 150 become recessed gate structures. The gate material 135 may be etched using etch processes that are selective with respect to the gate material 135, for example, by a wet chemical etch process. A capping material 145 is deposited in recesses over the gate material 135, for example using a CVD process, followed by a CMP process. The capping material 145 may be any suitable capping material, for example SiN, just to name one example.FIGS. 2A and 2B show the formation of shallow trench isolation (STI) regions in the ILD layer 130. In embodiments, the trenches 155 in the ILD layer 130 are formed using conventional lithography and etching techniques, for example, by an RIE process. For example, a resist layer formed over the ILD layer 130 is irradiated with energy (light) to generate a pattern (openings). A selective chemical etching process, such as RIE, is employed to form one or more trenches 155 in the ILD layer 130 through the openings of the resist. The paint may then be removed by a conventional oxygen ashing process or other known strippers.FIGS. 3A-3D show the structure 100 in an additional cross-sectional view. Specifically, FIG. 3A shows a plan view of the structure 100, and FIGS. 3B and 3C show a cross-sectional view in an X-axis direction, and FIG. 3D shows a cross-sectional view in a Y-axis direction. FIG. 3D shows the trenches 155 when filled with a dielectric material 160 to form STI structures 165. In embodiments, the dielectric material 160 may be made of a low dielectric constant dielectric material, for example, SiOC, among many other examples. The deposition of the dielectric material 160 is performed by a CVD process and a subsequent CMP process.FIGS. 4A-4C show photoresist 170 formed over STI structures 165 and ILD layer 130. In embodiments, the photoresist 170 is irradiated with energy (light) to form a pattern (openings). A selective chemical etching process, such as an RIE process, is employed to form one or more trenches 175 in the ILD layer 130 through the openings of the photoresist 170, exposing the α-Si material 125. In particular, FIG. 4C illustrates opening a portion of the dielectric cap, i.e., the ILD layer 130, thereby exposing the sacrificial layer, i.e., the α-Si material 125. As shown in FIGS. 4A and 4C, portions of the ILD layer 130 adjacent to the dielectric material 160 are retained.FIGS. 5A-5C show the removal of the α-Si material 125, thereby forming the trenches 175' exposing the source and drain (S / D) regions 115. The α-Si material 125 may be removed by conventional etching processes, for example a wet chemical process. In embodiments, etching of α-Si material 125 may be performed with or without photoresist 170. According to the present invention, the etching process for the α-Si material 125 is not directed, so that portions of the ILD layer 130 remain in the X-axis direction and the Y-axis direction, as shown in FIGS. 5A and 5C. The photoresist 170 may be stripped by a conventional oxygen ashing process or other known stripping agents.FIGS. 6A-6C show filling the trenches 175' with a sacrificial material 180. In embodiments, the sacrificial material 180 may be SOH, amorphous carbon (alpha-C), or an organic planarization layer (OPL), among other examples. The sacrificial material 180 is used to provide a planar surface for the deposition of the photoresist 170' which is used to etch the capping material 145 of the gate structures 150 (in subsequent processes in the X-axis direction). In embodiments, the photoresist 170' is formed over the STI structures 165, the ILD layer 130, and the sacrificial material 180. The resist 170' is irradiated with energy (light) to form a pattern (openings). A selective chemistry etch process, for example RIE, is applied to remove the capping material 145 through the openings of the resist, thereby forming one or more trenches 185 of the gate material 135 of the gate structures 150 in the X-axis direction. In particular, FIG. 6A illustrates the exposure of the gate materials 135 of the gate structures 150. The photoresist 170' may be removed by a conventional oxygen ashing process or other known strippers, while the sacrificial material 180 may be removed by selective etching. The removal of the capping material 145, i.e., the gate cap, serves for the subsequent formation of gate contacts to the gate structures 150.FIGS. 7A-7D show source and drain and gate metallization features, among other features, and corresponding fabrication processes, in accordance with aspects of the present disclosure. In particular, a silicide coating 190 is deposited in the trenches 185 (over the gate structures 150, and in particular, the gate materials 135) and over the S / D regions 115. In particular, FIG. 7B illustrates the deposition of a coating 190 on the exposed gate materials 135 and the exposed source and drain regions 115 prior to the formation of the metallization features. The coating 190 is subjected to a silicide process. The coating 190 may be deposited using physical vapor deposition (PVD) or CVD processes. The coating 190 may be Ti, TiN, TaN, Ru, and Co, among many other examples. After the silicide process, a metal material 195 is deposited on the liner 190 to form source and drain contacts 200 and the gate contacts 205. In this way, the source and drain contacts 200 and gate contacts 205 are simultaneously made of the same metal material 195.The metal material 195 may be deposited by CVD processes and may be any suitable conductive material. For example, the metal material 195 may be tungsten (W), cobalt (Co), or copper (Cu), for example. A CMP process follows the deposition of the metal material 195. The source and drain contacts 200 are connected to the S / D regions 115 while the gate contacts 205 are connected to the gate structures 150. In this way, the gate contacts 205 of the gate structures 150 include a coating 190 and a fill material, i.e., the metal material 195. Further, the liner 190 overlies the S / D regions 115, the gate materials 135, the gate contacts 205, and the at least one source and drain contact.As shown in FIG. 7A, the source and drain contacts 200 are offset with respect to the gate contacts 205 in both the X-axis direction and the Y-axis direction. In this way, the gate contacts 205 connecting to the gate structures 150 are offset from the source and drain contacts 200 connecting to the S / D regions 115. Specifically, the gate contacts 205 of the gate structures 150 are offset from the source and drain contacts 200 of the S / D regions 115 in an X-axis direction and a Y-axis direction. In particular, FIG. 7B illustrates the simultaneous formation of offset metallization features, i.e., the contacts 200, 205 on the exposed gate materials 135 and the exposed S / D regions 115. Further, as shown in FIG. 7B, the source and drain contacts 200 are at a height different from that of the gate contacts 205. In particular, the source and drain contacts 200 are at a lower height than the gate contacts 205, such that at least one source and drain contact 200 is at a different height than the gate contacts 205. In this way, the gate contacts 205 of the gate structures 150 are arranged at a different height than the source and drain contacts 200 of the S / D regions 115.In embodiments, the source and drain contact 200 is step-shaped with a dielectric cap overlying it, i.e., the ILD layer 130. In particular, the at least one source and drain contact 200 is step-shaped. In this way, the liner 190 is directly in contact with the S / D regions 115, for example, the silicide of the S / D region 115, the sidewall spacers 140 of the gate structures 150, and under the dielectric cap over the source and drain contacts 200. As shown particularly in FIG. 8B, the ILD layer 130 forms the dielectric cap over the source and drain contacts 200. In particular, the dielectric cap includes an oxide material, i.e., the oxide of the ILD layer 130, and the coating 120.The structures and processes described herein provide the advantage of preventing shorts in technologies where smaller dimensions are realized. In particular, short circuits are prevented by forming the source and drain contacts 200 and the gate contacts 205 simultaneously with the metal material 195, but at different heights and being offset from each other.FIGS. 8A-8D show the fabrication of metallization features (e.g., interconnect contact structures) extending from the source and drain contacts 200 and the gate contacts 205. In particular, an etch stop layer 210 is deposited over the ILD layer 130 and the gate contacts 205. In embodiments, the etch stop layer 210 is deposited by a CVD process and may be constructed of nitride material, for example, SiN. An ILD layer 215 is deposited over the etch stop layer 210 by, for example, a CVD process. In embodiments, the ILD layer 215 may be constructed of, for example, an oxide material. A CMP process is performed after the deposition of the ILD layer 215.Interconnect structures 220, 225 extending from the contacts 200, 205 may be formed using conventional lithography and etching processes, for example, an RIE process. For example, a resist formed over the ILD layer 215 is irradiated with energy (light) to form a pattern (openings). A selective chemical etch process, such as a reactive ion etch (RIE), is performed to form one or more trenches in the ILD layer 215 through the openings of the resist. The paint may then be removed by a conventional oxygen ashing process or other known strippers.The removal of the resist is followed by the deposition of a conductive material by conventional deposition processes, for example CVD processes, to form the interconnect structures 220, 225. Residual conductive material on the surface of the ILD layer 215 may be removed by conventional CMP processes. The conductive material used to form the interconnect structures 220, 225 may be any suitable conductive material, for example tungsten (W). In embodiments, the interconnect structures 220 are directly in electrical contact with the source and drain contacts 200, while the interconnect structures 225 are in direct electrical contact with the gate contacts 205. In this way, the interconnect structures 220, 225 are in direct electrical contact with the contacts of the gate structures 150 and the contacts of the source and drain regions (S / D) 115. FIG. 8B illustrates the formation of offset contacts, i.e., interconnect structures 220, 225, extending from the metallization features, i.e., contacts 200, 205. Further, FIG. 8B shows that the plurality of gate structures 150 include source and drain regions 115, the gate materials 135, the gate contacts 205, and the interconnect structures 225 extending from the gate contacts 205.It should now be appreciated that the processes and resulting structures described herein serve to better protect the gate metal of the gate structure during the MOL processes. The resulting structures, for example sidewall structures, thus prevent the occurrence of short circuits in interconnects or other wiring structures of the source / drain regions. Thus, the processes and structures described herein result in an increase in yield.The above-described methods are used in the production of integrated circuit chips. The resulting integrated circuit chips may be sold by the manufacturer in the form of non-fully processed wafers (i.e., as a single wafer on which multiple chips are unpackaged), as a bare chip, or in the form of chips in packages. In the latter case, the chip is packaged in a single chip package (such as a plastic carrier, with terminals attached to a motherboard or higher level carrier) or in a multi-chip package (such as a ceramic carrier on which one or both surfaces have interconnects or buried interconnects). In either case, the chip is then connected to other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product, such as a motherboard, or (b) as an end product. The final product may be any final product containing integrated circuit chips, ranging from toys or other applications with low demands to advanced computer products with a display, keyboard or other input devices, and a central processor.

Claims

A structure comprising: a plurality of gate structures (150) including source and drain regions (115); contacts (200) connected to the source and drain regions (115), the contacts (200) including regions along an X-axis direction and a Y-axis direction covered by a dielectric cover (130), and the contacts (200) further including regions not covered by the dielectric cover (130) such that a step is formed along the Y-axis direction; Contacts (205) connected to the gate structures (150) and offset from the contacts (200) connected to the source and drain regions (115) at least along the X-axis direction, wherein the areas of the contacts (200) connected to the source and drain regions (115) covered by the dielectric cover (130) have a reduced height compared to the contacts (205) connected to the gate structures (150); and interconnection structures (220, 225) in electrical contact with the contacts (205) connected to the gate structures (150) and the contacts (200) connected to the source and drain regions (115), wherein the contacts (205) connected to the gate structures (150) and the covered and uncovered regions of the contacts (200) connected to the source and drain regions (115) are made of a coating (120) and a same filling material (195).The structure of claim 1, wherein the coating (120) is TiN.The structure of claim 2, wherein the TiN coating (120) overlies the source and drain regions (115).The structure of claim 3, wherein the fill material (195) is cobalt or tungsten.The structure of claim 1, wherein the contacts (205) connected to the gate structures (150) are offset from the contacts (200) connected to the source and drain regions (115) in the Y-axis direction.The structure of claim 1, wherein the dielectric cover (130) comprises an oxide material and a coating (210).The structure of claim 6, wherein the coating (210) is constructed from a nitride material.The structure of claim 1, wherein the gate structures (150) are replacement gate structures.The structure of claim 1, wherein the gate structures (150) are recessed gate structures.A structure comprising: a plurality of gate structures (150) including source and drain regions (115), gate contacts (205), and interconnect structures (220, 225) extending from the gate contacts (205); at least one source and drain contact (200) including a first region having a first height and covered by a dielectric cover (130) and extending in an X-axis direction and a Y-axis direction, and a second region not covered by the dielectric cover (130) and having a second height higher than the first height, such that a step shape is formed, the first height being less than a height of the gate contacts (205); and a conductive coating (120) over the source and drain regions (115), the gate contacts (205), and over the first region of the at least one source and drain contact (200), wherein the source and drain contact (200) having the step shape is formed of a same fill material (195).The structure of claim 10, wherein the at least one source and drain contact (200) is offset from the gate contacts (205) in the X-axis direction or the Y-axis direction.The structure of claim 10, wherein the coating (120) is constructed from a TiN material.A method, comprising: forming a plurality of gate structures (150) comprising source and drain regions (115) and gate materials (135); forming an interlayer dielectric layer comprising a sacrificial layer (125) and a dielectric cap (130) over source and drain regions (115) of the gate structures (150); opening a portion of the dielectric cap (130) to expose the sacrificial layer (125); removing the sacrificial layer (125) by non-directional etching, wherein portions of the dielectric cap (130) remain in an X-axis direction and a Y-axis direction to expose the source and drain regions (115); exposing the gate materials (135); simultaneously forming offset metallization features over the exposed gate materials (135) and the exposed source and drain regions (115) also under the remaining regions of the dielectric cap (130), thereby creating a step shape in the Y-axis direction for the metallization structures formed over the source and drain regions (115), the height of which under the regions of the dielectric cap (130) is less than a height of the metallization structures over the gate materials (135); and forming offset contacts (220, 225) extending from the metallization features.The method of claim 13, further comprising: depositing a coating (120) on the exposed gate materials (135) and the exposed source and drain regions (115) prior to forming the metallization features.

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