Semiconductor device

Abstract

Semiconductor device comprising: a semiconductor substrate (1) containing a semiconductor material having a band gap wider than that of silicon; a first semiconductor layer (31) of a first conductivity type provided on a front surface of the semiconductor substrate (1), wherein the first semiconductor layer (31) contains a semiconductor material having a band gap wider than that of silicon; a second semiconductor layer (32) of a second conductivity type, which is provided on a first side of the first semiconductor layer (31) opposite a second side of the first semiconductor layer (31) which is arranged facing the semiconductor substrate (1), wherein the second semiconductor layer (32) contains a semiconductor material having a band gap wider than that of silicon; a first semiconductor region (5) of the first conductivity type, which is selectively provided in the second semiconductor layer (32); a trench (7) that penetrates the first semiconductor region (5) and the second semiconductor layer (32) and reaches the first semiconductor layer (31); a second semiconductor area (21) which lies below a bottom of the trench (7) and is selectively provided in the first semiconductor layer (31) separated from the second semiconductor layer (32); a conductive layer (22) provided in the trench (7); an insulating layer (8a) provided on top of the conductive layer (22) in the trench (7); an insulating film (8b) which is provided along a side wall of the trench (7) and in contact with and continuous with the insulating layer (8a); a gate electrode (9) provided on the insulating layer (8a) and the insulating film (8b) in the trench (7); a first electrode (12a) in contact with the second semiconductor layer (32) and the first semiconductor region (5); a second electrode (13) provided on a rear surface of the semiconductor substrate (1); and a Schottky junction diode formed from a Schottky junction (23) between the conductive layer (22) and the first semiconductor layer (31).

Description

BACKGROUND1. Area

[0001] Embodiments of the invention relate to a semiconductor device. 2. Description of related technology

[0002] Conventionally, a power semiconductor device using a semiconductor material (hereinafter: wide-bandgap semiconductor material) with a wider band gap than that of silicon is required to have a reduced on-resistance. For example, a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) uses a trench gate structure, which has a structurally low on-resistance characteristic compared to a planar gate structure in which an MOS gate is arranged in a flat, plate-like shape on a front surface of a semiconductor chip. A trench gate structure is a MOS gate structure in which an MOS gate is embedded in a trench formed on the front surface of the semiconductor chip. The trench gate structure enables a reduction in on-resistance by reducing the cell pitch.

[0003] A conventional trench-gate MOSFET is described using silicon carbide (SiC) as the wide bandgap semiconductor material as an example. Fig. 12 shows a cross-sectional view of a structure of a conventional semiconductor device. Fig. The trench gate MOSFET shown in Figure 12 is fabricated using a semiconductor substrate (hereinafter silicon carbide substrate) 110 containing silicon carbide and in which silicon carbide layers having a drift region of n - -type 102 and a p-type base region 104, by epitaxial growth sequentially on a front surface of a silicon carbide-containing starting substrate of n + -type (hereinafter referred to as silicon carbide substrate of n + -type) 101. The first and second areas of the p +-Type 121, 122 are selectively formed from the front surface of the silicon carbide substrate 110 at a deep position, closer to a drain than a bottom of a trench (hereinafter: gate trench) 107.

[0004] The first area of ​​the p + -Type 121 lies under the bottom of the gate trench 107. The second area of ​​the p + -Type 122 is selectively provided between (mesa region) adjacent gate trenches 107 and separated from the gate trench 107. The provision of the first and second regions of the p +-type 121, 122 suppresses the electric field applied to a gate insulating film in the OFF state. This allows the cell pitch and the ON resistance to be reduced while maintaining the breakdown voltage. A MOS gate in a gate trench 107 and adjacent mesa regions between which the MOS gate is arranged form a unit cell (configuration unit of an element). Reference numerals 103, 105, 106, 108, 109, 111 to 113 are an n-type current spreading region, an n-type source region, and + -Type, a contact area of ​​p ++ -type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode and a drain electrode.

[0005] To reduce the number of components and reduce costs, it is conventional to use a parasitic diode (substrate diode) formed within the trench-gate MOSFET instead of an externally provided Schottky junction diode (SBD). However, using a substrate diode of a trench-gate MOSFET instead of an external SBD results in increased OFF loss and degradation of the substrate diode. To overcome these problems, the fabrication of a built-in trench-type SBD on a single semiconductor chip in which the trench-gate MOSFET is fabricated has been proposed.

[0006] A conventional trench-gate MOSFET in which a trench-type SBD is incorporated on a single semiconductor chip is described. Fig. 13 shows a cross-sectional view of another example of a structure of a conventional semiconductor device. Fig. 13 is different from the conventional semiconductor device shown in Fig. 12 in that a trench-type SBD 132 is installed between adjacent gate trenches 107 of a trench-gate MOSFET 131.

[0007] The trench-type SBD 132 comprises a trench 141 between the gate trenches 107 and a conductive layer 142 embedded in the trench 141. The trench-type SBD 132 is formed by a Schottky junction 143 between the n-type current spreading region 103 and the conductive layer 142 formed along a sidewall of the trench 141. The first p-type region + -Type 121 lies under a floor of trench 141 and the second area of ​​the p + -Type is not present.

[0008] As a trench-gate MOSFET with built-in trench-type SBD on the single semiconductor chip, a device has been proposed in which a Schottky junction of a base region of p - -type and a barrier metal is formed at a bottom of a source contact trench (see, for example, Japanese Laid-Open Patent Publication JP 2011 - 9 387 A (paragraphs 0031 to 0032, Fig. 1)). In Japanese Patent Laid-Open Publication JP 2011 - 9 387 A, a path from a source electrode via a barrier metal forms a base region of the p - -Type, a channel range of n - -type, an n-type drift region and an n-type substrate + -Type to a drain electrode a Schottky junction diode and the reverse recovery properties of the installed diode are improved.

[0009] Further, as another trench-gate MOSFET in which a trench-type SBD is incorporated on a single semiconductor chip, a device has been proposed in which a Schottky electrode is embedded in a trench deeper than a gate trench and forms a Schottky junction with the semiconductor substrate (see Japanese Laid-Open Patent Publication JP 2010 - 259 278 A (paragraphs 0070 to 0071, Fig. 9)). In Japanese Laid-Open Patent Publication JP 2010-259278A, a semiconductor part is formed between trenches in which the Schottky electrode is embedded, in a region pinched by a depletion layer extending from the Schottky electrode, and an electric field significantly exceeding the electric field at the time of pinching is prevented from being applied to the bottom of the gate trench. SUMMARY

[0010] It is an object of the present invention to solve at least the above-mentioned problems in the conventional technologies.

[0011] According to one embodiment of the invention, a semiconductor device comprises a semiconductor substrate containing a semiconductor material having a band gap wider than that of silicon; a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate, the first semiconductor layer containing a semiconductor material having a band gap wider than that of silicon; a second semiconductor layer of a second conductivity type provided on a first side of the first semiconductor layer opposite a second side of the first semiconductor layer facing the semiconductor substrate, the second semiconductor layer containing a semiconductor material having a band gap wider than that of silicon; a first semiconductor region of the first conductivity type selectively provided in the second semiconductor layer;a trench penetrating the first semiconductor region and the second semiconductor layer and reaching the first semiconductor layer; a second semiconductor region located below a bottom of the trench and selectively provided in the first semiconductor layer separately from the second semiconductor layer; a conductive layer provided in the trench; an insulating layer provided on the conductive layer in the trench; an insulating film provided along a sidewall of the trench and in contact with and continuous with the insulating layer; a gate electrode provided on the insulating layer and the insulating film in the trench; a first electrode in contact with the second semiconductor layer and the first semiconductor region; a second electrode provided on a rear surface of the semiconductor substrate;and a Schottky barrier diode formed from a Schottky junction between the conductive layer and the first semiconductor layer;

[0012] In the embodiment, an interface between the conductive layer and the insulating layer is positioned closer to the semiconductor substrate than an interface between the second semiconductor layer and the first semiconductor layer.

[0013] In the embodiment, a distance from an interface between the conductive layer and the insulating layer to an interface between the second semiconductor layer and the first semiconductor layer is in the range of 0.3µm to 0.6µm.

[0014] In the embodiment, the trench has a depth in the range of 1.1µm to 3.2µm. The conductive layer has a thickness in the range of 0.1µm to 0.6µm.

[0015] In the embodiment, the semiconductor device further includes a third semiconductor region of the first conductivity type provided in the first semiconductor layer, the third semiconductor region being in contact with the second semiconductor layer and reaching a deep position closer to the second electrode from the interface between the first semiconductor layer and the second semiconductor layer than the bottom of the trench, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor layer. The Schottky barrier diode is formed of a Schottky junction between the conductive layer and the third semiconductor region.

[0016] In the embodiment, the trench is arranged in a stripe arrangement extending in a direction parallel to the front surface of the semiconductor substrate.

[0017] Objects, features and advantages of the present invention are set forth in or will become apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a structure of a semiconductor device according to an embodiment; Fig. 2 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 3 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 4 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 5 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 6 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 7 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 8 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 9 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 10 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 11 is a cross-sectional view of the semiconductor device according to the embodiment during manufacture; Fig. 12 is a cross-sectional view of a structure of a conventional semiconductor device; and Fig. 13 is a cross-sectional view of another example of a structure of a conventional semiconductor device. DESCRIPTION OF EMBODIMENTS

[0018] First, problems associated with conventional techniques are described. As described above, the conventional trench gate MOSFET 131 (see Fig. 13) with the trench-type SBD 132 incorporated therein, the trench-type SBD 132 is arranged between the adjacent gate trenches 107. Therefore, the cell pitch (the distance between the gate trenches 107) is difficult to reduce, and the problem arises that the ON resistance cannot be reduced.

[0019] Embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and the accompanying drawings, layers and regions preceded by n or p indicate that the majority carriers are electrons or holes. In addition, + or - added to n or p indicates that the impurity concentration is higher or lower, respectively, than in layers and regions without + or -. In the description of the following embodiments and the accompanying drawings, the main parts that are identical are denoted by the same reference numerals and will not be described repeatedly.

[0020] A semiconductor device according to an embodiment is designed using a semiconductor material (wide band gap semiconductor material) with a larger band gap than that of silicon. A structure of the semiconductor device according to the embodiment will be described using a case where, for example, silicon carbide (SiC) is used as the wide band gap semiconductor material. Fig. 1 is a cross-sectional view of a structure of the semiconductor device according to the embodiment. Fig. Figure 1 shows a unit cell (configuration unit of an element) of a trench-gate MOSFET 41 and 1 / 2 of each unit cell on each side of the one unit cell. Fig. 1 only some of the unit cells arranged in an active region are shown and an edge termination region surrounding an edge of the active region is not shown (similar to Fig. 2 to 11).

[0021] The active region is a region through which current flows when the semiconductor device is in the ON state. The edge termination region is a region between the active region and a side surface of a semiconductor substrate (semiconductor chip) 10, and is a region that separates the electric field at a side of the substrate front surface (a front surface of the semiconductor substrate 10) from a drift region of the n-type. - -Type 2 attenuates the breakdown voltage and maintains the breakdown voltage. A breakdown voltage structure, such as a p-type region forming a JTE (Junction Termination Extension) structure or a guard ring, a field plate, RESURF, etc., is arranged in the edge termination region. The breakdown voltage is a voltage limit that does not cause any malfunction or failure of the semiconductor device.

[0022] The Fig. The semiconductor device according to the embodiment shown in Figure 1 is the trench-gate MOSFET 41, in which a trench-type SBD is incorporated in the semiconductor substrate (silicon carbide substrate) 10 containing silicon carbide. The semiconductor substrate 10 is an epitaxial substrate in which silicon carbide layers (first and second semiconductor layers) 31, 32, which form the drift region of the n-type, are formed. - -type 2 and a p-type 4 base region, sequentially by epitaxial growth on a silicon carbide-containing starting substrate of n + -type (silicon carbide substrate of n + -type) 1. A MOS gate of the trench-gate MOSFET is composed of the p-type base region 4, a source region of the n + -type (first semiconductor region) 5, a contact region of p ++ -type 6, a gate trench 7, a gate insulating film 8 and a gate electrode 9 provided on the front surface side of the substrate.

[0023] In particular, in a surface layer on a source side (side facing a source electrode 12a) of a silicon carbide layer of n - -type region 31, an n-type region (hereinafter, n-type current spreading region (third semiconductor region)) 3 is provided so as to be in contact with a p-type silicon carbide layer 32 (the p-type base region 4). The n-type current spreading region 3 is a so-called current spreading layer (CSL) that reduces carrier spreading resistance. For example, the n-type current spreading region 3 is uniformly arranged in a direction parallel to the substrate front surface and exposed at an inner wall of the gate trench 7. The n-type current spreading region 3 reaches, from an interface with the p-type base region 4, a deep position closer to a drain (a drain electrode 13) than a bottom of the gate trench 7.

[0024] Part of the silicon carbide layer from the n- -Type 31 without the current spreading region of n-Type 3, the drift region of n - -Type 2 In other words, between the drift region of the n - -type 2 and the p-type base region 4, the n-type current spreading region 3 is provided, which is arranged exposed on the inner wall of the gate trench 7 and is connected to the n-type drift region. - -type 2 and the base region of p-type 4. In the current spreading region of n-type 3, a region (second semiconductor region) of p + -Type 21 is formed so that it lies below the bottom of the gate trench 7.

[0025] The area from p + -Type 21 is separated from the p-type 4 base region at a deep position closer to the drain than an interface between the p-type 4 base region and the n-type 3 current spreading region. The p +-Type 21 has a function of depleting during the OFF state of the trench gate MOSFET 41 and attenuating the electric field applied to a part of a later-described conductive layer 22 along the inner wall of the trench 7. The area of ​​the p + -Type 21 can extend from the bottom of the gate trench 7 to a bottom corner portion to completely cover the bottom of the gate trench 7 and the bottom corner portion. The bottom corner portion of the gate trench 7 is a boundary between the bottom of the gate trench 7 and a sidewall.

[0026] An edge of the region facing the drain from the p + -Type 21 may terminate in the current spreading region of n-type 3 or may form an interface between the current spreading region of n-type 3 and the drift region of n - -Type 2 or in the drift range of n - -Type 2. In other words, a pn junction of the area from the p +-Type 21 and the current spreading region of n-Type 3 (or the drift region of n - -Type 2) is positioned deeper towards the drain than the bottom of the gate trench 7 and a depth of the first region of the p + -Type 21 can be modified in different ways.

[0027] In the p-type silicon carbide layer 32, between (mesa region) the gate trench 7 and an adjacent gate trench 7, the source region of the n + -Type 5 and the contact area of ​​the p ++ -Type 6 are provided selectively. The source area of ​​the n + -Type 5, for example, is made up of a first area of ​​n + -Type 5a and a second area of ​​n + -Type 5b are formed, which are located at a position deeper from the substrate front surface than the first region of the n + -Type 5a. The first and second areas of the n + -Type 5a, 5b are in contact with each other. The first area of ​​the n +-Type 5a may have an impurity concentration that is higher than an impurity concentration of the second region of n + -Type 5b. The second area of ​​the n + -Type 5b can be omitted. The contact area of ​​the p ++ -Type 6 is in contact with the first area of ​​the n + -Type 5a. A depth of the contact area of ​​p ++ -Type 6, for example, is deeper than that of the first area of ​​the n + -Type 5a.

[0028] The gate trench 7 penetrates the source region of the n + -Type 5 (the first and second area of ​​the n + -type 5a, 5b) and the p-type base region 4 in a depth direction from the front surface (surface of the p-type silicon carbide layer 32) of the semiconductor substrate 10. The gate trench 7 reaches the n-type current spreading region 3 and ends in the p +-Type 21. The depth direction is a direction from the front surface of the semiconductor substrate 10 to a rear side. A depth d of the gate trench 7 may, for example, be in the range of approximately 1.1 µm to 3.2 µm. Furthermore, the gate trench 7, viewed from the front surface side of the semiconductor substrate 10, is arranged, for example, in a stripe arrangement extending along a direction (direction orthogonal to the viewing plane in Fig. 1) extends parallel to the front surface of the semiconductor substrate 10.

[0029] In the gate trench 7, the conductive layer 22, such as a metal layer or a polysilicon (poly-Si) layer, is embedded at the lowermost side of the gate trench 7. The conductive layer 22 is drawn to the front surface of the semiconductor substrate 10 at a portion not shown and is electrically connected to a source electrode pad 12b described below. An interface between the conductive layer 22 and an insulating layer 8a is located at a deep position closer to the drain than the interface between the p-type base region 4 and the n-type current spreading region 3. The conductive layer 22 is in contact with the n-type current spreading region 3 at a sidewall of the gate trench 7. A Schottky junction 23 is formed by the conductive layer 22 and the n-type current spreading region 3 along the sidewall of the gate trench 7.

[0030] In other words, a unit cell of the trench-type SBD is formed from the Schottky junction 23 formed along a sidewall of the gate trench 7. Each unit cell of the trench-type SBD extends in a direction in which the stripe shape of the gate trench 7 extends. A mathematical area (area of ​​the Schottky junction 23) of a unit cell of the trench-type SBD is adjustable by the depth d of the gate trench 7 and a length (length of the gate trench 7 in the longitudinal direction as viewed from the front surface side of the semiconductor substrate 10) in which the gate trench 7 extends in the stripe shape. The trench-type SBD 42 has a function of preventing the deterioration of the parasitic diode (substrate diode) formed in the trench-gate MOSFET 41.

[0031] Furthermore, in the gate trench 7, the insulating layer 8a is provided on the conductive layer 22, and a MOS gate of a unit cell of the trench-gate MOSFET 41 is embedded on the insulating layer 8a. That is, in one gate trench 7, a unit cell of the trench-gate MOSFET 41 and a unit cell of the trench-type SBD are arranged opposite each other in the depth direction via the insulating layer 8a. In one gate trench 7, one function of a MOSFET and one function of an SBD are realized.

[0032] The MOS gate of the trench-gate MOSFET is formed of the gate insulating film 8 and the gate electrode 9. The gate insulating film 8 is formed of the insulating layer 8a on the conductive layer 22 and an insulating film 8b arranged along a sidewall of the gate trench 7 so as to be in contact and continuous with the insulating layer 8a. The insulating layer 8a has a thickness t1 that is thicker than a thickness t2 of the insulating film 8b. The gate electrode 9 is provided on the gate insulating film 8 (the insulating layer 8a and the insulating film 8b) in the gate trench 7. The gate electrode 9 is electrically insulated from the conductive layer 22 by the insulating layer 8a and the insulating film 8b.

[0033] On the side wall of the gate trench 7, the gate electrode 9 is further exposed to the second region of the n + -Type 5b (or the first and second area of ​​the n +-type 5a, 5b) are arranged opposite each other via the insulating film 8b. An end of the gate electrode 9 toward the drain reaches a deep position closer to a drain than the interface between the p-type base region 4 and the n-type current spreading region 3. An interlayer insulating film 11 covers the gate electrode 9 embedded in the gate trench 7. The interlayer insulating film 11 may be provided on the gate electrode 9 in the gate trench 7.

[0034] The gate electrode 9 is drawn to the front surface of the semiconductor substrate 10 at a portion not shown and is electrically connected to a gate electrode pad (not shown). The source electrode 12a is connected to the source region of the n-type via a contact hole opened in the interlayer insulating film 11. + -Type 5 (the first area of ​​the n + -Type 5a) and the contact area of ​​the p ++ -Type 6 and is electrically connected to the source region of the n+ -Type 5 (the first area of ​​the n + -Type 5a).

[0035] The source electrode 12a is electrically insulated from the gate electrode 9 by the interlayer insulating film 11. The source electrode 12a is electrically connected to the source electrode pad 12b provided on the source electrode 12a and the interlayer insulating film 11. On the back side (the back side of the silicon carbide substrate of the n + -Type 1, which have a drain area of ​​n + -type) of the semiconductor substrate 10, the drain electrode 13 is provided.

[0036] The dimensions of the regions of the semiconductor device according to the embodiment have, for example, the following values, although they are not particularly limited thereto. A distance (thickness of the conductive layer 22) x1 from an interface between the conductive layer 22 and the insulating layer 8a to the bottom of the gate trench 7 is approximately 0.1 μm to 0.6 μm. A distance x2 from the interface between the p-type base region 4 and the n-type current spreading region 3 to the interface of the conductive layer 22 and the insulating layer 8a is approximately 0.3 μm to 0.6 μm. A distance x3 from an edge of the second n-type region + -type 5b to the drain to the interface between the p-type base region 4 and the n-type current spreading region 3 is about 0.1 µm to 1.0 µm. A distance x4 from an edge of the gate electrode 9 toward a source to an edge of the second n-type region +-Type 5b to the drain is approximately 0.3 µm to 0.5 µm. A distance x5 from an edge of the interlayer insulating film 11 toward the source to an edge of the gate electrode 9 toward the source is approximately 0.3 µm to 0.6 µm.

[0037] The operation of the semiconductor device according to the embodiment will be described. The conductive layer 22 forming the trench-type SBD is formed from the p-type region. + -Type 21 at the bottom and the bottom corner region of the gate trench 7. Therefore, when the trench gate MOSFET 41 is in the OFF state, a depletion layer is formed in the region from p + -Type 21 of the pn junction of the area of ​​the p + -Type 21 and the current spreading region of n-Type 3 (or the drift region of n --type 2 depending on the depth of the n-type current spreading region 3). As a result, an electric field applied to a part of the conductive layer 22 along the inner wall of the gate trench 7 is weakened and leakage current can thus be reduced. In other words, the breakdown voltage is determined by a depth position of a pn junction of the region from the p + -Type 21 and the current spreading region of n-Type 3 and the impurity concentrations of the region of p + -Type 21 and the current propagation area of ​​n-Type 3.

[0038] When a parasitic pn diode formed by the pn junction between the p-type base region 4 and the n-type current spreading region 3 of the trench-gate MOSFET 41 is further forward biased, the trench-type SBD is turned on earlier than the parasitic pn diode by a lower voltage than that for the parasitic pn diode of the trench-gate MOSFET 41. Therefore, no base current flows in a vertical parasitic npn bipolar transistor (substrate diode) consisting of the n-type current spreading region 3, the p-type base region 4, and the n-type source region. + -Type 5 of the trench-gate MOSFET 41 is formed, and thus the parasitic NPN bipolar transistor is not operating. Accordingly, forward bias deterioration due to the parasitic NPN bipolar transistor does not occur. In addition, the turn-off loss due to the parasitic NPN bipolar transistor can be reduced.

[0039] A method for manufacturing the semiconductor device according to the embodiment will be described. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 and Fig. 11 are cross-sectional views of the semiconductor device according to the embodiment during manufacture. First, as shown in Fig. 2, the silicon carbide substrate of n + -Type 1, which has a drain region of n + -type. Then, on the front surface of the silicon carbide substrate, the n + -Type 1 the silicon carbide layer of n - -type 31 is formed by epitaxial growth. Subsequently, photolithography and ion implantation of a p-type impurity are used to form the p + -Type 21 selectively in a surface layer of the silicon carbide layer of n - -Type 31 formed.

[0040] Subsequently, by photolithography and ion implantation of an n-type impurity, for example, an n-type region (hereinafter referred to as n-type sub-region) 3a is formed in the surface layer of the n-type silicon carbide layer 31. - -Type 31 is formed over the entire active region. The n-type 3a subregion is part of the n-type 3 current spreading region. The depth of the n-type 3a subregion can be varied in various ways. Fig. Figure 2 shows a case where the n-type subregion 3a is located at a depth deeper than the depth of the p-type region + -Type 21 and with a whole side (side facing the silicon carbide substrate from the n + -Type 1) of the area from the p + -Type 21 is in contact with the drain (similar to Fig. 3 to 11). A part of the silicon carbide layer from the n - -Type 31 closer to the drain than the n-type 3a portion is the drift region of the n --Type 2. An order in which the sub-area of ​​n-type 3a and the area of ​​p + -Type 21 can be reversed.

[0041] Then, as in Fig. 3, on the silicon carbide layer of n - -Type 31 by epitaxial growth a silicon carbide layer of n - -type, which reduces the thickness of the silicon carbide layer from n - -type 31. Subsequently, by photolithography and ion implantation of an n-type impurity, e.g., over the entire active area at a part 31a where the thickness of the silicon carbide layer is increased from n --type 31 is increased, an n-type subregion 3b is formed to a depth that reaches the n-type subregion 3a. The n-type subregion 3b has an impurity concentration substantially equal to that of the n-type subregion 3a. The n-type subregions 3a, 3b are connected in the depth direction, thereby forming the n-type current spreading region 3. When the thickness of the n-type silicon carbide layer - -type 31 is increased, an n-type silicon carbide layer having an impurity concentration equal to that of the n-type 3 current spreading region can be formed by epitaxial growth as the n-type partial region 3b.

[0042] Then, as in Fig. 4, the p-type silicon carbide layer 32 is formed by epitaxial growth on the p-type silicon carbide layer 31. This creates the silicon carbide substrate (semiconductor wafer) 10 in which the n-type silicon carbide layer- -type 31 and the p-type silicon carbide layer 32 are successively deposited onto the n-type silicon carbide substrate + -Type 1. Then, as in Fig. 5, by a method comprising photolithography and ion implantation as a set and repeated under different conditions, selectively in a surface layer of the p-type silicon carbide layer 32, the first and second regions of the n + -Type 5a, 5b (source area from n + -Type 5) or the contact area of ​​the p ++ -Type 6 is formed. Subsequently, a heat treatment (activation annealing) is carried out to activate the impurities in all areas formed by ion implantation.

[0043] During ion implantation to form the first region of the n + -Type 5a, for example, phosphorus (P) or arsenic (As) is used as a dopant, with the first region of the n +-Type 5a is formed with an impurity concentration higher than that of the second region of the n + -Type 5b. During ion implantation to form the second region of the n + -Type 5b, for example, nitrogen (N) is used as a dopant, with the second region of the n + -Type 5b deeper than the first area of ​​the n + -Type 5a is formed. A sequence in which the first and second areas of the n + -Type 5a, 5b and the contact area of ​​the p ++ -type 6 can be reversed. A part of the p-type silicon carbide layer 32 other than the first and second n-type regions + -Type 5a, 5b and the contact area of ​​the p ++ -Type 6 is the base region of p-type 4.

[0044] Then, as in Fig. 6, the gate trench 7 is formed, which separates the first and second regions from the n +-type 5a, 5b and the base region of p-type 4 to form the first region of p + -Type 21 in the current propagation range of n-Type 3. Then, as in Fig. 7, the conductive layer 22, such as a metal layer, polysilicon (poly-Si), etc., e.g. by a deposition process, is applied to the front surface of the semiconductor substrate 10 to be embedded in the gate trench 7. Subsequently, as in Fig. 8, the conductive layer 22 is etched only toward the bottom, leaving the conductive layer 22 in the trench 7; the conductive layer 22 has the predetermined thickness t11. The thickness t11 of the conductive layer 22 is assumed to be equal to the distance x1 from the interface between the conductive layer 22 and the insulating layer 8a to the bottom of the gate trench 7, as described above.

[0045] Then, as in Fig. 9, e.g., by a deposition process, the insulating layer 8a is applied to the front surface of the semiconductor substrate 10 to be embedded in the gate trench 7. Subsequently, the insulating layer 8a is etched so that the insulating layer 8a remains only in the gate trench 7, wherein the insulating layer 8a has the predetermined thickness t1. Subsequently, as shown in Fig. 10, the front surface of the semiconductor substrate 10 and the sidewalls of the gate trench 7 are thermally oxidized, thereby forming the insulating film 8b along the front surface of the semiconductor substrate 10 and the sidewalls of the gate trench 7. The insulating film 8b is formed in contact and continuous with the insulating layer 8a. As a result, the gate insulating film 8b formed from the insulating layer 8a and the insulating film 8b is formed in the gate trench 7.

[0046] Subsequently, a polysilicon layer is deposited on the front surface of the semiconductor substrate 10, e.g., by a deposition process, to be embedded in the gate trench 7. Subsequently, the polysilicon layer is etched, leaving the polysilicon layer only in the gate trench 7, so as to form the gate electrode 9. Subsequently, as shown in Fig. 11, for example, by a deposition process, the interlayer insulating film 11 is formed on the front surface of the semiconductor substrate 10 to be embedded in the gate trench 7. Subsequently, the interlayer insulating film 11 and the insulating film 8b are etched, leaving the interlayer insulating film 11 and the insulating film 8b only in the gate trench 7. This exposes the front surface of the semiconductor substrate 10 between adjacent gate trenches 7.

[0047] A part of the front surface of the semiconductor substrate 10 not covered by the interlayer insulating film 11 is a contact hole 11a for forming an electrical contact of the source electrode 12a and a silicon region (the first region of the n + -Type 5a and the contact area of ​​the p ++ -Type 6). Subsequently, the source electrode 12a is formed by a general method, which is in ohmic contact with the first region of the n + -Type 5a and the contact area of ​​the p ++ -Type 6. The source electrode contact area 12b is formed in contact with the source electrode 12a. The drain electrode 13 is formed on the back of the semiconductor substrate 10. Thereafter, the semiconductor wafer is cut into individual chips, thereby completing the Fig. MOSFET shown in Figure 1.

[0048] As described, according to the embodiment, a single unit cell of a trench-gate MOSFET and a single unit cell of a trench-type SBD are arranged in a single trench, and a function of a MOSFET and a function of a trench-type SBD are realized in the single gate trench. In other words, a trench-type SBD is arranged between adjacent gate trenches as in the conventional structure (see Fig. 13) is not required. Therefore, even if a trench-type SBD is mounted on the same semiconductor chip as a trench-gate MOSFET, the cell pitch (distance between adjacent gate trenches) can be reduced, and the ON resistance can be reduced by reducing the cell pitch.

[0049] Since the trench-type SBD according to the embodiment is mounted on the same semiconductor chip as the trench-gate MOSFET, increases in turn-on losses and deterioration of the parasitic diode (substrate diode) formed in the trench-gate MOSFET can be avoided.

[0050] In the embodiments of the present invention, various changes are possible within a scope that does not deviate from the spirit of the invention. For example, in the embodiments, dimensions, impurity concentrations, etc. of regions can be variously set according to requirements. Furthermore, in the embodiments, although a case where an epitaxial substrate in which a silicon carbide layer is formed by epitaxial growth on a silicon carbide substrate was described as an example, regions constituting a semiconductor device according to the present invention may be formed in the silicon carbide substrate, for example, by ion implantation, etc. Moreover, the present invention is also applicable to a wide band gap semiconductor material other than silicon carbide (e.g., gallium (Ga), etc.).The present invention is implemented in a similar manner when the conductivity types (n-type, p-type) are reversed.

[0051] According to the embodiments of the present invention, the provision of the trench-type SBD between adjacent gate trenches is as in the conventional structure (see Fig. 13) is not required. Even if a trench-type SBD is mounted on the same semiconductor chip as a trench-gate MOS semiconductor device, the cell pitch (distance between adjacent gate trenches) can be reduced.

[0052] The semiconductor device according to the present invention achieves an effect that the ON resistance can be reduced by reducing the cell pitch.

[0053] As described, the semiconductor device according to the present invention is suitable for MOS type semiconductor devices having a trench gate structure.

Claims

[1] Semiconductor device comprising: a semiconductor substrate (1) containing a semiconductor material having a band gap wider than that of silicon; a first semiconductor layer (31) of a first conductivity type provided on a front surface of the semiconductor substrate (1), the first semiconductor layer (31) containing a semiconductor material having a band gap wider than that of silicon; a second semiconductor layer (32) of a second conductivity type provided on a first side of the first semiconductor layer (31) opposite a second side of the first semiconductor layer (31) facing the semiconductor substrate (1), the second semiconductor layer (32) containing a semiconductor material having a band gap wider than that of silicon; a first semiconductor region (5) of the first conductivity type selectively provided in the second semiconductor layer (32); a trench (7) penetrating the first semiconductor region (5) and the second semiconductor layer (32) and reaching the first semiconductor layer (31); a second semiconductor region (21) located under a bottom of the trench (7) and selectively provided in the first semiconductor layer (31) separate from the second semiconductor layer (32); a conductive layer (22) provided in the trench (7); an insulating layer (8a) provided on the conductive layer (22) in the trench (7); an insulating film (8b) provided along a side wall of the trench (7) and in contact with and continuous with the insulating layer (8a); a gate electrode (9) provided on the insulating layer (8a) and the insulating film (8b) in the trench (7); a first electrode (12a) in contact with the second semiconductor layer (32) and the first semiconductor region (5); a second electrode (13) provided on a rear surface of the semiconductor substrate (1); and a Schottky barrier diode formed from a Schottky junction (23) between the conductive layer (22) and the first semiconductor layer (31). [2] A semiconductor device according to claim 1, wherein an interface between the conductive layer (22) and the insulating layer (8a) is positioned closer to the semiconductor substrate (1) than an interface between the second semiconductor layer (32) and the first semiconductor layer (31). [3] A semiconductor device according to claim 1 or 2, wherein a distance (x2) from an interface between the conductive layer (22) and the insulating layer (8a) to an interface between the second semiconductor layer (32) and the first semiconductor layer (31) is in a range of 0.3 μm to 0.6 μm. [4] A semiconductor device according to any one of claims 1 to 3, wherein the trench (7) has a depth in the range of 1.1 μm to 3.2 μm and the conductive layer (22) has a thickness in the range of 0.1 μm to 0.6 μm. [5] A semiconductor device according to any one of claims 1 to 4, further comprising: a third semiconductor region (3) of the first conductivity type provided in the first semiconductor layer (31), the third semiconductor region (3) being in contact with the second semiconductor layer (32) and reaching a deep position closer to the second electrode (13) from the interface between the first semiconductor layer (31) and the second semiconductor layer (32) than the bottom of the trench (7), the third semiconductor region (3) having an impurity concentration higher than an impurity concentration of the first semiconductor layer (31), the Schottky barrier diode is formed from a Schottky junction (23) between the conductive layer (22) and the third semiconductor region (3). [6] A semiconductor device according to any one of claims 1 to 5, wherein the trench (7) is arranged in a stripe arrangement extending in a direction parallel to the front surface of the semiconductor substrate 1.

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