A semiconductor device and a method for forming a semiconductor device

Abstract

A semiconductor device, comprising: a contact metallization layer (120) arranged on a semiconductor substrate (110) and comprising aluminium; an inorganic passivation structure (130) arranged on the semiconductor substrate (110); an organic passivation layer (140), wherein a first part of the organic passivation layer (140) is arranged on the contact metallization layer (120) and a second part of the organic passivation layer (140) is arranged on the inorganic passivation structure (130); and a layer (260, 652), wherein a first part of the layer (260, 652) is in contact with the contact metallization layer (120), wherein a second part of the layer (260, 652) is in contact with the inorganic passivation structure (130), wherein a third part of the layer (260, 652) is arranged in a region laterally between the contact metallization layer (120) and the inorganic passivation structure (130) on the semiconductor substrate (110), wherein the layer (260, 652) is a silicon nitride layer or an electrically conductive layer.

Description

AREA

[0001] Examples refer to passivation concepts for semiconductor devices and, in particular, to a semiconductor device and a method for forming a semiconductor device. BACKGROUND

[0002] Semiconductor devices can experience very high electric fields at the surface of the edge termination region, so passivation with a material exhibiting good breakdown resistance may be necessary. Solutions using organic passivation are prone to moisture accumulation and can cause corrosion. Solutions using inorganic passivation can be susceptible to thermo-mechanical stress. In this context, if the inorganic passivation is in contact with the metallization layer and this assembly is subjected to thermo-mechanical stress, cracking can occur. Documents US 2015 / 0091161 A1 and US 5,284,801 A describe known semiconductor devices.

[0003] Therefore, passivation that takes into account high electric fields, humidity and mechanical stress is important for the breakdown behavior and long-term reliability of semiconductor devices. SUMMARY

[0004] There is a need to provide concepts for the passivation of semiconductor devices that allow improvements in the robustness and / or reliability of the semiconductor devices.

[0005] Such a need can be met by the subject matter of the claims.

[0006] Examples refer to a semiconductor device comprising a contact metallization layer, which is arranged on a semiconductor substrate and includes aluminum, and an inorganic passivation structure, which is arranged on the semiconductor substrate. The semiconductor device further comprises an organic passivation layer and a layer. A first part of the organic passivation layer is arranged on the contact metallization layer, and a second part of the organic passivation layer is arranged on the inorganic passivation structure. A first part of the layer is in contact with the contact metallization layer, and a second part of the layer is in contact with the inorganic passivation structure. A third part of the layer is arranged laterally between the contact metallization layer and the inorganic passivation structure on the semiconductor substrate. BRIEF DESCRIPTION OF THE FIGURES

[0007] The following are some examples of devices and / or methods, described solely by way of example and with reference to the accompanying figures, in which the following applies: Fig. Figure 1 shows a schematic cross-section of part of a semiconductor device; Fig. Figure 2 shows a schematic cross-section of part of a semiconductor device; Fig. Figure 3 shows a flowchart of a process for forming a semiconductor device; Fig. Figure 4 showed a schematic cross-section of a semiconductor device after deposition of a contact metallization layer; Fig. Figure 5 shows a schematic cross-section of the semiconductor device of Fig. 4 after deposition of an inorganic passivation structure; Fig. Figures 6A-F show schematic cross-sections of a portion of a silicon carbide diode device comprising a TiAl3 buffer sublayer; Fig. Figures 7A-C show schematic cross-sections of a portion of a silicon carbide device having an oxide interlayer; Fig. Figures 8A-C show schematic cross-sections of part of a second silicon carbide device having an oxide interlayer; and Fig. Figure 9 shows schematic cross-sections of part of a third silicon carbide device having an oxide interlayer. DETAILED DESCRIPTION

[0008] Several examples will now be described in more detail with reference to the accompanying drawings, which illustrate some of these examples. For the sake of clarity, the thickness of lines, layers, and / or regions in the figures may be exaggerated.

[0009] While further examples of various modifications and alternative forms are possible, some specific examples are shown in the figures and are described in detail below. However, this detailed description does not limit further examples to the specific forms described. Further examples may encompass all modifications, correspondences, and alternatives that fall within the scope of revelation. Equal reference signs throughout the description of the figures refer to identical or similar elements that, upon comparison, may be implemented identically or in a modified form while providing the same or a similar function.

[0010] It is understood that when an element is described as "connected" or "coupled" to another element, the elements may be connected or coupled directly or via one or more intermediate elements. When two elements A and B are combined using "or," this is to be understood as revealing all possible combinations, i.e., only A, only B, and A and B. An alternative formulation for the same combinations is "at least one of A and B." The same applies to combinations of more than two elements.

[0011] The terminology used here to describe certain examples is not intended to be limiting for other examples. Where a singular form, e.g., "a" and "the," "a," "a," is used, and the use of only a single element is neither explicitly nor implicitly defined as mandatory, further examples may also use plural elements to implement the same function. Similarly, where a function is subsequently described as being implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity.It is further understood that the terms “include”, “comprehensive”, “exhibit” and / or “exhibit” when used specify the presence of the indicated features, integers, steps, operations, processes, elements and / or components thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or a group thereof.

[0012] Unless otherwise defined, all terms (including technical and scientific terms) are used here in their usual meaning within the field to which examples belong.

[0013] Fig. Figure 1 shows a block diagram of a cross-section of a semiconductor device 100 according to an exemplary embodiment. The semiconductor device 100 comprises a contact metallization layer 120 arranged on a semiconductor substrate 110, an inorganic passivation structure 130, and an organic passivation layer 140. A (first) part of the organic passivation layer 140 is positioned laterally between the contact metallization layer 120 and the inorganic passivation structure 130, and a (second) part of the organic passivation layer 140 is positioned on top of the inorganic passivation structure 130. The first part of the organic passivation layer is positioned vertically closer to the semiconductor substrate 110 than the second part of the organic passivation layer. Furthermore, a third part of the organic passivation layer 140 is positioned on top of the contact metallization layer 120.

[0014] The layout can be chosen such that a sufficiently large gap can be implemented between the contact metallization layer 120 and the inorganic passivation structure 130. Due to this gap, portions of the organic passivation layer 140 located within this gap are closer to the semiconductor substrate 110 than portions of the organic passivation layer 140 formed on top of the inorganic passivation structure 130. This gap between the contact metallization layer 120 and the inorganic passivation structure 130 can reduce or prevent damage during the fabrication or operation of the semiconductor device.In contrast, if the inorganic passivation layer 130 were placed over or in contact with the contact metallization layer 120, the probability of cracking, for example caused by temperature fluctuations, would be higher. However, if the inorganic passivation structure 130 is chosen such that there is a gap between it and the contact metallization layer 120, then the stress in the layer stack on the semiconductor substrate can be reduced. In this way, the robustness and / or reliability of the semiconductor device can be improved.

[0015] The contact metallization layer 120 and the inorganic passivation structure 130 can be spaced apart such that a lateral gap between the contact metallization layer 120 and the inorganic passivation structure 130 is at least partially filled by the organic passivation layer 140. A lateral distance d1 between the contact metallization layer 120 and the inorganic passivation structure 130 can be greater than (or greater than twice or greater than three times) the vertical thickness t1 of the contact metallization layer 120. Additionally or alternatively, the lateral distance d1 between the contact metallization layer 120 and the inorganic passivation structure 130 can be less than the width w1 of the inorganic passivation structure 130 (or less than 50% or less than 30% of the width).The width of the inorganic passivation structure 130 can be a minimum lateral dimension or a lateral dimension measured in a direction orthogonal to an edge of the semiconductor substrate 110 at the midpoint of the edge. For example, the lateral distance between the inorganic passivation structure and an edge of the semiconductor substrate can be greater than 10 µm (or 20 µm or 50 µm). In this way, the semiconductor substrate 110 can be cut during the fabrication of the semiconductor device without the need to cut through the passivation structure, which can lead to cracking or sticking effects with a saw blade.

[0016] The first part of the organic passivation layer 140, positioned laterally between the contact metallization layer 120 and the inorganic passivation structure 130, can be in contact with the semiconductor substrate 110, or one or more layers can be positioned vertically between the first part and the semiconductor substrate 110. One or more optional layers can be positioned vertically between the first part and the semiconductor substrate 110, which may have a thickness less than the thickness of the inorganic passivation structure 130.

[0017] The organic passivation layer 140 can be formed after the contact metallization layer 120, such that the third part of the organic passivation layer 140 is positioned on top of the contact metallization layer 120. For example, the contact metallization layer 120 is positioned vertically closer to the semiconductor substrate 110 than the third part of the organic passivation layer 140. For example, no part of the organic passivation layer 140 is positioned below the contact metallization layer 120. The organic passivation layer 140 can extend from the second part to the third part, with the first part positioned laterally between the second and third parts of the organic passivation layer 140. The organic passivation layer 140 could be fabricated or produced in a single fabrication step (e.g., by deposition) that is not interrupted by the formation of another layer.For example, the entire organic passivation layer 140 can be formed after the formation of the contact metallization layer 120.

[0018] The thickness of the inorganic passivation structure 130 can be greater than 500 nm (or greater than 750 nm or greater than 1 µm) and / or less than 6 µm (or less than 3 µm or less than 1 µm). The inorganic passivation structure can be a single layer or can have two or more sublayers. For example, the inorganic passivation structure 130 can be or include an oxide layer (e.g., a silicon oxide layer, an undoped silica glass (USG) layer, or a borophosphosilicate glass (BPSG) layer) that can have a thickness greater than 300 nm (or greater than 500 nm or greater than 750 nm) and / or less than 5 µm (or less than 3 µm or less than 1 µm). Alternatively or additionally, the inorganic passivation structure 130 can be a nitride layer (e.g.silicon nitride layer) or comprise, which may have a thickness greater than 400 nm (or greater than 500 nm or greater than 600 nm) and / or less than 800 nm (or less than 700 nm or less than 600 nm).

[0019] By selecting a suitable thickness and / or material for the inorganic passivation structure 130, the semiconductor device can be designed such that an electric field at the surface of the inorganic passivation structure 130 (e.g., interface between inorganic passivation structure and organic passivation layer) can be greater than 500 kV / cm (or greater than 600 kV / cm or greater than 800 kV / cm) in a blocking state of an electrical structure (e.g., diode structure or transistor structure) formed on the semiconductor substrate 110.

[0020] The thickness of the organic passivation layer 140 can be selected such that thermal stress can be compensated or absorbed without cracking, and / or electric fields at a surface of the organic passivation layer 140 can be below a threshold. The thickness and / or material of the organic passivation structure 140 can be designed such that an electric field at a surface of the organic passivation layer 140 (e.g., at an interface between the organic passivation layer and a molding compound) in a blocking state of an electrical structure formed on the semiconductor substrate 110 can be less than 500 kV / cm (or less than 400 kV / cm or less than 300 kV / cm). The organic passivation layer 140 can be a single layer or can have two or more sublayers. For example, the organic passivation layer 140 can be a polyimide layer.The organic passivation layer 140 can have a thickness of more than 1µm (or more than 3µm or more than 5µm) and / or less than 50µm (or less than 30µm or less than 15µm).

[0021] The contact metallization layer 120 can be a single layer or it can have two or more sublayers. The contact metallization layer 120 can contain a metal layer. For example, the contact metallization layer 120 can contain copper (Cu) or aluminum (Al), or it can contain an alloy of aluminum and copper (e.g., AlCu or AlCuSi). The contact metallization layer 120 can have a thickness of more than 2 µm (or more than 3 µm or more than 4 µm) and / or less than 20 µm (or less than 10 µm or less than 6 µm).

[0022] Optionally, the semiconductor device 100 can further comprise a barrier layer to prevent atoms from the contact metallization layer 120 from diffusing into the semiconductor substrate 110. The barrier layer can have a first part that is arranged vertically between the contact metallization layer 120 and the semiconductor substrate 110. Furthermore, the first part of the barrier layer can be in contact with both the contact metallization layer 120 and the semiconductor substrate 110. The barrier layer can also have a second part that is arranged between the inorganic passivation structure 130 and the semiconductor substrate 110. For example, the second part of the barrier layer can be in contact with both the inorganic passivation structure 130 and the semiconductor substrate 110. The barrier layer can extend at least from the first part of the barrier layer to the second part of the barrier layer.In this way, the barrier layer can be used as an etch stop layer during the structuring of the inorganic passivation structure 130. The barrier layer can be or comprise a titanium (Ti) layer, a titanium nitride (TiN) layer, and / or a tantalum (Ta) layer. The barrier layer can have a thickness greater than 100 nm (or greater than 150 nm or greater than 200 nm) and less than 300 nm (or less than 250 nm or less than 200 nm).

[0023] The barrier layer can comprise a first sublayer (e.g., barrier sublayer), also known as a Schottky barrier, and a second sublayer (e.g., buffer sublayer), e.g., an etchant barrier and / or buffer. The first sublayer can be in contact with the semiconductor substrate and can prevent atoms (e.g., metal atoms such as aluminum or copper) from diffusing into the semiconductor substrate from layers above the first sublayer. The second sublayer can be in contact with the first sublayer and the contact metallization layer 120. The second sublayer can prevent particles used in the etching processes (e.g., those described in relation to the passivation structure) from penetrating the first sublayer by absorbing and / or trapping the etching particles. The first sublayer can be titanium (e.g., a titanium layer), and the second sublayer can be a titanium-aluminum alloy (e.g., a TiAl3 layer) or titanium nitride (e.g., a titanium-aluminum alloy).B. a TiN layer).

[0024] Some examples relating to a diode structure are given in relation to the Fig. 2-6 discussed in more detail.

[0025] Some examples refer to a transistor structure (e.g., insulated gate field effect transistor (IGFET), metal-oxide-semiconductor field effect transistor (MOSFET), or insulated gate bipolar transistor (IGBT), as in Fig. Figures 7a-8 show this. In some examples where the semiconductor device is a MOSFET (or IGFET or IGBT), the MOSFET may further include an oxide interlayer (e.g., a silicon dioxide layer). For example, the oxide interlayer may be placed directly on the semiconductor substrate (in contact with the semiconductor substrate). The oxide interlayer may have a first sublayer, which is part of a gate oxide layer, and a second sublayer, which is an interlayer dielectric layer formed on top of the gate oxide layer.

[0026] For example, a first lateral part of the oxide interlayer can be arranged vertically between the contact metallization layer and the semiconductor substrate, and a second lateral part of the oxide interlayer can be arranged vertically between the inorganic passivation structure and the semiconductor substrate. The oxide interlayer can extend at least from the first part to the second part.

[0027] For example, the inorganic passivation structure 130 can have a nitride layer (e.g., a silicon nitride layer). The first part of the organic passivation layer 140 (e.g., the part positioned laterally between the inorganic passivation structure 130 and the contact metallization layer 120) can be positioned vertically closer to the oxide intermediate layer 731 than the second part of the organic passivation layer 140 (e.g., the part positioned on top of the inorganic passivation structure 130). In this example, the oxide intermediate layer can be used as an etch stop layer to structure the nitride layer. An example is given with regard to Fig. 7 discussed in more detail.

[0028] Alternatively, the first part of the barrier layer may be arranged vertically between the oxide interlayer and the contact metallization layer, and the second part of the barrier layer may be arranged vertically between the inorganic passivation structure and the oxide interlayer. In this example, the inorganic passivation structure 130 may comprise a silicon oxide layer, such as, but not limited to, an undoped silicate glass layer, boron phosphosilicate glass, phosphosilicate glass, and boron silicate glass, and / or a silicon nitride layer. The silicon oxide layer may be arranged vertically between the silicon nitride layer and the oxide interlayer. The barrier layer may be used as an etch stop layer to structure the silicon oxide layer and a silicon nitride layer. An example is given with regard to Fig. 8 discussed in more detail.

[0029] Optionally, the semiconductor device 100 can also have an adhesion layer to, for example, increase the adhesion of the organic passivation layer 140 on top of the inorganic passivation structure 130 and / or the contact metallization layer 120. The adhesion layer can have a first part that is arranged between the contact metallization layer 120 and the organic passivation layer 140. For example, the first part of the adhesion layer can be in contact with the contact metallization layer 120 and the organic passivation layer 140. The adhesion layer can have a second part that is arranged between the inorganic passivation structure 130 and the organic passivation layer 140. For example, the second part of the adhesion layer can be in contact with the inorganic passivation structure 130 and the organic passivation layer 140.The adhesion layer can extend at least from the first part to the second part, so that it can also improve the adhesion of the organic passivation layer 140 in the space between the contact metallization layer 120 and the inorganic passivation layer 130. The adhesion layer can have a thickness greater than 10 nm (or greater than 20 nm or greater than 30 nm) and less than 100 nm (or less than 60 nm or less than 40 nm). The adhesion layer can, for example, be a silicon nitride layer.

[0030] Optionally, a bonding wire or solder material (e.g., solder ball, solder bump, or already soldered material) can be in contact with the contact metallization layer 120. Optionally, the semiconductor device 100 can also have a molding compound structure that is in contact with the organic passivation layer 140. For example, after forming the organic passivation structure and bonding a bonding wire to the contact metallization layer 120 or soldering a solder structure to the contact metallization layer 120, a molding compound is formed on the semiconductor substrate of the semiconductor device 100 to connect the semiconductor substrate to a conductor frame or a package carrier of the semiconductor device 100. The molding compound can be an epoxy-based molding compound or a soft molding compound.

[0031] For example, one or more electrical structures can be implemented on the semiconductor substrate 100. An electrical structure can be a diode structure (e.g., a vertical diode structure) or a transistor structure (e.g., a vertical transistor structure) such as a MOSFET or an IGBT. For example, the electrical structure can be a vertical diode structure or a vertical transistor structure with a lightly doped drift region.

[0032] For example, the semiconductor device 100 can have a drift region of an electrical structure comprising dopants of a first conductivity type. The semiconductor device 100 can have an edge termination region comprising dopants of a second conductivity type. The edge termination region can extend laterally from a contact region to an edge of the semiconductor substrate 110, at least partially beneath the inorganic passivation structure 130. The edge termination region can be ohmically connected to the contact metallization layer 120 via the contact region. Two structures can be ohmically connected if an ohmic path or ohmic connection exists between the two structures. The contact region can be a highly doped section of the edge termination region or a doped region of an electrical structure (e.g.,anode or cathode region of a diode structure or source or body region of a transistor structure) to allow an ohmic contact to the contact metallization layer 120 or a wiring structure connected to the contact metallization layer 120.

[0033] The edge termination region can be selected such that the lateral distance between the inorganic passivation structure 130 and the edge of the semiconductor substrate 110 is smaller than (e.g., more than 1 µm, more than 5 µm, or more than 10 µm smaller than) the lateral distance between the edge termination doping region and the edge of the semiconductor substrate 110. Thus, the edge termination region can be completely covered by the inorganic passivation structure 130 or at least covered in the portion located closest to the edge of the semiconductor substrate 110. In this way, corrosion of the edge termination region by the covering of the inorganic passivation structure 130 can be prevented.

[0034] The edge termination region can be a scrapable doped region having an average doping concentration, such that the lightly p-doped edge termination region is scrapable when a maximum blocking voltage is applied to the semiconductor device 100 during normal operation.

[0035] The drift region exhibits dopants of the first conductivity type, which can be p-type doping (e.g., caused by the introduction of aluminum or boron ions) or n-type doping (e.g., caused by the introduction of nitrogen, phosphorus, or arsenic ions). Consequently, the second conductivity type indicates the opposite type, either n-type or p-type doping. In other words, the first conductivity type can indicate n-type doping, and the second conductivity type can indicate p-type doping, or vice versa.

[0036] A doped anode region or a doped cathode region of a diode structure and / or a doped source region and / or a doped body region of a transistor structure and / or the edge termination region of the semiconductor device 100 can be positioned on a front face or front surface of the semiconductor substrate 100. A doped drain region or a doped emitter or collector region of the transistor structure can be positioned on a back face or rear surface of the semiconductor substrate 100.

[0037] A front face or front surface of the semiconductor substrate 110 can be a semiconductor surface of the semiconductor substrate 110 facing towards metal layers, insulating layers, or passivation layers on top of the semiconductor surface. Compared to a substantially vertical edge (e.g., resulting from separating the semiconductor substrate from others) of the semiconductor substrate 100, the front face of the semiconductor substrate 110 can be a substantially horizontal surface extending laterally. The front face of the semiconductor substrate 110 can be a substantially flat plane (e.g., neglecting any unevenness of the semiconductor structure due to the fabrication process or grooves). The front face of the semiconductor substrate 110 can be a surface of the semiconductor substrate 110 that is used to form more complex structures (e.g.,Gates, source regions and / or body regions of transistors, wiring layer stacks) is used as on a back side of the semiconductor substrate 110.

[0038] A lateral direction or extent can be oriented essentially parallel to the front surface, and a vertical direction or extent can be oriented essentially orthogonal to the front surface. For example, the vertical direction and any vertical dimension or thickness of layers can be measured orthogonal to the front surface of the semiconductor substrate, and a lateral direction and lateral dimensions can be measured parallel to the front surface of the semiconductor substrate.

[0039] For example, the semiconductor substrate 110 can be a wide-bandgap semiconductor substrate having a bandgap larger than that of silicon (1.1 eV). For example, the semiconductor substrate 110 can be a silicon carbide (SiC)-based semiconductor substrate, a gallium arsenide (GaAs)-based semiconductor substrate, or a gallium nitride (GaN)-based semiconductor substrate. The semiconductor substrate 110 can be a semiconductor wafer or a semiconductor die. Although a silicon carbide substrate is discussed with reference to the accompanying figures and embodiments, it should be noted that such embodiments are not limited to a SiC substrate and that other substrates, such as a GaAs- or GaN-based substrate, are also possible.

[0040] A transistor structure (e.g., IGFET, MOSFET, or IGBT) of the semiconductor device 100 can be a vertical transistor structure that conducts current between a front surface of the semiconductor substrate and a back surface of the semiconductor substrate. For example, the transistor arrangement of the semiconductor device can have a plurality of doped source regions connected by a source wiring structure, a plurality of gate electrodes or a gate electrode grid connected by a gate wiring structure, and a back-drain metallization.

[0041] The transistor structure can be a transistor cell of a plurality of transistor cells in a transistor array. A transistor cell can, for example, comprise one or more source regions (e.g., distributed or positioned along a gate), at least one body region, and a gate (e.g., a trench gate positioned within a gate trench extending into the semiconductor substrate). Furthermore, the transistor cells of the plurality of transistor cells can share a common (mutual) drift region and / or a common drain region (e.g., the transistor cells are MOSFET cells) or a common collector region (e.g., the transistor cells are IGBT cells).

[0042] The semiconductor substrate can comprise a cell region (or active region) laterally surrounded by an edge termination region. The cell region can be a region of the semiconductor substrate used to conduct more than 90% of the current through the semiconductor substrate in an on-state or conducting state of the transistor array (or the entire semiconductor device). For example, the cell region can be an area containing all the source regions of the transistor array or all the transistor structures of the semiconductor device. The edge termination region can be positioned between an edge of the semiconductor substrate and the cell region to support, block, reduce, or dissipate a maximum voltage applied laterally between the front surface and a rear surface of the semiconductor substrate within the cell region, directed toward the edge of the semiconductor substrate.

[0043] The semiconductor device 100 can be a power semiconductor device. The semiconductor device may furthermore have an electrical structure formed on the semiconductor substrate 110 (e.g., a transistor structure and / or a diode structure) exhibiting a breakdown voltage or reverse voltage of more than 10 V (e.g., a breakdown voltage of 10 V, 20 V, or 50 V), more than 100 V (e.g., a breakdown voltage of 200 V, 300 V, 400 V, or 500 V), more than 500 V (e.g., a breakdown voltage of 600 V, 700 V, 800 V, or 1000 V), or more than 1000 V (e.g., a breakdown voltage of 1200 V, 1500 V, 1700 V, 2000 V, 3300 V, or 6500 V), for example.

[0044] The organic passivation layer 140 may completely cover the inorganic passivation layer 130 as well as at least parts of the contact metallization layer.

[0045] More details and aspects are mentioned in connection with the examples described above or below. The semiconductor device may have one or more additional optional features that relate to one or more aspects of the proposed concept or to one or more of those described below (e.g., Fig. 2-9) correspond to the examples described.

[0046] Fig. Figure 2 shows a schematic cross-section of a semiconductor device 200 according to an exemplary embodiment. The implementation of the semiconductor device 200 can be similar to the implementation described in connection with Fig. The organic passivation layer 140 (e.g., polyimide layer) is positioned closer than 300 nm to the semiconductor substrate in the space between the contact metallization layer 120 (e.g., AlCu alloy layer) and the inorganic passivation structure 130. A barrier layer 250 (e.g., Ti layer) and a silicon nitride adhesion layer 260 are positioned vertically between the organic passivation layer 140 and the semiconductor substrate. The inorganic passivation structure 130 comprises two layers: a silicon oxide layer 231 and a silicon nitride layer 232. Although the silicon oxide layer 231 is shown in the image of Fig. 2 is represented by a USG layer; it should be noted that the silicon oxide layer 231 may alternatively have other silicon oxide layers, such as BPSG, BSG and / or PSG. The organic passivation layer 140 extends laterally from a point between the edge 202 of the semiconductor device 200 and an edge of the inorganic passivation structure 130 to the contact metallization layer 120.

[0047] The barrier layer 250 has a first part positioned between the semiconductor substrate and the contact metallization layer 120. The barrier layer 250 has a second part positioned between the semiconductor substrate and the silicon oxide layer 231. The barrier layer 250 extends continuously from the first part to the second part. The barrier layer 250 has a third part positioned between the adhesion layer 260 and the semiconductor substrate in the space between the contact metallization layer 120 and the inorganic passivation structure 130.

[0048] The adhesion layer 260 has a first part positioned between the organic passivation layer 140 and the contact metallization layer 120. The adhesion layer 260 has a second part positioned between the organic passivation layer 140 and the silicon nitride layer 232. The adhesion layer 260 extends continuously from the first part to the second part. The adhesion layer 260 has a third part positioned between the organic passivation layer 140 and the barrier layer 250 in the space between the contact metallization layer 120 and the inorganic passivation structure 130.

[0049] In this example, the semiconductor device is a SiC diode. The semiconductor substrate comprises a drift layer or doped drift region 211, a doped field-stop region or buffer region 212, and a doped substrate region 213, which forms an n-doped cathode region of the SiC diode. The buffer region has an average doping concentration higher than the average doping concentration of the drift region, and the substrate region has an average doping concentration higher than the average doping concentration of the buffer region. Furthermore, the semiconductor substrate includes highly p-doped anode regions 214, which are positioned on the front surface 201 of the semiconductor substrate.The highly p-doped anode regions 214 can be non-removable doped regions that have an average doping concentration, such that the anode regions 214 are non-removable when a maximum blocking voltage is applied to the semiconductor device 200 during normal operation of the semiconductor device 200.

[0050] Furthermore, the semiconductor substrate comprises a lightly p-doped edge termination region 215, which extends at least partially beneath the inorganic passivation structure 130. The lateral distance d2 from the inorganic passivation structure 130 to the edge 202 is smaller than the lateral distance d3 from the edge termination region 215 to the edge 202 of the semiconductor device 200. The lightly p-doped edge termination region 215 can be a scrapable region with an average doping concentration, such that the lightly p-doped edge termination region 215 is scrapable when a maximum blocking voltage is applied to the semiconductor device 200 during normal operation. The lightly p-doped edge termination region 215 is connected to the contact metallization layer 120 via a highly p-doped anode region 214.

[0051] Further details and aspects of the semiconductor device 200 are mentioned in connection with the proposed concept or one or more of the examples described above. The semiconductor device 200 may have one or more additional optional features that precede one or more aspects of the proposed concept or one or more (e.g., Fig. 1) or subsequently (e.g. Fig. 3-9) correspond to the examples described.

[0052] Fig. Figure 3 shows a flowchart of a process 300 for forming a semiconductor device according to an exemplary embodiment. The process 300 comprises forming 310 a contact metallization layer on a semiconductor substrate, forming 320 an inorganic passivation structure on the semiconductor substrate, and forming 330 an organic passivation layer. A first part of the organic passivation layer, positioned laterally between the contact metallization layer and the inorganic passivation structure, is positioned vertically closer to the semiconductor substrate than a second part of the organic passivation layer, which is positioned on top of the inorganic passivation structure. Furthermore, a third part of the organic passivation layer is positioned on top of the contact metallization layer.

[0053] The layout can be designed to implement a sufficiently large distance between the contact metallization layer and the inorganic passivation structure. This distance reduces or prevents damage during the manufacturing or operation of the semiconductor device. In this way, the robustness and / or reliability of the semiconductor device can be improved.

[0054] Further details and aspects of Procedure 300 are mentioned in connection with the proposed concept or one or more of the examples described above. Procedure 300 may have one or more additional optional features that relate to one or more aspects of the proposed concept or to one or more of the examples described above (e.g., Fig. 1-2) or below (e.g. Fig. 4-9) correspond to the examples described.

[0055] Fig. 4 and Fig. Figure 5 shows schematic cross-sections of a SiC diode at different stages of fabrication. The SiC diode, which is used in Fig. 4 and Fig. As shown in section 5, the procedure can be similar to the one used in connection with Fig. As described in section 3, they will be manufactured.

[0056] Fig. Figure 4 shows a schematic cross-section of the SiC diode after the formation of doped regions (e.g., buffer region 212, drift region 211, anode regions 214, and doped edge termination region 215) of a diode structure in a semiconductor substrate of a semiconductor device to be formed. Furthermore, a titanium barrier layer 250 is formed and structured in contact with the semiconductor substrate. Fig. Figure 4 shows the SiC diode after deposition and structuring of the front face metallization (e.g. AlCu layer).

[0057] Fig. Figure 5 shows a schematic cross-section of the SiC diode after deposition and structuring of inorganic passivation layers (e.g., a silicon oxide layer and a silicon nitride layer). The Ti barrier layer 250 is used during structuring of the inorganic passivation layers as an etch stop between the front face metallization and an edge of the structured inorganic passivation layers.

[0058] For example, Fig. 2. Represent the SiC diode after forming (e.g., deposition and structuring) the organic passivation and opening (structuring) the optional silicon nitride adhesion layer 260.

[0059] After the deposition and structuring of the front-side metal (e.g. Fig. 4) The inorganic layer stack of the passivation is deposited. For example, the inorganic layer stack can consist of a silicon oxide / silicon nitride stack whose silicon oxide thickness is measured such that the charges at the silicon oxide / silicon nitride interface do not necessarily influence the blocking behavior of the component (e.g., the charge ratios and field distributions in the edge termination). A BPSG / silicon nitride, silicon oxide / BPSG / silicon nitride, or a similar layer structure is also conceivable. After fabrication of a resist mask, the inorganic passivation structure is patterned in a subsequent process using a plasma etching process, and the resist mask is removed (e.g., by etching). Fig. 5) Optionally, a thin adhesion layer, e.g., a thin silicon nitride layer, can be deposited, and in a subsequent process, a photosensitive organic passivation can be deposited, patterned, and then cured using a lithographic step. This organic passivation layer then serves as an etching mask for patterning the adhesion layer (optional) to expose the front-side metal in the bond termination area. One possible result is shown in Fig. 2 shown.

[0060] As in connection with Fig. 2, Fig. 4 and Fig. As described in section 5, the passivation can be created after the AlCu / Ti process blocks, whereby the layout can be chosen to ensure a sufficiently large distance between the AlCu edge and the passivation. By reducing the thickness of the inorganic passivation structure, stress-induced cracking can be prevented. However, to ensure that the electric field strength remains compatible with the molding compound, an additional organic passivation is deposited, which also absorbs some of the mechanical stress.

[0061] For example, the magnitude of the electric field strength at the interface between the inorganic and organic passivation, resulting from the thickness of the inorganic passivation, may be >500 kV / cm. In this case, the organic passivation can be dimensioned such that the magnitude of the electric field strength is significantly reduced at its surface, which represents the interface with the molding compound, in order to prevent deterioration of the molding compound and / or flashovers within it. Furthermore, the thickness of the organic passivation can be chosen so that the forces generated by thermal expansion do not lead to cracking within itself or in subsequent layers.

[0062] In this context, a sufficient gap can be implemented between the edge of the front-side metallization (anode, for example, Al-based) and the inorganic passivation. If, for example, the inorganic hard passivation is applied over the metal and this arrangement is subjected to thermomechanical stress, cracks can occur in the passivation due to the plastic deformation of the Al(SiCu).

[0063] If the inorganic hard passivation is chosen so that only the edge is covered, the area covered by the inorganic hard passivation is reduced, and thus a reduction in stress in the SiC oxide nitride layer structure can be achieved.

[0064] To improve the adhesion of the organic passivation to the front-end metal in this case, a thin layer of adhesive can be provided that partially covers the front-end metal and partially or completely covers the inorganic passivation.

[0065] More details and aspects of the procedure, which is in Fig. 4 and Fig. The features shown in Figure 5 are mentioned in connection with the proposed concept or one or more examples described above or below. The method may have one or more additional optional features that relate to one or more aspects of the proposed concept or one or more of the examples described above (e.g., Fig. 1-3) or below (e.g. Fig. Examples described in 6-9.

[0066] For example, the inorganic passivation structure is deposited on a surface with a high topology if the contact metallization layer is formed prior to the inorganic passivation structure. On the other hand, the barrier layer, a sublayer of the barrier layer, or an ohmic contact layer that enables an ohmic or Schottky contact between the contact metallization layer and the semiconductor substrate can be damaged during the structuring of the inorganic passivation structure if the inorganic passivation structure is formed prior to the contact metallization layer.

[0067] For example, the Schottky metal (also called Schottky metallization, Schottky barrier, or Schottky layer) of a SiC Schottky diode can deteriorate if there are any changes between the production of the Schottky metallization (in the example of Fig. 6, Ti) and the metallization of the contact surfaces (in the example of Fig. 6, AlCu) a dry chemical structuring of the dielectric passivation is to take place. The Schottky metallization can be exposed and subjected to the effects of dry chemical etching. The unprotected Ti can degrade, and consequently the Schottky interface can be compromised. Therefore, there may be a need to protect the Schottky metallization during dry chemical structuring.

[0068] In some examples, an edge termination for semiconductor devices with high electric field strengths can be introduced at the edge, which significantly improves robustness against moisture by supplementing a purely organic passivation layer with dielectric passivation. The dielectric passivation can serve to protect the edge termination (e.g., of the SiC diode) from moisture. In this form of passivation, the inorganic passivation can be structured via the imide, meaning that the porous inorganic oxide / nitride passivation is located above the AlCu metallization (see Fig. 2, Fig. 4 and Fig. 5). This may be a possible solution for packages that include soft molding compound, where there may be no mechanical stress between the semiconductor device and the molding compound material.

[0069] For other packages (molded packages or plastic packages), where mechanical stresses occur between the molding compound, passivation, and aluminum-based front-end material, particularly due to temperature increases, this approach may not work. The stress resulting from thermal changes causes mechanical stress cracks in the inorganic passivation structure. Moisture-resistant components are desirable because a so-called "hard molding compound" or "molding compound" may offer insufficient protection against moisture. For diodes that only have imide passivation in conjunction with a homogeneously doped junction termination edge (JTE), oxidation of the external JTE region can be detected as a consequence of high humidity. The remaining blocking capacitance of the device may be sufficient for some applications, but not all (e.g., automotive applications).

[0070] In some examples, inorganic passivation for plastic packages can be achieved after the front-side metallization via an additional mask (e.g., the Ti-Schottky and AlCu contact surfaces, see [reference]). Fig. 2, Fig. 4 and Fig. 5) be structured. This spatially separates the passivation from the AlCu edge, preventing the formation of cracks in the package due to thermal stresses. In this case, the Ti Schottky metal can be protected from the effects of dry chemical etching by the AlCu metallization. However, in this case, the passivation is deposited over the AlCu edge and should also be etched in this area. This is possible up to an AlCu thickness of 5 micrometers. The thicker the front-side metallization, the more critical this becomes, as the resist must extend over the edge; as the AlCu thickness increases, so does the resist thickness. To ensure the i 2To improve the T-performance (a measure of surge current withstand capability) of the diode or the short-circuit performance of the MOSFET, increasing the metallization thickness can provide a larger heat sink. However, the thicker the AlCu metallization becomes, the more difficult it can be to achieve dielectric passivation through this step.

[0071] Tall topologies can be avoided by creating dielectric passivation between the Schottky metallization and the terminal surface metallization. An example of a Schottky SiC diode is shown in Fig. Figures 6A-6F show that this may not be achieved simply by inserting the passivation layer. The Ti-SiC Schottky barrier can be so compromised by the dry chemical etching process that leakage currents can be significantly increased.

[0072] In some approaches, a silicon nitride / silicon oxide (SiNx / SiOx) passivation can be used in the boundary region. In these cases, the passivation can be formed either before the deposition of the Ti-Al(Cu) metallization or between the Ti and AlCu process blocks. The passivation may be in contact with the metallization, which can lead to adhesion problems or, in the case of thermal stress, to cracking in the passivation.

[0073] Schottky contact degradation can be improved by providing a buffer layer over the Ti layer that can absorb the effects of any process steps between Schottky and terminal metallization (e.g., dry etching processes). A TiAl3 layer can serve this purpose for several reasons: 1) For example, in production diodes, Ti can be used as a Schottky metal, and Al can be deposited in situ using a suitable tool. Thus, the SiC-Ti interface can be identical to that of the production parts. 2) In an annealing step, TiAl3 formation can be very precisely controlled, resulting in strong adhesion between the Ti and TiAl3 layers with a smooth, uninterrupted transition. 3) The TiAl3 acts as an etch stop for AlCu etching. This may result in the formation of deposits below the passivation layer (see Fig. 6E) No undercuts. A sufficient distance between the AlCu and the passivation can be maintained (e.g., 3-5 micrometers).

[0074] To ensure compatibility between the electric field strength and the molding compound material, an additional organic passivation layer can be used. This layer encapsulates the entire inorganic (silicon oxide-silicon nitride) passivation and also absorbs a portion of the mechanical stress. Therefore, the electric field strength at the interface between the inorganic and organic passivations can exceed 500 kV / cm due to the thickness of the inorganic passivation. The organic passivation layer can be dimensioned such that the electric field strength at its surface, which forms the interface with the molding compound material, is reduced to such an extent that deterioration of the molding compound material and / or arcing within it can be prevented. The thickness of the organic passivation layer can range from 5 micrometers (e.g., for 650 V devices) to 20 micrometers (e.g., for 2 kV devices).

[0075] For example, a TiA13 layer can be used to act as both a buffer layer and an etch stop layer. The TiAl3 can be produced from a Ti-Al layer sequence via a tempering step. The proportion of these layers can be chosen such that a Ti layer, forming the Schottky barrier, extends to the semiconductor body, and a TiAl3 layer is formed above the Ti layer. The TiAl3 layer can serve as a buffer layer for material remaining from the dry chemical etching (e.g., fluorine). This does not necessarily apply to impurities that settle on top of the TiAl3 (e.g., polymers). The Ti-Schottky metallization can thus be protected from being affected. The TiA13 layer can also serve as an etch stop layer during the wet chemical structuring of the AlCu metallization. This prevents under-etching of the dielectric passivation.

[0076] Some examples relate to the implementation of a TiA13 buffer layer to protect the Ti Schottky layer of a SiC diode for subsequent dry chemical etching processes during the fabrication of moisture-resistant and thermally robust SiC devices.

[0077] Fig. Figures 6A-6F show schematic cross-sections of a portion of a SiC diode that includes a TiAl3 barrier sublayer. For example, the implementation of the SiC diode may be similar to semiconductor devices used in conjunction with Fig. 1 and / or 2 are described, for example.

[0078] Fig. Figure 6A shows a schematic cross-section of a portion of a SiC diode after the deposition of titanium and aluminum metallization. For example, a first barrier sublayer 651 is deposited over the semiconductor substrate 110, and an intermediate barrier layer 653 is deposited over the first sublayer 651. The first sublayer 651 is a Ti layer, and the intermediate layer 653 is an Al layer. The first barrier sublayer 651 and the intermediate layer 653 can be deposited in a Ti / Al thickness ratio chosen such that, after annealing (see Figure 6A), the thickness of the Ti / Al sublayer is approximately 100%. Fig. 6C) the remaining Ti and the resulting TiA13 layers are sufficiently thick to prevent fractures due to stress. For example, a 2:1 (or 1.5:1 or 3:1) ratio of Tizu-Al can be deposited (e.g., a 180nm Ti layer and a 90nm Al layer).

[0079] Fig. Figure 6B shows the first sublayer 651 and the intermediate layer 653 after the two layers have been structured.

[0080] Fig. Figure 6C shows the SiC diode after annealing and formation of a TiAl13 layer. By appropriately adjusting the time, temperature, and / or pressure, the Ti and Al layers can be annealed, causing the intermediate layer 653 to react with the first barrier sublayer 651 and be converted from Al to a second barrier sublayer 652, which has a TiAl alloy layer (e.g., TiAl3 layer). Assuming an initial 180 nm Ti and 90 nm Al layer, this can result, after annealing, in an approximately 120 nm TiAl3 layer acting as a buffer layer to absorb inclusions from dry etching processes, and a 150 nm Ti layer serving as the Schottky metal / interface, forming a productive diode. For example, rapid thermal processing can be used for TiAl3 formation.

[0081] Fig. Figure 6D shows the SiC diode after the deposition and structuring of a silicon nitride-silicon oxide passivation, which forms the inorganic passivation structure. The inorganic passivation structure 130 comprises a silicon oxide layer 231 with a thickness of at least 500 nm (or at least 800 nm or at least 1000 nm) and a silicon nitride layer 232 with a thickness of at least 200 nm (or at least 300 nm or at least 400 nm). To structure the inorganic passivation structure, a photomask layer can be formed and lithography can be performed. Then, the inorganic passivation structure can be etched by a dry etching process. Afterward, the resist and / or polymer can be removed.

[0082] The inorganic passivation structure can be deposited and structured over the first sublayer 651 without degrading the Schottky interface of the first sublayer 651, since the second sublayer 652 protects the first sublayer 651 from the dry etching process. In this way, it may be possible to form the inorganic passivation structure before the metallization layer is formed.

[0083] Fig. Figure 6E shows the SiC diode after deposition and structuring of an AlCu terminal face metallization (e.g., contact metallization layer 120). The AlCu front face metallization can be deposited, and an etching mask can be formed by lithography. The contact metallization layer 120 can be structured by wet chemical etching, which may remove the AlCu layer but not the TiAl3 layer. Thus, under-etching of the inorganic passivation structure, for example, the silicon oxide layer 231, may not occur. As in other examples discussed herein, a gap d1 is maintained between the AlCu layer and the passivation to prevent passivation cracking during thermomechanical stress.

[0084] Fig. Figure 6F shows the SiC diode after completion of the imide passivation (implementation of an organic passivation layer) and etching of the adhesion layer passivation. An adhesion layer 260 (e.g., with a thickness of 40 nm) is deposited after forming the contact metallization layer 120, and an organic passivation layer 140 (e.g., an imide layer with a thickness of 5 µm) is deposited on the adhesion layer 260. Then, the organic passivation layer 140 and the adhesion layer 260 are patterned, and the surface is cleaned.

[0085] More details and aspects are mentioned in connection with the proposed concept or one or more examples described above or below. The procedure may have one or more additional optional features that relate to one or more aspects of the proposed concept or one or more above (e.g., Fig. 1-5) or below (e.g. Fig. The examples described in 7-9 correspond to those in the following.

[0086] Some examples relate to a semiconductor device that includes a barrier layer comprising a first sublayer and a second sublayer. The first sublayer can be a TiAl alloy layer, and the second sublayer can be a Ti layer. Furthermore, the semiconductor device includes a contact metallization layer comprising aluminum (e.g., AlCu, AlSiCu, or AlSi). At least a portion of the barrier layer can be positioned between the contact metallization layer and a semiconductor substrate of the semiconductor device. Furthermore, at least a portion of the first sublayer of the barrier layer is in contact with the second sublayer and in contact with the contact metallization layer.

[0087] More details and aspects are mentioned in connection with the proposed concept or one or more examples described above or below.

[0088] Some examples relate to a method for forming a semiconductor device that includes forming a barrier layer comprising a first sublayer and a second sublayer. The first sublayer can be a titanium layer, and the second sublayer can be a TiAl alloy layer. Furthermore, the method includes forming a contact metallization layer comprising aluminum (e.g., AlCu, AlSiCu, or AlSi). At least a portion of the barrier layer can be positioned between the contact metallization layer and a semiconductor substrate of the semiconductor device. Furthermore, at least a portion of the second sublayer of the barrier layer is in contact with both the first sublayer and the contact metallization layer.

[0089] For example, an inorganic passivation structure can be formed in front of the contact metallization layer. This prevents the deposition of the inorganic passivation structure on a surface with a high topology due to the contact metallization layer.

[0090] The TiAl alloy layer can be a TiA13 layer. The TiAl3 layer can be formed with a thickness of at least 80 nm (or at least 100 nm) and / or at most 400 nm (or at most 300 nm or at most 200 nm). The TiAl3 layer can be formed at a temperature of at least 300°C (or at least 350°C, e.g., 400°C), which is applied for at least 1 h (or at least 5 h) and / or at most 20 h (or at most 15 h).

[0091] More details and aspects are mentioned in connection with the proposed concept or one or more examples described above or below.

[0092] High humidity can cause edge degradation problems in SiC MOSFETs. In some cases, it may be necessary to protect the semiconductor body from moisture.

[0093] Some approaches may employ SiNx / SiOx passivation in the edge region. In these approaches, the passivation can be implemented either before the deposition of the Ti-Al(Cu) metallization or between Ti and AlCu process blocks. The passivation may be in contact with the metallization, which can lead to adhesion problems or, in the case of thermomechanical stress, cracking in the passivation. In some approaches, the processing and consequently the cross-section of SiC diodes may differ from that of a SiC MOSFET. Furthermore, these approaches may include a homogeneously doped edge termination instead of a p-in-p termination, which reduces the field strength in the edge.

[0094] The problem of moisture-permeable edge passivation for SiC MOSFETs can be solved by fabricating the passivation after the AlCu / Ti-Ti-TiN process blocks. The layout can be chosen to create a sufficiently large distance between the AlCu edge and the passivation, while the MOSFET's edge termination can be completely covered by the dielectric passivation. Compared to a diode, the processing and thus the cross-section can differ, as the edge region can be covered by a gate oxide (GOX) and / or an interlayer dielectric layer (ILD). Therefore, it may no longer be necessary to deposit an oxide / nitride passivation (as in the case of diodes). Instead, the ILD+GOX can serve as the silicon oxide layer, and only a nitride layer can be used.Regarding the function of the layers: The silicon nitride layer can serve as the actual moisture barrier, while the silicon oxide layer can act as an adhesion layer to SiC. The thickness of these layers can be selected to minimize the impact of changes at the silicon oxide-silicon nitride interface on the landing leveling at the edge. Since the inorganic silicon oxide-silicon nitride passivation layers may not be drawn over the AlCu metallization, and MOSFETs can be embedded in soft molding compound modules, thicknesses can be reduced accordingly, and an oxide thickness of at least 300 nm (or 400 nm or 500 nm) and at most 1000 nm (or 800 nm or 500 nm) may be sufficient.

[0095] To ensure compatibility between the electric field strength and the molding compound material, an additional organic passivation layer can be used. This layer encapsulates the entire silicon oxide-silicon nitride passivation and also absorbs a portion of the mechanical stress. For example, the electric field strength at the interface between the inorganic and organic passivation layers can be greater than 500 kV / cm due to the thickness of the inorganic passivation. The organic passivation layer can be dimensioned such that the electric field strength at its surface, which represents the interface with the molding compound material, is reduced to such an extent that deterioration of the molding compound material and / or arcing within it can be prevented.The thickness of the organic passivation, in turn, can be chosen so that the forces caused by thermal expansion do not lead to cracking within the same or within subsequent layers.

[0096] If the inorganic hard passivation is selected to cover only the edge, the area covered by the inorganic hard passivation may be reduced, and consequently, stress reduction in the SiC oxide / nitride layer structure can be achieved. To ensure adhesion of the organic passivation to the face metal in this case, a thin adhesive layer can be used that covers both the face metal beneath the imide and the inorganic passivation.

[0097] An edge structure for SiC MOSFETs can be implemented. The passivation can be selected such that the GOX and the ILD, in conjunction with an additionally deposited silicon oxide / silicon nitride layer, form the dielectric passivation to the moisture barrier. In some examples, a silicon oxide layer may be optional (not mandatory). To reduce or eliminate cracking in the inorganic passivation, the distance between the AlCu edge and the silicon oxide / silicon nitride passivation can be sufficiently large. To further reduce electric fields in the passivation, an imide passivation can be used. A thin silicon nitride adhesive layer can improve its adhesion.

[0098] This combination of inorganic and organic layers can meet both the mechanical requirements for package shapes with hard molding compound and the requirements for robustness against moisture for modern semiconductor devices and their applications.

[0099] This passivation can be used independently of the actual edge structure within the semiconductor. This applies, for example, to JTEs where the p-doping is homogeneously distributed in a ring structure around the device, but also to so-called p-in-p JTEs, where the field strengths at the edge of the device can be significantly reduced both in the semiconductor and in the passivation area above the semiconductor body.

[0100] Some examples relate to fabrication processes for moisture-resistant and thermally stable p-in-p transition termination edges for SiC MOSFETs. Some examples of SiC MOSFETs featuring an oxide interlayer (e.g., ILD+GOX layers) are described below. The example in Fig. As shown in Figure 7, only a silicon nitride layer (as an inorganic passivation structure) is deposited onto the ILD+GOX. In the example shown in Figure 7, only a silicon nitride layer (as an inorganic passivation structure) is deposited onto the ILD+GOX. Fig. As shown in Figure 8, an optional thin silicon oxide layer is present. In the example shown in Fig. As shown in Figure 9, the barrier layer extends over the edge region.

[0101] Fig. Figure 7A-C shows schematic cross-sections of a portion of a SiC MOSFET, comprising an oxide interlayer and a p-in-p edge termination structure. The implementation of the SiC MOSFET can be similar to the implementation of semiconductor devices associated with Fig. 1, Fig. 2 and / or 6a-f are described, for example.

[0102] Fig. Figure 7A shows a schematic cross-section of a SiC MOSFET produced by deposition and structuring of the front-side metallization (e.g., after AlCu wet and Ti / TiN dry etching). The SiC MOSFET comprises a SiC substrate 110, a contact metallization layer 120 (e.g., an AlCu layer with a thickness of 5 µm), a barrier layer 250, an oxide intermediate layer 731, and an ohmic contact layer 770.

[0103] In this example, the barrier layer 250 can have a Ti layer and / or a TiN layer. A first lateral part of the barrier layer 250 can be in vertical contact with the contact metallization layer 120 on one side and an ohmic contact layer 770 on the opposite side. A second lateral part of the barrier layer 250 can be in vertical contact with the contact metallization layer 120 on one side and the oxide intermediate layer 731 on the opposite side.

[0104] The ohmic contact layer 770 can have a nickel-aluminum (NiAl) alloy layer. The ohmic contact layer 770 can have a thickness of at least 20 nm and at most 60 nm. The ohmic contact layer 770 can be in vertical contact with the barrier sublayer 250 on one side and with the SiC substrate 110 on the opposite side.

[0105] The oxide interlayer 731 can comprise an ILD layer and a GOX layer. The oxide interlayer 731 can be formed in front of the contact metallization layer 120. At least part of the oxide interlayer 731 can be positioned vertically between the contact metallization layer 120 (and / or the barrier layer 250) and the SiC substrate 110.

[0106] Fig. Figure 7B shows a schematic cross-section of the SiC MOSFET after deposition and structuring of the inorganic passivation nitride layer (e.g., after silicon nitride deposition with a thickness of 400 nm, etching, resist removal, and surface cleaning). A silicon nitride layer 232 can be deposited on the oxide intermediate layer 731. The silicon nitride layer 232 can be structured using a resist mask, so that the oxide intermediate layer 731, located laterally between the contact metallization layer 120 (e.g., the AlCu edge) and the inorganic passivation structure (e.g., silicon nitride layer 232), is not removed or etched. In other words, the oxide intermediate layer 731 can be used as an etch stop for structuring the silicon nitride layer 232.

[0107] Fig. Figure 7C shows a schematic cross-section of the SiC MOSFET after completion of the organic passivation, opening of the silicon nitride adhesion layer 260, and etching of the ILD+GOX in the edge region (e.g., after HSP deposition of the adhesion layer 260 with a thickness of 40 nm and imide process block). Part of the organic passivation layer 140 can be located laterally in the space between the contact metallization layer 120 and the silicon nitride layer 232 (e.g., analogous to the one shown in Fig. 1 and Fig. (as shown in Figure 2). A distance d4 from a lateral edge of the silicon nitride layer 232 to an edge of the SiC MOSFET can be greater than a distance d5 from a lateral edge of the oxide interlayer 731 to an edge of the SiC MOSFET.

[0108] After the deposition and structuring of the front-side metal (see Fig. 7A) the silicon nitride layer 232 is deposited. It is then structured using a resist mask. For example, the etching process is selective, so that the ILD+GOX layer between the passivation and the AlCu edge is not etched. After removing the resist mask and cleaning the surface (see Fig. 7B) The adhesion layer 260 (40 nm silicon nitride) can be deposited, followed by the preparation of the imide passivation. Subsequently, the adhesion layer 260 can be opened via the imide mask, and finally, the ILD+GOX can be etched in the external edge region (see Fig. 7C). After cleaning the surface, the front-side process can be completed.

[0109] More details and aspects are mentioned in connection with the proposed concept or one or more examples described above or below. The SiC MOSFET may have one or more additional optional features that relate to one or more aspects of the proposed concept or one or more above (e.g., Fig. 1-6) or below (e.g. Fig. The examples described in sections 8-9 correspond to those in the following.

[0110] Fig. Figure 8A-C shows schematic cross-sections of a portion of a SiC MOSFET, comprising an oxide interlayer and a p-in-p edge termination structure. The implementation of the SiC MOSFET can be similar to the implementation of semiconductor devices associated with Fig. 1, Fig. 2 6A-6F and / or 7A-7C are described, for example.

[0111] Fig. Figure 8A shows a schematic cross-section of a SiC MOSFET after deposition and structuring of the front side (e.g., after AlCu wet and Ti / TiN dry etching with an additional mask). In contrast to Fig. 7A the Ti / TiN layer is structured via an extra mask so that the Ti / TiN layer can extend further along the oxide intermediate layer 731 than the contact metallization layer 120. Thus, the Ti / TiN layer 250 can serve as an etch stop for the subsequent silicon nitride / silicon oxide etching.

[0112] In other words, the barrier layer 250 can extend laterally beyond the contact metallization layer 120. This part of the barrier layer 250 (e.g., the part that is not in contact with the contact metallization layer 120) can act as an etch stop during subsequent etching of the silicon nitride 232 / silicon oxide 231 layers (e.g., inorganic passivation structure).

[0113] Fig. Figure 8B shows a schematic cross-section of a SiC MOSFET after deposition and structuring of the inorganic passivation nitride layers (e.g., after passivation sets, resist removal, and surface cleaning). In contrast to Fig. 7 comprises the inorganic passivation structure 130 of Fig. 8 furthermore a silicon oxide layer 231. As in Fig. As shown in Figure 8B, the oxide intermediate layer 731 (ILD and GOX layers) was etched at the edges (along with the silicon nitride layer and the silicon oxide layer of the inorganic passivation structure). The oxide intermediate layer 731, which is positioned under the Ti / TiN barrier layer 250 in the space 250, is not etched because the Ti / TiN barrier layer 250 acts as an etch stop in this region. For example, the Ti / TiN barrier layer 250 is sufficiently thick that it is not consumed when the oxide is etched.

[0114] Fig. Figure 8C shows a schematic cross-section of a SiC MOSFET after completion of the organic passivation and opening of the silicon nitride adhesion layer 260. The oxide layers have already been etched, so only the adhesion layer 260 needs to be removed (at the edge of the SiC substrate).

[0115] The SiC MOSFET comprises a semiconductor substrate 110, a contact metallization layer 120, silicon nitride 232 and silicon oxide 231 layers (e.g., an inorganic passivation structure 130), an oxide interlayer 731, a barrier layer 250, an organic passivation structure 140 (e.g., imide), an adhesion layer 260, and an ohmic contact layer 770. A distance d5 from a lateral edge of the oxide interlayer 731 to an edge of the SiC MOSFET can be equal to a distance d4 from a lateral edge of the inorganic passivation structure (from an edge of silicon nitride 232 / silicon oxide 231 layers) to the edge of the SiC MOSFET.

[0116] At the in Fig. In the example shown in Figures 8A-8C, a silicon oxide / silicon nitride stack layer is used to create a moisture barrier. This allows the distance between the silicon oxide-silicon nitride interface and the device's edge termination to be increased, thus further reducing the influence of boundary layer charges.

[0117] In this example, the Ti / TiN barrier layer 250 is structured using an additional mask. After deposition of silicon oxide / silicon nitride and fabrication of a resist mask, the inorganic passivation can be structured in a subsequent step using a plasma etching step, and the resist can then be re-structured (see Fig. 8B) are removed. Here, the Ti / TiN layer in the space between the passivation and the AlCu can serve as an etch stop layer. In the next process, the adhesive layer 260 is again deposited (e.g., 40 nm silicon nitride), followed by the production of the imide passivation. Subsequently, the adhesive layer 260 is opened via the imide mask, in contrast to the example of Fig. 7A-7C may not require re-etching of the GOX+ILD.

[0118] More details and aspects are mentioned in connection with the proposed concept or one or more examples described above or below. The SiC MOSFET may have one or more additional optional features that relate to one or more aspects of the proposed concept or one or more above (e.g., Fig. 1-7) or below (e.g. Fig. 9) correspond to the examples described.

[0119] Fig. Figure 9 shows schematic cross-sections of a portion of another SiC MOSFET, which has an oxide interlayer 731. The in Fig. The nine cross-sections shown illustrate a schematic process flow for the formation of the SiC MOSFET. The implementation of the SiC MOSFET can be similar to the implementation of the SiC device that is used in conjunction with Fig. 8A-8C is described, for example.

[0120] The example that is in Fig. The one shown in 9 differs from the one shown in Fig. 8A-8C in the barrier layer 250 structure. The barrier layer 250 of the SiC MOSFET differs from the barrier layer 250 of the SiC MOSFET in its lateral extent. That is, the barrier layer 250 of the SiC MOSFET extends towards the edge region of the device at least over the P-ring structures of the p-in-p edge termination, while the barrier layer 250 of the SiC MOSFET, which is in Fig. Figure 8 shows that it does not extend laterally over the outermost P-ring structure of the SiC substrate.

[0121] After forming a SiC substrate, including doped regions for implementing transistor cells, a boundary termination, and an oxide intermediate layer 731, a Ti / TiN layer (e.g., the barrier layer 250) is deposited. A lithographic mask is provided over the Ti / TiN layer. Dry etching of the Ti / TiN layer is performed, removing the Ti / TiN except for that covered by the mask.

[0122] Next, a contact metallization layer 120 (e.g., AlCu) is deposited over the SiC substrate. The AlCu layer is then etched. Next, an oxide layer (e.g., silicon oxide layer 231) and a nitride layer (e.g., silicon nitride layer 232) are deposited over the SiC substrate. A suitable mask (e.g., lithographic resist) is placed, and the oxide layers are then etched. The intermediate oxide layer 731, positioned vertically beneath the deposited oxide layers, can also be etched at the edge of the SiC substrate in this same step. Finally, an organic passivation layer 140 (e.g., imide) is deposited and etched.

[0123] More details and aspects are mentioned in connection with the proposed concept or one or more examples described above or below. The SiC MOSFET may have one or more additional optional features that relate to one or more aspects of the proposed concept or one or more above (e.g., Fig. 1-8) or correspond to the examples described below.

[0124] Some embodiments relate to moisture-resistant component passivation with good thermal properties. A passivation structure comprising both organic and inorganic layers can meet both the mechanical requirements for package types with hard molding compound and the requirements for the robustness of modern semiconductor devices and their applications with regard to moisture.

[0125] Some other concepts introduce an edge seal for semiconductor devices with high electric field strengths, significantly improving robustness against moisture without any organic passivation layers. This may only be feasible with soft molding compounds where no mechanical stress can occur between the semiconductor and the compound. For other packages where mechanical stress occurs between the molding compound and the passivation, especially due to temperature increases, this may not be a solution. However, moisture-resistant components are also desirable for these packages, as so-called "hard casting" or "molding compounds" do not provide sufficient protection against moisture.

[0126] There are several concepts that utilize SiNx / SiOx passivation in the boundary region, with the passivation in all cases being implemented either before the deposition of the Ti-Al(Cu) metallization or between the Ti and AlCu process blocks. This means that the passivation and metallization are in contact, which can lead to problems or, in the case of thermal stress, to cracking in the passivation.

[0127] The aspects and features mentioned and described along with one or more of the previously detailed examples and figures can also be combined with one or more of the other examples to replace an identical feature of the other example or to additionally introduce the feature into the other example.

[0128] Examples may further include a computer program with program code for performing one or more of the above procedures when the computer program is executed on a computer or processor. Steps, operations, or processes of various procedures described above may be performed by programmed computers or processors. Examples may also include program storage devices, such as digital data storage media, that are machine-, processor-, or computer-readable and encode machine-, processor-, or computer-executable programs of instructions. The instructions perform some or all of the steps of the procedures described above or cause them to be performed. The program storage devices may include, for example, digital storage media, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media.Other examples may also include computers, processors or control units programmed to perform the steps of the procedures described above, or (field) programmable logic arrays ((F)PLAs = (Field) Programmable Logic Arrays) or (field) programmable gate arrays ((F)PGA = (Field) Programmable Gate Arrays) programmed to perform the steps of the procedures described above.

[0129] The descriptions and drawings illustrate only the principles of revelation. Furthermore, all examples presented here are expressly intended for teaching purposes only, to assist the reader in understanding the principles of revelation and the concepts contributed by the inventor(s) to the advancement of technology. All statements made here regarding principles, aspects, and examples of revelation, as well as specific examples thereof, are intended to encompass their corresponding concepts.

[0130] A block diagram, for example, can represent a detailed circuit diagram that implements the principles of the disclosure. Similarly, a flowchart, a process flowchart, a state transition diagram, pseudocode, and the like can represent various processes, operations, or steps that are, for example, substantially depicted in a computer-readable medium and thus executed by a computer or processor, irrespective of whether such a computer or processor is explicitly shown. Methods disclosed in the description or in the claims can be implemented by an apparatus comprising means for performing each of the respective steps of these methods.

[0131] It is understood that the disclosure of multiple steps, processes, operations, or functions in the description or claims should not be interpreted as being in a specific order unless explicitly or implicitly stated otherwise, for example, for technical reasons. Therefore, the disclosure of multiple steps or functions does not restrict them to a specific order unless these steps or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single step, function, process, or operation may include and / or be broken down into multiple sub-steps, sub-functions, sub-processes, or sub-operations. Such sub-steps may be included and form part of the disclosure of that single step unless explicitly excluded.

Claims

[1] A semiconductor device comprising: a contact metallization layer (120) arranged on a semiconductor substrate (110) and comprising aluminium; an inorganic passivation structure (130) arranged on the semiconductor substrate (110); an organic passivation layer (140), wherein a first part of the organic passivation layer (140) is arranged on the contact metallization layer (120) and a second part of the organic passivation layer (140) is arranged on the inorganic passivation structure (130); and a layer (260, 652), wherein a first part of the layer (260, 652) is in contact with the contact metallization layer (120), wherein a second part of the layer (260, 652) is in contact with the inorganic passivation structure (130), wherein a third part of the layer (260, 652) is arranged in a region laterally between the contact metallization layer (120) and the inorganic passivation structure (130) on the semiconductor substrate (110), wherein the layer (260, 652) is a silicon nitride layer or an electrically conductive layer. [2] The semiconductor device according to claim 1, wherein the layer (260, 652) is an etch stop layer. [3] The semiconductor device according to one of the preceding claims, wherein the first part of the layer (260) is arranged between the contact metallization layer (120) and the organic passivation layer (140). [4] The semiconductor device according to one of claims 1 or 2, wherein the first part of the layer (652) is arranged between the contact metallization layer (120) and the semiconductor substrate (110). [5] The semiconductor device according to one of the preceding claims, wherein the second part of the layer (260) is arranged between the inorganic passivation structure (130) and the organic passivation layer (140). [6] The semiconductor device according to one of claims 1-4, wherein the second part of the layer (652) is arranged between the inorganic passivation structure (130) and the semiconductor substrate (110). [7] The semiconductor device according to any one of claims 1-5, wherein the layer (652) is a titanium-aluminium alloy layer. [8] The semiconductor device according to claim 7, wherein the layer (652) is a second sublayer of a barrier layer, wherein a first sublayer (651) of the barrier layer is a titanium layer. [9] The semiconductor device according to claim 7, wherein the first part of the layer (652) is in contact with the first sublayer (651) and in contact with the contact metallization layer (120). [10] The semiconductor device according to one of the preceding claims, wherein the thickness of the inorganic passivation structure (130) is at least 500 nm. [11] The semiconductor device according to one of the preceding claims, wherein the inorganic passivation structure (130) comprises at least one silicon oxide layer (231) with a thickness of at least 300 nm and at most 5 µm. [12] The semiconductor device according to one of the preceding claims, wherein the inorganic passivation structure (130) comprises at least one nitride layer (232) with a thickness of at least 300 nm and at most 900 nm. [13] The semiconductor device according to one of the preceding claims, wherein a lateral distance (d1) between the inorganic passivation structure (130) and the contact metallization layer (120) is greater than a thickness (t1) of the contact metallization layer (120). [14] The semiconductor device according to one of the preceding claims, wherein a lateral distance (d1) between the inorganic passivation structure (130) and the contact metallization layer (120) is smaller than a width (w1) of the inorganic passivation structure (130). [15] The semiconductor device according to one of the preceding claims, wherein the organic passivation layer (140) is a polyimide layer with a thickness of at least 1 µm and at most 50 µm. [16] The semiconductor device according to one of the preceding claims, further comprising a molding compound structure in contact with the organic passivation layer (140). [17] The semiconductor device according to one of the preceding claims, wherein the semiconductor substrate (110) comprises a drift region (211) of an electrical structure comprising dopants of a first conductivity type, wherein the semiconductor substrate (110) comprises an edge termination region (215) comprising dopants of a second conductivity type, wherein the edge termination region (215) extends laterally from a contact region towards an edge (202) of the semiconductor substrate (110), at least partially below the inorganic passivation structure (130), wherein the edge termination region (215) is ohmically connected to the contact metallization layer (120). [18] The semiconductor device according to claim 17, wherein a lateral distance (d2) between the inorganic passivation structure (130) and the edge (202) of the semiconductor substrate (110) is smaller than a lateral distance (d3) between the edge termination region (215) and the edge (202) of the semiconductor substrate (110). [19] The semiconductor device according to one of the preceding claims, wherein a bond wire or a solder structure is in contact with the contact metallization layer (120). [20] The semiconductor device according to one of the preceding claims, wherein the semiconductor substrate (110) is a wide-bandgap material semiconductor substrate. [21] The semiconductor device according to one of the preceding claims, further comprising an electrical structure formed on the semiconductor substrate (110) and having a breakdown voltage of at least 100V. [22] The semiconductor device according to one of the preceding claims, wherein the organic passivation layer (140) completely covers the inorganic passivation layer (130) and at least parts of the contact metallization layer (120). [23] A method for forming a semiconductor device comprising: Forming a contact metallization layer (120) arranged on a semiconductor substrate (110) and comprising aluminium; Forming an inorganic passivation structure (130) that is arranged on the semiconductor substrate (110); Forming an organic passivation layer (140), wherein a first part of the organic passivation layer (140) is arranged on the contact metallization layer (120) and a second part of the organic passivation layer (140) is arranged on the inorganic passivation structure (130); and Forming a layer (260, 652), wherein a first part of the layer (260, 652) is in contact with the contact metallization layer (120), wherein a second part of the layer (260, 652) is in contact with the inorganic passivation structure (130), wherein a third part of the layer (260, 652) is arranged in a region laterally between the contact metallization layer (120) and the inorganic passivation structure (130) on the semiconductor substrate (110), wherein the inorganic passivation structure (130) is formed in front of the contact metallization layer (120).

Images