TRANSISTOR SPACER STRUCTURE

Abstract

exhibiting structure (100): a gate structure (108) on a fin (104); a cover layer (126) on the gate structure (108); a conductive structure (118) adjacent to the gate structure (108); and a spacer structure (114) arranged between the gate structure (108) and the conductive structure (118), wherein the spacer structure (114) comprises the following: - a first spacer layer (310) that contacts the side wall surfaces of the gate structure (108) and the cover layer (126); - a second spacer layer (320) spaced a gap (400) away from the first spacer layer (310); and - a sealing layer (800) arranged above the gap (400) between the first spacer layer (310) and the second spacer layer (320), wherein the upper surfaces of the cover layer (126), the spacer structure (114) and the conductive structure (118) are coplanar, and wherein the first spacer layer (310) contains silicon oxycarbon nitride and the second spacer layer (320) contains silicon nitride.

Description

GENERAL STATE OF THE ART

[0001] In semiconductor chips, parasitic capacitances can form at locations where conductive structures separated by a dielectric layer are in close proximity. These conductive structures can include, for example, traces, vias, contacts, gate structures, or epitaxial layers. One method for preventing parasitic capacitances in densely packed chip layouts is to use insulating materials with a reduced dielectric constant.

[0002] From publications US 2019 / 0 237 560 A1 and US 2019 / 0 198 635 A1, a FinFET structure with an air gap spacer material is known.

[0003] A semiconductor device with dielectric spacers and air gaps is known from US patent application 2018 / 0053831A1. Similar semiconductor devices are known from German patent applications DE 102017126049A1 and DE 102012217491A1.

[0004] The invention provides a structure according to claim 1. Embodiments are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is an isometric view of fin field-effect transistor (finFET) structures according to some embodiments. Fig. Figure 2 is a flowchart of a method for forming gate spacer structures with air gaps or voids therein according to some embodiments. Fig. Figures 3-10 are cross-sectional views of fin field-effect transistor (finFET) structures during the formation of gate spacer structures with air gaps or voids therein according to some embodiments. Fig. Figure 11 is an isometric view of fin field-effect transistor (finFET) structures according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides various embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features, such that the first and second features are not in direct contact.

[0007] Furthermore, spatially related terms such as "underlying," "below," "lower," "above," "upper," and the like may be used herein for a more convenient description of the relationship of one element or feature to another element(s) or feature(s), as illustrated in the FIGS. These spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the FIGS. The device may be oriented differently (rotated by 90 degrees or with other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0008] The term "nominal," as used herein, refers to a desired or target value of a feature or parameter for a component or process operation, established during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. This range of values ​​is typically due to slight variations in manufacturing processes or tolerances.

[0009] In some embodiments, the terms "approximately" and "essentially" may indicate a value of a given quantity that varies within 5% of a target value (e.g., ±1%, ±2%, ±3%, ±4% and ±5% of the target value).

[0010] The term “vertical”, as used herein, nominally means perpendicular to the surface of a substrate.

[0011] Semiconductor chips can exhibit high transistor densities per unit area to increase chip functionality and reduce manufacturing costs. However, semiconductor chips with high transistor densities can suffer from parasitic capacitances due to conductive structures—such as transistor gates, contacts, vias, and traces—that are closely spaced. For example, in a front-end-of-the-line (FEOL) region of the chip, unwanted parasitic capacitances can form between the transistor gate structures and adjacent source / drain (S / D) contacts, between the transistor gate structures and the S / D connections, between the S / D contacts, and between the transistor gates.

[0012] To solve the problems of parasitic capacitance, the present disclosure is directed to a method for forming gate spacer structures that have air gaps which minimize an effective dielectric constant of the gate spacer structure, thereby reducing the parasitic capacitance between the transistor gate structures and adjacent S / D contacts.In some embodiments, the air gaps are formed by creating a gate spacer stack with a sacrificial spacer positioned between two spacer layers of the gate spacer stack, selectively removing the sacrificial spacer from the gate spacer stack to create an opening between the remaining spacer layers, etching an upper portion of the opening to form a tapered profile, and subsequently plugging the etched upper portion of the opening with a sealing material to create a permanent air gap within the gate spacer structure. In some embodiments, the formation of the tapered profile involves using a belt-jet etcher to perform one or more cycles of polymer material deposition and spacer layer etching.The deposited polymer material is configured to act as an etch mask during the etching operation, protecting structural elements that should not be etched. In some embodiments, multiple polymer deposition and etching cycles are possible until the desired aperture profile is achieved. In some embodiments, the deposited polymer material and the etching chemical can be selected to achieve optimal etch selectivity between the polymer material and the spacer layers of the gate spacer stack.

[0013] According to some embodiments, Fig. 1 A partially isometric view of fin field-effect transistor (finFET) structures 100 formed on the fins 104 above the substrate 102. Fig. Figure 1 shows selected sections of the finFET structures 100, and other sections may be omitted for simplicity. These other sections may include additional structural elements, such as additional layers, additional transistors, doped regions, isolation regions, and the like. Furthermore, the finFET structures 100 are shown in Fig. Figure 1 is shown for illustrative purposes and may not be drawn to scale.

[0014] As in Fig. As shown in Figure 1, the FinFET structures 100 are formed on semiconductor fins 104 (also referred to as "fins 104"). The fins 104 are formed perpendicular to the upper surface of the substrate 102 and are electrically isolated from each other by means of insulation regions 106. The fins 104 can be patterned by any suitable method. For example, the fins 104 can be patterned using one or more photolithography processes, including dual-pattern or multiple-pattern processes. Dual-pattern or multiple-pattern processes can combine photolithography and self-alignment processes, which makes it possible to create patterns that, for example, have spacings smaller than what can otherwise be obtained using a single direct photolithography process.For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fin 104. In some embodiments, the insulation regions 106 are filled with a dielectric material, such as silicon dioxide or a silicon-based oxide, forming shallow trench insulation (STI) regions between the fins 104.

[0015] In some embodiments, the substrate 102 and the fins 104 comprise (i) silicon, (ii) a composite semiconductor such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb), (iii) an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP), or (iv) combinations thereof. For illustrative purposes, the substrate 102 and the fins 104 are described in the context of crystalline silicon. Based on the revelation herein, other materials may be used, as previously discussed. These other materials fall within the nature and scope of this revelation.

[0016] The FinFET structures 100, as in Fig. Figure 1 shows gate structures 108 that wrap around the upper surfaces and sidewall surfaces of the fins 104; spacer structures 114 that are arranged on sidewall surfaces of the gate structures 108; and epitaxial source / drain (“S / D”) structures 116 that are grown on recessed sections of the fins 104 that are not covered by the gate structures 108 and the spacer structures 114. Additional gate structures not shown in Figure 1 are also shown. Fig. The gate structures 108 shown in Figure 1 can be arranged adjacent to the epitaxial S / D structure 116.

[0017] In Fig. 1. The epitaxial S / D structures 116 are joined by the adjacent fins 104 to form a single epitaxial structure. However, this is not restrictive, and the epitaxial S / D structures 116 grown on the fins 104 can remain unjoined. In some embodiments, joining one or more epitaxial S / D structures facilitates the formation of conductive structures 118. In some embodiments, a silicide layer 120 is grown between the conductive structure 118 and the epitaxial S / D structure 116 to reduce the contact resistance. In some embodiments, the epitaxial S / D structures comprise 116 epitaxial boron-doped silicon germanium (SiGe) layers for p-finFET structures 100, epitaxial carbon-doped silicon (Si:C) or phosphorus-doped silicon (S:P) layers for n-finFET structures 100.

[0018] According to some embodiments, each of the gate structures 108 has several layers, such as a gate dielectric 108A, working functional layers 108B, and a metal filling 108C. The gate structures 108 may also include additional layers, which for the sake of simplicity are not shown in Fig. Figure 1 shows these layers. These layers can include dielectric boundary layers inserted between the fin 104 and the gate dielectric 108A, cover layers and barrier layers arranged between the gate dielectric 108A and the working functional layers 108B, and additional barrier layers between the working functional layers 108B and the metal filling 108C.

[0019] In some embodiments, the gate dielectric 108A comprises a high-k dielectric, such as hafnium-based oxide; the working functional layers 108B comprise a stack of metal layers, such as titanium nitride, titanium aluminum, titanium aluminum carbon, etc.; and the metal filling 108C comprises a metal and liner, such as tungsten and titanium nitride.

[0020] In some embodiments, the gate structures 108, the spacer structures 114, and the epitaxial S / D structures 116 are covered by a cover layer 122 and surrounded by a dielectric layer 124, which is defined by a dashed line in Fig. Figure 1 is shown. In some embodiments, the spacer structures 114 electrically isolate the gate structures 108 from the epitaxial S / D structures 116, while the cover layer 122 further isolates the silicide layer 120 and the conductive structures 118 from the gate structures 108, as shown in Figure 1. Fig. 1 and Fig. 3 - a cross-sectional view of Fig. 1 across the intersection line AB - is shown.

[0021] In some embodiments, variations of the finFET structures 100 may be present and are within the nature and scope of this disclosure. For example, the adjacent gate structures 108 may be spaced apart by the dielectric layer 124, in contrast to an epitaxial S / D structure 116, as in Fig. Figure 11 is shown. In other embodiments, the top layer 122 can be an optional layer.

[0022] In some embodiments, parasitic capacitances can form between two adjacent gate structures separated by the dielectric layer 124, the spacer structures 114, and the cover layer 122. Parasitic capacitances can also form between a gate structure 108 and its respective conductive structure 108 or the epitaxial S / D structure 116. Based on the parallel plate capacitance formula, the parasitic capacitance is higher the shorter the distance between the gate structures 108 and other conductive elements of the finFET structures 100. C=kεoAd, where C is the capacitance of the parasitic capacitor, k is the dielectric constant of the insulating material between the plates of the capacitor (e.g., electrodes), ε o where is the dielectric constant of free space, A is the area of ​​the plates, and d is the distance between the plates.

[0023] In some embodiments, the gate structures 108 are recessed with respect to the spacer structures 114 to facilitate the formation of a gate cover layer 126, which protects the gate structure 108 during the formation of the openings for the conductive structures 118. In some embodiments, the gate cover layer 126 comprises a nitride layer, such as silicon nitride.

[0024] In some embodiments Fig. 2 a flowchart of a method 200 for forming air gaps or voids in the spacer structures 114 of the finFET structure 100, which are in Fig. Figure 1 shows that, according to some embodiments, the spacer structures with air gaps or voids exhibit a reduced effective dielectric constant and can lead to a lower parasitic capacitance. Other manufacturing operations can be performed between the various operations of Method 200 and are omitted only for clarity. By way of example and without limitation, Method 200 is described with reference to Fig. 3-10 will be described.

[0025] With reference to Fig. Procedure 200 begins with operation 202 and the process of forming a gate spacer structure with a sacrificial spacer layer inserted between two spacer layers. As an example, and without limitation, spacer structure 114, which is shown in Fig. 1 and Fig. Figure 3 shows a stack having a sacrificial spacer layer 300 inserted between an “inner” spacer layer 310 and an “outer” spacer layer 320. In some embodiments, the sacrificial spacer layer 300 is removed (e.g., etched) in a subsequent operation of the method 200.

[0026] By way of example, and without limitation, the sacrificial spacer layer 300 comprises boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B) material. In some embodiments, the inner spacer layer 310 comprises a low-k material (e.g., with a k-value lower than approximately 3.9), such as silicon oxycarbonitride (Si-OCN) or silicon oxycarbide (SiOC). By way of example, and without limitation, the outer spacer layer 320 comprises silicon nitride (Si3N4; also referred to as "SiN").

[0027] In some embodiments, the spacer structure 114 can be formed as follows. Initially, the inner spacer layer 310, the sacrificial spacer layer 300, and the outer spacer layer 320 are deposited successively over the entire surface as a stack over sacrificial gate structures, which are not in Fig. Figure 1 shows that they are replaced by the gate structure 108 during a “metal gate replacement process.” The deposited stack is then etched using an anisotropic etching process that selectively removes horizontal faces of the sacrificial gate structures, such as the top faces, to form the spacer structure 114. Alternatively, the inner spacer layer 310 and the sacrificial spacer layer 300 can be deposited first, followed by an anisotropic etching process that removes portions of the sacrificial spacer layer 300, followed by the deposition of the outer spacer layer 320, and then by another anisotropic etching process that removes portions of the outer spacer layer 320 to form the spacer structure 114. The subsequent fabrication sequence will form the “L-shaped” inner spacer layer 310, which is shown in Figure 1. Fig. 3-5 and 7-10 are shown.

[0028] After forming the spacer structure 114, a metal gate replacement process is then carried out to replace each sacrificial gate structure with a gate structure 108. The sacrificial gate structures are removed by a wet etching process. Doping the sacrificial spacer layer 300 with boron prevents its removal during the metal gate replacement process.

[0029] As previously mentioned, the spacer structure 114 is formed prior to the formation of the gate dielectric 108A, the working functional layers 108B, and the metal filling 108C of the gate structures 108. In some embodiments, each of the inner spacer layer, the sacrificial spacer layer, and the outer spacer layer is deposited with a thickness of between approximately 2 nm and approximately 3 nm. Consequently, each spacer structure 114 can have a width 114W of between approximately 6 nm and approximately 9 nm. Thinner or thicker spacer layers are possible and are within the nature and scope of this disclosure.

[0030] With reference to Fig. 2 continues the process 200 with operation 204 and the process of removing the sacrificial spacer layer 300 to form an opening between the inner spacer layer 310 and the outer spacer layer 320. By way of example and without limitation, the inner spacer layer 310 is removed by a dry etching process using a mixture of hydrogen and fluorine or a gas chemical that is highly selective with respect to the sacrificial spacer layer 300 and least selective with respect to the inner spacer layer 310 and the outer spacer layer 320. The resulting structure is shown in Fig. Figure 4 shows that removing the sacrificial spacer layer 300 leaves spacer openings in the spacer structure 114 between the inner spacer layer 310 and the outer spacer layer 320. In some embodiments, the spacer opening 400 has a width in the range of 2 nm to 3 nm, corresponding to the thickness of the etched sacrificial spacer layer 300. In some embodiments, the L-shaped inner spacer layer 310 protects the fin 104 during the removal of the sacrificial spacer layer 300. For example, if the fin 104 were not protected, it would have been partially etched by the dry etching chemical used to remove the sacrificial spacer layer 300.

[0031] With reference to Fig. 2 continues the process 200 with operation 206 and the process of depositing a polymer material on surfaces that are not to be etched, such as the upper surfaces of the inner spacer layer 310, the outer spacer layer 320, the cover layer 122, the gate cover layer 126, and the conductive structure 118. In other words, the polymer material acts as an etching mask during a subsequent etching process. By way of example and without limitation, the following is shown. Fig. Five finFET structures 100 after deposition of the polymer material 500 according to operation 206. In some embodiments, the polymer material 500 is primarily deposited on horizontal surfaces of the finFET structures 100 with a thickness of between approximately 0.5 nm and approximately 1 nm. In some embodiments, an upper section of the vertical sidewalls 510 of the spacer openings 400 is coated with a thin layer of polymer material, which is approximately half the thickness of that on the horizontal surfaces. For example, the polymer material 500 on the upper sections of the vertical sidewalls 510 of the spacer openings 400 can have a thickness of between approximately 0.25 nm and approximately 0.5 nm.

[0032] In some embodiments, the polymer material 500 is deposited in a belt sandblasting etcher 600 - of which a cross-section in Fig. Figure 6 is shown. By way of example, and without limitation, the belt sandblaster 600 can have a substrate stage 610 on which the substrate 102 (e.g., in Fig. (1 shown) remains during the polymer material deposition process. In some embodiments, the substrate stage 610 is equipped with an external power supply (not shown). Fig. (shown in Figure 6) coupled, which is configured to apply a voltage to the substrate 102. The belt-beam etcher 600 may also include a plasma chamber 620 arranged above the substrate 102. The belt-beam etcher 600 may include additional components not shown in Figure 6. Fig. Figure 6 is shown. The components not shown are examples only and are not exhaustive. Fig. 6 shown are gas lines, external power supplies, magnetic elements, mechanical and electrical components, computers, sensors, pumps, etc.

[0033] In some embodiments, a fluorocarbon gas (e.g., methane (CH4), hexafluoro-2-butyne (C4F6), octafluorocyclobutane (C4F8), or fluoromethane (CH3F)), tetrachlorosilane (SiCl4), or sulfur dioxide (SO2), diluted in argon (Ar), nitrogen (N2), helium (He), or hydrogen (H2) and mixed with oxygen (O2), is introduced into the plasma chamber 620 to generate a plasma 630. Ions from the plasma 630 are extracted through an aperture (e.g., ion extraction optics) to form a dual ion beam 640, which is then accelerated toward the substrate 102. In some embodiments, the dual ion beam 640 comprises a pair of ion beams, each inclined at an angle θ from a direction perpendicular to the upper surface of the substrate 102, as shown in Fig. Figure 6 is shown. In some embodiments, the angle θ (also referred to as the “beam angle θ” or “inclination angle θ”) is between approximately 1.3° and approximately 9°. According to some embodiments, the dual ion beam 640 interacts with the exposed surfaces of the substrate 102 to encode the polymer material 500 (e.g., C). x H y ), which in Fig. Figure 5 is shown. In some embodiments, the extraction voltage (e.g., the voltage applied to the substrate required to extract ions from the plasma 630 and form the dual ion beam 640) is approximately 0.5 kV or less (e.g., between approximately 0 kV and approximately 0.5 kV). According to some embodiments, the extraction voltage is a pulsed direct current (PDC) voltage (e.g., consisting of rectangular pulses).

[0034] By way of example and without limitation, during the polymer deposition process, the vertical distance D between the opening of the plasma chamber 620 and the upper surface of the substrate 102 is set between approximately 12 nm and approximately 16 nm. Since the plasma chamber 620 can be stationary, the substrate stage 610 can be configured to move in the xy-plane to achieve uniform deposition of the polymer material 500 over the entire surface of the substrate 102. In some embodiments, the vertical distance D can be used to modulate the beam splitting S of the dual ion beam 640 on the surface of the substrate 102. For example, a short vertical distance (e.g., 7 nm) produces a small beam splitting S on the surface of the substrate 102. In contrast, a large vertical distance (e.g., 20 nm) produces a large beam splitting S on the surface of the substrate 102.

[0035] In some embodiments, the extraction voltage, the beam angle θ, and the vertical distance D are some of the parameters used to modulate aspects of polymer material deposition, such as the deposition rate and the thickness of the polymer material 500, on upper sections of the vertical sidewalls 510. In some embodiments, O2 included in the gas mixture is used as an additional parameter to control the deposition rate of the polymer material 500. For example, adding O2 can decrease the deposition rate of the polymer material 500. Furthermore, different types of fluorocarbon gases (e.g., CH4, C4F6, C4F8, or CH3F), SiCl4, or SO2 can be selected to produce polymer materials exhibiting different etch rates for a given etching chemical.

[0036] In some embodiments, after deposition of the polymer material 500 in operation 206, the upper width 520 of the spacer opening 400 is equal to or greater than approximately 1.5 nm (e.g., ≥ 1.5 nm). If the upper width 520 is less than approximately 1.5 nm (e.g., < 1.5 nm), forming a tapered profile for the spacer opening 400 may be challenging and require additional processing.

[0037] With reference to Fig. 2 continues the process 200 with operation 208 and the process of etching an upper section of the spacer opening 400 to form a tapered profile. In some embodiments, operation 208 includes etching the exposed sidewall sections of the inner and outer spacer layers 310 and 320 to form a funnel-shaped upper opening. In some embodiments, the etching operation is performed in the belt-jet etcher 600, which is located in Fig. Figure 6 shows this. For example, after the deposition of the polymer material 500, an etching chemical is introduced into the plasma chamber 620 to produce a plasma, such as the plasma 630, from which ions can be extracted to form an ion beam, such as the dual ion beam 640, which selectively etches sections of the inner and outer spacer layers 310 and 320 that are not covered by the polymer material 500. In some embodiments, the etching chemical—which differs from the deposition chemical used for the polymer material 500—comprises tetrafluoromethane (CF4) or fluoroform (CHF3) diluted in Ar, N2, He, or H2 and mixed with O2. In some embodiments, the etching chemical and the polymer material deposition chemical are selected based on the desired selectivity between the polymer material 500 (e.g., the etching mask) and the materials to be etched (e.g.,the exposed sections of the inner and outer spacer layers 310 and 320) were selected.

[0038] In some embodiments, the aforementioned etching chemical is configured to etch the polymer material 500 at a lower etch rate than the exposed sections of the inner and outer spacer layers 310 and 320. Therefore, during operation 208, the thickness of the polymer material 500 on horizontal surfaces of the finFET structures 100 is reduced, and the polymer material 500 on the upper section of the vertical sidewalls 510 of the spacer opening 400 is consumed (e.g., etched).

[0039] In some embodiments, during the etching process of operation 208, the beam angle θ is set between approximately 5° and approximately 30°, while the vertical distance D is set between approximately 6 nm and approximately 12 nm. The beam angle θ, combined with the vertical distance D, can produce different etch profiles for the spacer aperture 400. For example, a wide beam angle θ (e.g., approximately 30°) combined with a short vertical distance D (e.g., approximately 7 nm) can provide a flatter and more tapered etch profile compared to a narrow beam angle θ (e.g., approximately 1.3°) combined with a larger vertical distance D of approximately 16 nm. In some embodiments, the directionality of the dual ion beam 640 delivers ions to the desired areas of the inner and outer spacer layers 310 and 320 to be etched.For example, the beam angle θ and the distance D can be configured such that the dual ion beam 640 is directed at upper sections of the vertical sidewalls 510 of the spacer opening 400. During etching, the dual ion beam 640 initially removes the polymer material 500 covering the upper sections of the vertical sidewalls 510 of the spacer openings 400 and then begins to etch sections of the inner and outer spacer layers 310 and 320 that are exposed opposite the direct path of the dual ion beam 640. The resulting structure with a tapered profile 700 (also referred to herein as "funnel 700") is shown in . Fig. Figure 7 shows. In some embodiments, the aforementioned etching process for the inner and outer spacer layers 310 and 320 is referred to as "pull back".

[0040] In some embodiments, as a result of the etching process in operation 208, the tapered profile or funnel 700 develops a side wall angle ξ which is between approximately 70° and 80° measured from the horizontal axis x, as shown in Fig. Figure 7 shows the following. Furthermore, the tapered profile or funnel 700 has an upper opening 710 of between approximately 4.5 nm and approximately 5.5 nm and a depth 720 of between approximately 5 nm and approximately 9 nm.

[0041] In some embodiments, operations 206 and 208 can be repeated as necessary to achieve the desired profile for the spacer opening 400 in the spacer structure 114. For example, with reference to Fig. 2. Operation 208 proceeds to checkpoint operation 210. According to operation 210, if the desired profile has not been achieved, a new layer of polymer material 500 can be deposited according to operation 208, followed by another etching process according to operation 208. If, on the other hand, the desired profile has been achieved, then the process 200 proceeds to operation 212. In some embodiments, process parameters for the deposition and etching operations 206 and 208 can be reset as they are repeated to achieve the desired tapered profile. For example, the beam angle θ, the distance D, and the extraction voltage in the etcher 600 can be adjusted accordingly as operations 206 and 208 are repeated.

[0042] With reference to Fig. 2 continues the process 200 with operation 212 and the process of depositing a sealing material on the etched upper section of the spacer opening 400 to plug the spacer opening 400 and form an air gap between the two spacer layers (e.g., the inner and outer spacer layers 310 and 320). For example, with reference to Fig. 8. The sealing material 800 is deposited over the finFET structures 100 and fills the hopper 700. In some embodiments, the sealing material 800 comprises silicon oxycarbide (SiOC), which is deposited at a temperature between approximately 300 °C and approximately 400 °C by plasma-enhanced chemical vapor deposition (PECVD) or plasma-assisted atomic layer deposition (PEALD). In some embodiments, the sealing material 800 comprises between approximately 25 at.% and approximately 40 at.% silicon, between approximately 25 at.% and approximately 50 at.% oxygen, and between approximately 4 at.% and approximately 40 at.% carbon. Furthermore, the sealing material 800 has a dielectric constant that is less than approximately 4 (e.g. 3.6) in order to reduce the effect on parasitic capacitance.In some embodiments, the as-deposited sealing material 800 is subjected to post-deposition annealing at approximately 400 °C in N2 or H2 for compaction purposes. The deposition rate of the sealing material 800 can be configured such that reaction gases do not have sufficient time to penetrate deep into the spacer opening 400 and form the sealing material 800 on the underside of the spacer opening 400. In some embodiments, the sealing material is deposited on the underside of the funnel to form a constriction that prevents reaction media from extending further into the spacer opening 400 to form sealing material 800 on the underside of the spacer opening 400.

[0043] In some embodiments, the sealing material 800 is deposited with a thickness greater than approximately 11 nm to adequately fill the funnel 700. In some embodiments, the sealing material 800 is deposited to a depth 820 within the spacer opening 400, which is between approximately 7 nm and 11 nm. The resulting air gaps or voids have a height 810 of between approximately 40 nm and approximately 70 nm and a width that is substantially equal to the thickness of the removed sacrificial spacer layer 300 (e.g., between approximately 2 nm and approximately 3 nm).

[0044] In some embodiments, tapered profiles or funnels 700 with a depth of less than approximately 5 nm and an upper opening 710 of less than approximately 4.5 nm can lead to limited sealing material formation within the funnels 700. Consequently, sludge from subsequent chemical-mechanical planarization (CMP) processes can enter the spacer opening 400 and erode the spacer structure 114, which is undesirable. On the other hand, tapered profiles or funnels 700 with an upper opening 710 wider than 5.5 nm can lead to a reduced air gap volume, as the sealing material 800 can be deposited deeper into the spacer opening 400. In situations where the funnel 700 is very wide and deep (e.g.,(wider than approximately 5.5 nm and deeper than approximately 9 nm), the sealing material 800 can fill the entire spacer opening 400, which is not desirable because the spacer structure 114 cannot exploit the air gap or void formation with a low dielectric constant of 1.

[0045] In some embodiments, after deposition and heat treatment of the sealing material 800, a CMP process removes excess sealing material 800 outside the spacer opening 400, as shown in Fig. Figure 9 is shown. In some embodiments, the aforementioned CMP process reduces the depth 820 to a depth 900 of between approximately 7 nm and approximately 11 nm to approximately 4 nm. This is because the CMP process also removes sections of the gate top layer 126, sections of the spacer structure 114, and sections of the conductive structure 118. After the aforementioned CMP process, the top surface of the finFET structures 100 is essentially planar. In some embodiments, after the aforementioned CMP process, the sealing material 800 has a width 800w of the top surface along the x-axis of between approximately 3 nm and approximately 5.5 nm and a depth 900 of between approximately 1 nm and approximately 4 nm. For example, an aspect ratio of the sealing material 800 is between approximately 0.2 and approximately 1.3. where the aspect ratio is defined as the ratio between the depth 900 and the area width 800w.In some embodiments, the sealing material 800 occupies between approximately 5% and approximately 9% of the spacer opening 400; the remainder of the opening 400 is occupied by the air gap or void. In some embodiments, the remaining sealing material 800 has a funnel shape, with its upper surface being wider than its lower surface. However, this is not limiting, and depending on the amount of sealing material 800 removed during the aforementioned CMP process, the width 800w of the sealing material 800 can substantially correspond to the width of the spacer opening 400 (e.g., approximately 3 nm).

[0046] With reference to Fig. 10 Additional conductive structures 1004 and 1006 can be formed on the gate structures 108 and the conductive structures 118 according to some embodiments. By way of example and without limitation, the conductive structures 1004 and 1006 can be formed as follows: a metal oxide etch stop layer (ESL) 1000 (e.g., aluminum oxide) and a dielectric layer 1002 (e.g., a silicon-based oxide) can be deposited over the entire area above the finFET structures 100, as shown in Fig. Figure 10 shows that an etching process creates openings in the dielectric layer 1002 and the metal oxide ESL 1000, which are essentially aligned with the gate structures 108 and the conductive structures 118. In some embodiments, a different etching chemical is used to etch the dielectric layer 1002 from the metal oxide ESL 1000. According to some embodiments, the etching chemical used to etch the metal oxide ESL 1000 is configured to have lower selectivity with respect to the sealing material 800 (e.g., SiOC), the inner spacer layer 310 (e.g., SiN), the outer spacer layer 320 (e.g., SiOC), and the cover layer 122 (e.g., SiN).This can be advantageous if the openings for the conductive structures 1004 and 1006 are unintentionally misaligned with respect to the gate structures 108 and the conductive structures 118, as shown by the misaligned dashed lines 1004' and 1006'. With such misalignment, the lower etch rates for the sealing material 800 (e.g., SiOC), the inner spacer layer 310 (e.g., SiN), the outer spacer layer 320 (e.g., SiOC), and the cover layer 122 (e.g., SiN) can prevent the etching chemical from substantially removing portions of these structures. Once the openings are formed, the conductive material fills them to form the conductive structures 1004 and 1006. In some embodiments, the conductive structures 1004 and 1006, like the conductive structure 118, comprise a metal filling, such as tungsten, cobalt or another suitable conductive material.In some embodiments, the conductive structures 1004 and 1006, like the conductive structure 118, comprise a liner or barrier layers, such as titanium nitride, or a stack of titanium and titanium nitride deposited prior to metal filling.

[0047] In some embodiments, the method 200 is not limited to finFET structures 100, which are in Fig. The method is shown in Figure 1 and can be applied to other types of transistors or variations of finFET structures 100 that are sensitive to parasitic capacitances. For example, the method 200 can be applied to planar transistors and gate-all-around transistors. Furthermore, the method 200 can be applied to selective transistors on the chip—for example, the method can be applied to transistors in high-density areas of the chip.

[0048] The present disclosure relates to a method for forming gate spacer structures that have air gaps to minimize the effective dielectric constant of the gate spacer structure and to reduce the parasitic capacitance between the transistor gate structures and adjacent S / D contacts.In some embodiments, the air gaps are formed by creating a gate spacer stack with a sacrificial spacer positioned between two spacer layers of the gate spacer stack, selectively removing the sacrificial spacer from the gate spacer stack to create an opening between the remaining spacer layers, etching an upper portion of the opening to form a tapered profile, and subsequently plugging the etched upper portion of the opening with a sealing material to create a permanent air gap within the gate spacer structure adjacent to the gate structure. In some embodiments, the formation of the tapered profile involves using a belt-jet etcher to perform one or more cycles of polymer material deposition and spacer layer etching.The deposited polymer material is configured to act as an etch mask during the etching operation, protecting structural elements that should not be etched. In some embodiments, multiple polymer deposition and etching cycles are possible until the desired aperture profile is achieved. In some embodiments, the deposited polymer material and the etching chemical can be selected to achieve optimal etch selectivity between the polymer material and the spacer layers of the gate spacer stack. Polymer material deposition and etching require different chemicals and ion beam characteristics, such as beam angle and ion energy. In some embodiments, the beam angle during polymer material deposition is between approximately 1.3° and approximately 9°, while the beam angle during the etching process is between 5° and approximately 30°.In some embodiments, the sealing material is a low-k dielectric comprising SiOC containing between approximately 25 atomic percent (at.%) and approximately 40 at.% silicon, between approximately 25 at.% and approximately 50 at.% oxygen, and between approximately 4 at.% and approximately 40 at.% carbon.

Claims

[1] exhibiting structure (100): a gate structure (108) on a fin (104); a cover layer (126) on the gate structure (108); a conductive structure (118) adjacent to the gate structure (108); and a spacer structure (114) arranged between the gate structure (108) and the conductive structure (118), wherein the spacer structure (114) comprises the following: - a first spacer layer (310) that contacts the side wall surfaces of the gate structure (108) and the cover layer (126); - a second spacer layer (320) spaced a gap (400) away from the first spacer layer (310); and - a sealing layer (800) arranged above the gap (400) between the first spacer layer (310) and the second spacer layer (320), wherein the upper surfaces of the cover layer (126), the spacer structure (114) and the conductive structure (118) are coplanar, and wherein the first spacer layer (310) contains silicon oxycarbon nitride and the second spacer layer (320) contains silicon nitride. [2] Structure (100) according to claim 1, wherein the gap (400) is surrounded by side wall surfaces of the first spacer layer (310) and the second spacer layer (320), a lower section of the first spacer layer (310) and the sealing layer (800). [3] Structure (100) according to claim 1 or 2, wherein the sealing layer (800) fills upper sections of the side wall surfaces of the first spacer layer (310) and the second spacer layer (320). [4] Structure (310) according to one of the preceding claims, wherein the upper section of the sealing layer (800) has a tapered shape (700) [5] Structure (100) according to one of the preceding claims, wherein the gap (400) has a width of between 2 nm and 3 nm and a height of between 40 nm and 70 nm. [6] Structure (100) according to one of the preceding claims, wherein a width (114W) of the spacer structure (114) is between 6 nm and 9 nm. [7] Structure (100) according to one of the preceding claims, wherein the sealing layer (800) contains silicon oxycarbide. [8] Structure (100) according to any one of the preceding claims, further comprising: a metal oxide etch stop layer (1000) arranged on the top layer (126), the spacer structure (114) and the conductive structure (118); a dielectric layer (1002) on the metal oxide etch stop layer (1000); and another conductive structure (1004) on the gate structure (108), wherein the other conductive structure (1004) extends across the cover layer (126), the metal oxide etch stop layer (1000) and the dielectric layer (1002). [9] Structure according to one of the preceding claims, wherein the gap (400) has a width corresponding to a distance between an inner side wall surface of the first spacer layer (310) and an inner side wall surface of the second spacer layer (320). [10] Structure according to one of the preceding claims, wherein the gap (400) has a height (810) corresponding to a distance between a lower section of the first spacer layer (310) and a lower section of the sealing layer (800).

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