MANUFACTURING METHOD FOR PHASE CONTROL IN CONTACT FORMATION

Abstract

Procedure that includes the following: Formation of a first metallic structural element (72, 84); Formation of a dielectric layer (92) over the first metallic structural element (72, 84); Etching of the dielectric layer to form an opening (94, 96) exposing a top surface of the first metallic structural element (72, 84) through the opening (94, 96); Performing a first treatment on the top surface of the first metallic structural element (72, 84), wherein the first treatment oxidizes a surface layer of the first metallic structural element (72, 84), wherein the first treatment is performed through the opening (94, 96), wherein the first treatment starts at a time when a horizontal surface of the dielectric layer (92) is exposed, and the first treatment is performed using a first process gas, wherein the first treatment comprises a thermal treatment in a temperature range of 100°C to 400°C; after the first treatment, a second treatment is carried out, the second treatment being carried out through the opening (94, 96), and the second treatment being carried out using a second process gas that differs from the first process gas; and Deposition of a second metallic structural element (108, 110) in the opening (94, 96).

Description

BACKGROUND

[0001] The integrated semiconductor (IC) industry has experienced exponential growth. Technological advances in IC materials and design have led to generations of ICs, each featuring smaller and more complex circuits than the previous one. As ICs evolved, functional density (the number of interconnected components per unit area) has generally increased, while geometric size (the smallest component or trace that can be formed using a manufacturing process) has decreased. This process of downscaling generally delivers benefits by increasing production efficiency and reducing manufacturing costs.

[0002] In addition to downscaling devices, manufacturers today use new and different materials and / or material combinations to facilitate downscaling. Downscaling, alone and in combination with new and different materials, has also introduced challenges that may not have been apparent in previous generations with larger geometries. A method for fabricating a semiconductor device is known from US 2017 / 0032975 A1. A similar method is known from US 4954214 A. US 6218303 B1 and US 2015 / 0270142 A1 describe other conventional methods for fabricating integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The invention relates to methods as specified in claims 1 and 9. Aspects of this disclosure are best understood with reference to the following detailed description, when read together with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale and are used for illustrative purposes only. The dimensions of the various features may, in fact, be enlarged or reduced as desired to improve clarity. Fig. Figures 1-7, 8A, 8B, 9, 10, 11A, 11B, and 12-16 illustrate the perspective views and cross-sectional views of intermediate stages in the formation of fin field-effect transistors (FinFETs) and contact connectors according to some embodiments. Fig. Figure 17 illustrates a cross-sectional view of a FinFET and contact connectors according to some embodiments. Fig. Figures 18 to 20 illustrate perspective views and cross-sectional views of intermediate stages in the formation of FinFETs and contact connectors according to some embodiments. Fig. Figure 21 illustrates a cross-sectional view of a FinFET and contact connectors according to some embodiments. Fig. Figure 22 illustrates the results showing the cumulative percentages of contact resistance values ​​as a function of normalized contact resistance values ​​according to some embodiments. Fig. Figure 23 illustrates a process flow for forming FinFETs and contact connectors according to some embodiments. DETAILED DESCRIPTION

[0004] The present disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which further structural elements may be formed between the first and second structural elements, so that the first and second structural elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves for simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or structural element to one or more other elements or structural elements, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may also be oriented differently (rotated 90 degrees or otherwise), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0006] Transistors and connectors, and the corresponding formation processes, are provided according to various embodiments. The intermediate steps for forming the transistors and connectors are illustrated according to some embodiments. Some variations of certain embodiments are discussed. In all the different views and illustrative embodiments, the same reference numerals denote the same elements. According to some embodiments, the formation of fin field-effect transistors (FinFETs) is used as an example to explain the concept of this disclosure. Other types of transistors, such as planar transistors and gate-all-around (GAA) transistors, and the corresponding connectors can also utilize the concept of this disclosure.

[0007] Furthermore, the concept of the present disclosure can be applied to the formation of other connections whenever an upper metallic structural element is formed to contact an underlying metallic structural element, such as metal conductors, vias, contact connectors, or the like. According to some embodiments of the present disclosure, the surfaces of the underlying metallic structural elements are treated or implanted with certain elements, such as oxygen, silicon, boron, phosphorus, arsenic, or the like, so that a more uniform phase formation can be achieved in the subsequently formed upper metallic structural elements, thereby making the resistivity of the upper metallic structural elements more uniform throughout the entire respective wafer or die.

[0008] Fig. Figures 1-7, 8A, 8B, 9, 10, 11A, 11B, and 12-16 illustrate cross-sectional and perspective views of intermediate stages in the formation of fin field-effect transistors (FinFETs) and contact connectors according to some embodiments of the present disclosure. The processes shown in these figures are also schematically represented in the Fig. The process flow shown in 23 is reflected in 200.

[0009] In Fig. 1. A substrate 20 is provided. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (for example, with a p-type or n-type dopant) or undoped. The semiconductor substrate 20 can be part of a wafer 10, such as a silicon wafer. In general, an SOI substrate contains a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is placed on a substrate, usually a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon, germanium, a composite semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof.

[0010] We'll stick with it Fig. 1, where a depression region 22 is formed in the substrate 20. The respective process is described in the Fig. The process flow 200 shown in Figure 23 is illustrated as process 202. According to some embodiments of the present disclosure, the trough region 22 is an n-type trough region formed by implanting an n-type perturbation atom, which may be phosphorus, arsenic, antimony, or the like, into the substrate 20. According to other embodiments of the present disclosure, the trough region 22 is a p-type trough region formed by implanting a p-type perturbation atom, which may be boron, indium, or the like, into the substrate 20. The resulting trough region 22 may extend to the top of the substrate 20. The concentration of the n-type or p-type perturbation atoms may be a maximum of 10 18 cm -3 for example in the range between approximately 10 17 cm -3 and about 10 18 cm -3 .

[0011] We turn to Fig. 2 to, where isolation regions 24 are formed such that they extend from a top surface of the substrate 20 into the substrate 20. The isolation regions 24 are subsequently referred to alternatively as shallow trench isolation (STI) regions. The respective process is described in the Fig. The process flow 200 shown in Figure 23 is illustrated as process 204. The sections of the substrate 20 between adjacent STI regions 24 are referred to as semiconductor strips 26. To form STI regions 24, a contact island oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The contact island oxide layer 28 can be a thin film formed from silicon oxide. According to some embodiments of the present disclosure, the contact island oxide layer 28 is formed in a thermal oxidation process, wherein a top layer of the semiconductor substrate 20 is oxidized. The contact island oxide layer 28 acts as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The contact island oxide layer 28 can also act as an etch stop layer for etching the hard mask layer 30.According to some embodiments of the present disclosure, the hard mask layer 30 is formed from silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitriding of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and is then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etching mask to create hard masks 30, as shown in [reference]. Fig. 2 shown, to form.

[0012] Next, the structured hard mask layer 30 is used as an etching mask to etch the contact island oxide layer 28 and the substrate 20, followed by filling the resulting trenches in the substrate 20 with one or more dielectric materials. A planarization process, such as a chemical-mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess sections of the dielectric materials, and the remaining sections of the one or more dielectric materials are STI regions 24. The STI regions 24 may contain a lining dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20.The lining dielectric can also be a deposited silicon oxide layer, silicon nitride layer, or the like, formed, for example, by atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 24 can also contain a dielectric material over the lining oxide, wherein the dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like. According to some embodiments, the dielectric material over the lining dielectric can contain silicon oxide.

[0013] The top surfaces of hard masks 30 and the top surfaces of STI regions 24 can be substantially flush with each other. Semiconductor strips 26 are located between adjacent STI regions 24. According to some embodiments of the present disclosure, the semiconductor strips 26 are parts of the original substrate 20, and consequently, the material of the semiconductor strips 26 is the same as that of the substrate 20. According to alternative embodiments of the present disclosure, the semiconductor strips 26 are replacement strips formed by etching the sections of the substrate 20 between STI regions 24 to form recesses and by performing epitaxy to re-grow a different semiconductor material in the recesses. Accordingly, the semiconductor strips 26 are formed from a semiconductor material that differs from that of the substrate 20.According to some embodiments, the semiconductor strips 26 are formed from silicon-germanium, silicon-carbon or a III-V composite semiconductor material.

[0014] We turn to Fig. 3 to where STI regions 24 are omitted, so that the upper sections of the semiconductor strips 26 protrude higher than the tops 24A of the remaining sections of the STI regions 24 to form projecting fins 36. The respective process is described in the Fig. The process flow shown in Figure 23 is illustrated as process 206. The etching can be carried out using a dry etching process, using, for example, HF3 and NH3 as the etching gases. Plasma can be generated during the etching process. Argon can also be included. According to alternative embodiments of the present disclosure, the recession of the STI regions 24 is carried out using a wet etching process. The etching chemical can, for example, contain HF.

[0015] In the embodiments illustrated above, the fins can be structured by any suitable method. For example, the fins can be structured using one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, center-to-center spacings smaller than those obtainable by a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured by a photolithography process. Spacers are formed along the structured sacrificial layer by a self-aligning process.The sacrificial layer is then removed, and the remaining spacers, or thorns, can then be used to structure the fins.

[0016] We turn to Fig. 4 to where dummy gate stacks 38 are formed such that they extend onto the tops and side walls of (projecting) fins 36. The respective process is described in the Fig. The process flow 200 shown in Figure 23 is illustrated as process 208. The dummy gate stacks 38 can contain dummy gate dielectrics 40 and dummy gate electrodes 42 over the dummy gate dielectrics 40. The dummy gate electrodes 42 can be formed, for example, using polysilicon, and other materials can also be used. Each of the dummy gate stacks 38 can also contain one or more hard mask layers 44 over the dummy gate electrodes 42. The hard mask layers 44 can be formed from silicon nitride, silicon oxide, silicon carbon nitride, or multiple layers thereof. The dummy gate stacks 38 can cross one or more of the projecting fins 36 and / or STI regions 24. The dummy gate stacks 38 also have longitudinal directions perpendicular to the longitudinal directions of the projecting fins 36.

[0017] Next, gate spacers 46 are formed on the side walls of the dummy gate stacks 38. This process is also known as process 208 in the Fig. The process flow shown in Figure 23 is shown in Figure 200. According to some embodiments of the present disclosure, the gate spacers 46 are formed from dielectric materials, such as silicon nitride, silicon carbon nitride or the like, and can have a single-layer structure or a multi-layer structure, including several dielectric layers.

[0018] Then an etching process is carried out to etch the sections of the protruding fins 36 that are not covered by dummy gate stacks 38 and gate spacers 46, resulting in the Fig. The structure shown in section 5 leads to the respective process. The respective process is designated as process 210 in the structure shown in the document. Fig. The process flow 200 shown in Figure 23 is illustrated. The recess can be anisotropic, and consequently, the sections of the fins 36 directly beneath the dummy gate stacks 38 and gate spacers 46 are protected and are not etched. According to some embodiments, the top surfaces of the recessed semiconductor strips 26 can be lower than the top surfaces 24A of the STI regions 24. The spaces left by the etched protruding fins 36 are referred to as recesses 50. The recesses 50 include sections located between adjacent gate stacks 38. Some lower sections of the recesses 50 are located between adjacent STI regions 24.

[0019] Next, epitaxial regions (source / drain regions) 54 are formed by selective growth (via epitaxy) of a semiconductor material in the recesses 50, resulting in the structure shown in Fig. 6 leads to the respective process. The respective process is designated as process 212 in the section on Fig. The process flow shown in Figure 23 illustrates the process flow. Depending on whether the resulting FinFET is a p-type or an n-type FinFET, an impurity atom of either p-type or n-type can be doped in situ as epitaxy progresses. For example, if the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or similar compounds can be grown. Conversely, if the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or similar compounds can be grown. According to alternative embodiments of the present disclosure, the epitaxial regions comprise 54 III-V composite semiconductors, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof or multiple layers thereof.After the recesses 50 have been filled with epitaxial regions 54, further epitaxial growth of the epitaxial regions 54 causes them to expand horizontally, and facets can be formed. Further growth of the epitaxial regions 54 can also cause adjacent epitaxial regions 54 to fuse together. This can generate cavities (air gaps) 56.

[0020] Following the epitaxy step, the epitaxy regions 54 can further be implanted with a p-type or n-type interfering atom to form source and drain regions, which are also designated by the reference numeral 54. According to alternative embodiments of the present disclosure, the implantation process is skipped if epitaxy regions 54 are doped in situ with the p-type or n-type interfering atom during epitaxy.

[0021] Fig. Figure 7 illustrates a perspective view of the structure after the formation of the contact etch stop layer (CESL) 58 and inter-layer dielectric (ILD) 60. The respective process is described as process 214 in the Fig. The process flow shown in Figure 23 illustrates the process flow 200. The CESL 58 can be formed from silicon oxide, silicon nitride, silicon carbon nitride, or the like, and can be formed using CVD, ALD, or the like. The ILD 60 can contain a dielectric material formed, for example, by FCVD, spin coating, CVD, or another deposition process. The ILD 60 can be formed from a dielectric material that may contain silicon oxide, phosphosilicate glass (PSG), boron silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. A planarization process, such as a CMP process or a mechanical grinding process, can be performed to level the top surfaces of the ILD 60, dummy gate stack 38, and gate spacer 46 with each other.

[0022] After the in Fig. Once the structure shown in Figure 7 has been formed, the dummy gate stacks 38 are replaced by substitute gate stacks, as in the processes in Fig. 8A, Fig. 8B, and Fig. 9 shown. Fig. 8B illustrates the top surface 24A of the STI regions 24, and the semiconductor fin 36 protrudes higher than the top surface 24A.

[0023] To form the replacement gates, the hard mask layers 44, the dummy gate electrodes 42 and the dummy gate dielectrics 40 are used, as shown in Fig. 7 shown, removed, thereby forming openings 62, as shown in Fig. 8A shows the respective process. The respective process is designated as process 216 in the section on Fig. The process flow shown in Figure 23 is illustrated in Figure 200. The upper surfaces and side walls of the projecting fins 36 are each exposed towards the openings 62.

[0024] Fig. 8B illustrates the in Fig. Reference cross-section 8B-8B shown in Figure 8A. Next, as shown in Fig. Figure 9 shows the replacement gate stack 64. The respective process is shown as process 218 in the diagram. Fig. The process flow 200 shown in Figure 23 illustrates this. The gate stack 64 contains the gate dielectric 70 and the gate electrode 72. The gate dielectric 70 can contain the interfacial layer (IL) 66 and a high k-value dielectric layer 68. The IL 66 is formed on the exposed surfaces of the projecting fins 36 and can contain an oxide layer, such as a silicon oxide layer, formed by thermal oxidation of the projecting fins 36, a chemical oxidation process, or a deposition process. A high k-value dielectric layer 68 contains a high k-value dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, or the like. The dielectric constant (the k-value) of the high k-value dielectric material is greater than 3.9 and can be greater than approximately 7.0.According to some embodiments of the present disclosure, a high k-value dielectric layer 68 is formed using ALD or CVD.

[0025] We'll stick with it Fig. 9, where the gate electrode 72 is formed on the gate dielectric 70. The gate electrode 72 can contain a diffusion barrier (cap layer) 74 and one or more work layers 76 above the diffusion barrier 74. The diffusion barrier 74 can be made of titanium nitride, which may be doped with silicon. Titanium nitride, when doped with silicon, is sometimes also called titanium silicon nitride (Ti-Si-N or TSN). The work layer 76 determines the work function of the gate electrode and contains at least one layer or several layers made of different materials. The specific material of the work layer can be selected depending on whether the FinFET is an n-type or a p-type FinFET.For example, if the FinFET is an n-type FinFET, the exit work layer 76 can contain a TaN layer and a titanium-aluminum (TiAl) layer over the TaN layer. If the FinFET is a p-type FinFET, the exit work layer 76 can contain a TaN layer, a TiN layer over the TaN layer, and a TiAl layer over the TiN layer. After deposition of the cap layer 74 and the exit work layer 76, a barrier layer 78 is formed, which can be another TiN layer. The barrier layer 78 can be formed using CVD.

[0026] Next, a metal-filling region 80 is deposited, having a bottom side in physical contact with the top side of the barrier layer. The formation of the metal-filling region 80 can be achieved by CVD, ALD, physical vapor deposition (PVD), or the like, and the metal-filling region 80 can be formed from or comprise cobalt, tungsten, alloys thereof, or other metals or metal alloys.

[0027] Next, planarization is performed, such as a chemical-mechanical polishing (CMP) process or a mechanical grinding process, so that the top surface of the gate stack 64 is coplanar with the top surface of the ILD 60. In a subsequent process, the gate stack 64 is back-etched, resulting in a recess formed between opposing gate spacers 46. Next, as in Fig. As shown in Figure 10, a hard mask 82 is formed over the replacement gate stack 64. According to some embodiments of the present disclosure, the formation of the hard mask 82 includes a deposition process to form a dielectric cover layer material and a planarization process to remove the excess dielectric material over the gate spacers 46 and the ILD 60. The hard mask 82 can, for example, be formed from silicon nitride or other similar dielectric materials.

[0028] Fig. 11A and Fig. Figure 11B illustrates the formation of the lower source / drain contact plugs 84 and silicide regions 86. The respective process is described as process 220 in the Fig. The process flow 200 shown in Figure 23 illustrates this. According to some embodiments of the present disclosure, the formation process includes the following: etching the ILD 60 and the CESL 58 to form contact openings, depositing a metal layer (such as a TiTaN layer or a tantalum layer) extending into the contact openings, depositing a barrier layer 88 (such as a titanium nitride layer), and performing a curing process such that the lower portion of the metal layer reacts with the source / drain region 54 to form silicide regions 86. The remaining sidewall portions of the metal layer may be removed or left in place. Source / drain contact plugs 84 are then formed. The source / drain contact plugs 84 may be formed from or comprise cobalt, tungsten, other suitable metals, or alloys thereof.A planarization process, such as a CMP process or a mechanical grinding process, is performed to level the top of the contact connector 84 with the top of the ILD 60.

[0029] Fig. Figure 12 illustrates the formation of the etch stop layer (ESL) 90 and the dielectric layer 92 (which can also be an ILD) over the ESL 90. The respective process is described as process 222 in the Fig. The process flow shown in Figure 23 illustrates the process flow. The ESL 90 can be formed from or comprise silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, and the like, or a combination thereof. The dielectric layer 92 can comprise or be silicon dioxide, a low k-value dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOC, a spin-on glass, a spin-on polymer, or the like. The ESL 90 and the dielectric layer 92 can be deposited using spin coating, CVD, ALD, LPCVD, plasma-enhanced chemical evaporation (PECVD), or the like.

[0030] Fig. Figure 13 illustrates the formation of openings 94 and 96 by etching to expose the contact plugs 84 and the gate electrode 70, respectively. The respective process is described as process 224 in the Fig. The process flow shown in Figure 23 illustrates the process flow 200. The dielectric layer 92 and the ESL 90 can, for example, be etched using photolithography and one or more etching processes. The etching process can include a dry etching process using reactive ion etch (RIE), neutral beam etch (NBE), inductively coupled plasma (ICP), capacitively coupled plasma (CCP), ion beam etch (IBE), and the like, or a combination thereof. The etching process can be anisotropic. In some examples, the etching process includes a plasma using a first gas comprising one or more carbon fluorides, such as CF4, CHF3, CH2F2, CH3F, and the like, or a combination thereof. Other gases, such as N2, H2, argon or the like, can be added.The pressure in each etching chamber can range from approximately 13.33 mPa to approximately 13.33 Pa. The power of the plasma generator for etching can range from approximately 30 watts to approximately 5,000 watts. The substrate bias voltage for the etching process can range from approximately 10 kV to approximately 100 kV, and the duty cycle can range from approximately 5% to approximately 95%.

[0031] According to some embodiments, as in Fig. As shown in Figure 13, the etching process includes a main etching process for etching through the dielectric layer 92 and the ESL 90, so that contact plugs 84 and the gate electrode 70 are exposed. According to some embodiments, an over-etching process is carried out because the over-etching process has a more isotropic effect than the main etching process (for example, by applying a smaller bias voltage than the main etching process). The widths W2 of the sections of the openings 94 and 96 in the contact plugs 84 and the gate electrode 70, respectively, are larger than the widths W1 of the respective overlying sections of the openings 94 and 96 in the dielectric layer 92 and the ESL 90. For example, the ratio W2 / W1 may be greater than about 1.2, or may be in the range between about 1.2 and about 2.0. According to alternative embodiments, the formation of the openings 94 and 96 is stopped when the ESL 90 is etched through, and no over-etching is carried out.The base area of ​​the respective openings 94 and 96 is therefore shown with dashed lines 94A and 96A. Depending on the processing conditions of the over-etching process and its duration, opening 96 can extend into and stop in any of the regions 80, 78, 76, and 74 in the gate electrode 72.

[0032] We turn to Fig. 14 to, where an initial treatment 98 is performed. The respective process is designated as process 226 in the Fig. The process flow shown in Figure 23 is illustrated. A carrier gas, such as argon, can be added. According to some embodiments, the first treatment 98 is a plasma treatment performed using oxygen (O2). The oxygen flow rate can range from about 1,000 sccm to about 9,000 sccm. The temperature of the wafer 10 can range from about room temperature (for example, about 21°C) to about 200°C. The duration of the plasma treatment can range from about 10 seconds to about 300 seconds. The power required to generate the plasma can range from about 1,000 watts to about 4,000 watts, which can be generated using ICP or CCP. The pressure in the respective chamber can range from about 2.66 Pa to about 133.32 Pa.

[0033] According to alternative embodiments, the first treatment 98 is a thermal treatment performed using oxygen (O2) with the plasma switched off, and wherein the temperature of the wafer 10 is raised. The oxygen flow rate can be in the range of approximately 1,000 sccm to approximately 20,000 sccm. The temperature of the wafer 10 can be in the range of approximately 100°C to approximately 400°C. The duration of the thermal treatment can be in the range of approximately 10 seconds to approximately 300 seconds. The pressure in the respective chamber can be in the range of approximately 1333 Pa to approximately 13,332 Paliegen.

[0034] During the first treatment, a surface layer of each of the exposed contact pins 84 and the gate electrode 70 is oxidized, resulting in metal oxide layers 102 (which consist of or comprise tungsten oxide, cobalt oxide, or the like). The metal oxide layer 102 in the opening 96 may contain the oxide of layers 74, 76, 78, and 80, etc., depending on the size of the opening 96. During the etching process ( Fig. 13) During the formation of openings 94 and 96, some unwanted elements may be introduced and may adhere to the exposed surfaces of the contact pins 84 and the gate electrode 70. The unwanted elements may be introduced by the etching gases; they may include carbon, fluorine, nitrogen, or the like, or combinations thereof. These elements cause the surfaces of the exposed contact pins 84 and the gate electrode 70 to be non-uniform. The initial treatment can break the bonds of these elements from the underlying contact pins 84 and the gate electrode 70, so that these unwanted elements can be removed in subsequent processes.

[0035] Furthermore, the surface layers of the dielectric layer 92 can be etched in the process ( Fig. 13) Lose oxygen atoms. For example, if the dielectric layer 92 is formed from or comprises silicon oxide, the dielectric layer 92 may have a Si:O ratio of close to about 1:2 before the etching process. The etching process may cause the Si:O ratio to decrease, for example, to about 1:1.5 (or higher or lower), where the Si:O ratio is an atomic ratio. The first treatment may cause the Si:O ratio in the surface layer 104 ( Fig. 14) of the dielectric layer 92 and the ESL 90 becomes larger. Throughout this description, layer 104 is referred to as a passivated layer of the dielectric layer 92 and the ESL 90. For example, the Si:O ratio can be increased to approximately 1:2.0. It is understood that the inner sections of the dielectric layer 92, which are close to (and in contact with) the passivated layer 104, have a Si:O ratio that is higher than the Si:O ratio in the passivated layer 104. For example, the Si:O ratio in the inner section of the dielectric layer 92 can be in the range between approximately 1:1.4 and approximately 1:1.8.

[0036] We turn to Fig. 15 to, where a second treatment 106 is carried out. The second treatment 106 may include a reduction reaction carried out on oxide layers 102. The respective process is designated as process 228 in the Fig. The process flow 200 shown in Figure 23 illustrates this. According to some embodiments, the second treatment 106 includes a plasma treatment performed using hydrogen (H2), with the plasma switched on. A carrier gas, such as argon, may be added. According to some embodiments, the hydrogen flow rate is in the range of approximately 1,000 sccm to approximately 6,000 sccm. The temperature of the wafer 10 can be in the range of 100°C to approximately 400°C. The duration of the second treatment can be in the range of approximately 10 seconds to approximately 360 seconds. The power required to generate the plasma can be in the range of approximately 1,000 watts to approximately 4,000 watts, which can be generated, for example, using CCP. The pressure in the respective chamber can be in the range of approximately 399.97 Pa to approximately 5999.51 Pa.

[0037] The second treatment results in the metal oxide layers 102 losing oxygen, and consequently, elemental metals (such as tungsten or cobalt) are produced by the reduction reaction. Furthermore, the unwanted elements, such as carbon, fluorine, and nitrogen, which are introduced by the etching process, are also removed. As a result, the surface conditions of the contact plugs 84 and the gate electrode 70 are more uniform due to the first and second treatments.

[0038] Fig. Figure 16 illustrates a bottom-to-top deposition process for forming (top) source / drain contact plugs 108 and a gate contact plug 110. The respective process is described as process 230 in the Fig. The process flow shown in Figure 23 illustrates the process flow 200. According to some embodiments, the bottom-up deposition process is carried out using a thermal CVD process. It is assumed that a thermal CVD process can provide thermal energy to support the formation of nucleation sites for the formation of the contact plug 108 and the gate contact plug 110. According to some embodiments, no plasma is generated in the bottom-up deposition process. The bottom-up deposition process can be carried out using WF6 and H2 as process gases (if tungsten is to be grown). According to some embodiments, the bottom-up deposition process is carried out with the hydrogen flow rate in the range of about 1,000 sccm to about 7,000 sccm and the WF6 flow rate in the range of about 50 sccm to about 450 sccm.The temperature of wafer 10 can range between 200°C and approximately 400°C. The pressure in the respective chamber can range between approximately 1333.22 Pa and approximately 39,996.7 Pa.

[0039] The thermal energy provided by the thermal CVD process can support the incubation of the nucleation sites over a relatively long period. Since the deposition rate is controlled to a relatively low rate, such as less than 1.5 nm per second, the slow growth process allows the nucleation sites to grow slowly. The low deposition rate can be controlled simply by supplying a deposition gas mixture with a relatively low metal precursor ratio in a hydrogen dilution gas mixture, as described in detail below. The nucleation sites preferentially form at certain locations on the substrate that have similar material properties to those of the nucleation sites. For example, since the nucleation sites contain metallic materials, they preferentially tend to adhere to and nucleate at the contact pins 84 and the gate electrode 70.Once the nucleation sites have formed at the selected positions, the elements or atoms can then continue to adhere to and anchor themselves at the nucleation sites, thereby accumulating the elements or atoms at the selected positions and achieving a selective deposition process as well as a bottom-up deposition process. The nucleation sites are selectively incubated on the exposed surfaces of the contact plugs 84 and the gate electrode 70, so that source / drain contact plugs 108 and a gate contact plug 110 can grow vertically from bottom to top to fill the openings 94 and 96. Dashed lines 111 schematically illustrate the top surfaces of the contact plugs 108 and 110 as the bottom-up deposition process progresses.

[0040] The deposited material may contain tungsten or a tungsten alloy. Alternatively, another metal capable of forming a selected phase (which will be discussed in the following paragraphs) may be used to form contact plugs 108 and 110.

[0041] As in Fig. As shown in Figure 16, the contact connectors 108 and 110 can have a lower section comprising a substantially rounded and / or convex structure 108A and 110A, which fills the concave spaces in the contact connectors 84 and the gate electrode 70, respectively. The convex structure 108A and 110A extends laterally and outwards beneath the ESL 90 and below the upper (e.g., horizontal) surface of the ILD 60. The convex structures 108A and 110A can have a depth D1 greater than 1.5 nm, such as in a range between approximately 2 nm and approximately 10 nm, and particularly, for example, in the range between approximately 3 nm and approximately 5 nm, although other depths are also possible. The convex structures 108A contain tip sections 108A1 and 108A2 directly beneath the dielectric layer 92. The tip sections 108A1 and 108A2 are in direct contact with the underside of the ESL 90 and can have a width W3 in a range between approximately 1 nm and approximately 5 nm.The convex structure results in an enlarged interface between contact plugs 108 / 110 and the respective underlying contact plugs 84 and the gate electrode 70, thus reducing contact resistance. Furthermore, the improved interface management provided by the convex structure and the pointed sections also prevents the contact plugs 108 and 110 from unintentionally retracting during the subsequent CMP process.

[0042] The bottom-up deposition process grows the deposited metallic material to a level higher than the top surface of dielectric layer 92. Excess material can be removed in a planarization process, such as a CMP process or mechanical grinding. As a result, the top surface of contact connectors 108 and 110 is coplanar with the top surface of dielectric layer 92. The upper horizontal sections of the passivated layer 104 can optionally be removed by the planarization process.

[0043] The contact connectors 108 and 110 are free of barrier layers (made of titanium nitride, tantalum nitride, or the like). Instead, the contact connectors 108 and 110 can be formed entirely from a homogeneous material, with different sections of the connectors containing the same elements and the same atomic percentages of those elements. Conventional barrier layers significantly increase the resistance of the contact connectors. Furthermore, the resistance of the contact connectors increases exponentially as the contact sections become progressively narrower. Therefore, if the barrier layers are not formed, the resistance of the contact connectors can be significantly reduced.

[0044] Fig. Figure 17 illustrates a structure formed according to alternative embodiments. The formation processes for this structure are essentially the same as those for forming the structure shown in Figure 17. Fig. The structure shown in Figure 16 is identical, except that the bottoms of openings 94 and 96 are located at the positions marked 94A and 96A, as shown in Figure 16. Fig. Figure 13 shows that there is no over-etching. The remaining processes are essentially the same as in the previous embodiments. In the resulting structure, as shown in Fig. As shown in Figure 17, the lower parts of the contact plugs 108 and 110 do not extend laterally in such a way that they lie directly under the ESL 90.

[0045] Tungsten contact plugs can have two phases, an alpha phase and a beta phase. The corresponding tungsten is referred to as alpha-phase tungsten (alpha-W) and beta-phase tungsten (beta-W), respectively. The resistivity of beta-W is much higher (sometimes six times higher) than that of alpha-W. If the first and second treatments are not performed, the phase of the resulting tungsten contact plug is random and cannot be controlled. This results in the resistivity of the tungsten contact plugs varying significantly from plug to plug, and the performance of the resulting components and circuits cannot be controlled. According to some embodiments of the present disclosure, performing the treatments before depositing the contact plugs forms a silicon-rich passivation layer 104.This makes it more likely that the formed contact plugs 108 and 110 are α-W. Furthermore, the removal of unwanted elements (such as F, C, and N) through the treatments ensures that the environment for tungsten growth becomes more uniform throughout wafer 10, and consequently, most (for example, more than 99 percent) of the contact plugs are formed to contain α-W. The device performance through wafer 10 and the dies within it becomes more uniform in this way, as shown in [reference]. Fig. Figure 22 shows what will be discussed in a subsequent paragraph. Furthermore, the formation of α-W results in low resistance values ​​for the contact plugs.

[0046] Fig. Figure 22 illustrates experimental results, showing cumulative percentages of contact resistance values ​​as a function of normalized contact resistance values. The solid circles represent the results of the samples according to the embodiments of the present disclosure. The crosses represent the results of the samples of tungsten plugs (which have no locking mechanism), except that no treatments are performed prior to the deposition of tungsten. Fig. Figure 22 shows that when treatments are performed, the contact resistance values ​​of several contact plugs are much more uniform throughout the entire wafer than when the treatments are not performed.

[0047] Fig. Figures 18 to 20 illustrate cross-sectional views of intermediate stages in the formation of a FinFET and of contact connectors according to alternative embodiments of the present disclosure. Unless otherwise stated, the materials and formation processes of the components in these embodiments are essentially the same as those of the same components in the preceding embodiments described in the Fig. Figures 1-7, 8A, 8B, 9, 10, 11A, 11B and 12-16 are shown, and are labeled with the same reference numbers. Details regarding the educational process and materials are provided in the Fig. The components shown in 18 to 20 are therefore found in the discussion of the embodiment given in the preceding embodiments.

[0048] The initial steps of these embodiments are essentially the same as those in the Fig. 1-7, 8A, 8B, 9, 10, 11A, 11B and 12-13 are shown. Next, as in Fig. Figure 18 shows a first treatment 128 performed to selectively deposit dopant-containing layers 130 in the openings 94 and 96 and on the contact plugs 84 and the gate electrode 72. The deposition can be carried out in a CVD chamber with the plasma switched on, and the respective precursor comprises a dopant that may contain silicon, boron, and phosphorus, or a combination thereof. For example, if silicon is to be deposited for the treatment, SiH4, Si2H6, or the like may be introduced. If boron is to be deposited, BH3, B2H6, or the like may be used. If phosphorus is to be deposited, PH3 or the like may be used.According to some embodiments, the deposition can be carried out with a flow rate of the aforementioned precursor in the range of approximately 10 sccm to approximately 500 sccm; the wafer temperature is in the range of approximately 100°C to approximately 400°C, and the chamber pressure is in the range of approximately 13.33 Pa to approximately 399.97 Pa. The resulting layer 130 can have a thickness in the range of approximately 0.3 nm to approximately 3 nm. Dopant-containing layers 130 can optionally be formed on the surfaces of the dielectric layer 92 and the ESL 90.

[0049] Fig. Figure 19 illustrates the second treatment, 106. Details of this process can be found in the discussion of treatment 106, as in Fig. 15 shown, which is why the details are not repeated here. As a result of the second treatment 106, the unwanted elements introduced by the etching process ( Fig. 13) were introduced, are removed. The deposited dopant-containing layers 130 are transformed into layer 134, which is similar to the dopant-containing layers 130 but contains purer silicon, boron, or phosphorus. According to some embodiments, the atomic percentages of silicon, boron, or phosphorus in layer 134 can be higher than about 2 percent and can range between about 2 percent and about 20 percent.

[0050] According to alternative embodiments, instead of depositing layer 130, an implantation process can be carried out in which silicon, boron, phosphorus, arsenic, or combinations thereof are implanted. Accordingly, the dopant-containing layers 130 represent in Fig. 18 The implanted surface layers of the contact plugs 84 and the gate electrode 72 and the implanted surface layers of the dielectric layer 92 and 90. The implantation is carried out using low energy, for example, less than about 10 keV, so that a flat surface layer of each of the contact plugs 84 and the gate electrode 70 is implanted. For example, the implanted species can be distributed within a surface layer of the contact plugs 84 and the gate electrode 70 and have a thickness of less than about 5 nm. The implantation can also include vertical and inclined implantation, so that the dopant-containing layers 130 can be formed on the sidewalls of the dielectric layer 92 and 90.The tilt implantation can be performed while the wafer 10 is rotated, and the tilt angle can be, for example, between approximately 10 degrees and approximately 20 degrees. It is understood that, due to the shadowing of the dielectric layer 92, the implanted species is more strongly concentrated in a region oriented vertically to the respective openings 94 and 96. After implantation (the first treatment), the second treatment 106 can be performed, as shown in [reference]. Fig. 19 shown, to be carried out. The second treatment 106 can be essentially the same as in Fig. 15, and the details will not be repeated here.

[0051] Fig. Figure 20 illustrates the selective bottom-to-top deposition process for forming contact connectors 108 and 110 according to some embodiments. The deposition process may be essentially the same as described in reference to Fig. This was discussed in Section 16, and consequently the details are not repeated here. If the dopant-containing layers 130 are the deposited layers, then—since the layers 130 are thin—tungsten can grow from the gaps between the molecules or atoms of the material of the dopant-containing layers 130. The effect of the elements in the dopant-containing layers 130 (deposited or implanted) makes it more likely that the formed contact plugs 108 and 110 are β-W. Furthermore, the elements on the surfaces of, or within, the dielectric layer 92 and the ESL 90 make it more likely that the formed contact plugs 108 and 110 are β-W. Experimental results indicate that in these embodiments, most (for example, more than 99 percent) of the contact plugs are formed from β-W. The device performance through the wafer 10 and the dies therein is thus more uniform.Although β-W has a higher resistivity than α-W, the uniformity within the wafer is improved, which more than compensates for the deterioration due to the higher resistivity.

[0052] Due to thermal processes, such as the deposition of contact plugs 108 and 110 and the subsequent thermal processes, atoms from the dopant-containing layers 130 can diffuse into the overlying contact plugs 108 and 110 and the underlying contact plugs 84 and the gate electrode 70 in the final structure, leading to the formation of dopant-rich regions 136. The essentially pure dopant-containing layers 130, on the other hand, may no longer exist. The dopant-rich regions 136 include the lower sections of contact plugs 108 and 110 and the upper sections of contact plugs 84 and the gate electrode 70.The concentrations of the dopant (such as silicon, boron, phosphorus, and / or arsenic) in the dopant-rich regions 136 are also higher than in the overlying sections of the contact connectors 108 and 110 and the underlying sections of the contact connectors 84 and the gate electrode 70, which may optionally be free of dopant. According to some embodiments, the thickness T1 of the dopant-rich regions 136 can be in the range of approximately 0.3 nm to approximately 5 nm. Furthermore, the shape of the dopant-rich regions 136 can follow the shape of the interface between the contact connectors 108 and 110 and the underlying contact connectors 84 and the gate electrode 70.

[0053] Furthermore, due to the diffusion of the dopant into the contact pins 108 and 110 and the surface layers of the dielectric layer 92 and the ESL 90, dopant-rich regions 138 can be formed in the final structure. These dopant-rich regions 138 contain sections of the dielectric layer 92 with the diffused dopant, and consequently, these sections have higher concentrations of the dopant than the inner parts of the dielectric layer 92. Additionally, the dopant can diffuse slightly into the sidewall sections of the contact pins 108 and 110, which may be distinguishable from one another. Accordingly, these sections of the contact pins 108 and 110 have higher concentrations of the dopant than the inner parts of the contact pins 108 and 110, which may be free of the dopant.According to some embodiments, the thickness T2 of the doping-rich regions 138 can be in the range between about 0.3 nm and about 5 nm.

[0054] Fig. Figure 21 illustrates a structure formed according to alternative embodiments. The formation processes for this structure are essentially the same as those for forming the structure shown in Figure 21. Fig. 20 structure shown, with the exception that when forming openings ( Fig. 13) the bottoms of openings 94 and 96 are essentially on the same plane as the bottom surfaces of ESL 90. The remaining processes are essentially the same as in the previous embodiments. In the resulting structure, as in Fig. As shown in Figure 21, the lower parts of the contact connectors 108 and 110 do not extend laterally in such a way that they lie directly under the ESL 90 and the ILD 92. Furthermore, doping-rich regions 136 and 138 can be formed.

[0055] The embodiments of the present disclosure have several advantageous features. By performing treatments on the top surfaces of lower metal structure elements before the upper metal structure elements are formed on the lower metal structure elements, the upper metal structure elements can have a more uniform phase formation, with most of the upper metal structure elements having the same phase and consequently a similar resistivity. Accordingly, the uniformity of the device performance of the devices containing the upper metal structure elements is more uniform within the wafer.

[0056] A method according to the invention comprises the following: forming a first metallic structural element; forming a dielectric layer over the first metallic structural element; etching the dielectric layer to form an opening, wherein a top surface of the first metallic structural element is exposed through the opening; performing a first treatment on the top surface of the first metallic structural element, wherein the first treatment is performed through the opening, the first treatment starting at a time when a horizontal surface of the dielectric layer is exposed, and the first treatment being performed using a first process gas, the first treatment comprising a thermal treatment; after the first treatment, performing a second treatment, wherein the second treatment is performed through the opening, and the second treatment is performed using a second process gas.which differs from the first process gas; and deposition of a second metallic structural element in the opening. In one embodiment, the first treatment is performed using the first process gas, which comprises oxygen (O2), and the second treatment is performed using the second process gas, which comprises hydrogen (H2). In one embodiment, the first treatment comprises plasma treatment. In one embodiment, the first treatment comprises thermal treatment. In one embodiment, the deposition of the second metallic structural element comprises bottom-to-top deposition of tungsten. In one embodiment, the first treatment is performed using the first process gas, which comprises a silicon-containing process gas, a boron-containing process gas, a phosphorus-containing process gas, or combinations thereof. In one embodiment, the first treatment results in the deposition of a layer,which comprises silicon, boron, phosphorus, or combinations thereof. In one embodiment, the first metallic structural element comprises a source / drain contact connector. In another embodiment, the first metallic structural element comprises a gate electrode, and the second metallic structural element comprises a contact connector.

[0057] Another method according to the invention comprises the following: forming a first metallic structural element, wherein the first metallic structural element comprises a gate electrode or a source / drain contact connector of a transistor; forming an etch stop layer over the first metallic structural element; forming a dielectric layer over the etch stop layer; etching the dielectric layer and the etch stop layer to form an opening, wherein the first metallic structural element is exposed towards the opening; oxidizing a surface layer of the first metallic structural element to form a metal oxide layer on a surface of the first metallic structural element, wherein the oxidation of the surface layer is carried out by thermal oxidation; carrying out a reduction reaction to reduce the metal oxide layer back to an elemental metal;and performing a bottom-to-top deposition process to deposit a tungsten connector in the opening. In one embodiment, the oxidation is carried out using oxygen (O2) as a process gas. In one embodiment, the reduction reaction is carried out using hydrogen (H2) as a process gas. In one embodiment, the surface layer is oxidized by plasma oxidation. In one embodiment, the surface layer is oxidized by thermal oxidation. In one embodiment, the tungsten connector has an alpha phase.

[0058] According to some non-inventive embodiments of the present disclosure, an integrated circuit device comprises a first metallic structural element comprising a first section and a second section above the first section, wherein the second section comprises an element selected from the group consisting essentially of silicon, boron, phosphorus, arsenic and combinations thereof, and the first section is free of the element; a dielectric layer above the first metallic structural element; and a second metallic structural element above the first metallic structural element, and with a section in the dielectric layer, wherein the second metallic structural element comprises a third section and a fourth section above the third section, the third section being above, and in contact with, the second section to form an interface between them.and wherein the third section comprises the element, and the fourth section is free of the element. In one embodiment, the integrated circuit device further comprises an element-rich region adjacent to an interface between side walls of the second metallic structural element and the dielectric layer, wherein the element-rich region comprises the element, and the element-rich region comprises a side wall surface section of the second metallic structural element and a side wall surface section of the dielectric layer. In a non-inventive embodiment, the element comprises silicon. In a non-inventive embodiment, the first metallic structural element comprises a lower source / drain contact connector or a gate electrode of a transistor,and the second metallic structural element comprises an upper source / drain contact connector or a gate contact connector of the transistor. In a non-inventive embodiment, the second metallic structural element comprises tungsten.

Claims

[1] Procedure comprising the following: Formation of a first metallic structural element (72, 84); Formation of a dielectric layer (92) over the first metallic structural element (72, 84); Etching of the dielectric layer to form an opening (94, 96) exposing a top surface of the first metallic structural element (72, 84) through the opening (94, 96); Performing a first treatment on the top surface of the first metallic structural element (72, 84), wherein the first treatment oxidizes a surface layer of the first metallic structural element (72, 84), wherein the first treatment is performed through the opening (94, 96), wherein the first treatment starts at a time when a horizontal surface of the dielectric layer (92) is exposed, and the first treatment is performed using a first process gas, wherein the first treatment comprises a thermal treatment in a temperature range of 100°C to 400°C; after the first treatment, a second treatment is carried out, the second treatment being carried out through the opening (94, 96), and the second treatment being carried out using a second process gas that differs from the first process gas; and Deposition of a second metallic structural element (108, 110) in the opening (94, 96). [2] Method according to claim 1, wherein the first treatment is carried out using the first process gas comprising oxygen and the second treatment is carried out using the second process gas comprising hydrogen. [3] Method according to claim 2, wherein the first treatment comprises a plasma treatment. [4] Method according to any of the preceding claims, wherein the deposition of the second metallic structural element (108, 110) comprises a bottom-to-top deposition of tungsten. [5] Method according to any of the preceding claims, wherein the first treatment is carried out using the first process gas comprising a silicon-containing process gas, a boron-containing process gas, a phosphorus-containing process gas or combinations thereof. [6] Method according to claim 5, wherein the first treatment results in the deposition of a layer comprising silicon, boron, phosphorus or combinations thereof. [7] Method according to any of the preceding claims, wherein the first metallic structural element (72, 84) comprises a source / drain contact connector (84). [8] Method according to one of the preceding claims, wherein the first metallic structural element (72, 84) comprises a gate electrode (72) and the second metallic structural element (108, 110) comprises a contact plug (108, 110). [9] Procedure comprising the following: Forming a first metallic structural element (72, 84), wherein the first metallic structural element (72, 84) comprises a gate electrode (72) or a source / drain contact plug (84) of a transistor; Forming an etch stop layer (90) over the first metallic structural element (72, 84); Forming a dielectric layer (92) over the etch stop layer (90); Etching of the dielectric layer (92) and the etch stop layer (90) to form an opening (94, 96) wherein the first metallic structural element (72, 84) is exposed towards the opening (94, 96); After forming the opening (94, 96): oxidizing a surface layer of the first metallic structural element (72, 84) to form a metal oxide layer (102) on a surface of the first metallic structural element (72, 84), wherein the oxidation of the surface layer is carried out by thermal oxidation; Performing a reduction reaction to reduce the metal oxide layer (102) back to an elemental metal; and Performing a bottom-to-top deposition process to deposit a tungsten plug in the opening (94, 96). [10] Method according to claim 9, wherein the oxidation is carried out using oxygen as a process gas. [11] Method according to claim 9 or 10, wherein the reduction reaction is carried out using hydrogen as a process gas. [12] Method according to any one of the preceding claims 9 to 11, wherein the oxidation of the surface layer is carried out by plasma oxidation. [13] Method according to any one of the preceding claims 9 to 12, wherein the tungsten connector has an alpha phase.

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