Transistor layout and dimensioning for high-speed applications

Abstract

Semiconductor device comprising: a first device type (200), the first device type (200) comprising: a first fin structure (104, 210) extending in a first direction (X); a first gate (230-234) enclosing the first fin structure (210), the first gate (230-234) extending in a second direction (Y) different from the first direction (X) and having a first gate dimension (290) measured in the first direction (X); and a plurality of first slot contacts (250-253) spaced apart in the first direction (X), wherein a first slot contact (250-253) is disposed over the first fin structure (104, 210), the first slot contact (250-253) having a first slot contact dimension (294) measured in the first direction (X); and one or more continuous first metal lines (260-263) each extending in the first direction (X) and electrically coupled to each of at least a subset of the first slot contacts (250-253); and a second device type (400), the second device type (400) comprising: a second fin structure (410) extending in the first direction (X); a second gate (430-434) enclosing the second fin structure (410), the second gate (430-434) extending in the second direction (Y) different from the first direction (X) and having a second gate dimension (490) measured in the first direction (X); and a plurality of additional second slot contacts (450-453) spaced apart in the first direction (X), wherein a second slot contact is disposed over the second fin structure (410), the second slot contact having a second slot contact dimension (494) measured in the first direction (X), the second slot contact dimension (494) being greater than the second gate dimension (490) and greater than the first slot contact dimension (494); and a plurality of metal islands (464-469), each electrically coupled to a different one of the second slot contacts (450-453).

Description

BACKGROUND

[0001] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technical advances in IC materials and designs have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are necessary. As integrated circuits have evolved, feature density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.However, conventional transistor layout designs have not been optimized for high-speed IC applications, where device performance can be significantly affected by parasitic capacitances and / or resistances.

[0002] Therefore, existing semiconductor IC devices, although generally suitable for their intended purposes, were not entirely satisfactory in every aspect.

[0003] Manufacturing methods of semiconductor devices are known, for example, from DE 10 2016 119 017 A1 and DE 10 2017 128 233 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, in accordance with common practice in the industry, various elements are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. It is also emphasized that the accompanying drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of the scope, as the invention may be equally applicable to other embodiments. Fig. 1 shows a perspective view of an exemplary FinFET device. The Fig. 2, 3A to 3B, 4A to 4B, 5A to 5B, 6A to 6B, 7A to 7B and 8A to 8B show top views of a portion of a semiconductor device according to embodiments of the present disclosure. The Fig. 3C, 4C, 5C, 6C to 6D, 7C to 7D and 8C to 8D show cross-sectional side views of a portion of a semiconductor device according to embodiments of the present disclosure. Fig. 9 shows a flowchart illustrating a method according to embodiments of the present disclosure. Fig. 10 shows a semiconductor manufacturing facility according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0007] Further, when a number or range of numbers is described with "about," "approximately," and the like, the term is intended to encompass numbers that are within a reasonable range of the described number, such as within 10% of the described number or other values ​​as understood by one of ordinary skill in the art. For example, the term "about 5 nm" includes the dimensional range of 4.5 nm to 5.5 nm.

[0008] As semiconductor device sizes continue to shrink, parasitic capacitances and / or resistances may play a more significant role in affecting the performance of a semiconductor device, particularly for high-speed applications such as serializer / deserializer devices or radio frequency (RF) devices. However, layout designs of conventional semiconductor devices have primarily focused on optimizing the performance of non-high-speed applications, such as logic devices. A layout design otherwise suitable for non-high-speed applications may result in excessive parasitic capacitances and / or resistances for high-speed devices, which could adversely affect the performance of the high-speed devices.

[0009] To solve the problems described above, the present disclosure relates to novel and non-obvious layout schemes that change the size or shift the various components of a semiconductor device, including, but not limited to, conductive contacts, vias, or metal lines, as described in more detail below.

[0010] It is understood that embodiments of the present disclosure may be applied to a variety of IC and / or transistor types. For example, the present disclosure may be applied to planar devices, fin-type field-effect transistor (FinFET) devices (which may be a two-dimensional structure or a three-dimensional structure), vertical gate-all-around (GAA) devices, horizontal GAA devices, nanowire devices, nanosheet devices, or combinations thereof. To provide an example, Fig. 1, an exemplary FinFET device is shown. However, it should be understood that the application should not be limited to any particular device type except as specifically claimed.

[0011] In Fig. 1 shows a perspective view of an exemplary FinFET device 10. The FinFET device structure 10 includes an n-type FinFET (NMOS) device structure 15 and a p-type FinFET (PMOS) device structure 25. The FinFET device structure 10 includes a substrate 102. The substrate 102 may be made of silicon or other semiconductor materials. Alternatively or additionally, the substrate 102 may include other elemental semiconductor materials such as germanium. In some embodiments, the substrate 102 is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, substrate 102 may include an epitaxial layer overlying a bulk semiconductor.

[0012] The FinFET device structure 10 also includes one or more fin structures 104 (e.g., Si fins) extending from the substrate 102 in the Z-direction and surrounded by spacers 105 in the Y-direction. The fin structures 104 are elongated in the X-direction and may optionally comprise germanium (Ge). The fin structure 104 may be formed using suitable processes such as photolithography and etching processes. In some embodiments, the fin structure 104 is etched from the substrate 102 using dry etching or plasma processes. In some further embodiments, the fin structure 104 may be formed by a double-pattern lithography (DPL) process. DPL is a method of creating a structure on a substrate by dividing the structure into two nested structures. DPL enables improved functional density (e.g., of the fins).The fin structure 104 also includes an epitaxially grown material 12, which (along with portions of the fin structure 104) may serve as the source / drain of the FinFET device structure 10. In some embodiments, for an NFET, the epitaxially grown material may include SiP, SiC, SiPC, SiAs, Si, or combinations thereof. In some embodiments, for a PFET, the epitaxially grown material may include SiGe, SiGeC, Ge, Si, a boron-doped material, or combinations thereof.

[0013] An isolation structure 108, such as a shallow trench isolation (STI) structure, is formed to surround the fin structure 104. In some embodiments, a lower portion of the fin structure 104 is surrounded by the isolation structure 108, and an upper portion of the fin structure 104 protrudes from the isolation structure 108, as shown in Fig. 1. In other words, a portion of the fin structure 104 is embedded in the isolation structure 108. The isolation structure 108 prevents electrical interference or crosstalk.

[0014] The FinFET device structure 10 further includes a gate stack structure having a gate electrode 110 and a gate dielectric layer (not shown) beneath the gate electrode 110. The gate electrode 110 may comprise polysilicon or metal. The metal includes tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials. The gate electrode 110 may be formed in a gate-last (or gate-replacement) process. Hard mask layers 112 and 114 may be used to define the gate electrode 110. A dielectric layer 115 may also be formed on the sidewalls of the gate electrode 110 and over the hard mask layers 112 and 114.

[0015] The gate dielectric layer (not shown) may comprise dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, one or more high-k dielectrics, or combinations thereof. Examples of high-k dielectrics include hafnium oxide, zirconium oxide, alumina, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or combinations thereof.

[0016] In some embodiments, the gate stack structure includes additional layers, such as interface layers, capping layers, diffusion / barrier layers, or other applicable layers. In some embodiments, the gate stack structure is formed over a central portion of the fin structure 104. In some further embodiments, multiple gate stack structures are formed over the fin structure 104. In some further embodiments, the gate stack structure includes a dummy gate stack and is later replaced with a metal gate (MG) after high thermal budget processes have been performed.

[0017] The gate stack structure is formed through a deposition process, a photolithography process, and an etching process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), and plasma-enhanced CVD (PECVD), plating, other suitable processes, and / or combinations thereof. The photolithography processes include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. Alternatively, the photolithography process is implemented or replaced by other suitable processes such as maskless photolithography, electron beam writing, and ion beam writing.

[0018] FinFET devices offer several advantages over conventional metal-oxide-semiconductor field-effect transistor (MOSFET) devices (also referred to as planar transistor devices). These advantages may include better chip area efficiency, improved carrier mobility, and manufacturing processing compatible with the production processing of planar devices. Therefore, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for part or all of the IC chip. Various aspects of the present disclosure are described below using ICs implemented using FinFET devices.However, it should be understood that this is only to provide an example, and that the present disclosure is not limited to FinFET devices and is applicable to planar devices, GAA devices, nanowire devices, or nanosheet devices, etc.

[0019] Fig. 2 shows a top view of a semiconductor device 200 according to an embodiment of the present disclosure. The semiconductor device 200 may be implemented as FinFET transistors in some embodiments. The semiconductor device 200 may represent (or include) a logic device, for example, a circuit comprising NOR gates, NAND gates, XOR gates, inverter gates, etc. Alternatively, the semiconductor device 200 may also represent (or include) non-logic devices, for example, high-speed devices that have not been optimized by the various aspects of the present disclosure. This is because conventional IC layout designs do not distinguish between logic devices and non-logic devices. As such, from a layout perspective, logic devices and non-logic devices may appear substantially the same.However, this is not the case according to the present disclosure, as will become clearer from the following descriptions.

[0020] The semiconductor device 200 includes a fin structure 210. The fin structure 210 may also be referred to as an active region. The fin structure 210 may be an embodiment of the fin structure 104 of Fig. 1. The fin structure 210 may also comprise epitaxially grown layers. The channel region and the source / drain region of the FinFET devices are formed by different sections of the fin structure 210. As shown in Fig. 2, the fin structure 210 is elongated and extends in the X-direction (the same X-direction as in Fig. 1).

[0021] The semiconductor device 200 includes a plurality of gate structures 230-234, each partially enclosing the fin structure 210. The gate structures 230-234 may each include a high-k gate dielectric and a metal gate electrode, for example, the gate electrode 110 of Fig. 1. The manner in which the gate structures 230-234 enclose the fin structure 210 is similar to the manner in which the gate electrode 110 encloses the fin structure 104 in Fig. 1. As in Fig. 2, the gate structures 230 - 234 are each elongated and extend in the Y-direction (the same Y-direction as in Fig. 1), which is perpendicular to the X-direction.

[0022] The semiconductor device 200 includes a plurality of slot contacts 250-253. The slot contacts 250-253 each include one or more electrically conductive layers. For example, the electrically conductive layers may include Ti, TiN, Pt, Co, Ru, W, TaN, Cu, or combinations thereof. The slot contacts 250-253 each extend elongated in the Y direction. As shown in Fig. As shown in Figure 2, the slot contacts 250-253 intersect with various portions of the fin structure 210 (or the epilayers formed thereon). The portions of the fin structure 210 (or the epilayers formed thereon) may be the source / drain regions of the FinFET devices, and thus the slot contacts 250-253 may provide electrical connection to the source / drain regions.

[0023] The semiconductor device 200 also includes a plurality of metal lines 260-263. The metal lines 260-263 are located above the fin structure 210 and the gate structures 230-234 and are part of a multilayer interconnect structure that includes metal lines and vias for electrically connecting various components of an IC. The metal lines 260-263 may be implemented in the lower interconnect layer—referred to as the Mo layer (or metal-o layer)—of the multilayer interconnect structure. The metal lines 260-263 may each extend elongated in the X direction.

[0024] The semiconductor device 200 includes a plurality of source / drain vias 270-273. The source / drain vias 270-273 are vertically (e.g., in the Z-direction of Fig. 1) between the slot contacts 250-253 and the metal lines 261-262. For example, the source / drain via 270 is arranged between the slot contact 250 and the metal line 261, the source / drain via 271 is arranged between the slot contact 251 and the metal line 262, the source / drain via 272 is arranged between the slot contact 252 and the metal line 261, and the source / drain via 273 is arranged between the slot contact 253 and the metal line 262. Thus, the slot contacts 250-253, the metal lines 261-262, and the source / drain vias 270-273 collectively provide electrical connection to the source / drain regions of the FinFET devices.

[0025] The semiconductor device 200 includes a plurality of gate contacts 280-289. The gate contacts 280-289 are vertically (e.g., in the Z-direction of Fig. 1) between the gate structures 230-234 and the metal lines 260 and 263. For example, the gate contacts 280-284 are arranged between the metal line 260 and the gate structures 230-234, and the gate contacts 285-289 are arranged between the metal line 263 and the gate structures 230-234. Thus, the metal lines 260, 263, and the gate contacts 280-289 together provide an electrical connection to the gates of the FinFET devices.

[0026] The dimensions of the various components described above are optimized for logic devices. For example, the gate structures 230-234 may each have a minimum gate length 290 measured in the X-direction. The minimum gate length 290 may also be referred to as a critical dimension (CD) of the semiconductor device 200. A contacted gate pitch (CPP) 292 is measured as a distance between adjacent ones of the gate structures 230-234 (e.g., between the gate structures 230-231). The minimum gate length 290 and the CPP 292 for logic devices are designed to be close for power / performance / area (PPA) reasons. In some embodiments, a ratio of the CPP 292 and the minimum gate length 290 may range between about 2:1 and about 4:1.

[0027] The slot contacts 250-253 may each have a dimension 294, which is also measured laterally in the X-direction. To optimize the performance of the logic devices of the semiconductor device 200, the dimension 294 may be substantially similar in size to the minimum gate length 290. For example, a ratio of the dimension 294 and the minimum gate length 290 may range between about 0.8:1 and about 1.3:1.

[0028] The source / drain vias 270-273 may each have a dimension 296 measured in the X-direction. To optimize the performance of the logic devices of the semiconductor device 200, the dimension 296 may be comparable to the dimension 294. For example, a ratio of the dimension 296 to the dimension 294 may range between about 0.7:1 and about 1.3:1.

[0029] Although the sizing of the various components of semiconductor device 200 optimizes the performance of the logic devices, they may not be ideal for other types of devices on an IC, such as transistors in high-speed applications. In some embodiments, a high-speed device may be a device operating at a data rate greater than 10 gigabits per second (Gbps) and may include, as non-limiting examples, a serializer / deserializer device or a radio frequency (RF) device.

[0030] Transistors in high-speed applications may be more sensitive to parasitic capacitance and / or parasitic resistance. Unfortunately, the device sizing scheme used for logic devices such as those in semiconductor device 200 may increase the parasitic capacitance and / or parasitic resistance, making such a device sizing scheme less suitable for non-logic devices such as high-speed devices. To address this issue, the present disclosure uses a different sizing scheme for non-logic devices (e.g., high-speed devices). It should be understood that the non-logic devices may be implemented on the same chip as the logic devices of semiconductor device 200.

[0031] An example dimensioning scheme is shown in the Fig. 3A, Fig. 3B and Fig. 3C. In this respect, the Fig. 3A to 3B show various plan views of a semiconductor device 400A that is a non-logic device (e.g., a high-speed device), and Fig. 3C shows a cross-sectional side view of the semiconductor device 400A, wherein the cross section is taken along a section line AA' of Fig. 3A. Since the section line AA' extends along the X-direction, Fig. 3C may also be referred to as an X-cut. In some embodiments, the semiconductor device 200 and the semiconductor device 400A may be fabricated on the same IC (but in different sections or regions of the IC). However, it should be understood that the Fig. 2 shown X-direction for the semiconductor device 200 may be the same or different than that shown in the Fig. 3A to 3C for the semiconductor device 400A. The same may apply to the Y direction.

[0032] Referring to the Fig. 3A and Fig. 3C, the semiconductor device 400A may have a fin structure 410 that is similar to the fin structure 210 of Fig. 2, a plurality of gate structures 430 - 434 which are similar to the gate structures 230 - 234 of Fig. 2, a plurality of slotted contacts 450 - 453 which are similar to the slotted contacts 250 - 253 of Fig. 2, a plurality of metal lines 460 - 463 which correspond to the metal lines 260 - 263 of Fig. 2, a plurality of source / drain vias 470 - 473, which correspond to the source / drain vias 270 - 273 of Fig. 2, and have a plurality of gate contacts 480 - 489 which correspond to the gate contacts 280 - 289 of Fig. 2. As shown in the cross-sectional view of Fig. 3C, the fin structure 410 may include a crystalline semiconductor fin portion 410B and epilayer portions 410A epitaxially grown on the semiconductor fin portion 410B. The similarity between these components may relate to their manufacturing methods / processes, material compositions, functionality, or even certain layout arrangements, etc. However, unlike the components of the semiconductor device 200, the components of the semiconductor device 400A may have different dimensioning schemes to minimize parasitic capacitance and / or parasitic resistance.

[0033] More specifically, the gate structures 430-434 may each have a minimum gate length 490 measured in the X-direction. The minimum gate length 490 is substantially equal in size to the minimum gate length 290 of Fig. 2. In other words, the gate structures 230-234 and the gate structures 430-434 are substantially similar in size. In some embodiments, a ratio of the minimum gate length 490 and the minimum gate length 290 may range from about 1.1:1 to about 0.9:1.

[0034] Still referring to the Fig. 3A and Fig. 3C, semiconductor device 400A has a significantly larger CPP 492 compared to semiconductor device 200. In some embodiments, a ratio of CPP 492 and CPP 492 ranges between about 1.1:1 and about 2:1. The increased CPP 492 also changes its relationship to the minimum gate length 490. In some embodiments, a ratio of CPP 492 and gate length 490 ranges between about 4:1 and about 8:1. Increasing the CPP effectively increases a distance between two conductive plates of a parasitic capacitor (e.g., the conductive plates may be the two adjacent gate structures). Since capacitance is inversely correlated with the distance between two conductive plates, increasing the CPP 492 reduces the parasitic capacitance of semiconductor device 400A, which in turn improves its performance, such as speed.

[0035] The enlargement of the CPP 492 also offers more space for the extension of the slotted contacts 450 - 453. As in the Fig. 3A and Fig. 3C, the slotted contacts 450-453 may each have a dimension 494 measured in the X-direction. Compared to the dimension shown in Fig. 2, dimension 494 is substantially larger. In some embodiments, a ratio of dimension 494 to dimension 294 ranges between about 1.5:1 and about 3:1.

[0036] The extension or enlargement of the slot contacts 450-453 may also be reflected in their size relative to the source / drain vias arranged thereon. For example, the source / drain vias 470-473 may each have a lateral dimension 496 measured in the X-direction. While the source / drain vias 270-273 may each be substantially larger than each of the slot contacts 250-253, the source / drain vias 470-473 may not be larger than each of the slot contacts 450-453, for example, they may be approximately the same size or smaller than each of the slot contacts 450-453. In some embodiments, a ratio of the dimension 496 and the dimension 494 ranges between about 1:1 and about 0.8:1.

[0037] Increasing the size of the slot contacts 450-453 effectively increases the interface surface area between the slot contacts 450-453 and the source / drain vias 470-473. Parasitic resistance may be generated due to the interface between the slot contacts 450-453 and the source / drain vias 470-473. Since resistance is inversely correlated with the interface surface area, increasing the size of the slot contacts 450-453 reduces the parasitic resistance of the semiconductor device 400A, which in turn improves its performance, such as speed.

[0038] As described above, the metal lines 460 - 463 belong to a metal-o-layer of a multilayer interconnect structure. Fig. Figure 3B shows the top view of another metal layer of the multilayer interconnect structure: the metal 1 layer, which is located above the metal o layer. For example, Fig. 3B Metal lines 500 - 503 of the metal 1 layer. The metal lines 500 - 503 each run elongated in the Y direction (e.g., perpendicular to the metal lines 460 - 463). The metal lines 460 - 463 are also shown in Fig. 3B. Metal lines 500-501 overlap or intersect with metal lines 460-461 in plan view, and metal lines 502-503 overlap or intersect with metal lines 462-463 in plan view. Metal lines 500-503 may also include a conductive material similar to that of metal lines 460-463, for example, materials including copper, aluminum, titanium, tungsten, etc.

[0039] A plurality of vias 520-523 are disposed between the metal 0 and metal 1 layers to electrically connect them. Specifically, via 520 is disposed between metal lines 461 and 500, via 521 is disposed between metal lines 461 and 501, via 522 is disposed between metal lines 462 and 502, and via 523 is disposed between metal lines 462 and 503.

[0040] The Fig. 4A, Fig. 4B and Fig. 4C show another embodiment of the present disclosure. More specifically, the Fig. 4A to 4B, similar to the Fig. 3A to 3B, the plan views of a semiconductor device 400B at different levels. And similar to Fig. 3C shows Fig. 4C shows the cross-sectional side view of the semiconductor device 400B, wherein the cross section is taken along the section line AA', although the location of the section line AA' in Fig. 4A extends from the location of the intersection line AA' in Fig. 3A. For consistency and clarity, similar components used in the Fig. 3A to 3C and the Fig. 4A to 4C are labeled alike, and their details are not repeated here. It should also be understood that the device dimensioning of semiconductor device 400B may be similar to that of semiconductor device 400A (unless specifically stated otherwise). Thus, semiconductor device 400B achieves similar benefits as offered by semiconductor device 400A, such as reduced parasitic resistance and / or reduced parasitic capacitance, which in turn improves device performance, such as speed.

[0041] A difference between the semiconductor device 400A and the semiconductor device 400B is that the semiconductor device 400B, instead of two metal lines 461-462 over the slot contacts 450-453 (see Fig. 3A), a plurality of metal "islands" 464-469 are implemented over the slotted contacts 450-453. These metal islands 464-469 may still be formed in the metal-o-layer and may be formed using similar manufacturing processes as to form the metal lines 461-462, although they are structured differently. Fig. The dashed boxes shown in Figure 4C represent the sections of the metal line 461 (see Fig. 3C) that are "missing" due to the implementation of the metal islands 465 - 568. As in Fig. 4C, metal island 465 is disposed between vias 470 and 520, metal island 466 is disposed between vias 471 and 521, metal island 467 is disposed between vias 472 and 522, and metal island 468 is disposed between vias 473 and 523.

[0042] The implementation of the metal islands 464-469 allows the vias 470-473 to be more "centered" compared to the semiconductor device 400A. For example, in the Fig. In the semiconductor device 400A shown in Figure 3A, the vias 470 and 472 are arranged to intersect with the metal line 461 in a top view, while the vias 471 and 473 are arranged to intersect with the metal line 462 in a top view. As a result, the vias 470 and 472 are not aligned with the vias 471 and 473. In comparison, the vias 470-473 in the semiconductor device 400B are substantially aligned in the X direction. The fact that each of the vias 470-473 can be electrically routed to a respective one of the metal lines 500-503 through a respective one of the metal islands 465-468 means that the source / drain regions (e.g., the epi layers 410A) have a more direct and shorter electrical path to the metal lines 500-503. This helps to reduce the resistance (e.g.,the parasitic source / drain resistance) and in turn improves the performance of the semiconductor device 400B, such as speed.

[0043] Another advantage of the semiconductor device 400B is that the gate contacts 480-484 are now arranged closer to the gate contacts 485-489. As in Fig. As shown in Figure 4A, a distance 550 separates gate contact 484 from the nearest gate contact 489 in the Y direction. Note that the same distance 550 separates the other pairs of gate contacts 480 / 485, 481 / 486, 482 / 487, and 483 / 488.

[0044] In comparison, a larger distance 560 separates the gate contact 484 from the nearest gate contact 489 in the Y direction in the semiconductor device 400A in Fig. 3A. Shortening the distance between the gate contacts (i.e., the smaller distance 550 versus the larger distance 560) results in a reduction in parasitic gate resistance, which in turn improves the performance of the semiconductor device 400B, such as speed.

[0045] Another difference between semiconductor devices 400A and 400B is the extent of the “active fin extension” associated with the slot contact. For example, as shown in Fig. 4A, the slot contact 450 (as an example of one of the slot contacts 450-453) extends a distance 570 in the Y direction beyond the fin structure 410. In comparison, in the Fig. In the semiconductor device 400A shown in FIG. 3A, the slot contact 450 extends beyond the fin structure 410 by a distance 580, which is significantly larger than the distance 570, in the Y direction. The distances 570 or 580 can be considered the "active fin extension" associated with the slot contacts 450-453, and they contribute to the parasitic capacitance. Because the "active fin extension" is shortened in the semiconductor device 400B, the parasitic capacitance is also reduced, which in turn improves the performance of the semiconductor device 400B.

[0046] The Fig. 4A to 4C show an embodiment of the semiconductor device 400B as a single transistor. Fig. 5A to 5C show another embodiment of the semiconductor device 400B as a plurality of transistors. As in the Fig. As shown in Figures 5A to 5B, metal line 460 is split into metal line 460A and metal line 460B, and metal line 463 is split into metal line 463A and metal line 463B. This allows the source / drain regions for different transistors to be electrically isolated from each other because metal lines 460A and 460B (or metal lines 463A and 463B) are no longer electrically connected to each other. A first transistor may include gate structures 430-431 and the source / drain regions on one of the sides of these gate structures 430-431. A second transistor may include gate structures 433-434 and the source / drain regions on one of the sides of these gate structures 433-434. It should be understood that the multi-transistor embodiment of semiconductor device 400B still offers the same advantages as the single-transistor embodiment of semiconductor device 400B.

[0047] The Fig. 6A, Fig. 6B, Fig. 6C and Fig. 6D show yet another embodiment of the present disclosure. More specifically, the Fig. 6A to 6B, similar to the Fig. 3A to 3B, the plan views of a semiconductor device 400C at different levels. And similar to Fig. 3C shows Fig. 6C shows the cross-sectional side view of the semiconductor device 400C, wherein the cross section is taken along the section line AA', although the location of the section line AA' in Fig. 6A extends from the location of the section line AA' in Fig. 3A. Furthermore, Fig. 6D shows the cross-sectional side view of the semiconductor device 400C, wherein the cross-section is taken along a section line BB'. For consistency and clarity, similar components used in the Fig. 3A to 3C and the Fig. 6A to 6C, are labeled alike, and their details are not repeated here. It should also be understood that the device dimensions of semiconductor device 400C may be similar to that of semiconductor device 400A (unless specifically stated otherwise). Thus, semiconductor device 400C achieves similar benefits as offered by semiconductor device 400A, such as reduced parasitic resistance and / or reduced parasitic capacitance, which in turn improves speed.

[0048] One difference between semiconductor device 400A and semiconductor device 400C is that semiconductor device 400C does not include metal lines 461-462, but instead implements a metal line 600 (still located in the metal o-layer) to establish electrical connections to gate structures 430-434. For example, the two rows of gate contacts 480-484 and 485-489 in Fig. 3A to a single row of gate contacts 480 - 484 in Fig. 6A. The gate contacts 480-484 are each arranged between the metal line 600 and the gate structures 430-434 and therefore establish an electrical connection to the gate structures 430-434. This is also spatially visible in the cross-sectional view of Fig. 6C. By "centering" the gate contacts 480-484 from two rows to a single row between the metal lines 460 and 463, the gate structures 430-434 each have a direct connection to the metal line 600. This helps to reduce the parasitic gate resistance, which minimizes a two-terminal effect on the bandwidth of the semiconductor device 400C.

[0049] The vias 470 - 473 have also been relocated to reduce the risk of electrical bridging (e.g., a short circuit) with the gate contacts 480 - 484. This is achieved by extending the slot contacts 450 - 453 in the Y direction. For example, in the Fig. 3A, the slotted contacts 450-453 do not connect with the metal lines 460 and 463 in the plan view. In the semiconductor device 400A shown in Fig. However, in the semiconductor device 400C shown in Figure 6A, the slot contacts 450-453 are long enough to intersect or overlap the metal lines 460 and 463 in plan view. This allows the vias 470 and 472 to electrically connect the slot contacts 450 and 452 to the metal line 460, and the vias 471 and 473 to electrically connect the slot contacts 451 and 453 to the metal line 463.

[0050] The Fig. 7A, Fig. 7B, Fig. 7C and Fig. 7D show yet another embodiment of the present disclosure. More specifically, the Fig. 7A to 7B, similar to the Fig. 6A to 6B, the plan views of a semiconductor device 400D at different levels. And similar to the Fig. 6C to 6D, show the Fig. 7C to 7D show cross-sectional side views of the semiconductor device 400D, wherein the cross section is taken along section lines AA' and BB', respectively. For consistency and clarity, similar components used in the Fig. 6A to 6D and the Fig. 7A through 7C are labeled alike, and their details are not repeated here. It should also be understood that the device dimensions of semiconductor device 400D may be similar to those of semiconductor devices 400A or 400C (unless specifically stated otherwise). Thus, semiconductor device 400D achieves similar benefits as offered by semiconductor device 400A or 400C, such as reduced parasitic resistance and / or reduced parasitic capacitance, which in turn improves speed.

[0051] For example, similar to semiconductor device 400C, the gate contacts 480-484 for semiconductor device 400D have also been "centered." Furthermore, semiconductor device 400D adds additional source / drain vias 470-477 to electrically connect the source / drain regions. This is shown in the Fig. 7A, Fig. 7B and Fig. 7D, where each of the slot contacts 450-453 is electrically connected to two vias, respectively, whereas in the previous embodiments, each slot contact is electrically connected to only one via. Implementing additional vias helps reduce parasitic source / drain resistance, which in turn improves speed. It should also be understood that additional vias 520-527 are also implemented between the metal 0 and metal 1 layers to align with the vias 470-477.

[0052] The semiconductor device 400D also divides the metal line 460 into a plurality of metal islands 460A to 460F and the metal line 463 into a plurality of metal islands 463A to 463F. This allows each of the metal islands 460A to 460F or 463A to 463F to be individually electrically coupled to a different source / drain region via the vias 470-477.

[0053] The Fig. 7A to 7D show an embodiment of the semiconductor device 400D as a single transistor. Fig. 8A to 8D show another embodiment of the semiconductor device 400D as a plurality of transistors. As shown in the Fig. 8A to 8B, the metal line 600 is split, for example, into a metal line 600A and a metal line 600B. This allows the gate structures for different transistors to be electrically isolated from each other since the metal lines 600A and 600B are no longer electrically connected to each other. A first transistor may include the gate structures 430-431 and the source / drain regions on one of the sides of these gate structures 430-431. A second transistor may include the gate structures 433-434 and the source / drain regions on one of the sides of these gate structures 433-434. It should be understood that the multi-transistor embodiment of the semiconductor device 400D still offers at least the same advantages as the single-transistor embodiment of the semiconductor device 400D.

[0054] Fig. 9 is a flowchart illustrating a method 650 according to an embodiment of the present disclosure. The method 650 includes a step 660 of receiving a layout design of an integrated circuit (IC layout design). The IC layout design includes an active area extending in a first direction, a plurality of gates each extending in a second direction and intersecting the active area in a plan view, and a plurality of slot contacts each intersecting the active area in the plan view.

[0055] The method 650 includes a step 670 of at least partially revising the IC layout design by: enlarging each of the slot contacts in the first direction; or increasing a center-to-center distance separating the plurality of gates in the first direction.

[0056] The method 650 includes a step 680 of facilitating fabrication of an IC according to the revised IC layout design.

[0057] In some embodiments, the IC layout design is an IC layout design for a serializer / deserializer (SerDes) device or a radio frequency (RF) device.

[0058] In some embodiments, reworking the IC layout is performed without substantially changing the dimension of each of the gates in the first direction.

[0059] In some embodiments, the IC layout design further comprises a first metal line, a second metal line, a third metal line, and a fourth metal line each extending in the first direction, wherein the first metal line and the second metal line intersect with the gates in plan view, and wherein the third metal line and the fourth metal line intersect with the slot contacts in plan view. Revising the IC layout design comprises replacing the third metal line and the fourth metal line with a series of metal islands spatially separated from each other in the first direction.

[0060] In some embodiments, revising the IC layout further comprises reducing a distance separating the first metal line and the second metal line in the second direction.

[0061] In some embodiments, the IC layout design further includes a first metal line and a second metal line intersecting the gates in plan view, a third metal line and a fourth metal line intersecting the slot contacts in plan view, a plurality of first gate contacts disposed between the gates and the first metal line, and a plurality of second gate contacts disposed between the gates and the second metal line. Revising the IC layout design further includes: replacing the third metal line and the fourth metal line with a fifth metal line disposed between the first metal line and the second metal line in plan view; and replacing the first gate contacts and the second gate contacts with a plurality of third gate contacts disposed between the gates and the fifth metal line.

[0062] In some embodiments, the IC layout design further comprises a first metal line and a second metal line intersecting the gates in plan view, a third metal line and a fourth metal line intersecting the slot contacts in plan view, a plurality of first source / drain vias disposed between the third metal line and a first subset of the slot contacts, and a plurality of second source / drain vias disposed between the fourth metal line and a second subset of the slot contacts.Revising the IC layout design further comprises: replacing the first metal line with a first row of metal islands; replacing the second metal line with a second row of metal islands; replacing the first source / drain vias with a plurality of third source / drain vias arranged between the first row of metal islands and the slot contacts; and replacing the second source / drain vias with a plurality of fourth source / drain vias arranged between the second row of metal islands and the slot contacts.

[0063] In some embodiments, a number of the third source / drain vias is greater than a number of the first source / drain vias and a number of the fourth source / drain vias is greater than a number of the second source / drain vias.

[0064] It will be appreciated that additional processes may be performed before, during, or after steps 660-680 of method 650. For simplicity, these additional steps are not described in detail here.

[0065] Fig. Figure 10 shows an integrated circuit fabrication system 700 according to embodiments of the present disclosure. The fabrication system 700 includes a plurality of units 702, 704, 706, 708, 710, 712, 714, 716, ..., N connected by a data transmission network 718. The network 718 may be a single network or may be a plurality of different networks, such as an intranet and the Internet, and may include both wired and wireless communication channels.

[0066] In one embodiment, unit 702 represents a manufacturing collaboration service system; unit 704 represents a user, such asa product engineer who monitors the products of interest; unit 706 represents an engineer, such as a processing engineer, who controls the process and relevant recipes, or an equipment engineer who monitors or adjusts the conditions and settings of the processing tools; unit 708 represents a metrology tool for testing and measuring ICs; unit 710 represents a semiconductor processing tool; unit 712 represents a virtual metrology module associated with processing tool 710; unit 714 represents an advanced processing control module associated with processing tool 710 and, in addition, other processing tools; and unit 716 represents a sampling module associated with processing tool 710.

[0067] Each unit may interact with other units and provide integrated circuit fabrication, processing control, and / or computational capability and / or receive such capabilities from the other units. Each unit may also include one or more computer systems for performing computations and executing automation. For example, the advanced processing control module of unit 714 may include a plurality of computer hardware devices with software instructions encoded therein. The computer hardware devices may include hard drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), and input / output devices (e.g., mouse and keyboard).The software instructions may be written in any suitable programming language and may be designed to perform specific tasks, such as the tasks associated with optimizing the CPP process controls as described above.

[0068] The integrated circuit fabrication system 700 enables interaction between the units for the purpose of integrated circuit fabrication (IC fabrication) as well as advanced processing control of the IC fabrication. In one embodiment, the advanced processing control includes adjusting the processing conditions, settings, and / or recipes of a processing tool applicable to the relevant wafers according to the measurement results.

[0069] In another embodiment, the measurement results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, the measurement results are measured from selected fields and points of the subset of processed wafers according to an optimal sampling field / point determined based on various process quality and / or product quality characteristics.

[0070] One of the capabilities provided by the IC fabrication system 700 may enable collaboration and information access in areas such as design, engineering and processing, metrology, and advanced processing control. Another capability provided by the IC fabrication system 700 may integrate systems between facilities, for example, between the metrology tool and the processing tool. Such integration allows the facilities to coordinate their activities. For example, integrating the metrology tool and the processing tool may enable manufacturing information to be more efficiently integrated into the manufacturing process or APC module, and may enable wafer data from online or on-site metrology with the metrology tool integrated with the associated processing tool.

[0071] The integrated circuit fabrication system 700 may be used to implement the method described above with reference to Fig. 9. For example, one or more of the units 702-716 may receive an IC layout design from a design provider and thereafter revise the received IC layout design by resizing and / or moving the slot contacts, the gates, the source / drain vias, and the metal lines, as described above with reference to the Fig. 2, 3A to 8A, 3B to 8B, 3C to 8C and 6D to 8D.

[0072] In summary, the present disclosure reconfigures the IC layout design for a non-logic device to reduce its parasitic capacitance and parasitic resistance. The non-logic device may include high-speed devices such as serializer-deserializer devices or high-frequency devices. Reconfiguring the IC layout design may include increasing the gate pitch, enlarging slot contacts, centering source / drain vias, shortening the distance between gate contacts, shrinking an active fin extension, centering gate contacts, replacing continuous metal lines with discontinuous metal islands, etc.

[0073] Based on the above descriptions, it can be seen that the present disclosure offers advantages over conventional devices. However, it should be understood that other embodiments may offer additional advantages, not all advantages are necessarily disclosed herein, and no particular advantage is required for all embodiments. One advantage is improved device performance. As described above, a conventional IC layout design is optimized for logic devices, but does not account for parasitic resistance or capacitance that may be caused by the conventional IC layout design. For high-speed devices, parasitic resistance or capacitance can significantly degrade device performance, such as speed.Here, reconfiguring the IC layout design for specific non-logic devices reduces parasitic resistance and / or capacitance, improving device performance. Other benefits include compatibility with existing manufacturing processes and ease of implementation.

[0074] One aspect of the present disclosure relates to a semiconductor device comprising a first device type and a second device type. The first device type includes a first fin structure extending in a first direction, a first gate enclosing the first fin structure, and a first slot contact disposed over the first fin structure. The first gate extends in a second direction and has a first gate dimension measured in the first direction. The first slot contact has a first slot contact dimension measured in the first direction. The second device type includes: a second fin structure extending in a third direction, a second gate enclosing the second fin structure, and a second slot contact disposed over the second fin structure.The second gate extends in a fourth direction and has a second gate dimension measured in the third direction. The second slot contact has a second slot contact dimension measured in the third direction. The second slot contact dimension is larger than the second gate dimension and larger than the first slot contact dimension.

[0075] Yet another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a logic device. The logic device includes a first active area extending in a first direction. The logic device includes a plurality of first gates each intersecting with the first active area in a plan view. The first gates each extend in a second direction different from the first direction. Each pair of adjacent first gates defines a first gate pitch. The logic device includes a plurality of first slot contacts disposed over the first active area. The first slot contacts each have a first slot contact width measured in the first direction. The semiconductor device also includes a non-logic device.The non-logic device includes a second active region extending in the first direction. The non-logic device includes a plurality of second gates each intersecting the second active region in plan view. The second gates each extend in the second direction. Each pair of adjacent second gates defines a second gate pitch that is substantially greater than the first gate pitch. The non-logic device includes a plurality of second slot contacts disposed over the second active region. The second slot contacts each have a second slot contact width measured in the first direction. The second slot contact width is substantially greater than the first slot contact width.

[0076] Another aspect of the present disclosure relates to a method. A layout design of an integrated circuit (IC layout design) is received. The IC layout design includes an active area extending in a first direction, a plurality of gates each extending in a second direction and intersecting with the active area in a plan view, and a plurality of slot contacts each intersecting with the active area in a plan view. The IC layout design is at least partially revised by: extending each of the slot contacts in the first direction; or increasing a center-to-center distance separating the plurality of gates in the first direction.

Claims

[1] A semiconductor device comprising: a first device type (200), the first device type (200) comprising: a first fin structure (104, 210) extending in a first direction (X); a first gate (230-234) enclosing the first fin structure (210), the first gate (230-234) extending in a second direction (Y) different from the first direction (X) and having a first gate dimension (290) measured in the first direction (X); and a plurality of first slot contacts (250-253) spaced apart in the first direction (X), wherein a first slot contact (250-253) is disposed over the first fin structure (104, 210), the first slot contact (250-253) having a first slot contact dimension (294) measured in the first direction (X); and one or more continuous first metal lines (260-263) each extending in the first direction (X) and electrically coupled to each of at least a subset of the first slot contacts (250-253); and a second device type (400), the second device type (400) comprising: a second fin structure (410) extending in the first direction (X); a second gate (430-434) enclosing the second fin structure (410), the second gate (430-434) extending in the second direction (Y) different from the first direction (X) and having a second gate dimension (490) measured in the first direction (X); and a plurality of additional second slot contacts (450-453) spaced apart in the first direction (X), wherein a second slot contact is disposed over the second fin structure (410), the second slot contact having a second slot contact dimension (494) measured in the first direction (X), the second slot contact dimension (494) being greater than the second gate dimension (490) and greater than the first slot contact dimension (494); and a plurality of metal islands (464-469), each electrically coupled to a different one of the second slot contacts (450-453). [2] A semiconductor device according to claim 1, wherein: the first device type (200) comprises a logic device; the second device type (400) comprises a non-logical device; and the first device type (200) and the second device type (400) are manufactured on the same integrated semiconductor chip, IC chip. [3] A semiconductor device according to claim 1 or 2, wherein: a first relationship exists between the first slot contact dimension (294) and the first gate dimension (290); a second ratio exists between the second slot contact dimension (494) and the second gate dimension (490); and the second ratio is greater than the first ratio. [4] A semiconductor device according to any one of the preceding claims, wherein: the first device type (200) further comprises a third gate (230-234) separated from the first gate (230-234) by a first gate pitch (292); the second device type (400) further comprises a fourth gate (430-434) separated from the second gate (430-434) by a second gate pitch (492); and the second gate center-to-center distance (492) is greater than the first gate center-to-center distance (292). [5] A semiconductor device according to any one of the preceding claims, wherein: the first device type (200) further comprises a first via (270-273) disposed over the first slot contact (250-253), the first via (270-273) having a first via dimension (296) that is larger than the first slot contact dimension (294); and the second device type (400) further comprises a second via (470-473) disposed over the second slot contact (450-453), the second via (470-473) having a second via dimension (496) that is smaller than the second slot contact dimension (494). [6] A semiconductor device comprising: a logic device (200), the logic device (200) comprising: a first active region (104, 210) extending in a first direction (X); a plurality of first gates (110, 230-234) each intersecting with the first active region (104, 210) in a plan view, the first gates (230-234) each extending in a second direction (Y) different from the first direction (X), and each pair of adjacent first gates defining a first gate pitch (292); a plurality of first slot contacts (250-253) disposed over the first active region (104, 210), the first slot contacts (250-253) each having a first slot contact width (294) measured in the first direction (X); one or more continuous first metal lines (260-263) each extending in the first direction (X) and electrically coupled to each of at least a subset of the first slot contacts (250-253); and a non-logical device (400), the non-logical device (400) comprising: a second active region (410) extending in the first direction (X); a plurality of second gates (430-434) each intersecting the second active region (410) in plan view, the second gates (430-434) each extending in the second direction (Y), and each pair of adjacent second gates (430-434) defining a second gate pitch (492) that is substantially greater than the first gate pitch (292); and a plurality of second slot contacts (450-453) disposed over the second active region (410), the second slot contacts (450-453) each having a second slot contact width (490) measured in the first direction (X), the second slot contact width (494) being substantially greater than the first slot contact width (294); and a plurality of metal islands (464-469), each electrically coupled to a different one of the second slot contacts (450-453). [7] A semiconductor device according to claim 6, wherein: the first gates (230-234) each have a first gate width (290) measured in the first direction (X); the second gates (430-434) each have a second gate width (490) measured in the first direction (X); and the first gate width (290) is substantially equal to the second gate width (490). [8] Method (650) comprising: Receiving (660) a layout design of an integrated circuit, IC layout design, the IC layout design comprising an active area extending in a first direction, a plurality of gates each extending in a second direction and intersecting with the active area in a plan view, and a plurality of slot contacts each intersecting with the active area in the plan view; and Revise (670), at least partially, the IC layout design by: Enlarging each of the slotted contacts in the first direction; or Increasing a center-to-center distance separating the plurality of gates in the first direction, wherein the IC layout design further comprises a first metal line, a second metal line, a third metal line, and a fourth metal line each extending in the first direction, wherein the first metal line and the second metal line intersect with the gates in plan view, and wherein the third metal line and the fourth metal line intersect with the slot contacts in plan view. [9] The method (650) of claim 8, wherein the IC layout design is an IC layout design for a serializer / deserializer device, SerDes device, or a radio frequency device, RF device. [10] The method (650) of claim 8 or 9, wherein reworking the IC layout is performed without substantially affecting the dimension of each of the gates in the first direction. [11] The method of any one of claims 8 to 10, wherein revising the IC layout design comprises replacing the third metal line and the fourth metal line with a series of metal islands that are spatially separated from each other in the first direction. [12] The method (650) of claim 11, wherein revising the IC layout further comprises reducing a distance separating the first metal line and the second metal line in the second direction. [13] Method (650) according to one of claims 8 to 10, wherein the IC layout design further comprises a first metal line and a second metal line intersecting the gates in plan view, a third metal line and a fourth metal line intersecting the slot contacts in plan view, a plurality of first gate contacts arranged between the gates and the first metal line, and a plurality of second gate contacts arranged between the gates and the second metal line; and Revising the IC layout design also includes: Replacing the first metal line and the second metal line with a fifth metal line arranged between the third metal line and the fourth metal line in plan view; and Replacing the first gate contacts and the second gate contacts with a plurality of third gate contacts arranged between the gates and the fifth metal line. [14] Method (650) according to one of claims 8 to 10, wherein the IC layout design further comprises a first metal line and a second metal line intersecting the gates in plan view, a third metal line and a fourth metal line intersecting the slot contacts in plan view, a plurality of first source / drain vias arranged between the third metal line and a first subset of the slot contacts, and a plurality of second source / drain vias arranged between the fourth metal line and a second subset of the slot contacts; and Revising the IC layout design also includes: Replacing the third metal line with a first row of metal islands; Replacing the fourth metal line with a second row of metal islands; Replacing the first source / drain vias with a plurality of third source / drain vias arranged between the first row of metal islands and the slot contacts; and Replacing the second source / drain vias with a plurality of fourth source / drain vias arranged between the second row of metal islands and the slot contacts. [15] The method (650) of claim 14, wherein: the number of third source / drain vias is greater than the number of first source / drain vias; and the number of fourth source / drain vias is greater than the number of second source / drain vias.

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