Structuring ultra-narrow trenches by plasma etching

Abstract

Procedure comprehensive: Forming a four-layer etch mask (74) over a target layer (72; 36A; 92), wherein the four-layer etch mask (74) has the following: - a first lower anti-reflective coating, BARC, (74A); - a hard mask (74B) on the first BARC (74A); - a second BARC (74C) on the hard mask (74B); and - a photoresist (74D) on the second BARC (74C); Structuring the photoresist (74D) to form an opening (75), wherein a top surface of the second BARC (74C) is exposed towards the opening (75), and the top surface is a top surface of a first section and a second section (74C2) of the second BARC (74C); Forming a polymer layer (76) on the photoresist (74D), wherein the polymer layer (76) comprises a higher section directly above the photoresist (74D) and a lower section (76A1) extending into the opening (75) and contacting the top of the first section of the second BARC (74C); Etching of the polymer layer (76) and the second BARC (74C), wherein the first section of the second BARC (74C) is removed during etching and the second section (74C2) of the second BARC (74C) remains after etching; Etching of the hard mask (74B) using the second BARC (74C) as the etching mask; Etching of the first BARC (74A); and Etching of the target layer (72; 36A; 92).

Description

TECHNICAL BACKGROUND

[0001] As integrated circuits become increasingly compact, features such as metal lines, trenches, dielectric regions, etc., also become smaller. A bottleneck in the reduction process occurs when the limits of the photolithography process are reached. For example, if 193 nm immersion patterning is used to form regular trenches, the smallest trench width is approximately 50 nm. While this dimension is small enough for some existing integrated circuits, it is still too large for forming smaller integrated circuits.

[0002] US 6,797,610 B1 describes a method for forming a sublithographic trench in a semiconductor substrate. First, a micro-trench is formed, which is then used as a mask. Filled sublithographic trenches have a width corresponding to the width of the micro-trench.

[0003] US 2018 / 0 314 155 A1 describes a method for forming structures. A semiconductor substrate is provided. A photoresist structure is formed over the semiconductor substrate, wherein the photoresist structure consists of a photoresist composition containing a first polymer comprising acid-labile groups and a photoacid generator. The photoresist structure is coated with a structural overcoat composition containing a second polymer and an organic solvent with one or more ester solvents of the formula R1-C(O)O-R2, where R1 is a C3-C6 alkyl group and R2 is a C5-C10 alkyl group. The coated photoresist structure is baked. The coated photoresist structure is rinsed with a rinsing agent to remove the second polymer. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various structural elements are not drawn to scale. Indeed, the dimensions of various structural elements may be arbitrarily exaggerated or reduced for purposes of illustration. The Fig. 1 to 7, 8A, 8B, 9, 10A, 10B, 10C, and 11 to 17 illustrate perspective views, top views, and cross-sectional views of intermediate stages in forming a fin field-effect transistor (FinFET) according to some embodiments. The Fig. 18 to 22 illustrate cross-sectional views of intermediate stages in a fin cutting process according to some embodiments. The Fig. 23 to 27 illustrate cross-sectional views of intermediate stages in forming conductive features in a dielectric layer according to some embodiments. Fig. Figure 28 illustrates the chemical reactions involved in depositing a polymer layer according to some embodiments. Fig. 29 illustrates a process flow for forming a FinFET according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples of implementing various features of the invention. Certain example components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In the following description, for example, the formation of a first feature on or at a second feature may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. In addition, throughout the present disclosure, reference numbers and / or reference symbols may be repeated throughout the various examples.This repetition is for clarity and convenience and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Spatially relatable terms such as "underlying," "beneath," "lower," "overlying," "upper," and the like may also be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the FIGS. The spatially relatable terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation depicted in the FIGS. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relatable descriptors used herein may also be interpreted accordingly.

[0007] According to various embodiments, patterning processes employing four-layer etch masks are provided. The intermediate stages in the etch processes are illustrated according to some embodiments. Some variations of some embodiments are explained. Similar reference numerals are used throughout the various views and embodiments to denote similar elements. According to some embodiments of the present disclosure, adjacent FinFETs having fins in close proximity to each other are formed using four-layer etch masks used to split a trench structure into two narrower trench structures. Accordingly, the dimension and / or spacing of structures may be reduced by more than half.

[0008] Embodiments are described with reference to a specific context, namely the patterning process using a four-layer etch mask, and in particular to the formation of metal gates and cut-fin processes in FinFETs and the formation of conductive features in dielectric layers. The concepts of the illustrated embodiments may also be applied in the design and processing of other structures, such as, but not limited to, the formation of trenches and the etching of metal, semiconductor, and / or dielectric features. Embodiments explained herein are intended to serve as examples enabling the manufacture or use of the subject matter of this disclosure, and those of ordinary skill in the art will readily appreciate possible modifications that are nevertheless within the intended scope of the various embodiments.While embodiments of methods may be described as being performed in a particular order, others may be performed in any reasonable order.

[0009] The Fig. 1 to 7, 8A, 8B, 9, 10A, 10B, 10C and 11 to 17 illustrate the perspective views, top views and cross-sectional views of intermediate stages in forming fin field effect transistors (FinFET) according to some embodiments. The corresponding processes are described in the Fig. The process flow shown in Figure 29 is also shown schematically.

[0010] In Fig. 1, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped or undoped (e.g., with a p-type or an n-type dopant). The semiconductor substrate 20 may be a portion of a wafer 10, such as a silicon wafer. An SOI substrate is typically a layer of a semiconductor material formed on an insulator layer. The insulator layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon, germanium, a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof.

[0011] In Fig. 1, a well region 22 is further formed in the substrate 20. The respective process is shown in the process flow 300 in Fig. 29 as process 302. According to some embodiments of the present disclosure, the well region 22 is a p-well region formed by implanting a p-type impurity such as boron, indium, or the like into the substrate 20. According to other embodiments of the present disclosure, the well region 22 is an n-well region formed by implanting an n-type impurity such as phosphorus, arsenic, antimony, or the like into the substrate 20. The resulting well region 22 may extend to the top of the substrate 20. The concentration of the n- or p-type impurity may be a maximum of 10 18 cm -3 be, for example in the range between about 10 17 cm -3 and about 10 18 cm -3 lay.

[0012] Fig. 1 illustrates device region 100 in which a first FinFET is to be formed and device region 200 in which a second FinFET is to be formed. Each of device regions 100 and 200 may be a p-type or an n-type FinFET region. According to alternative embodiments of the present disclosure, device region 100 is an n-type FinFET region and device region 200 is a p-type FinFET region. Alternatively, device region 100 is a p-type FinFET region and device region 200 is an n-type FinFET region. In the illustrated example, device regions 100 and 200 are an n-type and a p-type FinFET region, respectively, although other FinFET combinations are also contemplated.

[0013] In Fig. 2, isolation regions 24 are formed such that they extend from a top side of the substrate 20 into the substrate 20. The isolation regions 24 are also referred to hereinafter as shallow trench isolation regions (STI). The respective process is described in the process flow 300 in Fig. 29 as process 304. The portions of the substrate 20 located between adjacent STI regions 24 are referred to as semiconductor stripes 26. To form STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20 and then patterned. The pad oxide layer 28 may be a thin film of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process in which a top layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30.According to some embodiments of the present disclosure, the hard mask layer 30 is formed from silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD). According to other embodiments of the present disclosure, the hard mask layer 30 is formed by thermal nitriding of silicon or plasma-enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. Then, using the patterned photoresist as an etch mask, the hard mask layer 30 is patterned as shown in FIG. Fig. 2 shown hard masks 30 are created.

[0014] Next, the patterned hard mask layer 30 is used as an etch mask to etch the pad oxide layer 28 and the substrate 20, after which the trenches created in the substrate 20 are filled with one or more dielectric materials. A planarization process, such as chemical mechanical polishing (CMP) or a mechanical grinding process, is performed to remove excess portions of the dielectric material, and the remaining portions of the dielectric material are STI regions 24. The STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20.The liner dielectric may also be a deposited silicon oxide layer, silicon nitride layer, or the like, formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 24 may also include a dielectric material on the liner oxide, where the dielectric material may be formed using FCVD (flowable chemical vapor deposition), spin-coating, or the like. The dielectric material on the liner dielectric may include silicon oxide, according to some embodiments.

[0015] The top surfaces of the hard masks 30 and the top surfaces of the STI regions 24 may be substantially the same height. The semiconductor stripes 26 are located between adjacent STI regions 24. According to some embodiments of the present disclosure, the semiconductor stripes 26 are components of the original substrate 20, and thus the material of the semiconductor stripes 26 is the same as that of the substrate 20. According to alternative embodiments of the present disclosure, the semiconductor stripes 26 are replacement stripes formed by etching the portions of the substrate 20 between the STI regions 24 to form recesses and performing an epitaxial process to regrow another semiconductor material in the recesses. The semiconductor stripes 26 are accordingly formed from a different semiconductor material than that of the substrate 20.According to some embodiments, the semiconductor stripes 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0016] The STI areas 24 in Fig. 3 are recessed so that the upper portions of the semiconductor strips 26 protrude further upward than the upper surfaces 24A of the remaining portions of the STI regions 24, thus forming protruding fins 36. The protruding fin in the component region 100 is also referred to as protruding fin 36A, and the protruding fins in the component region 200 are also referred to as protruding fins 36B. The respective process is described in the process flow 300 in Fig. 29 as process 306. The etching may be performed using a dry etching process, for example, using HF3 and NH3 as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to alternative embodiments of the present disclosure, the STI regions 24 are recessed using a wet etching process. The etching chemical may include, for example, HF.

[0017] In the embodiments illustrated above, the fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, such as, but not limited to, double or multiple patterning processes. Double or multiple patterning processes typically combine photolithography with self-alignment processes, which may create structures that, for example, have smaller pitches than those otherwise achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0018] In Fig. 4, dummy gate stacks 38 are formed to extend over the tops and sidewalls of the (protruding) fins 36. The respective process is shown in the process flow 300 in Fig. 29 as process 308. The dummy gate stacks 38 may include dummy gate dielectrics 40 and dummy gate electrodes 42 on the dummy gate dielectrics 40. The dummy gate dielectrics 40 may be formed from silicon oxide. The dummy gate electrodes 42 may be formed using polysilicon, for example, and other material may be used. Each of the dummy gate stacks 38 may also include one (or more) hard mask layers 44 on the dummy gate electrodes 42. The hard mask layers 44 may be formed from silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stacks 38 may intersect a plurality of protruding fins 36 and STI regions 24. The dummy gate stacks 38 also have a longitudinal direction that is perpendicular to the longitudinal direction of the protruding fins 36.

[0019] Next, gate spacers 46 are formed on the side walls of the dummy gate stacks 38. The respective process is described in the process flow 300 in Fig. 29 also illustrated as process 308. According to some embodiments of the present disclosure, the gate spacers 46 are formed from one (or more) dielectric materials such as silicon nitride, silicon carbonitride, or the like, and may have a single-layer or multi-layer construction having multiple dielectric layers.

[0020] Then, an etching process is performed to etch the portions of the protruding fins 36 that are not covered by the dummy gate stacks 38 and the gate spacers 46, thereby forming the Fig. 5 shown construction is created. The respective process is shown in the process flow 300 in Fig. 29 as process 310. The recessing may be performed anisotropically, and thus the portions of the fins 36 directly beneath the dummy gate stacks 38 and the gate spacers 46 are protected and not etched. The semiconductor stripes 26 may be recessed, and the top surfaces of the recessed semiconductor stripes 26 may be lower than the top surfaces 24A of the STI regions 24, according to some embodiments. Accordingly, recesses 50 are formed. The recesses 50 include portions on opposite sides of the dummy gate stacks 38 and portions between remaining portions of the protruding fins 36.

[0021] Next, by selectively growing (via epitaxy) suitable semiconductor material in the recesses 50, epitaxial regions (source-drain regions) 154 and 254 are formed, whereby the construction in Fig. 6 is created. The respective process is in the process flow 300 in Fig. 29 as process 312. According to some embodiments of the present disclosure, the formation of the epitaxial regions 154 and 254 occurs in separate epitaxial processes, and details thereof are not discussed here. In an embodiment where the device region 100 is an n-type FinFET region and the device region 200 is a p-type FinFET region, an n-type impurity is doped in situ into the epitaxial regions 154 and a p-type impurity is doped in situ into the epitaxial regions 254 during the epitaxy. For example, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP) may be grown as the epitaxial regions 154 and silicon germanium boron (SiGeB) or silicon boron (SiB) may be grown as the epitaxial regions 254.The recesses 50 are filled with the epitaxial regions 154 and 254, and the further epitaxial growth of the epitaxial regions 154 and / or 254 causes the respective epitaxial regions to expand horizontally, and facets may form. The further growth of epitaxial regions may also cause neighboring epitaxial regions (such as regions 254) to merge with each other. Gaps (air gaps, such as 256) may arise. According to some embodiments of the present disclosure, the formation of epitaxial regions (such as 254) may be completed when the top surface of the epitaxial regions 154 and / or 254 is still wavy or when the top surfaces of the merged epitaxial regions 154 and / or 254 have become flat.

[0022] After the epitaxial growth process, a p-type or n-type impurity may be further implanted into the epitaxial regions 154 and / or 254 to form source and drain regions, which are also designated by reference numerals 154 and 254. According to alternative embodiments of the present disclosure, the implantation is skipped if the epitaxial regions 154 and 254 are doped in situ with the n-type or p-type impurity, respectively, during the epitaxial growth process.

[0023] Fig. Figure 7 shows a perspective view of the construction after forming a contact etch stop layer (CESL) 58 and an inter-layer dielectric (ILD) 60. The respective process is shown in the process flow 300 in Fig. 29 as process 314. The CESL 58 may be formed from silicon oxide, silicon nitride, silicon carbonitride, or the like using CVD, ALD, or the like. The ILD 60 may include a dielectric material formed, for example, using FCVD, spin-on deposition, CVD, or the like. The ILD 60 may be formed from an oxygen-containing dielectric material, which may be a silicon oxide-based material such as tetraethyl orthosilicate oxide (TEOS oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. A planarization process such as a CMP or mechanical grinding process may be performed to align the top surfaces of the ILD 60, the dummy gate stack 38, and the gate spacer 46.

[0024] Next, the dummy gate stacks 38 including the hard mask layers 44, the dummy gate electrodes 42 and the dummy gate dielectrics 40 are etched such that, as shown in Fig. 8A form trenches 62 between the gate spacers 46. The respective process is shown in the process flow 300 in Fig. 29 as process 316. The tops and side walls of some portions of the projecting fins 36 are exposed to the trenches 62. Fig. 8B represents the reference cross section 8B-8B in Fig. 8A.

[0025] The Fig. 9, 10A, 10B, 10C and 11 to 14 illustrate the formation of replacement gate stacks. In Fig. 9, a gate dielectric 68 is formed. The respective process is shown in the process flow 300 in Fig. 29 as process 318. According to some embodiments of the present disclosure, the gate dielectric 68 includes an interfacial layer (IL) 64 as a bottom component. The IL 64 is formed on the exposed surfaces of the protruding fins 36. The IL 64 may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation of the protruding fins 36, a chemical oxidation process, or a deposition process. The gate dielectric 68 may also include a high-k dielectric layer 66 formed on the IL 64. The high-k dielectric layer 66 includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconia, or the like. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0, and sometimes 21.0 or more. The high-k dielectric layer 66 lies on the IL 64 and can contact it.The high-k dielectric layer 66 is formed as a conformal layer and extends over the sidewalls of the protruding fins 36 and the tops and sidewalls of the gate spacers 46. According to some embodiments of the present disclosure, the high-k dielectric layer 66 is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), or the like.

[0026] According to some embodiments, an adhesion layer (which may also be a diffusion barrier layer, not shown) may be formed on the high-k dielectric layer 66. The adhesion layer may be formed of TiN or titanium silicon nitride (TSN).

[0027] A lower work function layer 70 and an upper work function layer 72 are formed on the adhesion layer and the gate dielectric 68. The respective process is shown in the process flow 300 in Fig. 29 as process 320. The work function layer 72 is also referred to as a target layer or target region, as it is the target element to be patterned in subsequent processes. According to some embodiments of the present disclosure, the work function layer 70 is an n-type work function layer suitable for forming n-type FinFETs and having a low work function (e.g., less than about 4.5 eV), and the work function layer 72 is a p-type work function layer suitable for forming p-type FinFETs and having a high work function (e.g., greater than about 4.6 eV). According to some embodiments of the present disclosure, the work function layer 70 may include a titanium aluminum (TiAl) layer, and the work function layer 72 may include a TaN layer, a TiN layer on the TaN layer, and possibly also a TiAl layer on the TiN layer.It is understood that the work function layers 70 and 72 may include various materials, which are also contemplated.

[0028] In Fig. 9, a four-layer etching mask 74 is further formed, which is used for the subsequent structuring of the work function layer 72. The respective process is shown in the process flow 300 in Fig. 29 as process 322. The four-layer etch mask 74 includes a bottom anti-reflective coating (BARC) 74A, a hard mask 74B, a BARC 74C, and a photoresist 74D, which are also referred to as the first, second, third, and fourth layers of the etch mask 74, respectively. According to some embodiments of the present disclosure, BARC 74A and 74C are formed from cross-linked photoresist. The hard mask 74B may be formed from an oxide (e.g., a metal oxide), a nitride (e.g., a metal nitride), or the like. For example, the hard mask 74B may be formed from aluminum oxide, titanium nitride, or the like. The thickness of the BARC 74A may range between about 100 nm and about 200 nm. The BARC 74A may completely fill the trenches 62 ( Fig. 8A), and the top of the BARC 74A is higher than the top 60A of the ILD 60 ( Fig. 9). The thickness of the hard mask 74B may range between about 10 nm and about 20 nm. The thickness of the BARC layer 74C may range between about 20 nm and about 40 nm. The photoresist 74D is patterned to form an opening 75. According to some embodiments, patterning the photoresist 74D includes an exposure and a development process. The width W1 of the opening 75 may be approximately or exactly the minimum width achievable using the corresponding lithography process. The width W1 may range between about 50 nm and about 100 nm, depending on the lithography technology. For example, if the photoresist 74D is patterned using an immersion patterning process that uses 193 nm light, the width W1 may be about 50 nm. According to some embodiments, one or more protruding fins 36A and one or more protruding fins 36B are located directly below the opening 75.

[0029] Loud Fig. 9, a polymer layer 76 is deposited, which can be formed using a conformal deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or the like. The respective process is shown in the process flow 300 in Fig. 29 as process 324. The polymer layer 76 is formed as a conformal layer whose thickness T1 of the vertical sections is substantially equal to, for example, less than about 20 percent of the thickness T2 of the horizontal sections. The thicknesses T1 and T2 may range between about 10 nm and about 25 nm. The polymer layer 76 may be formed from elements including, but not limited to, carbon (C), hydrogen (H), nitrogen (N), boron (B), chlorine (Cl), and the like. The polymer layer 76 may, for example, contain C x H y , C x Hy CN, NC(CH2) x CN, C x H y NH2, CH y N2H3, B x N y , B x Cl y (where x and y are integers) or combinations thereof.

[0030] The precursors used for the polymer layer 76 may include CH4, N2, or combinations thereof. Helium (He) may be used as a dilute gas and may assist in plasma ignition and stabilization during the deposition of the polymer layer 76. In an exemplary deposition process for forming the polymer layer 76, the deposition time ranges between about 10 seconds and 40 seconds, the pressure in the respective reaction chamber ranges between about 2 mtorr and about 15 mtorr, the power ranges between about 400 watts and about 700 watts, the flow rate of CH4 ranges between about 10 sccm and about 50 sccm, and the flow rate of He ranges between about 20 sccm and about 300 sccm.

[0031] Fig. Figure 28 shows the chemical reactions when using CH4 as the process gas to produce the polymer layer 76 (the C x H y contains). As in Fig. As shown in Figure 28, CH4 molecules absorb the energy of electrons (e - ) and thus produce CH3 and H ions, CH2 and H2, CH, H ions and H2 and / or carbon ions and H2. These ions, molecules, radicals, etc. react to form C x H y -Polymer.

[0032] According to some embodiments of the present disclosure, CH4 and N2 are among the precursors, and He can be used as a dilute gas and assist in igniting and stabilizing the plasma. The resulting polymer layer 76 can be C x H y CN, NC(CH2) x CN, C x H y NH2, CH y N2H3 and / or combinations thereof.

[0033] According to some embodiments of the present disclosure, BCl3 and N2 are among the precursors, and He can be used as a dilute gas and assist in igniting and stabilizing the plasma. The resulting polymer layer 76 can be B x Ny , B x Cl y and / or combinations thereof.

[0034] Next, the polymer layer 76 and the BARC 74C are etched to create openings 77 in the BARC 74C ( Fig. 10A), wherein the photoresist 74D is used as an etching mask. The respective process is shown in the process flow 300 in Fig. 29 as process 326. In the etching process, no etch mask is formed on the polymer layer 76, which also extends into the opening 75. In the etching process, the portions of the polymer layer 76 directly above the photoresist 74D are etched until the photoresist 74D is exposed, which is then used as an etch mask to protect the underlying portions of the BARC 74C. In the etching process, the horizontal portions 76A1 of the polymer layer 76 that are at the bottom of the opening 75 and near the sidewalls of the photoresist 74D are etched faster than the portions 76A2 that are at the bottom of the opening 75 and near its center. The horizontal portions 76A1 of the polymer layer 76 are also etched. Accordingly, after the complete etching of the polymer sections 76A1, the underlying sections of the BARC 74C are etched, while the polymer sections 76A2 are etched as in Fig. 10A, some sections remain. The etching time is controlled so that when the sections of the BARC 74C are etched through, the sections 74C2 of the BARC 74C directly beneath the polymer sections 76A2 still remain. Some lower sections also remain in the photoresist 74D. Furthermore, when the etching is stopped, the polymer layer 76 may be completely removed, or alternatively, as shown in Fig. 10A, some sections 76A2 may still remain. Throughout the description, the remaining sections of the BARC 74C are referred to as sections 74C1 (which lie directly beneath the photoresist 74D) and sections 74C2 (which lie directly beneath the opening 75). Openings 77 in the BARC 74C separate the BARC sections 74C1 from the BARC section 74C2.

[0035] The Fig. 10B and Fig. 10C schematically illustrate top views of openings 75 and 77 and underlying features including source-drain regions 154 and 254, gate spacers 46, and protruding fins 36A and 36B, according to some embodiments. Fig. 10B shows a plan view of the Fig. 10A, according to some embodiments, wherein the BARC portion 74C2 is depicted as an island surrounded by and spaced from the BARC portion 74C1 and the opening 77. The protruding fins 36B are covered by the BARC portion 74C2, while the protruding fin 36A is exposed via the BARC 74C.

[0036] Fig. Figure 10C shows a plan view of the Fig. 10A, according to alternative embodiments, wherein the opposite ends of BARC sections 74C2 are connected to BARC section 74C1. Openings 77 are formed as two separate strips, each surrounded by the remaining portion of BARC 74C.

[0037] The etching of the polymer layer 76 and the BARC 74C can occur in the same etching process or in separate processes. According to some embodiments of the present disclosure, the etching gas includes N2- and H2-based gases, as well as other gases selected from CH4, O2, He, HBr, Ar, Cl, and combinations thereof. The duration of the etching process can range between about 20 seconds and about 50 seconds. The pressure in the etching chamber can range between about 5 mtorr and about 15 mtorr. The flow rate of CH4 can range between about 5 sccm and about 50 sccm. The ratio of the flow rate of N2 to the flow rate of H2 can range between about 1:10 and about 1:1.

[0038] The width W2 of the BARC section 74C2 and the width W3 of the openings 77 in Fig. 10A can be adjusted by adjusting the thickness T1 and T2 ( Fig. 9) of the polymer layer 76. For example, if the thickness of the polymer layer 76 is increased (by increasing the deposition time), the width W2 of the BARC portion 74C2 increases, and the width W3 of the trenches 77 decreases. Conversely, if the thickness T1 / T2 of the polymer layer 76 is decreased (by decreasing the deposition time), the width W2 of the BARC portion 74C2 decreases, while the width W3 of the trenches 77 increases.

[0039] The width W2 of the BARC section 74C2 and the width W3 of the openings 77 can also be adjusted by adjusting the process parameters during etching of the polymer layer 76. For example, if the etching time is increased, the width W2 of the BARC section 74C2 decreases, while the width W3 of the trenches 77 increases. Conversely, if the etching time is decreased, the width W2 of the BARC section 74C2 increases, while the width W3 of the trenches 77 decreases. In addition, other etching parameters, such as power, also influence the profile and the widths W2 and W3 and can be adjusted to achieve the desired widths W2 and W3.

[0040] According to some embodiments of the present disclosure, the width W3 of the trenches 77 may be reduced to the range between about 20 nm and about 40 nm, which is less than half, and may be in the range between about 25 percent and about 40 percent of the width W1 of the original trench ( Fig. 10). The width W2 can range between approximately 20 percent and approximately 50 percent of the width W1.

[0041] The structured BARC 74C is then used as an etching mask for etching the underlying hard mask 74B. The respective process is shown in the process flow 300 in Fig. 29 as process 328. The remaining portions of the photoresist 74D may be removed prior to etching the hard mask 74B or used as part of the etch mask. After etching, the remaining portions of the photoresist 74D and the BARC 74C may be removed, thereby forming the Fig. 11 is formed. According to some embodiments where the hard mask 74B comprises alumina, the etching gas may include chlorine-based gases such as BCl3 / Cl2, as well as other gases selected from He, CH4, He, HBr, Ar, and combinations thereof.

[0042] In a subsequent process, the BARC 74A is used as in Fig. 12 in an etching process using the patterned hard mask 74B as an etching mask. The respective process is shown in the process flow 300 in Fig. 29 as process 330. According to some embodiments of the present disclosure, the etch gas for the BARC 74A may include N2 and H2-based gases, as well as other gases selected from CH4, O2, He, HBr, Ar, and combinations thereof. The power and other etch conditions for etching the BARC 74C, the hard mask 74B, and the BARC 74A may differ from each other.

[0043] Next, in the device region 100, the upper work function layer 72 is etched over the openings 78 in the BARC 74A, thereby exposing the underlying work function layer 70. In the device region 200, the work function layer 72 is protected by the hard mask 74B and the BARC 74A. The respective process is described in the process flow 300 in Fig. 29 as process 332. Etching is performed by selecting an etching gas or chemical solution that attacks the work function layer 72, but not the work function layer 70. After etching, the hard mask 74B and the BARC 74A are removed, and the resulting structure is shown in Fig. 13, in which the work function layer 70 is exposed in the device region 100 and the work function layer 72 is exposed in the device region 200.

[0044] The stacked conductive layers 80 in Fig. 14. The respective process is in the process flow 300 in Fig. 29 as process 334. The conductive layers 80 may include a metal cap layer and a conduction gap fill layer on the metal cap layer. The metal cap layer may be formed of TiN, for example, and the conduction gap fill layer may include cobalt, tungsten, or the like. After forming the conduction gap fill layer, a planarization process may be performed to remove excess portions of the deposited layers. In the resulting construction, the stacked layers 80 and the underlying work function layer 70 together form portions of the gate electrode 83A of the FinFET 82A in the device region 100. The stacked layers 80 and the underlying work function layers 70 and 72 together form portions of the gate electrode 83B of the FinFET 82B in the device region 100.According to some embodiments of the present disclosure, work function layer 70 is an n-type work function layer and FinFET 82A is an n-type FinFET, and work function layer 72 is a p-type work function layer and FinFET 82B is a p-type FinFET. In the illustrated example, the gate electrodes of FinFETs 82A and 82B are connected to each other and can be used to form circuits such as an inverter.

[0045] Fig. Figure 15 shows a perspective view of FinFETs 82A and 82B. Fig. 16 illustrates the formation of hard masks 84 according to some embodiments. Forming hard masks 84 may include performing an etching process to deepen gate stacks 83A and 83B (which are metal gates) to form recesses between gate spacers 46, filling the recesses with a dielectric material, and then performing a planarization process to remove excess portions of the dielectric material. Hard masks 84 may be formed from silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like. According to some embodiments, gate stacks (including 83A and 83B) may be formed as long strips that are then cut apart.For example, gate stacks 83 and 84 may belong to the same gate strip, and an opening may be formed by etching a portion of the gate strip between gate stacks 83A and 83B to form an opening and then filling the respective opening with a dielectric material to form a dielectric isolation region electrically separating gate stacks 83A and 83B. Hard masks 84 may be formed before or after forming the dielectric isolation region. According to alternative embodiments, no hard mask (84) is formed.

[0046] Fig. Figure 17 illustrates the formation of source / drain contact plugs 86 and silicide regions 88. The gate contact plugs 87 are also formed to extend through a portion of each hard mask 84 and thus contact the gate electrodes 83A and 83B ( Fig. 14). The details of the educational processes are not repeated here.

[0047] The Fig. 18 to 22 illustrate cross-sectional views of intermediate stages in a fin cutting process according to some embodiments of the present disclosure. Unless otherwise indicated, the materials and formation processes for the components in these embodiments are substantially the same as those for similar components used in the preceding Fig. 1 to 7, 8A, 8B, 9, 10A, 10B, 10C and 11 to 17 are provided with similar reference numerals. The details of the formation process and the materials for the embodiments shown in the Fig. 18 to 22 (and the Fig. 23 to 27) can therefore be found in the explanation of the embodiments shown in the previous FIGS.

[0048] The first steps in these embodiments essentially correspond to those in Fig. 1 to 3 shown. Fig. 18 shows a cross-sectional view of the Fig. 3, to which the four-layer etch mask 74 is added. The four-layer etch mask 74 includes the BARC 74A, the hard mask 74B, the BARC 74C, and the patterned photoresist 74D. The opening 75 is formed in the patterned photoresist 74D. The polymer layer 76 is deposited. The details of the materials, dimensions, and formation processes, etc., for the four-layer etch mask 74 and the polymer layer 76 are described in the embodiments in Fig. 9. The opening 75 is located directly above the projecting fin 36B and the projecting fins 36A, which are located on opposite sides of the projecting fin 36B.

[0049] Then, the polymer layer 76 and the BARC 74C are etched, and the resulting BARC sections 74C1 and 74C2 are in Fig. 19. Next, the patterned BARC 74C is used as an etchant to etch the hard mask 74B, and the resulting patterned hard mask 74B is shown in Fig. 20. The BARC 74A is then patterned using the patterned hard mask 74B as an etch mask, so that the underlying protruding fins 36A are exposed, while the protruding fin 36B is protected by the BARC 74A. The exposed protruding fins 36A are also referred to as target layers or target areas. The protruding fins 36A are then cut in an etching process so that the Fig. 21 is created. The BARC 74A and the hard mask 74B can then be Fig. 22. In subsequent processes, some or all of the Fig. 4 to 7, 8A, 8B, 9, 10A, 10B, 10C and 11 to 17 are performed to form FinFET.

[0050] The Fig. 23 to 27 represent the intermediate stages in a damascene process for forming closely spaced conductive features such as metal lines. In Fig. 23, a dielectric layer 92 (also a target layer or target region in this embodiment) is formed on a base structure 90. The base structure 90 may include a semiconductor substrate and components such as transistors, dielectric layers, metal lines, or the like on the semiconductor substrate. The dielectric layer 92 may be formed of silicon oxide, silicon nitride, a low-k dielectric material, or the like. The four-layer etch mask 74, including the BARC 74A, the hard mask 74B, the BARC 74C, and the patterned photoresist 74D, is formed on the dielectric layer 92. Then, the polymer layer 76 is deposited. The details of the materials, dimensions, and formation processes, and the like, for the four-layer etch mask 74 and the polymer layer 76 are described in the Fig. 9 shown embodiments.

[0051] Then, the polymer layer 76 and the BARC 74C are etched, and the resulting BARC sections 74C1 and 74C2 are in Fig. 24. Next, the patterned BARC 74C is used as an etchant to etch the hard mask 74B, and the resulting patterned hard mask 74B is shown in Fig. 25. Next, the BARC 74A is patterned using the patterned hard mask 74B as an etch mask, so that the underlying dielectric layer 92 is exposed. Then, the dielectric layer 92 is etched in an etching process, so that, as shown in Fig. 26, openings 94 are formed in the dielectric layer 92. The BARC 74A and the hard mask 74B can then be removed. To form conductive features 96, which may include diffusion barrier layers 96A and metal regions 96B, conductive material can be filled into the openings 94 ( Fig.27). The diffusion barrier layers 96A may be formed from titanium, titanium nitride, tantalum, tantalum nitride, or the like. The metal regions 96B may be formed from copper or a copper alloy.

[0052] The embodiments of the present disclosure may have several advantageous features. The widths and spacing of the formed features can be reduced by more than half by utilizing the difference in etch rate between different sections of the various BARCs, as well as by adjusting process parameters and depositing an additional polymer layer. The embodiments of the present disclosure may be applied to any patterning process that utilizes four-layer etch masks, allowing the widths and spacing of the features to be formed to be reduced to below the limits of the photolithography process.For example, the embodiments of the present disclosure may be used in etching dielectric layers to form metal lines, etching the semiconductor substrate to form narrow STI regions, etching dielectric layers to form dielectric lines, and the like.

[0053] According to some embodiments of the present disclosure, a method comprises: forming a four-layer etch mask on a target layer, the four-layer etch mask comprising: a first BARC, a hard mask on the first BARC, a second BARC on the hard mask, and a photoresist on the second BARC; patterning the photoresist to form an opening, wherein a top surface of the second BARC is exposed toward the opening, the top surface being a top surface of a first and a second portion of the second BARC; forming a polymer layer on the photoresist, the polymer layer comprising a higher portion directly on the photoresist and a lower portion extending into the opening and contacting the top surface of the first portion of the second BARC; etching the polymer layer and the second BARC,wherein the first portion of the second BARC is removed during etching and the second portion of the second BARC remains after etching; etching the hard mask using the second BARC as an etch mask; etching the first BARC; and etching the target layer. In one embodiment, forming the polymer layer comprises forming a conformal layer. In one embodiment, after etching the second BARC, the second BARC further comprises a third portion surrounding the second portion, and the second portion is spaced from opposite sidewalls of the third portion of the second BARC. In one embodiment, the second portion is completely separated from the third portion of the second BARC. In one embodiment, the second portion has opposite ends,connected to the third portion of the second BARC. In one embodiment, the opening has a first width and the second portion has a second width ranging between about 25 percent and about 40 percent of the first width. In one embodiment, etching the target layer comprises etching a work function layer of a gate electrode of a transistor. In one embodiment, etching the target layer comprises etching a semiconductor fin. In one embodiment, etching the target layer comprises etching a dielectric layer to form an opening, and the method further comprises forming a conductive feature to fill the opening.

[0054] According to some embodiments of the present disclosure, a method comprises: forming a polymer layer on a patterned photoresist, the polymer layer extending into an opening in the patterned photoresist; etching the polymer layer to expose the patterned photoresist; etching the polymer layer and a top BARC to pattern the top BARC using the patterned photoresist as an etch mask; and using the top BARC as an etch mask to etch an underlying layer. In one embodiment, etching the underlying layer comprises etching a hard mask underlying the top BARC and etching a bottom BARC underlying the hard mask. In one embodiment, the polymer layer comprises a first portion on the patterned photoresist and a second portion in the opening contacting the top BARC.In one embodiment, the first and second portions of the polymer layer have substantially the same depth. In one embodiment, the polymer layer comprises an element selected from the group consisting of carbon, hydrogen, nitrogen, boron, chlorine, and combinations thereof. In one embodiment, the polymer layer and the upper BARC are etched using N2, H2, and CH4.

[0055] According to some embodiments of the present disclosure, a method comprises: forming a four-layer etch mask on a target layer, the four-layer etch mask comprising: a first BARC, a hard mask on the first BARC, a second BARC on the hard mask, and a photoresist on the second BARC; patterning the photoresist to form an opening and etching the second BARC, the hard mask, and the first BARC, the patterned photoresist being used as a portion of an etch mask, wherein after etching, two openings are formed in the second BARC, the two openings being separated by a remaining portion of the second BARC, and the two openings and the remaining portion of the second BARC together having a width substantially equal to a corresponding width of the opening in the photoresist.In one embodiment, the two openings are formed by removing two portions of the second BARC, and before the second BARC is etched, the two portions of the second BARC and the remaining portion of the second BARC are overlapped by the opening in the photoresist. In one embodiment, the method further comprises forming a polymer layer on the photoresist and the second BARC, contacting the photoresist and the BARC, and etching the polymer layer. In one embodiment, the polymer layer is etched without forming an etch mask thereon. In one embodiment, the polymer layer is a conformal layer.

Claims

[1] Procedure comprising: Forming a four-layer etch mask (74) over a target layer (72; 36A; 92), the four-layer etch mask (74) comprising: - a first bottom anti-reflective coating, BARC, (74A); - a hard mask (74B) on the first BARC (74A); - a second BARC (74C) on the hard mask (74B); and - a photoresist (74D) on the second BARC (74C); Patterning the photoresist (74D) to form an opening (75), wherein a top surface of the second BARC (74C) is exposed to the opening (75), and the top surface is a top surface of a first portion and a second portion (74C2) of the second BARC (74C); Forming a polymer layer (76) on the photoresist (74D), the polymer layer (76) comprising a higher portion directly above the photoresist (74D) and a lower portion (76A1) extending into the opening (75) and contacting the top of the first portion of the second BARC (74C); Etching the polymer layer (76) and the second BARC (74C), wherein the first portion of the second BARC (74C) is removed during etching and the second portion (74C2) of the second BARC (74C) remains after etching; Etching the hard mask (74B) using the second BARC (74C) as an etching mask; Etching the first BARC (74A); and Etching the target layer (72; 36A; 92). [2] The method of claim 1, wherein forming the polymer layer (76) comprises forming a conformal layer. [3] The method of claim 1 or 2, wherein, after etching the second BARC (74C), the second BARC (74C) further comprises a third portion (74C1) surrounding the second portion (74C2), and the second portion (74C2) is spaced from opposite sidewalls of the third portion (74C1) of the second BARC (74C). [4] The method of claim 3, wherein the second portion is completely separated from the third portion (74C1) of the second BARC (74C). [5] The method of claim 3 or 4, wherein the second portion (74C2) has opposite ends connected to the third portion (74C1) of the second BARC (74C). [6] The method of any preceding claim, wherein the opening (75) has a first width (W1), and the second portion (74C2) has a second width (W2) between about 25 percent and about 40 percent of the first width (W1). [7] The method of any preceding claim, wherein etching the target layer (72; 36A; 92) comprises etching a work function layer (72) of a gate electrode (83A, 83B) of a transistor (82A, 82B). [8] The method of any preceding claim, wherein etching the target layer (72; 36A; 92) comprises etching a semiconductor fin (36A). [9] The method of any preceding claim, wherein etching the target layer (72; 36A; 92) comprises etching a dielectric layer (92) to form an opening (94), and the method further comprises forming a conductive feature (96) to fill the opening (94). [10] Procedure comprising: Forming a polymer layer (76) on a patterned photoresist (74D), the polymer layer (76) extending into an opening (75) in the patterned photoresist (74D); Etching the polymer layer (76) to expose the patterned photoresist (74D); Etching the polymer layer (76) and an upper lower anti-reflective coating, BARC (74C) for patterning the upper BARC (74C), wherein the patterned photoresist (74D) is used as an etch mask; and Using the upper BARC (74C) as an etching mask for etching an underlying layer (72; 36A; 92), wherein the polymer layer (76) has a first portion on the patterned photoresist (74D) and a second portion (76A1, 74A2) in the opening (75) contacting the upper BARC (74C), the first and second portions (76A1, 76A2) of the polymer layer (76) having substantially the same depth (T1, T2). [11] The method of claim 10, wherein etching the underlying layer (72; 36A; 92) comprises: Etching a hard mask (74B) located beneath the upper BARC (74C); and Etching a lower BARC (74A) located under the hard mask (74B). [12] The method of any one of the preceding claims 10 and 11, wherein the polymer layer (76) comprises an element selected from carbon, hydrogen, nitrogen, boron, chlorine, and combinations of the foregoing. [13] The method of any one of the preceding claims 10 to 12, wherein the polymer layer (76) and the upper BARC (74C) are etched using N2, H2 and CH4. [14] Procedure comprising: Forming a four-layer etch mask (74) on a target layer (72; 36A; 92), the four-layer etch mask (74) comprising: - a first bottom anti-reflective coating, BARC, (74A); - a hard mask (74B) on the first BARC (74A); - a second BARC (74C) on the hard mask (74B); and - a photoresist (74D) on the second BARC (74C); Patterning the photoresist (74D) to form an opening (75); Forming a polymer layer (76) on the photoresist (74D) and the second BARC (74C) that contacts the photoresist (74D) and the second BARC (74C); Etching the polymer layer (76); and Etching the second BARC (74C), the hard mask (74B) and the first BARC (74A), wherein the patterned photoresist (74D) is used as a portion of an etch mask, wherein after etching two openings (77) are formed in the second BARC (74C), wherein the two openings (77) are separated from one another by a remaining portion (74C2) of the second BARC (74C), and the two openings (77) and the remaining portion (74C2) of the second BARC (74C) together have a width (W1) that is substantially equal to a corresponding width (W1) of the opening (75) in the photoresist (74D). [15] The method of claim 14, wherein the two openings (77) are formed by removing two portions of the second BARC (74C) and, before the second BARC (74C) is etched, the two portions of the second BARC (74C) and the remaining portion (74C2) of the second BARC (74C) are overlapped by the opening (75) in the photoresist (74D). [16] The method of claim 14, wherein the polymer layer (76) is etched without forming an etching mask thereon. [17] The method of any one of claims 14 to 16, wherein the polymer layer (76) is a conformal layer.

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