STORAGE CELL WITH SINGLE-POLE SELECTORS

Abstract

Integrated chip, comprehensive: an MTJ device (102) arranged within a dielectric structure (204) over a substrate (202), wherein the MTJ device (102) has an MTJ (210) arranged between a first electrode (208, 212) and a second electrode (208, 212); a first unipolar selector (106a, 106b, 108a, 108b) arranged within the dielectric structure (204) and connected to the first electrode (208, 212), wherein the first unipolar selector (106a, 106b, 108a, 108b) is configured to allow current to flow along a first direction through the MTJ device (102); and a second unipolar selector (106a, 106b, 108a, 108b) arranged within the dielectric structure (204) and connected to the first electrode (208, 212), wherein the second unipolar selector (106a, 106b, 108a, 108b) is configured to allow current to flow along a second direction opposite to the first direction through the MTJ device (102); wherein the first unipolar selector (106a, 106b, 108a, 108b) and the second unipolar selector (106a, 106b, 108a, 108b) are vertically separated; and wherein the first unipolar selector (106a, 106b, 108a, 108b) has a first width and the second unipolar selector (106a, 106b, 108a, 108b) has a second width which is less than the first width.

Description

BACKGROUND

[0001] Many modern electronic components and devices contain electronic memory designed to store data. This electronic memory can be volatile or non-volatile. Volatile memory retains data while powered, while non-volatile memory retains data even when power is lost. Magnetoresistive random-access memory (MRAM) is a promising candidate for next-generation non-volatile memory technology. State-of-the-art memory cells are described in US 2009 / 0180310A1, US 2018 / 0174650A1, US 9923027B2, US 2012 / 0044736A1, US 2012 / 0063192A1, US 2014 / 0160830A1 and DE 102019113405A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, for the clarity of the discussion, the dimensions of the various features may have been enlarged or reduced as desired. Fig. Figure 1 illustrates a schematic diagram of some embodiments of a memory circuit with an access device comprising several unipolar selectors configured to provide joint access to a magnetic tunnel junction (MTJ) device. The Fig. Figures 2A-2C illustrate cross-sectional views of some embodiments of integrated circuits with a memory cell having an access device comprising multiple unipolar selectors. The Fig. Figures 3A-3C illustrate schematic diagrams of some embodiments of read and write operations of a disclosed memory cell. Fig. 2A. Fig. Figure 4A illustrates a block diagram of some embodiments of a memory circuit comprising a memory array with multiple MRAM cells, each having an access device with multiple unipolar selectors. Fig. Figure 4B illustrates a table showing some embodiments of exemplary operating conditions of the memory array of Fig. 4A is shown. The Fig. Figures 5A-5C illustrate some additional embodiments of a memory circuit with an access device comprising several unipolar selectors having diodes. The Fig. Figures 6A-6B illustrate some additional embodiments of a memory circuit with an access device comprising several unipolar selectors having diodes. The Fig. Figures 7-15 illustrate some embodiments of a method for forming an integrated chip with an access device comprising multiple unipolar selectors configured to selectively provide access to an MTJ device. Fig. Figure 16 illustrates a flowchart of some embodiments of a method for forming an integrated chip with an access device comprising several unipolar selectors configured to selectively provide access to an MTJ device. DETAILED DESCRIPTION

[0003] The following disclosure provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element above or on top of a second element in the following description may have embodiments in which the first and second elements are formed in direct contact, and may also have embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, spatial relative terms such as "below," "under," "below," "above," "above," and the like may be used herein to facilitate description and to simplify the relationship of one element or feature to another element (or elements) or feature (or features), as illustrated in the figures. These spatial relative terms are intended to encompass different orientations of the component used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used here may be interpreted accordingly.

[0005] Magnetic tunnel junction (MTJ) devices comprise an MTJ arranged vertically between conductive electrodes. The MTJ includes a pinned layer separated from a free layer by a tunnel barrier layer. The magnetic orientation of the pinned layer is static (i.e., fixed), while the magnetic orientation of the free layer relative to that of the pinned layer is capable of switching between a parallel and an antiparallel configuration. The parallel configuration provides a low-resistance state in which data is digitally stored as a first data state (e.g., a logical "1"). The antiparallel configuration provides a high-resistance state in which data is digitally stored as a second data state (e.g., a logical "o").

[0006] Typically, MTJ devices are arranged in rows and columns within a memory array. A read or write operation is performed on an MTJ within the memory array by activating word lines and bit lines to operate an access device that selectively applies a voltage and / or current to the MTJ. To achieve different data states, the access device is typically a bipolar selector, which allows current to flow in opposite directions. This is because an MTJ switches between a high and a low resistance state depending on the direction of an applied current. For example, a current from a ground electrode or a high-voltage electrode can be applied to the data in a high-voltage state.A current flowing from the lower electrode to an upper electrode can give an MTJ device a high resistance state, while a current flowing from the upper electrode to the lower electrode can give the MTJ device a low resistance state.

[0007] One type of bipolar selector commonly used as an access device for MTJ devices is a MOSFET transistor. While a MOSFET transistor offers good performance, the relatively high voltage and / or current used during write operations of an MTJ device can cause the MOSFET transistor to be relatively large compared to MTJ devices. The large size of the MOSFET transistor limits how much small memory cells within a memory array can be miniaturized. Other types of bipolar selectors (e.g., stack-layer selectors) can alternatively be used as access devices for MTJ devices. While other types of bipolar selectors can be designed smaller, such bipolar selectors may fail to provide the speed and / or endurance advantages that MTJ devices offer over other memory types (e.g.,DRAM and / or SRAM) to maintain.

[0008] The present disclosure relates, in some embodiments, to an integrated chip comprising a memory cell with a magnetic tunnel junction (MTJ) device and an access device comprising multiple unipolar selectors (i.e., devices that, during normal operation, each conduct current in a single direction). Because the access device comprises multiple unipolar selectors, it is capable of conducting current through the MTJ device in opposite directions, thereby enabling the writing and reading of data from the MTJ device. Furthermore, the unipolar selectors are capable of being formed with a smaller size than an access transistor and with a higher quality than other types of bipolar selectors. Accordingly, the resulting memory cell is capable of a relatively small size (e.g., between 1 and 5 times the area of ​​an MTJ) and good performance (e.g.,high lifespan and low access speed).

[0009] Fig. Figure 1 illustrates a schematic diagram of some embodiments of a memory cell 100 with an access device comprising several unipolar selectors configured to jointly provide access to a magnetic tunnel junction (MTJ) device.

[0010] The memory cell 100 comprises an MTJ device 102 with a data storage layer 103b, which is arranged between a first electrode 103a and a second electrode 103c. The first electrode 103a is connected to a bit line BL, and the second electrode 103c is connected to an access device 104, which is configured to grant selective access (e.g., read access and / or write access) to the MTJ device 102. The access device 104 is further connected to a first word line WL1 and a second word line WL2. The MTJ device 102 is configured to store data based on its resistance. For example, the MTJ device 102 is configured to store either a first data state (e.g., a logic "1") if the MTJ device 102 is in a low-resistance state, or a second data state (e.g.,to store a logical “0”) if the MTJ component 102 is in a high-resistance state that has a higher resistance value than the low-resistance state.

[0011] The access device 104 comprises a first unipolar selector 106 and a second unipolar selector 108. The first unipolar selector 106 and the second unipolar selector 108 each comprise an anode terminal (an electrode into which positive current flows) and a cathode terminal (an electrode from which positive current flows). In some embodiments, a first cathode C1 of the first unipolar selector 106 and a second anode A2 of the second unipolar selector 108 are connected to the second electrode 103c of the MTJ device 102. In such embodiments, a first anode A1 of the first unipolar selector 106 is further connected to the first word line WL1, and a second cathode C2 of the second unipolar selector 108 is further connected to the second word line WL2.

[0012] In some embodiments, the first unipolar selector 106 and the second unipolar selector 108 may comprise diodes (e.g., PN diodes, PiN diodes, Schottky diodes, oxide semiconductor diodes, or the like). In such embodiments, an applied signal used to access (e.g., read and / or write) the MTJ device 102 is greater than a threshold value of the diodes. In other embodiments, the first unipolar selector 106 and the second unipolar selector 108 may comprise filament-based selectors, rectifiers, varistor-type selectors, ovonic threshold switches (OTS), doped chalcogenide-based selectors, Mott effect-based selectors, mixed ionic electronic conductivity (MIEC)-based selectors, field-assisted superliner threshold (FAST) selectors, or the like.In some embodiments, the first unipolar selector 106 and the second unipolar selector 108 can be unipolar selectors of the same type. In other embodiments, the first unipolar selector 106 and the second unipolar selector 108 can be different types of unipolar selectors. For example, in some embodiments, the first unipolar selector 106 can be a diode, and the second unipolar selector can be a filament-based selector.

[0013] During operation, the first unipolar selector 106 and the second unipolar selector 108 are each configured to allow current to flow in a single direction during normal operation (e.g., outside of a breakdown). For example, the first unipolar selector 106 is configured to allow current to flow through the MTJ device 102 along the first direction 110 (e.g., from the first word line WL1 to the bit line BL), and the second unipolar selector 108 is configured to allow current to flow through the MTJ device 102 along a second direction 112 that is opposite to the first direction 110 (e.g., from the bit line BL to the second word line WL2). When current is passed through the MTJ component 102 along the first direction 110, a first data state (e.g. a logical “o”) can be written into the MTJ component 102.When current of the second direction 112 flows through the MTJ component 102, a second data state (e.g. a logical “1”) can be written to the MTJ component 102.

[0014] Therefore, by using the first unipolar selector 106 and the second unipolar selector 108 to jointly control access to the MTJ device 102, the current flow through the MTJ device 102 can be selectively controlled along the first direction 110 and the second direction 112. Furthermore, the use of unipolar selectors within an access device offers several advantages over other types of access devices. For example, because the first unipolar selector 106 and the second unipolar selector 108 can be relatively small (e.g., approximately 1 to 5 times the size of the MTJ), the size of a memory cell 100 can be made relatively small (e.g., less than 50 nm).Furthermore, the wide variety of available unipolar selectors and the ability to use different unipolar selectors allows the access device 104 to be designed with high design flexibility and good resistance to voltage changes (e.g., due to high reverse bias threshold voltages), as well as good lifetime, operating voltage, current density, and speed. In addition, the use of unipolar selectors allows the biasing scheme of a storage array to be limited to a single bias polarity, thereby simplifying the power rails serving the storage array (e.g., a storage array can be served by positive voltage power rails and without negative voltage power rails).

[0015] The Fig. Figures 2A-2C illustrate cross-sectional views 200, 214 and 216 of some embodiments of integrated chips with a memory cell, which have an access device comprising multiple unipolar selectors.

[0016] Fig. Figure 2A illustrates a cross-sectional view 200 of some embodiments of an integrated chip comprising a dielectric structure 204 arranged over a substrate 202. The dielectric structure 204 comprises several stacked dielectric intermediate layer (ILD) layers and surrounds a first memory cell 205a and a second memory cell 205b, which is laterally adjacent to the first memory cell 205a. The first memory cell 205a comprises a first magnetic tunnel junction (MTJ) 102a configured to store a first data state. The second memory cell 205b comprises a second MTJ 102b configured to store a second data state. The first MTJ 102a and the second MTJ 102b each comprise an MTJ 210 arranged between a lower electrode 208 and an upper electrode 212.In some embodiments, the MTJ 210 comprises a pinned layer 210a separated from a free layer 210c by a dielectric tunnel barrier 210b. The pinned layer 210a has a fixed magnetization, while the free layer 210c has a magnetization that can be changed during operation (by the tunnel magnetoresistance (TMR) effect) to be either parallel (i.e., a "P" state) or antiparallel (i.e., an "AP" state) with respect to the magnetization of the pinned layer 210a. A relationship between the magnetizations of the pinned layer 210a and the free layer 210c defines a resistance state of the MTJ 210, thereby enabling the MTJ 210 to store a data state.

[0017] In some embodiments, the pinned layer 210a may comprise cobalt (Co), iron (Fe), boron (B), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), or the like. In some embodiments, the dielectric tunnel barrier 210b may comprise magnesium oxide (MgO), aluminum oxide (Al₂O₃), or the like. In some embodiments, the free layer 210c may comprise cobalt (Co), iron (Fe), boron (B), or the like. In some embodiments, the lower electrode 208 and the upper electrode 212 may comprise one or more of titanium, tantalum, tungsten, titanium nitride, tantalum nitride, or the like.

[0018] The dielectric structure 204 further surrounds several conductive interconnect layers 206. The several conductive interconnect layers 206 are configured to connect the first MTJ device 102a to a first access device 104a and the second MTJ device 102b to a second access device 104b. In various embodiments, the several conductive interconnect layers 206 can include conductive interconnect wires and conductive interconnect vias. The conductive interconnect wires and conductive interconnect vias comprise a conductive material (e.g., copper, aluminum, tungsten, or the like). In some embodiments, the conductive interconnect wires and conductive interconnect vias can further comprise a diffusion barrier layer and / or an adhesive layer surrounding the conductive material.

[0019] The first access device 104a has a first pair of unipolar selectors 106a and 108a, and the second access device 104b has a second pair of unipolar selectors 106b and 108b. The first pair of unipolar selectors 106a and 108a is configured to allow a current to flow in a single direction each, and together to allow a current to flow in opposite directions through the first MTJ device 102a. For example, a first unipolar selector 106a is configured to allow current to pass through the first MTJ device 102a along a first direction 110 (but not along a second direction 112 during normal operation), while a second unipolar selector 108a is configured to allow current to pass through the first MTJ device 102a along the second direction 112 (but not along the first direction 110 during normal operation).The second pair of unipolar selectors 106b and 108b is also each configured to allow current to flow in a single direction, and together to allow current to flow in opposite directions through the second MTJ device 102b.

[0020] It is understood that in different embodiments the unipolar selectors of an access device can be arranged at different positions within the dielectric structure 204 (e.g., on different metal planes). For example, the Fig. 2A-2C describe different embodiments of a first access device 104a comprising a first unipolar selector 106a and a second unipolar selector 106b arranged at different positions within the dielectric structure 204. These embodiments are not limiting but merely examples of possible positions of unipolar selectors within a disclosed access device.

[0021] As shown in the cross-sectional view 200 of Fig. As shown in Figure 2A, the first access device 104a in some embodiments comprises a first unipolar selector 106a and a second unipolar selector 108a, which are arranged vertically between a first MTJ device 102a and the substrate 202. In some such embodiments, the first unipolar selector 106a and the second unipolar selector 108a may be arranged along a horizontal plane that is parallel to an upper surface of the substrate 202. In other embodiments (not shown), the first unipolar selector 106a and the second unipolar selector 108a may be vertically separated.

[0022] As shown in cross-sectional view 214 of Fig. As shown in Figure 2B, in some other embodiments the first access device 104a comprises a first unipolar selector 106a and a second unipolar selector 108a, which are located vertically above the first MTJ device 102a. In still other embodiments, shown in cross-sectional view 216 of Fig. As shown in Figure 2C, the first access device 104a comprises a first unipolar selector 106a, which is arranged vertically between the first MTJ device 102a and the substrate 202, and a second unipolar selector 108a, which is located vertically above the first MTJ device 102a.

[0023] The Fig. 3A-3C illustrate schematic diagrams of some embodiments of read and write operations of the first memory cell of Fig. 2A.

[0024] Fig. Figure 3A illustrates a schematic diagram 300 of a first write operation that writes a first data state to the first MTJ device 102a. The first write operation is performed by applying a first non-zero bias voltage V1 (e.g., 6 V) to a first word line WL1 and a second word line WL2, and a second non-zero bias voltage V2 (e.g., 2 V) to a bit line BL. A difference between the first non-zero bias voltage V1 and the second non-zero bias voltage V2 (e.g., 6 V - 2 V) causes a first current I1 to flow from the first word line WL1 to the bit line BL and through the first unipolar selector 106a and the first MTJ device 102a. The second unipolar selector 108a prevents current from flowing from the second word line WL2 to the bit line BL.The first current I1 causes the resistance of the first MTJ device 102a to increase by switching the free layer 210c from a parallel to an antiparallel configuration with respect to the pinned layer 210a. The antiparallel configuration gives the first MTJ device 102a a high-resistance state, corresponding to a first data state (e.g., a logic "o").

[0025] Fig. Figure 3B illustrates a schematic diagram 302 of a second write operation that writes a second data state to the first MTJ device 102a. The second write operation is performed by applying a first non-zero bias V1 (e.g., 2 V) to the first word line WL1 and the second word line WL2, and a second non-zero bias V2 (e.g., 6 V) to the bit line BL. A difference between the first non-zero bias V1 and the second non-zero bias V2 (e.g., 6 V - 2 V) causes a second current I2 to flow from the bit line BL to the second word line WL2 and through the second unipolar selector 108a and the first MTJ device 102a. The first unipolar selector 106a prevents current from flowing from the bit line BL to the first word line WL1. The second current I2 causes the free layer 210c to switch from an antiparallel configuration to a parallel configuration with respect to the pinned layer 210a.The parallel configuration has a low-impedance state, which corresponds to a second data state (e.g., a logical "1").

[0026] Fig. Figure 3C illustrates a schematic diagram 304 of a read operation that reads data from the first MTJ device 102a. The read operation is performed by holding the first word line WL1 and the second word line WL2 to ground (GND) and applying a read voltage V. lesen (e.g., 1.2 V) to the bit line BL. A difference between the read voltage V lesenand ground (e.g., 1.2 V - 0 V) ​​causes a third current I3 to flow from the bit line BL to the second word line WL2 and through the second unipolar selector 108a and the first MTJ device 102a. The value of the third current I3 will depend on the resistance of the first MTJ device 102a (e.g., due to Ohm's law (V = IR), an MTJ with a high resistance will output a lower current than an MTJ with a low resistance). The third current I3 is supplied to a comparator 306, which is configured to compare the third current I3 with a reference current I. REF to compare in order to determine a data state stored in the first MTJ component 102a.

[0027] Fig. Figure 4A illustrates a block diagram of some embodiments of a memory circuit 400 comprising a memory array with multiple MRAM cells, each having an access device with multiple unipolar selectors.

[0028] The memory circuit 400 comprises a memory array 402 with several magnetoresistive direct access memory (MRAM) cells 404. a,1 -404 c,4 The multiple MRAM cells 404 a,1 -404 c,4 are arranged in rows and / or columns within the 402 memory array. For example, the first row of MRAM cells comprises the 404 MRAM cells. a,1 -404 c,1 , while a first column of MRAM cells the MRAM cells 404 a,1 -404 a,4 includes the multiple MRAM cells 404 a,1 -404 c,4Each MRAM cell 404 comprises an MTJ device 102n (n = ac) connected to an access device 104n (n = ac) having a first unipolar selector 106n (n = ac) and a second unipolar selector 108n (n = ac). The access device 104n is configured to selectively access an MTJ device 102n (n = ac) within one or more of the multiple MRAM cells 404n. a,1 -404 c,4 to be provided by controlling a current supplied to an associated MTJ device 102n (n = ac).

[0029] The memory array 402 is connected to a control circuit via several bit lines BL1-BL4 and several word lines WL1-WL6. In some embodiments, the control circuit comprises a bit line decoder 406 connected to the several bit lines BL1-BL4 and a word line decoder 408 connected to the several word lines WL1-WL6. In some embodiments, the control circuit may further comprise a sample / read amplifier 410 connected to the memory array 402 via several word lines WL1-WL6. The read amplifier 410 is configured to read data from the several MRAM cells 404. a,1 -404 c,4 to read.

[0030] An access device 104n (n = ac) is located between an MTJ component 102n (n = ac) and a pair of word lines WL x and WL x+1(x = 1-5) connected, while the MTJ component 102n (n = ac) is connected between the access device 104n (n = ac) and a bit line BL y (y = 1-4) is connected. It is understood that connecting the different unipolar selectors of an access device to different word lines can reduce leakage in unselected memory cells.

[0031] To access an MTJ component 102n (n = ac), the bit line decoder 406 is configured to selectively apply a first voltage to one or more of the bit lines BL1-BL4, based on a first address S ADDR1 , which is received by a control circuit, while the word line decoder 408 is configured to selectively apply a second voltage to one or more of the word lines WL1-WL6, based on a second address S ADDR2, which is received by the control circuit 412. The applied voltages cause a current to flow through either the first unipolar selector 106a or the second unipolar selector 108a, which is greater than or equal to a threshold voltage of the first unipolar selector 106a and the second unipolar selector 108a.

[0032] For example, it illustrates Fig. 4B a Table 414 which shows some exemplary bias conditions for read and write operations on a first MRAM cell 404 a,1 of the memory array 402 of Fig. 4A illustrates this. The in Fig. Figure 4B illustrated read and write operations read or write a single data state into a single MRAM cell, to use a multi-step process to read or write data into an entire row of the memory array 402.

[0033] A first row 416 of Table 414 illustrates some exemplary bias conditions of a first write operation that writes a first data state to the first MRAM cell 404 a,1 The first write operation is performed by changing the first MTJ component 102a to a high-impedance state (i.e., an antiparallel configuration). The first write operation holds the first bit line BL1 at ground (GND) and the first word line WL1 at V. DD , and the second word order WL2 on V DD A voltage difference between the first word line WL1 and the first bit line BL1 (e.g., V) DDA voltage difference (-GND) causes a current to flow through the first unipolar selector 106a and through the first MTJ device 102a in a direction extending from the first word line WL1 to the first bit line BL1. A voltage difference between the second word line WL2 and the first bit line BL1 prevents current from flowing through the first MTJ device 102a, as the second unipolar selector 108a prevents current flow in a direction extending from the second word line WL2 to the first bit line BL1.

[0034] During the first write operation, the second bit line BL2 is set to V DD -ΔV, the third bit line BL3 on V DD -ΔV, a third word line WL3 on a floating voltage state ("Float"), and a fourth word line WL4 on V DD -2Δ maintained. A voltage difference between the second bit line BL2 and the first word line WL1 (e.g., V) DD -(VDD -ΔV)) is too small to store data in the second MRAM cell 404 a,2 to write, while the second unipolar selector 108b prevents current flow in a direction extending from the third word line WL3 to the second bit line BL2. A voltage difference between the first bit line BL1 and the third word line WL3 (e.g., GND float) is too small to write data to the second MRAM cell 404. a,2 to write, while the second unipolar selector 108c prevents the current flow along a direction extending from the fourth word line WL4 to the first bit line BL1.

[0035] A second row 418 of Table 414 illustrates some exemplary bias conditions of a second write operation that writes a second data state to the first MRAM cell 404 a,1writes by changing the first MTJ component 102a to a low-resistance state (i.e., a parallel configuration). A third row 420 of Table 414 shows some example bias conditions of a read operation that writes a data state from the first MRAM cell 404. a,1 reads. In some embodiments, a reading voltage V can be applied. lesen , which is used during the reading operation, is approximately equal to V DD / 5. In some embodiments, ΔV may be approximately equal to or less than V. lesen be.

[0036] The Fig. Figures 5A-5C illustrate some additional embodiments of a memory circuit with an access device comprising several diodes configured to collectively provide access to an MTJ device. Although the memory circuits of Fig. While the memory circuits described in sections 5A-6B relate to unipolar selectors with diodes, they can also be applied to other types of unipolar selectors (e.g., filament-based unipolar selectors, rectifiers, varistor selectors, or the like).

[0037] Fig. Figure 5A illustrates a schematic diagram 500 of a memory cell with an access device comprising diodes configured to collectively provide access to an MTJ device.

[0038] The memory cell comprises an MTJ component 102, which is connected between a bit line BL and an access device 104 by a first diode 502 and a second diode 504. The first diode 502 has a first anode terminal A1, which is connected to a first word line WL1, and a first cathode terminal C1, which is connected to the MTJ component 102. The second diode 504 has a second cathode terminal C2, which is connected to a second word line WL2, and a second anode terminal A2, which is connected to the MTJ component 102.

[0039] Fig. Figure 5B illustrates a cross-sectional view of some embodiments of an integrated chip 506 according to the schematic diagram 500 of Fig. 5A.

[0040] The integrated chip 506 comprises a substrate 202 with an embedded memory area 508 and a logic area 510. A dielectric structure 204 is arranged over the substrate 202. The dielectric structure 204 comprises several stacked interlayer dielectric (ILD) layers 512a-512f, which are vertically separated by etch stop layers 513a-513e. In some embodiments, the several stacked ILD layers 512a-512f may comprise one or more silicon dioxide, SiCOH, a fluorosilicate glass, a phosphate glass (e.g., borophosphate silicate glass, etc.), or the like. In some embodiments, the etch stop layers 513a-513e may comprise a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

[0041] Within the embedded memory area 508, an access device 104 is connected to an MTJ device 102. The access device 104 comprises a first diode 502 and a second diode 504. The first diode 502 is arranged between a first connecting wire 514a and a second connecting wire 514b. In some embodiments, the first diode 502 may have a width that decreases with increasing distance from the substrate 202, while the second connecting wire 514b may have a width that increases with increasing distance from the substrate 202. In some embodiments, the second connecting wire 514b extends vertically to a distance d below a top surface of the first diode 502. In such embodiments, the second connecting wire 514b is arranged along portions of side walls of the first diode 502.In some embodiments, the diode 502 comprises a Schottky diode with a first metal layer 516a and a first semiconductor layer 518a contacting a top surface of the first metal layer 516a.

[0042] The first metal layer 516a acts as the anode terminal, and the first semiconductor layer 518a acts as the cathode terminal. In some embodiments, the first semiconductor layer 518a is arranged along a first conductive path between the first metal layer 516a and the MTJ device 102, such that the first diode 502 is configured to allow current to flow from the first connecting wire 514a to the second connecting wire 514b (i.e., along a first direction through the MTJ device 102). In some embodiments, the first metal layer 516a may comprise platinum, palladium, iridium, ruthenium, or the like. In some embodiments, the first semiconductor layer 518a may comprise silicon (e.g., n-doped silicon), germanium, a III-V semiconductor, a semiconductor oxide, indium gallium zinc oxide (IGZO), or the like.

[0043] The second connecting wire 514b is further connected to the MTJ component 102, which is arranged above the second connecting wire 514b. The MTJ component 102 has an MTJ 210, which is arranged between a lower electrode 208 and an upper electrode 212. In some embodiments, sidewall spacers 530 are arranged along opposite sides of the MTJ 210. The sidewall spacers 530 may have curved outermost sidewalls facing away from the MTJ 210. In various embodiments, the sidewall spacers 530 may comprise silicon nitride, silicon dioxide (SiO2), silicon oxynitride (e.g., SiON), or the like. In some embodiments, a cover layer 532 may be arranged over the MTJ 210 and the sidewall spacers 530. In various embodiments, the cover layer 532 can comprise silicon nitride, silicon dioxide (SiO2), silicon oxynitride (e.g. SiON), silicon carbide or the like.In some embodiments, an encapsulation layer 534 is located over the sidewall spacers 530 and the cover layer 532. In some embodiments, the encapsulation layer 534 may comprise an oxide (e.g., silicon-rich oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like. In some embodiments, an upper electrode via 536 extends through the encapsulation layer 534 and the cover layer 532 to contact the upper electrode 212. The upper electrode via 536 couples the upper electrode 212 to a third connecting wire 514c. In some embodiments, the upper electrode via 536 may comprise aluminum, copper, tungsten, or the like.

[0044] In some embodiments, a lower insulating structure 520 can be arranged between the second connecting wire 514b and the MTJ device 102. In some embodiments, the lower insulating structure 520 can be separated from a fourth ILD layer 512d by a fourth etch stop layer 513d. The lower insulating structure 520 comprises side walls that define an opening between the lower electrode 208 and the second connecting wire 514b. A lower electrode via 524 extends through the opening in the lower insulating structure 520. In some embodiments, the lower electrode via 524 can comprise a diffusion barrier layer 524a and an overlying metal 524b.

[0045] In some embodiments, the lower insulating structure 520 comprises a first dielectric layer 522, a second dielectric layer 526 above the first dielectric layer 522, and a third dielectric layer 528 above the first dielectric layer 522 and laterally adjacent to the second dielectric layer. In some embodiments, the first dielectric layer 522 extends to the top surface of a bottom electrode or bottom electrode via 524. In such embodiments, a bottom electrode or bottom electrode 208 may be located on the top surface of the first dielectric layer 522. In some embodiments, the third dielectric layer 528 is located entirely above the bottom electrode via 524 and laterally surrounds the bottom electrode 208.

[0046] In some embodiments, the first dielectric layer 522 may comprise silicon-rich oxide or the like. In some embodiments, the first dielectric layer 522 in the logic area 510 may have a greater (i.e., thicker) thickness than in the embedded memory area 508. In some embodiments, the second dielectric layer 526 may comprise silicon carbide, silicon nitride, or the like. In some embodiments, the second dielectric layer 526 may be the same material as the cover layer 532 over the MTJ device 102. In some embodiments, the third dielectric layer 528 may comprise tetraethyl orthosilicate (TEOS) or the like.

[0047] The second connecting wire 514b is further connected to the second diode 504 via a connecting via 515 and a fourth connecting wire 514d. In some embodiments, the first diode 502 extends laterally between a first vertical line that crosses the MTJ device 102 and a second vertical line that crosses the second diode 504. In some such embodiments, the first diode 504 has a top surface that extends continuously from directly below the MTJ device 102 to directly below the second diode 504.

[0048] In some embodiments, the second diode 504 comprises a Schottky diode with a second metal layer 516b and a second semiconductor layer 518b contacting a top surface of the second metal layer 516b. The second metal layer 516b acts as the anode terminal, and the second semiconductor layer 518b acts as the cathode terminal. In some embodiments, the second metal layer 516b is arranged between the first semiconductor layer 518a and the MTJ device 102 along a second conductive path, such that the second diode 504 is configured to allow current to flow from the second connecting wire 514b to a fifth connecting wire 514e (i.e., along a second direction) through the MTJ device 102. In some embodiments, the second metal layer 516b may comprise platinum, palladium, iridium, ruthenium, or the like. In some embodiments, the second semiconductor layer 518b may comprise silicon (e.g.,n-doped silicon), germanium, a III-V semiconductor, a semiconductor oxide, indium gallium zinc oxide (IGZO) or the like.

[0049] Within the logic area 510, one or more additional interconnect layers are arranged within the dielectric structure 204. The one or more additional interconnect layers comprise a conductive contact 540, a connecting wire 542, and a connecting via 544. The one or more additional interconnect layers are connected to a logic element 538 arranged within the substrate 202. In some embodiments, the logic element 538 may comprise a transistor device (e.g., a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT)), or the like.

[0050] In some embodiments, the first diode 502 may have a first width w1 (e.g., measured along an interface between the first metal layer 516a and the first semiconductor layer 518a), and the second diode 504 may have a second width w2 (e.g., measured along an interface between the second metal layer 516b and the second semiconductor layer 518b). In some embodiments, the first width w1 is essentially equal to the second width w2. In other embodiments, the first width w1 and the second width w2 may be different. In some embodiments, the first width w1 and the second width w2 are proportional to currents used to establish transitions between resistive states of the MTJ device 102.By making the first width w1 and the second width w2 proportional to currents used to establish transitions between resistive states, an intrinsic asymmetry of the operation of an MTJ can be optimized in the states of the MTJ device 102. For example, illustrated by... Fig. 5C some embodiments of a graphene 546 showing an exemplary current versus a resistance for the MTJ device 102.

[0051] As shown in graph 546, resistance (R) is shown on the y-axis and current (I) is shown on the x-axis. Transitions between a high-resistance state R H (i.e., an antiparallel configuration) and a low-impedance state R L (i.e., in a parallel configuration) change according to a hysteresis loop that is asymmetric. For example, if an MTJ device is in the high-resistance state R H , causes a current I AP-Pwith a first parameter that the MTJ device changes from a high-resistance state to a low-resistance state along segment 548 of the hysteresis loop. When the MTJ device is in a low-resistance state, a current I causes AP-P with a second parameter that the MTJ device changes from the low-resistance state to the high-resistance state along segment 550 of the hysteresis loop.

[0052] Therefore, a transition from the high-resistance state R is used. H to the low-resistance state R L a current I AP-P with a first quantity, while a transition from the low-resistance state R L to the high-resistance state R H a current I AP-Pwith a second size that is larger than the first size. In such embodiments, the first width w1 of the first diode 502 (i.e., the diode configured to provide a current through the MTJ device 102 along a first direction that simplifies a parallel-to-antiparallel transition) can be larger than a second width w2 of the second diode 504 (i.e., the diode configured to provide a current through the MTJ device 102 along a second direction that simplifies an antiparallel-to-parallel transition). It is understood that aligning the first diode 502 to provide a larger current through the MTJ device 102 than the second diode 504 allows the density of a memory array to be further increased, since the first diode 502 is subject to both the MTJ device 102 and the second diode 504 (and can thus be made larger without increasing the size of a memory cell).

[0053] Fig. Figure 6A illustrates a cross-sectional view of some alternative embodiments of an integrated chip 600 comprising a memory circuit with an access device having multiple diodes configured to collectively provide access to an MTJ device.

[0054] The integrated chip 600 comprises a substrate 202 with an embedded memory area 508 and a logic area 510. A dielectric structure 204 is arranged over the substrate 202 and comprises several stacked dielectric intermediate layer (ILD) layers 512a-512f, which are vertically separated by etch stop layers 513a-513e.

[0055] Within the embedded memory area 508, an access device 104 is connected to an MTJ device 102. The access device 104 comprises a first diode 502 and a second diode 504. The first diode 502 is arranged across a first interconnect 514a. The first diode 502 comprises a first metal layer 516a and a first semiconductor layer 518a, which contacts a top surface of the first metal layer 516a.

[0056] An additional metal layer 602 is arranged on a top surface of the first semiconductor layer 518a. In some embodiments, the additional metal layer 602 may comprise a metal that forms an ohmic contact with the first semiconductor layer 518a. For example, in some embodiments, the additional metal layer 602 may comprise molybdenum, titanium nitride, silver, or the like. In some embodiments, the first diode 502 and the additional metal layer 602 may each have widths that decrease with increasing distance from the substrate 202. In some embodiments, the side walls of the first diode 502 and the side walls of the additional metal layer 602 may be substantially aligned (e.g., along a conductor).

[0057] An MTJ device 102 and a connecting via 515 are arranged on an upper surface of the additional metal layer 602. In some embodiments, an additional etch stop layer (not shown) may be arranged between the additional metal layer 602 and the MTJ device. The connecting via 515 is further connected to a second diode 504.

[0058] Within the logic area 510, a connection via 544 is laterally separated from the MTJ component 102 and the connection via 515. A top surface of the additional metal layer 602 extends along a horizontal plane 604 that intersects the connection via 544 at a position between a top surface and a bottom surface of the connection via 544.

[0059] Fig. Figure 6B illustrates a cross-sectional view of some alternative embodiments of a diode 606 which can be used as the first diode or second diode in the access device.

[0060] The diode 606 is arranged above a first connecting wire 514a and comprises a first metal layer 516a and a first semiconductor layer 518a, which contacts a top surface of the first metal layer 516a. An additional metal layer 602 is arranged on the top surface of the first semiconductor layer 518a. In some embodiments, an adhesion-enhancing layer 608 (e.g., titanium, tantalum, or the like) may be arranged between the first metal layer 516a and the first connecting wire 514a. In some embodiments, the first semiconductor layer 518a may extend along the side walls of the adhesion-enhancing layer 608 and the first metal layer 516a. In some such embodiments, the first semiconductor layer 518a may contact the first connecting wire 514a along the outermost side walls of the first metal layer 516a.In some embodiments, the additional metal layer 602 can extend along the side wall and over a horizontally extending surface of the first semiconductor layer 518a.

[0061] The Fig. Figures 7-15 illustrate cross-sectional views 700-1500 of some embodiments of a method for forming an integrated chip with an access device comprising several unipolar selectors configured to selectively provide access to an MTJ device. Although the Fig. 7-15, which describe a procedure, it is understood that the information contained in the Fig. The structures revealed in 7-15 are not limited to such a procedure, but can stand on their own as structures independent of the procedure. Although the Fig. Although the procedure described in 7-15 refers to unipolar selectors with diodes, it can also be applied to other types of unipolar selectors.

[0062] As shown in the cross-sectional view 700 of Fig. As shown in Figure 7, a first connecting wire 514a is formed over a substrate 202. In some embodiments, the first connecting wire 514a is formed within a second dielectric intermediate layer (ILD) layer 512b, which is separated from the substrate 202 by a first ILD layer 512a. In some embodiments, the first ILD layer 512a and the second ILD layer 512b are separated by a first etch stop layer 513a. The second ILD layer 512b is structured to define a trench 702. In some embodiments, the second ILD layer 512b can be structured by forming a structured masking layer (not shown) over the second ILD layer 512b and performing an etching process to remove portions of the second ILD layer 512b that are not covered by the structured masking layer. Within trench 702, a conductive material is formed, followed by a subsequent planarization process (e.g.a chemical-mechanical planarization process) to form the first connecting wire 514a.

[0063] In various embodiments, the substrate 202 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more chips on a wafer, as well as any other type of semiconductor and / or epitaxial layers associated therewith. In some embodiments, the first ILD layer 512a and the second ILD layer 512b can comprise one or more dielectric materials, such as silicon dioxide (SiO2), SiCOH, a fluorosilicate glass, a phosphate glass (e.g., borophosphate silicate glass), or the like. In some embodiments, the conductive material can comprise a metal (e.g., aluminum, copper, tungsten, etc.) formed by a deposition process (e.g., CVD, PVD, PE-CVD, ALD, etc.).In various embodiments, the first connecting wire 514a can be a first connecting wire layer, a second connecting wire layer, a third connecting wire layer, or a higher metal connecting wire layer.

[0064] The Fig. Figures 8A-8C illustrate some embodiments of cross-sectional views showing the formation of a first diode 502 on the first connecting wire 514a.

[0065] As shown in the cross-sectional view 800 of 8A, in some embodiments a second etch stop layer 513b can be formed over the second ILD layer 512b and the first connecting wire 514a. The second etch stop layer 513b can be formed by a deposition process. The second etch stop layer 513b is subsequently structured to form an opening 802 over the first connecting wire 514a.

[0066] A first layer of diode metal 804 is formed over the second etch stop layer 513b and within the opening 802. The first layer of diode metal 804 can be formed by a deposition process. In some embodiments, the first layer of diode metal 804 can be formed with a thickness between approximately 10 nm and approximately 50 nm. In some embodiments, the first layer of diode metal 804 can be formed with a thickness between approximately 20 nm and approximately 100 nm. A first layer of semiconductor material 806 is formed on top of the first layer of diode metal 804. In some embodiments, the first layer of semiconductor material 806 can be formed with a thickness between approximately 50 nm and approximately 150 nm. The first layer of semiconductor material 806 forms a Schottky barrier at an interface between the first layer of semiconductor material 806 and the first layer of diode metal 804.

[0067] As shown in the cross-sectional view 808 of 8B, the first layer is made of diode metal (804 of Fig. 8A) and the first layer of semiconductor material (806 of Fig. 8B) selectively structured to define a first diode 502 across the first connecting wire 514a. The first diode 502 comprises a Schottky diode with a first metal layer 516a and a first semiconductor layer 518a. In some embodiments, the first layer is composed of diode metal (804 of Fig. 8A) and the first layer of semiconductor material (806 of Fig. 8B) in areas not covered by a first masking layer 812, selectively exposed to an etchant 810. In some embodiments, the first masking layer 812 may comprise a photoresist or a hard mask (e.g., titanium, silicon nitride, or the like). The first masking layer 812 is removed after structuring the first diode 502.

[0068] As shown in cross-sectional view 814 of Fig. As shown in Figure 8C, a third ILD layer 512c is formed over the first diode 502. The third ILD layer 512c is structured to define a trench 816 located over the first diode 502. The trench 816 is filled with a conductive material, followed by a planarization process (along the conductor 818) to remove conductive material over the third ILD layer 512c. The planarization process defines a second connecting wire 514b located between a top surface of the first diode 502 and a top surface of the third ILD layer 512c.

[0069] The Fig. Figures 9A-9C illustrate some alternative embodiments of cross-sectional views showing the formation of a first diode 502 on the first connecting wire 514a.

[0070] As shown in cross-sectional view 900 of 9A, a second etch stop layer 513b is formed over the second ILD layer 512b and the first connecting wire 514a. The second etch stop layer 513b is then structured to form an opening 802 over the first connecting wire 514a. A first layer of diode metal 804 is formed over the second etch stop layer 513b, and within the opening 802, a first layer of semiconductor material 806 is formed on top of the first layer of diode metal 804, and a layer of additional metal 902 is formed on top of this. The layer of additional metal 902 comprises a metal configured to form an ohmic contact with the first layer of semiconductor material 806.

[0071] As shown in cross-sectional view 904 of Fig. As shown in 9B, the first layer is made of diode metal (804 of Fig. 9A), the first layer of semiconductor material (806 of Fig. 9A) and the layer of additional metal (902 of Fig. 9A) selectively structured to define a first diode 502 above the first connecting wire 514a. The first diode 502 comprises a Schottky diode with a first metal layer 516a and a first semiconductor layer 518a. An additional metal layer 602 is arranged above the first diode 502. In some embodiments, the first layer is made of diode metal (804 of Fig. 9A), the first layer of semiconductor material (806 of Fig. 9A) and the layer of additional metal (902 of Fig. 9A) in areas not covered by a second masking layer 908, selectively exposed to an etchant 906. In some embodiments, the second masking layer 908 may comprise a photoresist or a hard mask (e.g., titanium, silicon nitride, or the like). The second masking layer 908 is removed after structuring the first diode 502.

[0072] As shown in the cross-sectional view 910 of Fig. As shown in Figure 9C, a third ILD layer 512c is formed over the first diode 502. Subsequently, a planarization process (along the line 912) is carried out to remove part of the third ILD layer 512c and expose a top surface of the additional metal layer 602.

[0073] As shown in the cross-sectional view 1000 of Fig. As shown in Figure 10, a lower insulating structure 520 is formed over the third ILD layer 512c. In some embodiments, the lower insulating structure 520 can be deposited and then selectively patterned to define a lower electrode via opening 1002 over the second connecting wire 514b. In some embodiments, the lower insulating structure 520 can comprise a fourth etch stop layer 513d and a first dielectric layer 522 arranged over the fourth etch stop layer 513d. In various embodiments, the first dielectric layer 522 can comprise silicon carbide, silicon-rich oxide, TEOS (tetraethyl orthosilicate), or the like.

[0074] As shown in the cross-sectional view 1100 of Fig. As shown in Figure 11, a bottom electrode structure, or lower electrode structure, 1102 is formed above the lower insulation structure 520 and within the lower electrode via opening 1002. In some embodiments, the lower electrode structure 1102 may comprise a lower electrode via layer 1104 and an overlying lower electrode layer 1106. An MRAM stack 1108 is formed above the lower electrode structure 1102. In some embodiments, the MRAM stack 1108 may comprise a pinned layer 1110, a dielectric barrier tunnel layer 1112, and a free layer 1114. In some embodiments, the pinned layer 1110 may be formed between the free layer 1114 and the bottom electrode structure 1102. In other embodiments (not shown) the free layer 1114 can be formed between the pinned layer 1110 and the lower electrode structure 1102.An upper electrode structure 1116 is formed above the MRAM stack 1108.

[0075] As shown in the cross-sectional view 1200 of Fig. 12 shows the upper electrode structure (1116 of Fig. 11), the MTJ stack (1108 of Fig. 11) and the lower electrode structure (1102 of Fig. 11) selectively structured to define an MTJ device 102 with a lower electrode 208 separated from an upper electrode 212 by an MTJ 210. In some embodiments, the upper electrode structure (1116 of Fig. 11) and the MTJ stack (1108 of Fig. 11) A mask layer 1202 (e.g., silicon nitride, silicon carbide, or the like) formed over the upper electrode structure is selectively etched to define an upper electrode 212 and an MTJ 210. Subsequently, sidewall spacers 530 are formed along sides of the MTJ 210, and a second etching process is carried out to define the lower electrode structure (1102 of Fig. 11) to selectively etch and define a lower electrode 208 and a lower electrode via 524. After its formation, an encapsulation layer 534 can be formed over the MTJ device 102.

[0076] As shown in the cross-sectional view 1300 of Fig. As shown in Figure 13, a fourth ILD layer 512d is formed above the encapsulation layer 534. The fourth ILD layer 512d is structured to define a first opening 1302 and a second opening 1304. The opening 1302 extends from the top surface of the fourth ILD layer 512d to the upper electrode 212. The second opening 1304 extends from the top surface of the fourth ILD layer 512d to the second connecting wire 514b. The first opening 1302 and the second opening 1304 are then filled with a conductive material, followed by a planarization process (along the conductor 1306). The conductive material within the first opening 1302 defines an upper electrode via 536, which contacts the upper electrode 212 and a third connecting wire 514c above the upper electrode via 536.The conductive material inside the second opening 1304 defines a connecting via 515 and a fourth connecting wire 514d above the connecting via 515.

[0077] The Fig. Figures 14A-14B illustrate some alternative embodiments of cross-sectional views showing the formation of a second diode 504 on the fourth connecting wire 514d.

[0078] As shown in the cross-sectional view 1400 of Fig. As shown in Figure 14A, a fourth etch stop layer 513d is formed over the fourth ILD layer 512d. The fourth etch stop layer 513d can be formed by a deposition process. The fourth etch stop layer 513d is then structured to form a second opening 1406 over the fourth connecting wire 514d.

[0079] A second layer of diode metal 1402 is formed above the fourth etch stop layer 513d and within the second opening 1406. This second layer of diode metal 1402 can be deposited with a thickness between approximately 10 nm and approximately 100 nm. A second layer of semiconductor material 1404 is deposited on top of the second layer of diode metal 1402. This second layer of semiconductor material 1404 can be deposited with a thickness between approximately 50 nm and approximately 150 nm. The second layer of semiconductor material 1404 forms a Schottky barrier at the interface between the second layer of semiconductor material 1404 and the second layer of diode metal 1402.

[0080] As shown in the cross-sectional view 1408 of Fig. As shown in 14B, the second layer is made of diode metal (1402 of Fig. 14A) and the second layer of semiconductor material (1404 of Fig. 14A) selectively structured to define a second diode 504 comprising a Schottky diode with a second metal layer 516b and a second semiconductor layer 518b over the second metal layer 516b. In some embodiments, the second layer is composed of diode metal (1402 of Fig. 14A) and the second layer of semiconductor material (1404 of Fig. 14A) in areas not covered by a third masking layer 1412, selectively exposed to an etchant 1410. In some embodiments, the third masking layer 1412 may comprise a photoresist or a hard mask (e.g., titanium, silicon nitride, or the like). The third masking layer 1412 is removed after structuring the second diode 504.

[0081] As shown in the cross-sectional view 1500 of Fig. As shown in Figure 15, a fifth ILD layer 512e is formed above the second diode 504. The fifth ILD layer 512e is structured to define a trench 1502 above the second diode 504. The trench 1502 is filled with a conductive material, followed by a planarization process (e.g., a chemical-mechanical planarization process along the conductor 1504) to remove conductive material above the fifth ILD layer 512e. The planarization process defines a fifth connecting wire 514e.

[0082] Fig. Figure 16 illustrates a flowchart of some embodiments of a method 1600 for forming an integrated chip with a memory circuit comprising memory cells (e.g. MRAM cells) with an access device comprising several unipolar selectors.

[0083] While Procedure 1600 is subsequently illustrated and described as a series of operations or events, it is understood that the illustrated sequence of such operations or events is not to be interpreted in a restrictive sense. For example, some operations may occur in a different order and / or concurrently with other operations or events than those illustrated and / or described herein. Additionally, it may not be necessary to include all of the operations illustrated herein to implement one or more aspects or embodiments of the description. Furthermore, one or more of the operations illustrated herein may be performed in one or more separate operations and / or phases.

[0084] At 1602, a first unipolar selector is formed over a substrate. The first unipolar selector has a first anode and a first cathode. Fig. Figures 8A-8C illustrate cross-sectional views 800, 808 and 814 of some embodiments corresponding to process 1604. Fig. Figures 9A-9C illustrate cross-sectional views 900, 906 and 912 of some alternative embodiments corresponding to process 1602.

[0085] In 1604, a second unipolar selector is formed above the substrate. In some embodiments, the second unipolar selector is fabricated separately from the first unipolar selector (e.g., at different interconnect layers). The separate fabrication of the first and second unipolar selectors allows for the optimization of a region within a corresponding memory cell and also enables the simple fabrication of the first and second unipolar selectors as different types of unipolar selectors. Fig. Figures 14A-14B illustrate cross-sectional views 1400 and 1408 of some embodiments corresponding to process 1604.

[0086] At 1606, an MTJ device is formed above the substrate. The MTJ device has a first electrode configured to be connected to the first cathode and the second anode, and a second electrode configured to be connected to the first anode and the second cathode. Fig. Figures 11-12 illustrate cross-sectional views 1100-1200 of some embodiments corresponding to process 1606.

[0087] In device 1608, several interconnect layers are formed over the substrate. These interconnect layers are configured to connect the first cathode to the second anode and / or to the first electrode. Furthermore, the interconnect layers are configured to connect the first anode to a first word line, the second cathode to a second word line, and the second electrode to a bit line. In various embodiments, the interconnect layers can be formed before, after, or between the formation of the first unipolar selector, the second unipolar selector, and the MTJ device. Fig. 7, Fig. 10, Fig. 13 and Fig. Figure 15 illustrates cross-sectional views 700, 1000, 1300 and 1500 of some embodiments corresponding to process 1608.

[0088] Accordingly, in some embodiments, the present disclosure relates to an integrated chip comprising a memory cell with a magnetic tunnel junction (MTJ) device and an access device with multiple unipolar selectors (i.e., devices which each conduct current in a single direction during normal operation).

[0089] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises: a magnetic tunnel junction (MTJ) device arranged within a dielectric structure over a substrate, the MTJ device having an MTJ arranged between a first electrode and a second electrode; a first unipolar selector arranged within the dielectric structure and connected to the first electrode, the first unipolar selector being configured to allow current to flow through the MTJ device in a first direction; and a second unipolar selector arranged within the dielectric structure and connected to the first electrode, the second unipolar selector being configured to allow current to flow through the MTJ device in a second direction opposite to the first direction.In some embodiments, the first unipolar selector is a first diode and the second unipolar selector is a second diode. In some embodiments, the first unipolar selector is connected between a first word line and the first electrode of the MTJ device; the second unipolar selector is connected between a second word line and the first electrode of the MTJ device; and the second electrode of the MTJ device is connected to a bit line. In some embodiments, the first unipolar selector extends laterally between a first vertical line crossing the MTJ device and the substrate, and a second vertical line crossing the second unipolar selector and the substrate. In some embodiments, the first unipolar selector is arranged vertically below the MTJ device, and the second unipolar selector is arranged vertically above the MTJ device.In some embodiments, the first unipolar selector comprises a first metal layer and a first semiconductor layer, the first semiconductor layer being arranged along a first conductive path between the first metal layer and the MTJ device; and the second unipolar selector comprises a second semiconductor layer and a second metal layer, the second metal layer being arranged along a second conductive path between the second semiconductor layer and the MTJ device. In some embodiments, the integrated chip further comprises an additional metal layer arranged between a top surface of the first unipolar selector and a bottom surface of the MTJ device, the additional metal layer having a first width that decreases with increasing distance from the substrate, and the first unipolar selector having a second width that decreases with increasing distance from the substrate.In some embodiments, the integrated chip further comprises a interconnect via located within the substrate at a position laterally separated from the additional metal layer, wherein a horizontal plane runs parallel to an upper surface of the substrate, extending along an upper surface of the additional metal layer and through a side wall of the interconnect via. In some embodiments, the integrated chip further comprises an interconnect via laterally separated from the MTJ device, having a bottom surface that contacts a top surface of the additional metal layer and a top surface that is connected to the second unipolar selector.In some embodiments, the integrated chip further comprises a connecting wire arranged between a top surface of the first unipolar selector and a bottom surface of the MTJ device, the connecting wire extending along the side walls of the first unipolar selector. In some embodiments, the first unipolar selector has a first width, and the second unipolar selector has a second width that is less than the first width. In some embodiments, the first unipolar selector is configured to conduct current through the MTJ device in a direction that facilitates a parallel-to-antiparallel transition. In some embodiments, the first unipolar selector has a top surface that extends continuously from directly below the MTJ device to directly below the second unipolar selector.

[0090] In other embodiments, the present disclosure relates to an integrated circuit. The integrated chip comprises a magnetic tunnel junction (MTJ) device with a first electrode connected to a bit line and a second electrode; and an access device connected to the second electrode, comprising several unipolar selectors, each configured to conduct current through the MTJ device in a single direction, the several unipolar selectors collectively configured to conduct currents through the MTJ device in opposite directions. In some embodiments, the access device comprises a first unipolar selector connected between a first word line and the first electrode of the MTJ device; and a second unipolar selector connected between a second word line and the first electrode of the MTJ device.In some embodiments, the access device comprises a first unipolar selector with a first cathode terminal connected to the first electrode; and a second unipolar selector with a second anode terminal connected to the first electrode. In some embodiments, the access device comprises a first unipolar selector with a first cathode terminal connected to the first electrode and a first anode terminal connected to a first word line; and a second unipolar selector with a second anode terminal connected to the first electrode and a second cathode terminal connected to a second word line.In some embodiments, the integrated chip further includes a control circuit configured to operate a word line decoder to simultaneously apply a first non-zero bias to multiple word lines connected to the access device of the MTJ device during a write operation into which a data state is written.

[0091] In other embodiments, the present disclosure relates to a method for forming an integrated chip. The method comprises forming a magnetic tunnel junction (MTJ) device over a semiconductor substrate, wherein the MTJ device includes an MTJ arranged between a first electrode and a second electrode; forming a first unipolar selector over the semiconductor substrate, wherein the first unipolar selector is configured to be connected to the first electrode and to allow current to flow through the MTJ device in a first direction; and forming a second unipolar selector over the semiconductor substrate, wherein the second unipolar selector is configured to be connected to the first electrode and to allow current to flow through the MTJ device in a second direction opposite to the first direction.In some embodiments, the method further comprises forming the MTJ device directly above or directly below a first connecting wire, wherein the first unipolar selector is formed such that it has a first anode terminal configured to be connected to the first connecting wire, and the second unipolar selector is formed such that it has a second cathode terminal configured to be connected to the first connecting wire.

Claims

[1] Integrated chip, comprising: an MTJ device (102) arranged within a dielectric structure (204) over a substrate (202), wherein the MTJ device (102) has an MTJ (210) arranged between a first electrode (208, 212) and a second electrode (208, 212); a first unipolar selector (106a, 106b, 108a, 108b) arranged within the dielectric structure (204) and connected to the first electrode (208, 212), wherein the first unipolar selector (106a, 106b, 108a, 108b) is configured to allow current to flow along a first direction through the MTJ device (102); and a second unipolar selector (106a, 106b, 108a, 108b) arranged within the dielectric structure (204) and connected to the first electrode (208, 212), wherein the second unipolar selector (106a, 106b, 108a, 108b) is configured to allow current to flow along a second direction opposite to the first direction through the MTJ device (102); wherein the first unipolar selector (106a, 106b, 108a, 108b) and the second unipolar selector (106a, 106b, 108a, 108b) are vertically separated; and wherein the first unipolar selector (106a, 106b, 108a, 108b) has a first width and the second unipolar selector (106a, 106b, 108a, 108b) has a second width which is less than the first width. [2] Integrated chip according to claim 1, wherein the first unipolar selector (106a, 106b, 108a, 108b) is a first diode and the second unipolar selector (106a, 106b, 108a, 108b) is a second diode. [3] Integrated chip according to claim 1 or 2, wherein the first unipolar selector (106a, 106b, 108a, 108b) is connected between a first word line (WL1, WL2) and the first electrode (208, 212) of the MTJ device (102); wherein the second unipolar selector (106a, 106b, 108a, 108b) is connected between a second word line (WL1, WL2) and the first electrode (208, 212) of the MTJ device (102); and wherein the second electrode (208, 212) of the MTJ device (102) is connected to a bit line (BL). [4] Integrated chip according to any of the preceding claims, wherein the first unipolar selector (106a, 106b, 108a, 108b) extends laterally between a first vertical line intersecting the MTJ device (102) and the substrate (202) and a second vertical line intersecting the second unipolar selector (106a, 106b, 108a, 108b) and the substrate (202). [5] Integrated chip according to any one of claims 1 to 3, wherein the first unipolar selector (106a, 106b, 108a, 108b) is arranged vertically below the MTJ device (102) and the second unipolar selector (106a, 106b, 108a, 108b) is arranged vertically above the MTJ device (102). [6] Integrated chip according to any of the preceding claims, wherein the first unipolar selector (106a, 106b, 108a, 108b) comprises a first metal layer and a first semiconductor layer, the first semiconductor layer being arranged along a first conductive path between the first metal layer and the MTJ device (102); and wherein the second unipolar selector (106a, 106b, 108a, 108b) comprises a second semiconductor layer and a second metal layer, wherein the second metal layer is arranged along a second conductive path between the second semiconductor layer and the MTJ device (102). [7] Integrated chip according to any of the preceding claims, further comprising: an additional metal layer arranged between a top surface of the first unipolar selector (106a, 106b, 108a, 108b) and a bottom surface of the MTJ device (102), wherein the additional metal layer has a width that decreases with increasing distance from the substrate (202), and wherein the first width of the first unipolar selector (106a, 106b, 108a, 108b) decreases with increasing distance from the substrate (202). [8] Integrated chip according to claim 7, further comprising: a connection via located within the substrate (202) at a position laterally separated from the additional metal layer, wherein a horizontal plane, forming an extension of an upper surface of the additional metal layer parallel to an upper surface of the substrate (202), passes through a side wall of the connection via. [9] Integrated chip according to claim 7, further comprising: a connecting via that is laterally separated from the MTJ device (102) and has a bottom surface that contacts an upper surface of the additional metal layer and a top surface that is connected to the second unipolar selector (106a, 106b, 108a, 108b). [10] Integrated chip according to any of the preceding claims, further comprising: a connecting wire arranged between a top side of the first unipolar selector (106a, 106b, 108a, 108b) and a bottom side of the MTJ device (102), the connecting wire forming an extension of the side walls of the first unipolar selector (106a, 106b, 108a, 108b). [11] Integrated chip according to any of the preceding claims, wherein the MTJ device (102) comprises a pinned layer and a free layer, and the pinned layer has a magnetization that is fixed, while the free layer has a magnetization that can be changed to be either parallel or antiparallel with respect to the magnetization of the pinned layer, and the first unipolar selector (106a, 106b, 108a, 108b) is configured to conduct current through the MTJ device (102) along a direction that facilitates a parallel-to-antiparallel transition. [12] Integrated chip according to any of the preceding claims, wherein the first unipolar selector (106a, 106b, 108a, 108b) has a top surface extending continuously from directly below the MTJ device (102) to directly below the second unipolar selector (106a, 106b, 108a, 108b). [13] Integrated chip, comprising: an MTJ device with a first electrode (208, 212) and a second electrode (208, 212) connected to a bit line (BL); and an access device (104) connected to the first electrode (208, 212) comprising several unipolar selectors (106a, 106b, 108a, 108b) each configured to conduct current along a single direction through the MTJ device (102), wherein the several unipolar selectors (106a, 106b, 108a, 108b) are jointly configured to conduct currents along opposite directions through the MTJ device (102), wherein a first unipolar selector (106a, 106b, 108a, 108b) of the multiple unipolar selectors (106a, 106b, 108a, 108b) has a first width and a second unipolar selector (106a, 106b, 108a, 108b) of the multiple unipolar selectors (106a, 106b, 108a, 108b) has a second width which is less than the first width; and wherein the first unipolar selector (106a, 106b, 108a, 108b) and the second unipolar selector (106a, 106b, 108a, 108b) are vertically separated. [14] Integrated chip according to claim 13, wherein the first unipolar selector (106a, 106b, 108a, 108b) is connected between a first word line (WL1, WL2) and the first electrode (208, 212) of the MTJ device (102); and the second unipolar selector (106a, 106b, 108a, 108b) is connected between a second word line (WL1, WL2) and the first electrode (208, 212) of the MTJ device (102). [15] Integrated chip according to claim 13, wherein the first unipolar selector (106a, 106b, 108a, 108b) has a cathode terminal connected to the first electrode (208, 212); and the second unipolar selector (106a, 106b, 108a, 108b) has an anode terminal connected to the first electrode (208, 212). [16] Integrated chip according to claim 13, wherein the first unipolar selector (106a, 106b, 108a, 108b) has a first cathode terminal connected to the first electrode (208, 212) and a first anode terminal connected to a first word line (WL1, WL2); and the second unipolar selector (106a, 106b, 108a, 108b) has a second anode terminal connected to the first electrode (208, 212) and a second cathode terminal connected to a second word line (WL1, WL2). [17] Integrated chip according to any one of claims 13 to 16, further comprising: a control circuit configured to operate a word line decoder to simultaneously apply an initial non-zero bias to multiple word lines (WL1, WL2) connected to the access device (104) during a write operation that writes a data state to the MTJ device (102). [18] Method for forming an integrated chip, comprising: Forming an MTJ device (102) over a semiconductor substrate (202), wherein the MTJ device (102) has an MTJ (210) arranged between a first electrode (208, 212) and a second electrode (208, 212); Forming a first unipolar selector (106a, 106b, 108a, 108b) over the semiconductor substrate (202), wherein the first unipolar selector (106a, 106b, 108a, 108b) is configured to be connected to the first electrode (208, 212) and to allow current to flow along a first direction through the MTJ device (102); and Forming a second unipolar selector (106a, 106b, 108a, 108b) over the semiconductor substrate (202), wherein the second unipolar selector (106a, 106b, 108a, 108b) is configured to be connected to the first electrode (208, 212) and to allow current to flow through the MTJ device (102) in a second direction opposite to the first direction, wherein the first unipolar selector (106a, 106b, 108a, 108b) has a first width and the second unipolar selector (106a, 106b, 108a, 108b) has a second width which is less than the first width, and wherein the first unipolar selector (106a, 106b, 108a, 108b) and the second unipolar selector (106a, 106b, 108a, 108b) are vertically separated. [19] The method of claim 18, further comprising: Forming the MTJ device (102) directly above or directly below a first connecting wire, wherein the first unipolar selector (106a, 106b, 108a, 108b) is formed, having a first anode terminal configured to be connected to the first connecting wire, and the second unipolar selector (106a, 106b, 108a, 108b) is formed, having a second cathode terminal configured to be connected to the first connecting wire.

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