Magnetic tunnel junction structure and methods for its manufacture

Abstract

A method for fabricating a magnetic tunnel junction structure, hereinafter referred to as an MTJ structure, comprising: depositing an MTJ stack on a bottom electrode (10), the MTJ stack comprising at least a seed layer (12), a pinned layer (14) on the seed layer (12), a barrier layer (16) on the pinned layer (14), and a free layer (18) on the barrier layer (16); depositing a top electrode layer (20) on the MTJ stack; depositing a hard mask (22) on the top electrode layer (20); first etching the top electrode layer (20) and the hard mask (22); then second etching of the MTJ stack not covered by the hard mask (22), and stopping the second etching at or within the seed layer (12);then depositing an encapsulation layer (26) over the partially etched MTJ stack and etching away the encapsulation layer (26) on horizontal surfaces, leaving a self-aligning hard mask (28) on the sidewalls of the partially etched MTJ stack, wherein the self-aligning hard mask (28) is arranged along the sidewalls of the pinned layer (14) and extends to and physically contacts a top surface of the nucleation layer (12); then a third etching of the remaining MTJ stack not covered by the hard mask layer (22) and the self-aligning hard mask (28) to complete the MTJ structure, wherein after the third etching the self-aligning hard mask (28) covers the sidewalls of the free layer (18), the barrier layer (16) and the pinned layer (14) and does not contact the sidewall of the top electrode layer (20).

Description

TECHNICAL FIELDThis application relates to the general field of magnetic tunneling junctions (MTJs), and more particularly to etching methods for forming MTJ structures.GENERAL STATE OF THE ARTThe fabrication of magnetoresistive random-access memory (MRAM) devices typically involves a sequence of processing steps during which many layers of metals and dielectrics are deposited and then patterned to form a magnetoresistive stack as well as electrodes for electrical connections. Defining the magnetic tunnel junctions (MTJ) in each MRAM device typically involves precise patterning steps, including photolithography and reactive ion etching (RIE), ion beam etching (IBE), or combinations thereof. During RIE, high energy ions vertically remove materials in those areas that are not masked by photoresist, thereby separating one MTJ cell from another.However, the high energy ions may also react laterally with the unremoved materials, oxygen, moisture and other chemicals, causing sidewall damage and reducing device performance. To solve this problem, physical etching techniques such as Ar-RIE or ion beam etching (IBE) have been used to etch the MTJ stack. However, due to the non-volatile nature, physically etched conductive materials in the MTJ and bottom electrode may form a continuous path across the tunnel barrier, resulting in short-circuited devices. A new approach to overcoming this dilemmas is therefore required when it is desired to develop the full potential of this physical etch to pattern the future MRAM products below 60 nm.Several references teach multiple step etching processes for forming MTJs, including U.S. Patents US 9 793 126 B2 (Dhindsa et al.), US 9 722 174 B1 (Nagel et al.), and US 8 883 520 B2 (Satoh et al.). All of these references are different from the present disclosure. US 2018 / 0 033 957 A1 discloses a method for manufacturing a magnetic tunnel junction structure in which a self-aligning hard mask is at least partially removed from the sidewalls of the top electrode to prevent short circuits across the tunnel barrier.Further prior art relating to the invention can be found, for example, in the publications U.S. Pat. No. 2016 / 0 225 981 A1, U.S. Pat. No. 2004 / 0 063 223 A1 and U.S. Pat. No. 2006 / 0 261425 A1.SUMMARYIt is an object of the present disclosure to provide an improved method of forming MTJ structures.Yet another object of the present disclosure is to provide a method of forming MTJ devices using incomplete physical etching to prevent both chemical damage and physical shorts.Another object of the present disclosure is to provide a method of forming MTJ devices using incomplete physical etching to prevent both chemical damage and physical shorts when manufacturing separate non-interacting MTJ cells using encapsulant as a self-aligning process.In accordance with the objectives of the present disclosure, a method of etching a magnetic tunneling junction (MTJ) structure is achieved. An MTJ stack is deposited on a bottom electrode, the MTJ stack comprising at least one pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer. A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and the hard mask are etched. Subsequently, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned or seed layer. An encapsulation layer is then deposited over the partially etched MTJ stack and etched away on horizontal surfaces, leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by the hard mask and self-aligned hard mask is etched to complete the MTJ structure.BRIEF DESCRIPTION OF THE DRAWINGSIn the accompanying drawings, which form a principal part of this disclosure, the following is shown:FIGS. 1, 2, 3, 4, 5-6 illustrate steps in a cross-sectional view in a preferred embodiment of the present disclosure.DETAILED DESCRIPTIONIn a typical process, the entire MTJ stack is patterned by a single etch step, either chemical RIE or physical Ar-RIE or IBE. It thus creates either chemical damage or physical shorts on the MTJ sidewall. In the process of the present disclosure, first, the MTJ stack is partially etched to minimize physical reprint. Then, using encapsulant as a self-aligned hard mask, the remaining MTJ is etched. This new process simultaneously prevents chemical damage and physical shorts. Moreover, the second etching step is a self-aligning process, which means that it does not require a complicated photolithography step in which the capping accuracy is difficult to control, particularly for sub-60 nm MRAM devices.In the process of the present disclosure, the MTJ stack is first partially etched by a physical etch such as RIE or IBE using different gas plasmas such as Ar and Xe, so that there is no chemical damage but only conductive deposition on the sidewall. The amount of address depends on the amount of etching. By intentionally incomplete etching, for example by etching away only the free layer, the tunnel barrier and / or a part of the pinned or the seed layer, the disposition of the address on the tunnel barrier sidewall can be significantly reduced or completely removed. An encapsulating material is deposited to protect the previously etched MTJ. RIE or IBE etching partially eliminates the portion of encapsulation material that is on top and bottom of the MTJ structures. Next, using the encapsulant remaining on the MTJ sidewalls as a self-aligned hard mask, the remaining MTJ is etched, creating separate and non-interacting MTJ cells. Regardless of the type of etch used, the free layer and the tunnel barrier layer are not affected by this step due to protection by the encapsulation material, thus preserving high device performance. Referring now to FIGS. 1, 2, 3, 4, 5 to 6, the novel method of the present disclosure will be described in detail. Referring more specifically to Fig. 1, there is shown a bottom electrode 10 formed on a substrate, not shown. Now, layers are deposited on the bottom electrode to form a magnetic tunnel junction. For example, a seed layer 12, a pinned layer 14, a tunnel barrier layer 16, and a free layer 18 are deposited.There may be one or more pinned, barrier and / or free layers. A metal hardmask 20, such as Ta, TaN, Ti, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys, is deposited to a thickness of 10 to 100 nm and preferably ≥50 nm on top of the MTJ stack. This hard mask is used as a top electrode. Finally, a hard mask dielectric material 22, comprising SiO 2, SiN, SiON, SiC or SiCN, is deposited on top electrode 20 to a thickness of ≥20 nm. The photoresist is patterned by 248 nm photolithography, for example, to form photoresist pillar patterns 24 having a size d1of ~70 to 80 nm and a height of ≥200 nm.Now, as illustrated in FIG. 2, the dielectric and metal hard masks 22 and 20 are etched by a fluorine-carbon-based plasma such as CF 4 or CHF 3 alone or mixed with Ar and N2. O 2 may be added to reduce the pillar size d2from 50 to 60 nm to 30 to 40 nm. They can also be etched by physical RIE or IBE (pure Ar) followed by large angle IBE trimming (70 to 90° with respect to the vertical line of the column) forming a column size d2of 30 to 40 nm.Referring to FIG. 3, the MTJ stack is only partially etched using physical RIE (pure argon or pure Xe) or IBE, stopping on either the pinned layer or the seed layer of similar feature size to minimize metal deposition on the tunnel barrier. Due to the nature of physical etching, no chemical damage occurs. The height h of the partially etched MTJ stack is between 5 and 30 nm.As illustrated in FIG. 4, an encapsulation material 26 consisting of dielectric materials such as SiN, SiC, SiCN, carbon or TaC, or metal oxides such as Al 2 O 3 or MgO, having a thickness d4of 5 to 30 nm, is now deposited on the partially etched MTJ structures either in situ or ex situ by CVD, PVD or ALD. The portion of the encapsulation material on the top and bottom of the structures is etched away by RIE or IBE, leaving encapsulation spacers 28 on the sidewalls as shown in FIG. 5 with thickness d 6 of 10 to 30 nm. Depending on the material used for the spacer, a different plasma may be used for this etching step. A fluorocarbon-based plasma such as CF 4 or CHF 3, may be used for SiN, SiC and SiCN, O 2 may be used for carbon, a fluorocarbon such as CF 4 or CHF 3, or a halogen such as Cl 2 or their combinations may be used for TaC, and a halogen such as Cl 2 alone or with Ar may be used for Al 2 O 3 and MgO.Finally, using the encapsulant 28 remaining on the sidewalls of the MTJ structures as a self-aligned hard mask, as shown in FIG. 6, the remaining MTJ stack, such as the pinned layer 14 and / or the seed layer 12, may be etched by RIE or IBE. Since, when RIE etching is used, the pinned layer and seed layer formed by this method are larger than the free layer, chemical damage on the pinned layer and seed layer would not interfere with its central portion aligned with the free layer. If physical RIE or IBE is used, the metal redeposition from the pinned and seed layers would not be in contact with the tunnel barrier due to protection by the encapsulation. Note that this etching of the pinned layer and seed layer is a self-aligned step, meaning that it does not have a problem with control of overlay accuracy, commonly associated with sub-60 nm MRAM device fabrication.Notably, the sizes of the pinned layer and the encapsulation layer largely depend on the thickness of the encapsulation sidewall, which serves as the hard mask, determined by their original deposition thickness and the subsequent etch conditions. By tuning these parameters, the sizes of the pinned layer and the seed layer can be accurately controlled according to the device design. For example, a thick spacer having a thickness d8of 10 to 20 nm may be provided on the side wall of the free layer so that the tunnel barrier defined later and the pinned layers have the size d 7 of 50 to 60 nm larger than that of the free layer d3of 40 to 50 nm. This is particularly critical for devices with small size cells because it allows strong pinning strength, increases the energy barrier and reduces switching current. Summarisch, the process of the present disclosure uses incomplete physical etching to avoid both chemical damage and physical shorts. Moreover, separate and non-interacting MTJ cells are fabricated using encapsulant as a self-aligned process, meaning that there is no problem with controlling coverage accuracy commonly associated with sub-60 nm MRAM device fabrication. It is therefore possible to replace the widely used RIE chemical etching inevitably involving chemical damage on the MTJ sidewall. This process is used for MRAM chips with the size smaller than 60 nm, as problems associated with chemically damaged sidewalls and pitch from the MTJ stack and bottom electrode become very serious for the MRAM chips.Although the preferred embodiment of the present disclosure has been illustrated and this form has been described in detail, it will be readily understood by those skilled in the art that various changes may be made therein without departing from the spirit of the disclosure or the scope of the appended claims.

Claims

A method of fabricating a magnetic tunnel junction structure, hereinafter referred to as an MTJ structure, comprising: depositing an MTJ stack on a bottom electrode (10), the MTJ stack comprising at least a seed layer (12), a pinned layer (14) on the seed layer (12), a barrier layer (16) on the pinned layer (14), and a free layer (18) on the barrier layer (16); depositing a top electrode layer (20) on the MTJ stack; depositing a hard mask (22) on the top electrode layer (20); first etching the top electrode layer (20) and the hard mask (22); thereafter, second etching of the MTJ stack not covered by the hard mask (22) and stopping the second etching at or within the seed layer (12); thereafter depositing an encapsulation layer (26) over the partially etched MTJ stack and etching away the encapsulation layer (26) on horizontal surfaces by leaving a self-aligned hard mask (28) on sidewalls of the partially etched MTJ stack, wherein the self-aligned hard mask (28) is disposed along the sidewalls of the pinned layer (14) and extends to and physically contacts an upper surface of the seed layer (12); thereafter, third etching of the remaining MTJ stack not covered by the hard mask layer (22) and the self-aligned hard mask (28) to complete the MTJ structure, wherein after the third etching, the self-aligned hard mask (28) covers the sidewalls of the free layer (18), the barrier layer (16), and the pinned layer (14) and does not contact the sidewall of the top electrode layer (20).The method of claim 1, wherein a feature size of the seed layer (12) is greater than a feature size of the free layer (18).The method of claim 1 or 2, wherein the top electrode layer (20) comprises Ta, TaN, Ti, TiN, W, Cu, Mg, Ru, Cr, Co, Fe, Ni, or their alloys, and the hard mask layer (22) comprises SiO 2, SiN, SiON, SiC, or SiCN.The method of any one of claims 1 to 3, wherein the hard mask (22) and the top electrode (20) are etched by a fluorine-carbon-based plasma comprising CF 4 or CHF 3 alone or mixed with Ar and N 2 optionally adding O 2 to reduce a feature size of the hard mask (22), or by physical reactive ion etching or ion milling followed by wide-angle ion milling to reduce a feature size of the hard mask (22).The method of any one of claims 1 to 4, wherein the second and third etchings comprise physical reactive ion etching using Ar or Xe gas plasma or ion beam etching.The method of any of claims 1 to 5, wherein no chemical damage occurs to sidewalls of the MTJ stack, and wherein the self-aligned hard mask is formed such that any first conductive metal residue after the second etch and a second conductive metal residue after the third etch are separated from each other by the self-aligned hard mask.The method of any of claims 1 to 6, wherein depositing the encapsulation layer (26) comprises depositing a dielectric layer comprising SiN, SiC, SiCN, carbon or TaC or a metal oxide layer comprising Al 2 O 3 or MgO in situ or ex situ by chemical vapor deposition, physical vapor deposition or atomic layer deposition to a thickness of 5 to 30 nm.A magnetic tunnel junction structure, referred to herein as an MTJ structure, comprising: separate and non-interacting MTJ cells on a bottom electrode (10), each MTJ cell comprising: a seed layer (12) on the bottom electrode (10), a pinned layer (14) on the seed layer (12), a barrier layer (16) on the pinned layer (14), and a free layer (18) on the barrier layer (16); a self-aligned hard mask (28) disposed along the sidewalls of the free layer (18), the barrier layer (16), and the pinned layer (14) and extending to a top surface of the seed layer (12) physically contacted by the self-aligned hard mask (28); and a top electrode layer (20) on the free layer (18), wherein the self-aligning hard mask (28) does not contact the sidewall of the top electrode layer (20).The MTJ structure of claim 8, wherein the self-aligned hard mask (28) comprises a dielectric layer comprising SiN, SiC, SiCN, carbon or TaC, or a metal oxide layer comprising Al 2 O 3 or MgO.The MTJ structure of claim 8 or 9, wherein a structure size of the seed layer (12) is larger than a structure size of the free layer (18).

Images