INTEGRATED CHIPS AND METHOD FOR MAKING AN INTEGRATED CHIP

Abstract

Integrated chip (100, 200, 300) that includes the following: a dielectric structure (106) arranged over a substrate (102); several lower interconnect layers (108, 110, 112) arranged within the dielectric structure (106); a storage device (115a, 204a) comprising a data storage structure (118, 206) arranged between a lower electrode (116) and an upper electrode (120), wherein the lower electrode (116) is electrically coupled to the multiple lower interconnect layers (108); and a side wall spacer (122) that extends continuously from an outermost side wall of the data storage structure (118, 206) to below an outermost side wall of the lower electrode (116), wherein the dielectric structure (106) comprises the following: several lower interlayer dielectric layers (107a, 107b) arranged above the substrate (102) and surrounding the several lower interconnect layers (108, 110, 112); an etch stop layer (304b) arranged over the several lower ILD layers (107a, 107b); and a lower insulating structure (202) arranged above the etch stop layer (304b), wherein the lower electrode (116) extends from above the lower insulating structure (202) to one of the several lower interconnect layers (108, 110, 112).

Description

BACKGROUND

[0001] Many modern electronic devices contain electronic memory configured to store data. This electronic memory can be volatile or non-volatile. Volatile memory retains data while it receives power, while non-volatile memory retains data even when power is lost. Magneto-resistive random-access (MRAM) memory is a promising candidate for next-generation non-volatile memory technology. MRAM devices use magnetic tunnel junctions (MTJs) to store data in a way that allows for fast data access and low power consumption. Integrated circuits with RRAM memory cells are described in publications US 2013 / 0119494A1 and US 2016 / 0380183A1, as well as in publications US 2017 / 0309682A1 and US 2016 / 0365512A1.Document US 9 502 466 B1 describes an integrated circuit with memory cells with reduced susceptibility to wafer warping.

[0002] The task is to improve integrated chips with corresponding memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The problem is solved by integrated chips according to claims 1 and 11 and the method according to claim 16. Further embodiments are described in the dependent claims. Aspects of this disclosure are best understood by referring to the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity. Fig. Figure 1 illustrates a cross-sectional view of some embodiments of an integrated chip comprising a disclosed storage device formed by a process that structures a bottom electrode prior to forming sidewall spacers. Fig. Figure 2 illustrates a cross-sectional view of some embodiments of an integrated chip incorporating a disclosed storage device. Fig. Figure 3 illustrates a cross-sectional view of some embodiments of an integrated chip incorporating a disclosed storage device. Fig. Figure 4 illustrates a cross-sectional view of some embodiments of an integrated chip incorporating a disclosed storage device. Fig. Figures 5-21 illustrate cross-sectional views of some embodiments of a method for forming multiple MTJ devices, defining lower electrodes of the MTJ devices before sidewall spacers are formed along sides of the MTJ devices. Fig. Figure 22 illustrates a flowchart of some embodiments of a method 2200 for forming multiple MTJ devices, defining lower electrodes of the MTJ devices before sidewall spacers are formed along sides of the MTJ devices. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0006] Magnetic Tunnel Junction (MTJ) devices comprise an MTJ positioned vertically between lower and upper conductive electrodes. The MTJ includes a pinned layer separated from a free layer by a tunnel barrier layer. The magnetic orientation of the pinned layer is static (fixed), while the magnetic orientation of the free layer can switch between a parallel and an antiparallel configuration with respect to that of the pinned layer. The parallel configuration forms a low-impedance state, which digitally stores data as a first data state (for example, a logical "1"). The antiparallel configuration forms a high-impedance state, which digitally stores data as a second data state (for example, a logical "0").

[0007] Typically, MTJ devices are formed by depositing an MTJ stack over a bottom electrode layer, followed by the deposition of an upper electrode layer over the MTJ stack. The upper electrode layer and the MTJ stack are then patterned according to an initial structuring process to define upper electrodes and multiple MTJs above the bottom electrode layer. Multiple sidewall spacers and an etch stop layer are formed along the sidewalls of the multiple MTJs. The one or more bottom electrode layers are then patterned according to the sidewall spacers to define bottom electrodes beneath the multiple MTJs. Finally, upper electrode vias are formed over the upper electrodes. The etch stop layer prevents the upper electrode vias from damaging the multiple MTJs.

[0008] It was observed that as the size of the MTJ devices decreased, the size between adjacent MTJ devices also decreased. With decreasing size between adjacent MTJ devices, the distance between the sidewall spacers of neighboring MTJ devices became smaller (for example, between approximately 1 nm and 50 nm), making it increasingly difficult for the second etching process to pattern the bottom electrode layer. Thinning the sidewall spacers can improve the ability of the second etching process to pattern the bottom electrode layer. However, thinning the sidewall spacers can also cause the etch stop layer to be exposed and etched during the second etching process.Etching of the etch stop layer can lead to MTJ damage during the formation of an upper electrode via and / or re-deposition of the etch stop material (for example, aluminum oxide), which can lead to leakage currents between the lower electrodes of adjacent MTJ devices.

[0009] In some embodiments, the present disclosure relates to a method for forming an MTJ device that eliminates the second structuring process used to define lower electrodes. Instead, the present disclosure uses a single etching process to define an upper electrode, an MTJ, and a lower electrode. Subsequently, a sidewall spacer is formed along the sidewalls of the upper electrode, the MTJ, and the lower electrode, followed by the formation of an etch stop layer over the sidewall spacer. By using a single structuring process to define the upper electrodes, the MTJs, and the lower electrodes, the size of a gap defining an etching area of ​​a lower electrode layer is increased.Furthermore, the formation of the etch stop layer after defining the lower electrode prevents re-deposition of the etch stop layer and thus reduces leakage current between adjacent MTJ devices.

[0010] Fig. Figure 1 illustrates a cross-sectional view of some embodiments of an integrated chip 100, which has a disclosed storage device formed by a process that structures a bottom electrode prior to forming sidewall spacers.

[0011] The integrated chip 100 comprises an access device 104 arranged over a substrate 102. A dielectric structure 106 is also arranged over the substrate 102 and surrounds the access device 104. The dielectric structure 106 comprises a lower dielectric structure 106a, which surrounds several lower interconnect layers 108 that are electrically coupled to the access device 104. In some embodiments, the access device 104 may include a transistor device (for example, a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like). In some embodiments, the several lower interconnect layers 108 comprise layers of conductive contacts 110, interconnect wires 112, and interconnect vias 114.

[0012] Several storage devices 115a-115b are arranged within the dielectric structure 106 across the multiple lower interconnect layers 108. The multiple storage devices 115a-115b comprise a data storage structure 118 located between a lower electrode 116 and an upper electrode 120. The data storage structure 118 is configured to store a data state (corresponding, for example, to a logical "0" or a logical "1"). In various embodiments, the data storage structure 118 may comprise a magnetic tunnel junction, a high k-value dielectric material, or the like.

[0013] One or more sidewall spacers 122 are arranged along sidewalls of the multiple storage devices 115a-115b. The sidewall spacers 122 extend continuously along the outermost sidewalls 120s of the upper electrode 120, the outermost sidewalls 118s of the data storage structure 118, and the outermost sidewalls 116s of the lower electrode 116 to below the outermost sidewalls 116s of the lower electrode 116. For example, in some embodiments, the sidewall spacers 122 can extend a distance d1 below a base of the outermost sidewalls 116s of the lower electrode 116. In some embodiments, the sidewall spacers 122 can extend along a sidewall 106s of the lower dielectric structure 106a, which lies below a bottom surface 116L of the lower electrode 116.The side wall spacers 122 have inner side walls that completely cover the outermost side walls 116s of the lower electrode 116. In some embodiments, the inner side walls of the side wall spacers 122 can directly contact the outermost side walls 120s of the upper electrode 120, the outermost side walls 118s of the data storage structure 118, and the outermost side walls 116s of the lower electrode 116. In some additional embodiments, the inner side walls of the side wall spacers 122 can also contact the side walls 106s of the lower dielectric structure 106a.

[0014] A top electrode via (TEVA) etch stop layer 124 is arranged along the outer sidewalls of the sidewall spacer 122, and a top dielectric structure 106b is arranged on the TEVA etch stop layer 124. In some embodiments, the TEVA etch stop layer 124 can extend continuously from a sidewall of a first storage device 115a of the multiple storage devices 115a-115b to a sidewall of a second storage device 115b of the multiple storage devices 115a-115b. In such embodiments, the TEVA etch stop layer 124 has a vertically extending segment and a horizontally extending segment.The vertically extending segment is arranged along a side wall of the side wall spacers 122 and projects outwards from a top of the horizontally extending segment to a horizontal line that runs parallel to and is arranged along a top of the upper electrode 120.

[0015] The sidewall spacers 122 completely cover the outermost sidewalls 116s of the lower electrode 116 because they are formed after one or more structuring processes that define the lower electrode 116. The formation of the sidewall spacers 122 after the structuring process allows the lower electrode 116 to be structured with a small center-to-center spacing (i.e., with little space between adjacent storage devices 115a-115b). Because the TEVA etch stop layer 124 is positioned over the sidewall spacers 122, it is not subjected to any etching process. This prevents the redeposition of material from the TEVA etch stop layer 124, which could lead to leakage current between adjacent storage devices 115a-115b.

[0016] Fig. Figure 2 illustrates a cross-sectional view of some additional embodiments of an integrated chip 200 which includes a disclosed storage device.

[0017] The integrated chip 200 comprises a dielectric structure 106 arranged on a substrate 102. The dielectric structure 106 comprises several stacked inter-level dielectric (ILD) layers 107a-107d. In some embodiments, the several stacked ILD layers 107a-107d may comprise one or more of silicon dioxide, doped silicon dioxide (for example, carbon-doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or the like.

[0018] Several lower interconnect layers 108 are arranged within several lower ILD layers 107a-107b of the dielectric structure 106. In some embodiments, the several lower interconnect layers 108 comprise conductive contacts 110 and interconnect wires 112, each surrounded by one of the several lower ILD layers 107a-107b. In some additional embodiments (not shown), the several lower interconnect layers 108 may further comprise conductive vias. In some embodiments, the interconnect wires 112 and / or conductive vias may comprise a diffusion barrier layer (for example, tantalum, titanium nitride, or the like) surrounding a metal core (for example, copper, tungsten, aluminum, or the like).

[0019] A lower insulating structure 202, comprising one or more dielectric materials, is arranged above the multiple lower ILD layers 107a-107b. In various embodiments, the lower insulating structure 202 may comprise an oxide (for example, silicon oxide, silicon-rich oxide, etc.), a nitride (for example, silicon nitride, silicon oxynitride, etc.), a carbide (for example, silicon carbide, silicon oxycarbide, etc.), tetraethyl orthosilicate (TEOS), and / or the like. For example, in some embodiments, the lower insulating structure 202 may comprise a layer of silicon oxide, while in other embodiments, the lower insulating structure 202 may comprise a layer of silicon-rich oxide arranged between layers of silicon carbide.

[0020] Several MTJ devices 204a-204b are arranged within the dielectric structure 106 above the lower insulating structure 202. The multiple MTJ devices 204a-204b include a lower electrode 116, which is separated from an upper electrode 120 by a magnetic tunnel junction (MTJ) 206. The lower electrode 116 extends from above the lower insulating structure 202 to the multiple lower interconnect structures 108 below the lower insulating structure 202. In some embodiments, the lower electrode 116 may comprise a lining (for example, an adhesive layer and / or a diffusion barrier layer) and an overlying conductive material. In some embodiments, the lining may comprise tantalum nitride, titanium nitride, or the like. In some embodiments, the conductive material may comprise titanium, tantalum, or the like.In some embodiments, the upper electrode 120 may comprise one or more of titanium, tantalum, tungsten, tantalum nitride, titanium nitride or the like.

[0021] In some embodiments, the MTJ 206 can comprise a pinned layer 208 separated from a free layer 212 by a dielectric tunnel barrier 210. The pinned layer 208 has a fixed magnetization, while the free layer 212 has a magnetization that, during operation (due to the tunnel magnetoresistance (TMR) effect), can be changed either to parallel (i.e., a state "P") or antiparallel (i.e., a state "AP") with respect to the magnetization of the pinned layer 208. A relationship between the magnetizations of the pinned layer 208 and the free layer 212 defines an ohmic state of the MTJ 206 and thereby enables the MTJ 206 to store a data state.

[0022] In some embodiments, the pinned layer 208 may comprise cobalt, iron, boron, nickel, ruthenium, iridium, platinum, or the like. In some embodiments, the dielectric tunnel barrier 210 may comprise magnesium oxide, aluminum oxide, nickel oxide, gadolinium oxide, tantalum oxide, molybdenum oxide, titanium oxide, tungsten oxide, or the like. In some embodiments, the free layer 212 may comprise cobalt, iron, boron, iron-cobalt, nickel-cobalt, cobalt-iron boride, iron boride, iron-platinum, iron-palladium, or the like.

[0023] One or more sidewall spacers 122 and a top electrode via (TEVA) etch stop layer 124 extend along sidewalls of the multiple MTJ devices 204a-204b. In various embodiments, the sidewall spacers 122 may comprise silicon nitride, silicon dioxide (SiO2), a nitride (for example, silicon oxynitride, silicon nitride, etc.), a carbide (for example, silicon carbide, etc.), or the like. In various embodiments, the TEVA etch stop layer 124 may comprise one or more silicon nitrides (for example, Si3N4), a metal oxide (for example, aluminum oxide, hafnium oxide, etc.), or the like. An ILD interlayer 107c is arranged above the TEVA etch stop layer 124.In some embodiments, a top surface of the ILD intermediate layer 107c is substantially coplanar (for example, coplanar within a tolerance of a chemical-mechanical planarization (CMP) process) with top surfaces of the TEVA etch stop layer 124 and / or the top electrode 120.

[0024] An upper interconnect structure 126 is arranged within an upper ILD structure 107d above the ILD interlayer 107c. The upper interconnect structure 126 contacts the upper electrode 120. In some embodiments, the upper interconnect structure 126 can extend vertically beneath a top surface of the ILD interlayer 107c. In some such embodiments, the TEVA etch stop layer 124 can laterally separate the upper interconnect structure 126 from side walls of the upper electrode 120.

[0025] Fig. Figure 3 illustrates a cross-sectional view of some additional embodiments of an integrated chip 300 which includes a disclosed storage device.

[0026] The integrated chip 300 comprises one or more access devices 104 arranged within a substrate 102. In some embodiments, the one or more access devices 104 are laterally separated by an insulating structure 302 arranged within the substrate 102. In some embodiments, the insulating structure 302 may comprise a shallow trench insulation (STI) structure comprising one or more dielectric materials arranged within a trench defined by the sidewalls of the substrate 102.

[0027] A dielectric structure 106 is arranged over the substrate 102. The dielectric structure 106 comprises several lower ILD layers 107a-107b, which surround several lower interconnect layers 108. In some embodiments, the several lower ILD layers 107a-107b may comprise a first ILD layer 107a, which is separated from a second ILD layer 107b by a first etch stop layer 304a. A second etch stop layer 304b is arranged over the several lower ILD layers 107a-107b. In some embodiments, the first etch stop layer 304a and / or the second etch stop layer 304b may comprise a carbide, a nitride, or the like. A lower insulating structure 202 is arranged over the second etch stop layer 304b. The lower insulating structure 202 comprises first side walls that lie directly above one of the several lower interconnect layers 108.The first side walls extend between a bottom surface of the lower insulating structure 202 and a top surface of the lower insulating structure 202. The lower insulating structure 202 further comprises second side walls that extend between the top surface of the lower insulating structure 202 and an upper surface of the lower insulating structure 202.

[0028] A lower electrode 116 is arranged within the opening and above the uppermost surface of the lower insulating structure 202. The lower electrode 116 comprises a top surface with a first width and a bottom surface with a second width that is smaller than the first width. The top surface extends between the outermost side walls 116s of the lower electrode 116s. The lower electrode 116 extends through the lower insulating structure 202 and the second etch stop layer 304b to one of the several lower interconnect layers 108. In some embodiments, the lower insulating structure 202 may have a greater thickness directly beneath the lower electrode 116 than laterally outside the lower electrode 116.

[0029] An MTJ 206 is arranged above the top surface of the lower electrode 116, and an upper electrode 120 is arranged above the MTJ 206. In some embodiments, the MTJ 206 can be in direct contact with the top surface of the lower electrode 116. In some embodiments, the top surface of the lower electrode 116 can have a width that is substantially equal to the width of a bottom surface of the MTJ 206. In some embodiments, the lower electrode 116, the MTJ 206, and the upper electrode 120 can have outermost side walls oriented at a first angle α with respect to a horizontal line extending along the top surface of the lower electrode 116. In some embodiments, the first angle α can be an acute angle. For example, in some embodiments, the first angle α can be in a range between 80° and 90°.

[0030] One or more sidewall spacers 122 extend along the outermost sidewalls of the upper electrode 120, the MTJ 206, and the lower electrode 116. In some embodiments, the sidewall spacers 122 may extend further along the second sidewalls of the lower insulating structure 202. In some embodiments, the sidewall spacers 122 may have a top surface that is recessed beneath a top surface of the upper electrode 120. In some embodiments, the sidewall spacers 122 may each have a substantially constant width between a bottom surface of the sidewall spacers 122 and a top surface of the sidewall spacers 122. In some embodiments, the sidewall spacers 122 may have a width in the range of approximately 4 nanometers to approximately 20 nanometers.

[0031] A top electrode via (TEVA) etch stop layer 124 is arranged above the sidewall spacer 122 and the lower insulating structure 202. The TEVA etch stop layer 124 extends vertically from above a top surface of the sidewall spacers 122 to below the top surface of the lower insulating structure 202. In some embodiments, a bottom surface of the TEVA etch stop layer 124 is arranged along a horizontal plane extending through the first sidewalls of the lower insulating structure 202. In some embodiments, the TEVA etch stop layer 124 directly contacts a top surface of the lower insulating structure 202 at a position located between sidewalls of the sidewall spacers 122. In some embodiments, the TEVA etch stop layer 124 can extend to a position below the bottom surface of the sidewall spacers 122.For example, in some embodiments, the TEVA etch stop layer 124 can extend below the underside of the sidewall spacers 122 by a distance in the range of approximately 0 nm to approximately 20.0 nm. In some embodiments (not shown), the TEVA etch stop layer 124 can extend through the lower insulating structure 202 to contact the second etch stop layer 304b. In some embodiments, the TEVA etch stop layer 124 can have a thickness in the range of approximately 1.0 nm to approximately 10.0 nm.

[0032] An ILD interlayer 107c is arranged above the TEVA etch stop layer 124. In some embodiments, the ILD interlayer 107c extends laterally by a distance d2 between the sidewall spacers 122 surrounding a first MTJ device 204a and the sidewall spacers 122 surrounding a second MTJ device 204b. In some embodiments, the distance d2 is in a range between approximately 20 nanometers and approximately 150 nanometers. In some embodiments, the ILD interlayer 107c directly contacts sidewalls of the sidewall spacers 122. A third etch stop layer 304c (comprising, for example, an oxide, a nitride, a carbide, or the like) is located above the ILD interlayer 107c, and an upper ILD structure 107d lies above the third etch stop layer 304c. An upper interconnect structure 126 extends through the upper ILD structure 107d and the third etch stop layer 304c to contact the upper electrode 120.

[0033] Fig. Figure 4 illustrates a cross-sectional view of some additional embodiments of an integrated chip 400 which includes a disclosed storage device.

[0034] The integrated chip 400 comprises a substrate 102 containing an embedded memory region 402 and a logic region 404. Within the embedded memory region 402, several lower interconnect layers 108 are arranged within one or more lower ILD layers 107a-107b. The several lower interconnect layers 108 are coupled between access devices 104 located within the substrate 102 and MTJ devices 204a-204b located above a lower insulating structure 202. The MTJ devices 204a-204b each comprise an MTJ 206 located between a lower electrode 116 and an upper electrode 120. One or more sidewall spacers 122 are arranged along opposite sides of the upper electrode 120, the MTJ 206, the lower electrode 116, and the lower insulating structure 202. A TEVA etch stop layer 124 is arranged on the sidewall spacers 122.

[0035] An ILD interlayer 107c is arranged above the lower insulating structure 202 and surrounds the MTJ devices 204a-204b. An upper interconnect structure 126 is arranged within an upper ILD structure 107d above the ILD interlayer 107c. The upper interconnect structure 126 can include an upper electrode via 406 and an upper interconnect wire 408 that extends laterally past one or more sides of the upper electrode via 406. The upper electrode via 406 couples the upper electrode 120 to the upper interconnect wire 408. The upper electrode via 406 is arranged directly on the upper electrode 120. In some embodiments, the upper electrode via 406 and the upper interconnect wire 408 may comprise aluminium, copper, tungsten or the like.

[0036] In some embodiments, the upper electrode via 406 can extend vertically beneath a top surface of the ILD interlayer 107c. In some such embodiments, the upper electrode via 406 can extend from above the upper electrode 120 to sides of the TEVA etch stop layer 124. In such embodiments, the upper electrode via 406 can be separated laterally from side walls of the upper electrode 120 by means of the TEVA etch stop layer 124.

[0037] Within the logic region 404, one or more additional interconnect layers are arranged within the dielectric structure 106. The one or more additional interconnect layers comprise a conductive contact 414, an interconnect wire 416, and an interconnect via 418. The one or more additional interconnect layers are coupled to a logic device 412 arranged within the substrate 102. In some embodiments, the logic device 412 may comprise a transistor device (for example, a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like).

[0038] In some embodiments, the dielectric structure 106 may comprise an ILD logic layer 410 arranged above one or more lower ILD layers 107a-107b within the logic region 404. The ILD logic layer 410 may comprise a different material than the ILD intermediate layer 107c. In some embodiments, the ILD logic layer 410 may have a lower dielectric constant than the ILD intermediate layer 107c. For example, in some embodiments, the ILD logic layer 410 may comprise a dielectric material with a low k-value (that is, a dielectric material with a dielectric constant of less than about 3.9), while the ILD intermediate layer 107c may comprise an oxide.In some embodiments, the ILD logic layer 410 may comprise carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a porous dielectric material or the like.

[0039] In some embodiments, the ILD logic layer 410 may have a side wall that contacts an outermost side wall of the TEVA etch stop layer 124 and a side wall of the lower insulating structure 202. In some such embodiments, the lower insulating structure 202 may have a lower height within the logic region 404 than within the embedded memory region 402.

[0040] Fig. Figures 5-21 and 500-2100 illustrate cross-sectional views of some embodiments of a method for forming multiple MTJ devices by defining lower electrodes of the MTJ devices prior to forming sidewall spacers along sides of the MTJ devices. Although the Fig. 5-21, which are described in relation to a procedure, it is understood that the [documents] described in the Fig. 5-21 disclosed structures are not limited to such a procedure, but rather can exist as independent structures separate from the procedure.

[0041] As shown in the cross-sectional view 500 of Fig. As shown in Figure 5, a substrate 102 is provided. The substrate 102 comprises an embedded memory region 402 and a logic region 404. An access device 104 is formed within the embedded memory region 402 of the substrate 102, and a logic device 412 is formed within the logic region 404 of the substrate 102. In various embodiments, the substrate 102 can be any type of semiconductor body (for example, silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers associated with it. In some embodiments, the access device 104 and / or the logic device 412 can comprise a transistor. In some such embodiments, the access device 104 can be formed by depositing a gate dielectric film and a gate electrode film on the substrate 102.The gate dielectric film and the gate electrode film are subsequently structured to form a gate dielectric 104g and a gate electrode 104e. The substrate 102 can then be implanted to form a source region 104s and a drain region 104d within the substrate 102 on opposite sides of the gate electrode 104e.

[0042] As shown in the cross-sectional view 600 of Fig. As shown in Figure 6, several lower interconnect layers 108 are formed within one or more lower interlayer dielectric (ILD) layers 107a-107b above the substrate 102. In some embodiments, the one or more lower ILD layers 107a-107b may comprise a first ILD layer 107a and a second ILD layer 107b separated by a first etch stop layer 304a. In some embodiments, the several lower interconnect layers 108 may include a conductive contact 110 and an interconnect wire 112. In some additional embodiments (not shown), the several lower interconnect layers 108 may further comprise an interconnect via.The multiple lower interconnect layers 108 can be formed by forming one or more of the lower ILD layers 107a-107b over the substrate 102 (for example, an oxide, a low k-value dielectric, or an ultra-low k-value dielectric), selectively etching one or more of the lower ILD layers 107a-107b to define a via hole and / or a trench within the ILD layer, forming a conductive material (for example, copper, aluminum, etc.) within the via hole and / or a trench, and performing a planarization process (for example, a chemical-mechanical planarization process).

[0043] As shown in the cross-sectional view 700 of Fig. As shown in Figure 7, a second etch stop layer 304b is formed over one or more lower ILD layers 107a-107b, and a lower insulating structure 202 is formed on the second etch stop layer 304b. In some embodiments, the second etch stop layer 304b may comprise one or more silicon nitride, silicon carbide, or the like. In some embodiments, the lower insulating structure 202 may comprise one or more oxides, silicon nitride, silicon carbide, TEOS, or the like. In some embodiments, the lower insulating structure 202 may be formed by several different deposition processes (for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.) to a thickness in the range between about 20.0 nm and about 30.0 nm.

[0044] As shown in the cross-sectional view 800 of Fig. As shown in Figure 8, the second etch stop layer 304b and the lower insulating structure 202 are selectively structured to define multiple openings 802 extending through the second etch stop layer 304b and the lower insulating structure 202. The multiple openings 802 expose one of the multiple lower interconnect layers 108 (for example, the interconnect wire 112) beneath the lower insulating structure 202. In some embodiments, the second etch stop layer 304b and the lower insulating structure 202 can be selectively structured by exposing the second etch stop layer 304b and the lower insulating structure 202 to an etchant 804 according to a structured masking layer 806 arranged on the lower insulating structure 202.

[0045] As shown in the cross-sectional view 900 of Fig. As shown in Figure 9, one or more lower electrode layers 902 can be formed above the lower insulating structure 202 and within the openings 802. The one or more lower electrode layers 902 extend through the lower insulating structure to one of the several lower interconnect layers 108 (for example, the interconnect wire 112). In some embodiments, the one or more lower electrode layers 902 can be formed by depositing a lining and subsequently depositing a conductive material. In various embodiments, the lining can include an adhesive layer configured to enhance adhesion between adjacent layers and / or a diffusion barrier layer configured to prevent diffusion between adjacent layers. In some embodiments, the lining can comprise tantalum nitride, titanium nitride, or the like.In some embodiments, the conductive material may comprise tantalum, titanium, or the like. In some embodiments, a planarization process (for example, a chemical-mechanical planarization process) may be performed after the deposition of the conductive material, followed by the deposition of an additional conductive material on top of the lower insulating layer and the conductive material. In other embodiments, no planarization process is performed after the deposition of the conductive material.

[0046] As shown in the cross-sectional view 1000 of Fig. As shown in Figure 10, an MTJ stack 1002 is formed over one or more lower electrode layers 902. In some embodiments, the MTJ stack 1002 may comprise: a lower ferromagnetic layer 1004 formed over the one or more lower electrode layers 902, a tunneling barrier layer 1006 formed over the lower ferromagnetic layer 1004, and an upper ferromagnetic electrode 1008 formed over the tunneling barrier layer 1006. Subsequently, one or more upper electrode layers 1010 (for example, titanium, tantalum, titanium nitride, or the like) are formed over the MTJ stack 1002.

[0047] As shown in the cross-sectional view 1100 of Fig. As shown in Figure 11, one or more structuring processes are performed to define multiple MTJ device stacks 1106a-1106b. The one or more structuring processes selectively set the one or more upper electrode layers (1010 of Fig. 10), the MTJ stack (1002 of Fig. 10) and the one or more lower electrode layers (902 of Fig. 10) an etching agent 1102 to define an MTJ 206 located between a lower electrode 116 and an upper electrode structure 1108. The one or more structuring processes can further etch the lower insulating structure 202 to define sidewalls of the lower insulating structure beneath the lower electrode 116. Etching the lower insulating structure 202 causes the lower insulating structure 202 to have a thinner sidewall outside the lower electrode 116 than directly below the lower electrode 116. In some embodiments, the thickness of the lower insulating structure 202 directly below the lower electrode 116 can be between about 2 and about 5 times greater than the thickness of the lower insulating structure 202 outside the lower electrode 116.In other embodiments, the thickness of the lower insulating structure 202 directly below the lower electrode 116 can be more than 5 times greater than the thickness of the lower insulating structure 202 outside the lower electrode 116.

[0048] In some embodiments, the one or more structuring processes may comprise a single etching process (for example, a continuous etching process using the same etchant). In other embodiments, the one or more structuring processes may comprise multiple etching processes (for example, multiple time-separated, discrete etching processes) performed in situ in a processing chamber. In some embodiments, the one or more structuring processes may be performed with a masking layer (for example, a photoresist layer, a hard mask layer, or the like) applied over the top electrode layer (1010 of Fig. 10) is arranged.

[0049] As shown in the cross-sectional view 1200 of Fig. As shown in Figure 12, a spacer layer 1202 is formed over the lower insulating structure 202 and the multiple MTJ device stacks 1106a-1106b after completion of one or more structuring processes. The spacer layer 1202 is formed such that it contacts the side walls of the lower insulating structure 202, the lower electrode 116, the MTJ 206, and the upper electrode structure 1108. In some embodiments, the spacer layer 1202 can be formed to a substantially constant thickness in a range between approximately 4.0 nm and approximately 40.0 nm. In some embodiments, the spacer layer 1202 can be formed by a deposition technique (for example, PVD, CVD, PE-CVD, ALD, sputtering, etc.). In various embodiments, the spacer layer 1202 can comprise silicon nitride, silicon dioxide (SiO2), silicon oxynitride (for example SiON) or the like.

[0050] As shown in the cross-sectional view 1300 of Fig. As shown in 13, the spacer layer (1202 of Fig. 12) exposed to an etchant 1302 that removes the spacer layer from horizontal surfaces. Removing the spacer layer from horizontal surfaces leaves a portion of the spacer layer along opposite sides of the multiple MTJ device stacks 1106a-1106b as the sidewall spacers 122. In some embodiments, etching the spacer layer can cause the sidewall spacers 122 to be recessed beneath a top surface of the upper electrode structure 1108. In some embodiments, the etchant 1302 can comprise a dry etchant.

[0051] As shown in the cross-sectional view 1400 of Fig. As shown in Figure 14, a top electrode via (TEVA) etch stop layer 124 is formed over the sidewall spacers 122, the upper electrode structure 1108, and the lower insulating structure 202. In some embodiments, the TEVA etch stop layer 124 can comprise a metal oxide (for example, aluminum oxide, hafnium oxide, etc.), silicon nitride, or the like. In some embodiments, the TEVA etch stop layer 124 can be formed by a deposition process (for example, PVD, CVD, PE-CVD, ALD, or the like) to a thickness in the range of about 1 nanometer to about 10 nanometers.

[0052] As shown in the cross-sectional view 1500 of Fig. As shown in Figure 15, an ILD interlayer 107c is formed over the TEVA etch stop layer 124. The ILD interlayer 107c is configured to completely cover one top surface of the TEVA etch stop layer 124. In some embodiments, the ILD interlayer 107c can be formed by a deposition process (for example, PVD, CVD, PE-CVD, ALD, or the like). In other embodiments, the ILD interlayer 107c can comprise an oxide (for example, silicon dioxide) or the like.

[0053] As shown in the cross-sectional view 1600 of Fig. As shown in Figure 16, a planarization process (along line 1602) is carried out to remove parts of the ILD intermediate layer 107c, the TEVA etch stop layer 124 and the upper electrode structure (1108 of Fig. 15) to remove. By removing part of the upper electrode structure, the planarization process defines several MTJ devices 204a-204b, each having an upper electrode 120 above the MTJ 206. In some embodiments, the planarization process may include a chemical-mechanical planarization (CMP) process.

[0054] As shown in the cross-sectional view 1700 of Fig. As shown in Figure 17, the ILD interlayer 107c, the TEVA etch stop layer 124, and part of the lower insulating structure 202 are removed from the logic region 404. In some embodiments, a masking layer 1702 is formed over the ILD interlayer 107c within the embedded memory region 402. The ILD interlayer 107c is then exposed to an etchant 1704, which etches the ILD interlayer 107c according to the masking layer 1702 to remove the ILD interlayer 107c from the logic region 404. In some embodiments (not shown), the etching process can result in the ILD interlayer 107c having an angled sidewall facing the logic region 404. In various embodiments, the masking layer 1702 can comprise one or more silicon carbide, silicon nitride or the like.

[0055] As shown in the cross-sectional view 1800 of Fig. As shown in Figure 18, an ILD logic layer 410 is formed above the ILD interlayer 107c within the embedded memory region 402 and above the lower insulating structure 202 within the logic region 404. In some embodiments, the ILD logic layer 410 can be deposited by a deposition process (for example, PVD, CVD, PE-CVD, ALD, or the like). In various embodiments, the ILD logic layer 410 can comprise a different material than the ILD interlayer 107c. In some embodiments where the spaces between adjacent interconnect structures in the logic region 404 are larger than the spaces between adjacent MTJ devices in the embedded memory region 402, the ILD logic layer 410 can comprise a material that has a lower dielectric constant and poorer gap-filling capabilities than the ILD interlayer 107c.In some embodiments, the ILD logic layer 410 may comprise silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a porous dielectric material or the like.

[0056] As shown in the cross-sectional view from 1900 Fig. As shown in Figure 19, one or more additional interconnect layers are formed within the logic ILD layer 410. In some embodiments, the one or more additional interconnect layers may include an interconnect via 418 and an interconnect wire 416. The one or more additional interconnect layers may be formed by: selectively etching the ILD logic layer 410 to define a via hole and / or a trench within the ILD logic layer 410; forming a conductive material (for example, copper, aluminum, etc.) within the via hole and / or a trench; and performing a planarization process (for example, a chemical-mechanical planarization process). In some embodiments, the planarization process removes the ILD logic layer 410 from above the ILD intermediate layer 107c.In some embodiments, the planarization process may include a chemical-mechanical planarization (CMP) process.

[0057] As shown in the cross-sectional view 2000 from Fig. As shown in Figure 20, an upper ILD structure 107d is formed above the ILD intermediate layer 107c within the embedded memory region 402 and above the ILD logic layer 410 within the logic region 404. In some embodiments, a third etch stop layer 304c can be formed on the ILD intermediate layer 107c and the ILD logic layer 410 before the formation of the upper ILD structure 107d. In some embodiments, the upper ILD structure 107d can be deposited by a deposition process (for example, PVD, CVD, PE-CVD, ALD, or the like). In some embodiments, the upper ILD structure 107d may comprise silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a porous dielectric material or the like.

[0058] As shown in the cross-sectional view 2100 of Fig. As shown in Figure 21, an upper interconnect structure 126 is formed within the upper ILD structure 107d. In some embodiments, the upper interconnect structure 126 can comprise an upper electrode via 406, which is arranged on the upper electrode 120 of one of the MTJ devices 204a-204b, and an upper interconnect wire 408, which is located vertically above the upper electrode via 406 and extends laterally past one or more sides of the upper electrode via 406. In some embodiments, the upper interconnect structure 126 can be formed by etching the upper ILD structure 107d to create a via hole and / or trench that is filled with a conductive material (for example, tungsten, copper, and / or aluminum).Subsequently, a chemical-mechanical planarization (CMP) process is performed to remove excess conductive material from above the upper ILD structure 107d.

[0059] Fig. Figure 22 illustrates a flowchart of some embodiments of a method 2200 for forming multiple MTJ devices by defining lower electrodes of the MTJ devices before forming sidewall spacers along sides of the MTJ devices.

[0060] Although the procedure 2200 is illustrated and described in this text as a series of actions or events, it is understood that the illustrated sequence of such actions or events is not to be interpreted in a restrictive sense. For example, some actions may be performed in a different order than shown and / or described in this text and / or simultaneously with other actions or events. Furthermore, not all of the illustrated actions need be required to implement one or more aspects or embodiments of the description given in this text. In addition, one or more of the actions shown in this text may be performed in one or more separate actions and / or phases.

[0061] In 2202, an access device is formed within an embedded memory region of a substrate. Fig. Figure 5 illustrates a cross-sectional view of 500 of some embodiments according to Action 2202.

[0062] In 2204, lower interconnect layers are formed within one or more lower ILD layers above the substrate. In some embodiments, the lower interconnect layers are coupled to the access device. Fig. Figure 6 illustrates a cross-sectional view of 600 of some embodiments according to Action 2204.

[0063] In 2206, a lower insulating structure is formed over one or more lower ILD layers. Fig. Figures 7-8 illustrate cross-sectional views 700-800 of some embodiments corresponding to Action 2206.

[0064] In 2208, a stack of MTJ fixture layers is formed above the lower insulating structure. In some embodiments, the stack of MTJ fixture layers can be formed according to actions 2010-1014.

[0065] In 2210, one or more lower electrode layers are formed above the lower insulating structure and in openings that extend through the lower insulating structure to the lower interconnect layers. Fig. Figure 9 illustrates a cross-sectional view of 900 of some embodiments according to Action 2210.

[0066] At 2212, an MTJ stack is formed above one or more lower electrode layers. Fig. Figure 10 illustrates a cross-sectional view of 1000 of some embodiments according to Action 2212.

[0067] In 2214, one or more upper electrode layers are formed above the MTJ stack. Fig. Figure 10 illustrates a cross-sectional view of 1000 of some embodiments according to Action 2214.

[0068] In 2216, one or more etching processes are performed on the stack of MTJ fixture layers to etch the one or more upper electrode layers, the MTJ stack and the lower electrode structure, and to define multiple MTJ fixture stacks, each having an MTJ positioned between a lower electrode and an upper electrode structure. Fig. Figure 11 illustrates a cross-sectional view 1100 of some embodiments according to action 2216.

[0069] In 2218, one or more sidewall spacers are formed along the sidewalls of the MTJ fixture stacks after one or more etching processes are completed. In some embodiments, the sidewall spacers can extend to a sidewall of the lower insulating layer. Fig. Figures 12-13 illustrate cross-sectional views 1200-1300 of some embodiments corresponding to Action 2218.

[0070] At 2220, a top electrode via (TEVA) etch stop layer is formed above the side wall spacers. Fig. Figure 14 illustrates a cross-sectional view 1400 of some embodiments according to action 2220.

[0071] In 2222, an ILD intermediate layer is formed above the TEVA etch stop layer. Fig. Figure 15 illustrates a cross-sectional view 1500 of some embodiments according to Action 2222.

[0072] At 2224, a planarization process is performed to remove parts of the ILD interlayer and the TEVA etch stop layer, exposing the top surface of an upper electrode. Fig. Figure 16 illustrates a cross-sectional view 1600 of some embodiments according to Action 2224.

[0073] At 2226, an upper interconnect structure is formed on the upper electrode. Fig.Figures 20-21 illustrate cross-sectional views 2000-2100 of some embodiments corresponding to Action 2226.

[0074] Accordingly, in some embodiments, the present disclosure relates to a method for forming an MTJ device that uses a single etching process to define an upper electrode, an MTJ, and a lower electrode. By using a single structuring process to define the MTJ device, a gap defining an etching area of ​​a lower electrode layer is enlarged.

[0075] In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises: a dielectric structure arranged over a substrate; several lower interconnect layers arranged within the dielectric structure; a storage device comprising a data storage structure located between a lower electrode and an upper electrode, the lower electrode being electrically coupled to the several lower interconnect layers; and a sidewall spacer extending continuously from an outermost sidewall of the data storage structure to below an outermost sidewall of the lower electrode. The sidewall spacer completely covers the outermost sidewall of the lower electrode and an outermost sidewall of the data storage structure.In some embodiments, the sidewall spacer extends continuously from the outermost sidewall of the data storage structure to an outermost sidewall of the upper electrode. In some embodiments, the sidewall spacer has an inner sidewall that contacts the outermost sidewall of the data storage structure and the outermost sidewall of the lower electrode. In some embodiments, the dielectric structure comprises: multiple lower interlayer dielectric (ILD) layers arranged above the substrate and surrounding the multiple lower interconnect layers; an etch stop layer arranged above the multiple lower ILD layers; and a lower insulating structure arranged above the etch stop layer, with the lower electrode extending from above the lower insulating structure to one of the multiple lower interconnect layers.In some embodiments, the lower insulating structure has a greater thickness directly beneath the lower electrode than laterally outside the lower electrode. In some embodiments, the inner sidewall of the sidewall spacer also contacts a sidewall of the lower insulating structure. Furthermore, in some embodiments, the integrated chip includes an upper electrode via etch stop layer that extends continuously from a sidewall of the sidewall spacer to an outermost sidewall of the upper electrode.In some embodiments, the integrated chip further includes a second storage device comprising a second data storage structure located between a second lower electrode and a second upper electrode, wherein the upper electrode via etch stop layer extends continuously from one side wall of the storage device to a side wall of the second storage device. In some embodiments, the integrated chip further includes an upper interconnect structure located on the upper electrode, wherein the upper interconnect structure extends from the upper electrode to sides of the upper electrode via etch stop layer.In some embodiments, a horizontal line extending along a bottom surface of the upper electrode via etch stop layer also extends through side walls of the lower insulating structure, the horizontal line being parallel to a bottom surface of the lower electrode. In some embodiments, the lower electrode has a bottom surface with a first width and a top surface with a second width greater than the first width; and the side wall spacer has a bottom surface arranged along a horizontal line extending between the top surface and the bottom surface.

[0076] In further embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises: a lower interlayer dielectric (ILD) layer arranged over a substrate; a lower interconnect layer arranged within the lower ILD layer; a lower insulating structure arranged over the lower ILD layer; a magnetic tunnel junction (MTJ) device comprising an MTJ arranged between a lower electrode and an upper electrode, the lower electrode being arranged on the lower interconnect layer and extending through the lower insulating structure; and an upper electrode via etch stop layer extending continuously from an outermost sidewall of the upper electrode to below an outermost sidewall of the lower electrode.The integrated chip further comprises a sidewall spacer that completely covers the outermost sidewall of the lower electrode and an outermost sidewall of the MTJ. In some embodiments, the sidewall spacer contacts the outermost sidewall of the MTJ, the outermost sidewall of the lower electrode, and a sidewall of the lower insulating structure. In some embodiments, the upper electrode via etch stop layer has a vertically extending segment projecting outward from the top surface of a horizontally extending segment, the vertically extending segment extending along a sidewall of the sidewall spacer to a horizontal line parallel to and along the top surface of the upper electrode.In some embodiments, the integrated chip further comprises an ILD interlayer that laterally surrounds the MTJ device, wherein the upper electrode via etch stop layer has a top surface facing away from the substrate and contacting a bottom surface of the ILD interlayer. In some embodiments, the integrated chip further comprises an ILD interlayer that laterally surrounds the MTJ device and is laterally separated from the MTJ device by the upper electrode via etch stop layer, wherein the upper electrode via etch stop layer extends continuously from directly below the ILD interlayer to a horizontal line that runs parallel to and is arranged along a top surface of the upper electrode.

[0077] In further embodiments, the present disclosure relates to a method for forming an integrated chip. The method comprises the following: forming a lower interconnect layer within a lower interlayer dielectric (ILD) layer over a substrate; forming one or more lower electrode layers over the lower interconnect layer; forming a magnetic tunnel junction (MTJ) stack over the one or more lower electrode layers; forming one or more upper electrode layers over the MTJ stack;Performing, after forming one or more lower electrode layers (902), forming the MTJ stack (1002), and forming one or more upper electrode layers (1010), one or more etching processes to selectively structure the one or more upper electrode layers, the MTJ stack, and the one or more lower electrode layers and to define an upper electrode structure, an MTJ, and a lower electrode; and forming a sidewall spacer along the outermost sidewalls of the MTJ and the lower electrode after completion of the one or more etching processes. In some embodiments, the method further includes: forming a lower insulating structure over the lower ILD layer; etching the lower insulating structure to form first sidewalls of the lower insulating structure that define an opening exposing the lower interconnect layer;Forming one or more lower electrode layers within the opening and over the lower insulating structure; and forming the sidewall spacer along second sidewalls of the lower insulating structure after the one or more etching processes are completed. In some embodiments, the method further includes: forming an upper electrode via etch stop layer on a vertically extending face of the sidewall spacer and on a horizontally extending face of the lower insulating structure; forming an upper ILD layer over the upper electrode via etch stop layer; and performing a planarization process to remove a portion of the upper ILD layer, the upper electrode via etch stop layer, and the upper electrode structure.

Claims

[1] Integrated chip (100, 200, 300) comprising the following: a dielectric structure (106) arranged over a substrate (102); several lower interconnect layers (108, 110, 112) arranged within the dielectric structure (106); a storage device (115a, 204a) comprising a data storage structure (118, 206) arranged between a lower electrode (116) and an upper electrode (120), wherein the lower electrode (116) is electrically coupled to the multiple lower interconnect layers (108); and a side wall spacer (122) that extends continuously from an outermost side wall of the data storage structure (118, 206) to below an outermost side wall of the lower electrode (116), wherein the dielectric structure (106) comprises the following: several lower interlayer dielectric layers (107a, 107b) arranged above the substrate (102) and surrounding the several lower interconnect layers (108, 110, 112); an etch stop layer (304b) arranged over the several lower ILD layers (107a, 107b); and a lower insulating structure (202) arranged above the etch stop layer (304b), wherein the lower electrode (116) extends from above the lower insulating structure (202) to one of the several lower interconnect layers (108, 110, 112). [2] Integrated chip (100, 200, 300) according to claim 1, wherein the side wall spacer (122) extends continuously from the outermost side wall of the data storage structure (118, 206) to an outermost side wall of the upper electrode (120). [3] Integrated chip (100, 200, 300) according to claim 1 or 2, wherein the side wall spacer (122) has an inner side wall which contacts the outermost side wall of the data storage structure (118, 206) and the outermost side wall of the lower electrode (116). [4] Integrated chip (300) according to one of the preceding claims, wherein the lower insulating structure (202) has a greater thickness directly under the lower electrode (116) than laterally outside the lower electrode (116). [5] Integrated chip (300) according to one of the preceding claims, wherein the inner side wall of the side wall spacer (122) further contacts a side wall of the lower insulating structure (202). [6] Integrated chip (100, 200, 300) according to any one of the preceding claims, further comprising: an upper electrode via etch stop layer (124) extending continuously from a side wall of the side wall spacer (122) to an outermost side wall of the upper electrode (120). [7] Integrated chip (100, 200, 300) according to claim 6, further comprising: a second storage device (115b, 204b) comprising a second data storage structure (118, 206) arranged between a second lower electrode (116) and a second upper electrode (120), wherein the upper electrode via etch stop layer (124) extends continuously from a side wall of the storage device (115a, 204a) to a side wall of the second storage device (115b, 204b). [8] Integrated chip (300) according to claim 6 or 7, wherein a horizontal straight line extending along a bottom side of the upper electrode through-hole etch stop layer (124) also extends through side walls of the lower insulating structure (202). [9] Integrated chip (100, 200, 300) according to any of the preceding claims, wherein the data storage structure (118, 206) comprises a magnetic tunnel junction. [10] Integrated chip (300) according to any one of the preceding claims, wherein the lower electrode (116) has a bottom surface with a first width and a top surface with a second width that is greater than the first width; and wherein the side wall spacer (122) has a bottom side of the side wall spacer which is arranged along a horizontal line which runs at a height between that of the top and that of the bottom of the lower electrode (116). [11] Integrated chip (300, 400) comprising the following: a lower interlayer dielectric layer (107a, 107b) arranged over a substrate (102); a lower interconnect layer (108, 110, 112) arranged within the lower interlayer dielectric layer (107a, 107b); a lower insulating structure (202) arranged above the lower interlayer dielectric layer (107a, 107b); an MTJ device (204a, 204b) comprising an MTJ (206) arranged between a lower electrode (116) and an upper electrode (120), wherein the lower electrode (116) is arranged on the lower interconnect layer (108, 110, 112) and extends through the lower insulating structure (202); an upper electrode via etch stop layer (124) extending continuously from an outermost side wall of the upper electrode (120) to below an outermost side wall of the lower electrode (116); and a side wall spacer (122) completely covering the outermost side wall of the lower electrode (116) and an outermost side wall of the MTJ (206). [12] Integrated chip (300, 400) according to claim 11, wherein the side wall spacer (122) contacts the outermost side wall of the MTJ (206), the outermost side wall of the lower electrode (116) and a side wall of the lower insulating structure (202). [13] Integrated chip (300, 400) according to claim 11 or 12, wherein the upper electrode through-hole etch stop layer (124) comprises a vertically extending segment projecting outwards from a top surface of a horizontally extending segment, the vertically extending segment extending along a side wall of the side wall spacer (122) to a straight line running along a top surface of the upper electrode (120). [14] Integrated chip (300, 400) according to one of claims 11 to 13, further comprising: an interlayer dielectric interlayer (107c) which laterally surrounds the MTJ device (204a, 204b), wherein the upper electrode via etch stop layer (124) has a top surface which faces away from the substrate (102) and contacts the interlayer dielectric interlayer (107c). [15] Integrated chip (300, 400) according to one of claims 11 to 13, further comprising: an interlayer dielectric intermediate layer (107c) which laterally surrounds the MTJ device (204a, 204b) and is laterally separated from the MTJ device (204a, 204b) by the upper electrode via etch stop layer (124), wherein the upper electrode via etch stop layer (124) extends continuously from directly below the interlayer dielectric intermediate layer (107c) to a straight line running along a top surface of the upper electrode (120). [16] Method for forming an integrated chip (100, 200, 300, 400) comprising the following: Forming a dielectric structure (106) over a substrate (102) having the dielectric structure (106): a lower interconnect layer (108, 110, 112) within the dielectric structure (106) and within a lower interlayer dielectric layer (107a, 107b) above the substrate (102); an etch stop layer (304b) arranged above the lower interlayer dielectric layer (107a, 107b); and a lower insulating structure (202) arranged above the etch stop layer (304b); Forming one or more lower electrode layers (902) above the lower interconnect layer (108, 110, 112) and at least partially above the lower insulating structure (202), wherein at least one of the lower electrode layers (902) extends to the lower interconnect layer (108); Forming an MTJ stack (1002) over one or more lower electrode layers (902); Forming one or more upper electrode layers (1010) over the MTJ stack (1002); Performing, after forming one or more lower electrode layers (902), forming the MTJ stack (1002) and forming one or more upper electrode layers (1010), one or more etching processes for selectively structuring the one or more upper electrode layers (1010), the MTJ stack (1002) and the one or more lower electrode layers (902) and for forming an upper electrode structure (1108, 120), an MTJ (118, 206) and a lower electrode (116), wherein the lower electrode (116) extends from above the lower insulating structure (202) to the lower interconnect layer (108); and Forming a sidewall spacer (122) along the outermost sidewalls of the MTJ (118, 206) and the lower electrode (116) and extending to below an outermost sidewall of the lower electrode (116) after completion of one or more etching processes.

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