METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES

Abstract

Method for manufacturing a semiconductor device, comprising: Forming a first dielectric layer (80, 200) over a substrate; Formation of an adhesion-enhancing layer (110, 210) on an area of ​​the first dielectric layer (80, 200); and Forming a second dielectric layer (120, 220, 230) on the adhesion-enhancing layer (110, 210), wherein the second dielectric layer (120, 220, 230) comprises an aluminium nitride-based material, wherein the adhesion improvement layer (110, 210) is formed by treating the surface of the first dielectric layer (80, 200) with an oxygen-containing gas.

Description

GENERAL STATE OF THE ART

[0001] Delamination is a problem between aluminum nitride layers and silicon nitride contact etch stop layers. One way to address the delamination problem is to increase the thickness of the aluminum nitride layer; however, this increases the overall device thickness and reduces the device density. A solution to the aluminum nitride delamination problem is desirable.

[0002] US 2018 / 0261546A1 relates to a semiconductor device comprising a metal film and a complex cover layer covering a top surface of the metal film. The metal film comprises a first metal and penetrates at least a portion of an insulating film formed over a substrate, and the complex cover layer comprises a cover layer of a conductive alloy covering the top surface of the metal film and an insulating cover layer covering a top surface of the conductive alloy cover layer and a top surface of the insulating film.

[0003] US 2016 / 0 133 512 A1 relates to a method for manufacturing the semiconductor device with a first and a second dielectric intermediate layer with a conductive pattern using a first and a second etch stop layer.

[0004] US 2017 / 0018458A1 relates to a method for forming a semiconductor device structure comprising a metal layer in a first dielectric layer over a substrate, an etch stop layer of metal-containing material over the metal layer, and a second dielectric layer over the etch stop layer. The fabrication process also utilizes a plasma containing nitrogen gas (N2) and hydrogen gas (H2). BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following detailed description is best understood when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale and are for illustrative purposes only. The dimensions of the various features may, in fact, be arbitrarily enlarged or reduced to clarify the explanation. Fig. 1A, Fig. 1B, Fig. 1C and Fig. Figure 1D illustrates different stages of a sequential fabrication operation of a semiconductor device according to this disclosure. Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D illustrates different stages of a sequential manufacturing operation of a semiconductor device according to this disclosure. Fig. 3A, Fig. 3B, Fig. 3C and Fig. 3D illustrates various stages of a sequential manufacturing operation of a semiconductor device according to this disclosure. Fig. 3E, Fig. 3F, Fig. 3G and Fig. Figures 3H illustrate various stages of a sequential fabrication operation of a semiconductor device according to this disclosure. Fig. Figure 4A shows a top view (viewed from above) illustrating one of the various stages of a sequential manufacturing process of a semiconductor device according to an embodiment of this disclosure. Fig. 4B shows a cross-sectional view along line X1-X1 of Fig. 4A. Fig. 4C and Fig. 4D images are enlarged views of the gate structure. Fig. Figure 4E shows a perspective view illustrating one of the different stages of a sequential manufacturing process of a semiconductor device according to an embodiment of this disclosure. Fig. 5A, Fig. 5B, Fig. 5C, Fig. 5D and Fig. Figure 5E shows cross-sectional views of various stages of the sequential manufacturing process of a semiconductor device according to an embodiment of this disclosure. Fig. 6A, Fig. 6B, Fig. 6C and Fig. Figure 6D shows cross-sectional views of various stages of the sequential manufacturing process of a semiconductor device according to an embodiment of this disclosure. Fig. 7A, Fig. 7B, Fig. 7C and Fig. Figure 7D shows cross-sectional views of various stages of the sequential manufacturing process of a semiconductor device according to an embodiment of this disclosure. Fig. 8A, Fig. 8B and Fig. Figure 8C shows cross-sectional views of various stages of the sequential manufacturing process of a semiconductor device according to an embodiment of this disclosure. Fig. 9A, Fig. 9B, Fig. 9C and Fig. Figure 9D shows different views of a semiconductor device according to one embodiment of this disclosure. DETAILED DESCRIPTION

[0006] The invention is defined by the subject matter of the independent claims. The dependent claims relate to corresponding embodiments. The following disclosure provides many different embodiments or examples for implementing various functions of the presented content. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which further features can be formed between the first and second features, so that the first and second features do not have to be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various designs and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms should encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative designators used herein may be interpreted accordingly. Furthermore, the term "made of" may mean either "comprising" or "consisting of."In this revelation, the term “one of A, B and C” means “A, B and / or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element of A, one element of B and one element of C, unless otherwise described.

[0008] In a semiconductor device, a metallization layer is formed over a semiconductor device structure. In some embodiments, the semiconductor device structure includes a transistor. In some embodiments, the transistor includes a fin-field-effect (FinFET) transistor or a gate all-around-field-effect (GAAFET) transistor. The metallization layer comprises an electrically conductive layer embedded in a dielectric layer. A metallization layer formed over a semiconductor device structure comprises an electrically conductive layer, such as tungsten, embedded in an insulating layer, such as silicon nitride, silicon oxynitride, or silicon oxide. An etch stop layer, such as an aluminum-based insulating layer (e.g., an AlN layer), is formed over the metallization layer.In some embodiments, the electrically conductive layer is a contact that is in contact with the underlying semiconductor device structure. In some embodiments, an aluminum nitride layer is oxidized to form an aluminum oxynitride (Al. 10⁻¹⁵) upon contact of the aluminum nitride layer with oxygen in the ambient air. x O y N z The insertion of oxygen atoms into the aluminum nitride lattice through oxidation causes a loss of adhesion between the aluminum nitride layer and the silicon nitride layer, leading to detachment of the aluminum nitride layer from the silicon nitride surface. This detachment can result in the formation of aluminum oxide hillocks. Hillocks are defects that create an uneven surface on the semiconductor device, thus reducing its yield. The inserted oxygen atom disrupts the crystal lattice structure and induces stress.

[0009] In embodiments of this disclosure, an adhesion-enhancing layer (adhesion layer) is formed on the underlying layer (e.g. silicon nitride layer) before an etch-stop layer (e.g. aluminum nitride layer) is formed to absorb or reduce the stress caused by the oxidation of the aluminum nitride layer and to suppress the detachment of the etch-stop layer.

[0010] Fig. 1A, Fig. 1B, Fig. 1C and Fig. Figure 1D illustrates various stages of a sequential fabrication operation of a semiconductor device according to this disclosure. It is understood that further operations may occur before, during, and after the operations described above. Fig. Figures 1A to 1D illustrate that the methods can be provided and that some of the operations described below can be replaced or eliminated for other embodiments of the method. The sequence of operations / processes can be interchangeable.

[0011] As in Fig. As shown in Figure 1, a first dielectric layer 200 is formed over an underlying structure (not shown) on a semiconductor substrate (not shown). In some embodiments, the first dielectric layer 200 comprises one or more layers of nitride-based insulating material. In some embodiments, the nitride-based insulating layer is silicon nitride or oxynitride, or silicon germanide (SiGe). In some embodiments, the nitride-based insulating material comprises silicon nitride and silicon oxynitride. In the case of silicon oxynitride, the amount of nitrogen is greater than the amount of oxygen (Si) in some embodiments. x O y N z, where y < z). In certain embodiments, silicon nitride is used as the first dielectric layer 200. The first dielectric layer 200 is formed by chemical vapor deposition (CVD), including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable process.

[0012] Then, as in Fig. Figure 1B shows an adhesion-enhancing layer 210 formed on the surface of the first dielectric layer 200. In some embodiments, the adhesion-enhancing layer 210 is an oxygen-rich layer with a higher oxygen content than the first dielectric layer 200. In some embodiments, the adhesion-enhancing layer 210 comprises silicon oxide. In certain embodiments, the silicon oxide is an oxygen-deficient silicon oxide (SiO₂). x, where 0 < x < 2). In other embodiments, the silicon oxide is silicon dioxide (SiO2). In other embodiments, the adhesion-enhancing layer 210 comprises oxygen-rich silicon oxynitride, Si x O y N z , where y > z.

[0013] In some embodiments, the adhesion-enhancing layer 210 is formed by contact of the first dielectric layer 200 with an oxygen-containing gas under heat (heat oxidation). In some embodiments, the oxygen-containing gas is at least one of oxygen (O2), ozone (O3), a nitrogen oxide (N2O, NO2), and a carbon oxide (CO, CO2). In some embodiments, the nitrogen oxide is nitrous oxide and the carbon oxide is carbon dioxide. In some embodiments, no silicon-containing gas is included. In some embodiments, the oxygen-containing gas is applied at a pressure of approximately 0.67 mbar to approximately 26.67 mbar. In other embodiments, the oxygen-containing gas is applied at a pressure of approximately 2 mbar to approximately 10.67 mbar. In some embodiments, the oxygen treatment takes place at a substrate temperature in the range of approximately 150 °C to approximately 500 °C.In other embodiments, the substrate temperature is in a range of approximately 250 °C to approximately 400 °C.

[0014] In some embodiments, plasma-containing oxygen is used to treat (oxidize) the surface of the first dielectric layer 200. In other embodiments, the adhesion-enhancing layer 210 is a deposited film formed by CVD, PVD, ALD, or another suitable process.

[0015] In some embodiments, the adhesion-enhancing layer 210 has a thickness in the range of approximately 0.5 nm to approximately 10 nm. In other embodiments, the adhesion-enhancing layer 210 has a thickness in the range of approximately 1 nm to approximately 5 nm. If the thickness of the adhesion-enhancing layer 210 is less than the lowest value in the range, detachment of the adhesion-enhancing layer and / or of an upper layer subsequently formed on top of the adhesion-enhancing layer may occur. If the thickness of the adhesion-enhancing layer 210 is greater than the highest value in the range, this may trigger a subsequent etching operation.

[0016] Furthermore, as in Fig. Figure 1C shows a second dielectric layer 220 formed above the adhesion-enhancing layer 210. In some embodiments, the second dielectric layer 220 acts as an etch-stop layer. In some embodiments, the second dielectric layer 220 comprises a nitride-based insulating material. In some embodiments, the second dielectric layer 220 comprises an aluminum-based insulating material. In certain embodiments, the second dielectric layer 220 comprises aluminum nitride and / or aluminum oxynitride (Al x O y N z In the case of aluminum oxynitride, the amount of nitrogen is greater than the amount of oxygen in some embodiments (Al x O y N z , where y < z).

[0017] In some embodiments, the thickness of the second dielectric layer 220 is greater than the thickness of the adhesion-enhancing layer 210. In some embodiments, the thickness of the second dielectric layer 220 is in the range of approximately 1 nm to approximately 20 nm. In other embodiments, the thickness of the second dielectric layer 220 is in the range of approximately 2 nm to approximately 10 nm. In other embodiments, the second dielectric layer 220 is formed by CVD, PVD, ALD, or another suitable process. The aluminum-based insulating layer is formed, for example, by metal-organic CVD (MOCVD) or ALD using trimethylaluminum (TMA). In some embodiments, the aluminum nitride layer is crystalline, e.g., wurtzite(2H)AlN.

[0018] Subsequently, in some embodiments, the second dielectric layer 220 is further oxidized to form an oxidized second dielectric layer 230 as in Fig. Figure 1D shows that in some embodiments, when the second dielectric layer 220 is made of aluminum nitride, the oxidized second dielectric layer 230 is aluminum oxide or aluminum oxynitride. In some embodiments, plasma treatment using O2, CO2, and / or CO gases (oxygen-containing gas) is applied to the aluminum nitride layer to convert at least part of the aluminum nitride layer to aluminum oxide. In some embodiments, the concentrations of Al, O, and / or N in the plasma-treated aluminum nitride layer are not uniform, particularly along a vertical direction. In some embodiments, the oxidized second dielectric layer 230 comprises an aluminum oxide layer (top) and an aluminum oxynitride layer (bottom). In other embodiments, the oxidized second dielectric layer 230 comprises an aluminum oxide layer (top), an aluminum oxynitride layer (middle), and an aluminum nitride layer (bottom).In some embodiments, the oxidized second dielectric layer 230 is an aluminum oxide layer. In some embodiments, the aluminum oxide layer is crystalline, such as γ-Al₂O₃ or α-Al₂O₃. In some embodiments, the oxidized second dielectric layer 230 is oxygen-rich aluminum oxynitride, AlₓOyNz, where y > z. In some embodiments, the oxygen and / or nitrogen concentration in the aluminum oxynitride layer is not uniform, and in certain embodiments, the oxygen concentration decreases from the upper surface to the lower surface of the oxidized second dielectric layer 230, while the nitrogen concentration increases from the upper surface to the lower surface of the oxidized second dielectric layer 230.

[0019] In some embodiments, if the plasma contains carbon, the oxidized second dielectric layer 230 comprises AlOC with a non-uniform carbon concentration. In some embodiments, a thermal oxidation process is carried out to form the oxidized second dielectric layer 230.

[0020] In some embodiments, the oxidized second dielectric layer 220 has a thickness in the range of approximately 1 nm to approximately 20 nm. In other embodiments, the oxidized second dielectric layer 220 has a thickness in the range of approximately 2 nm to approximately 10 nm.

[0021] Fig. 2A, Fig. 2B, Fig. 2C and Fig. Figure 2D illustrates various stages of a sequential fabrication operation of a semiconductor device according to this disclosure. It is understood that further operations may occur before, during, and after the operations described in Figure 2D. Fig. The methods described in Figures 2A to 2D can be provided, and some of the operations described below can be substituted or eliminated for other embodiments of the method. The sequence of operations / processes can be interchangeable. Materials, configurations, dimensions, methods, and / or operations as explained with respect to the embodiments above can be used in the following embodiments; a detailed explanation thereof can be omitted.

[0022] In some embodiments, the first dielectric layer 200 is formed over an underlying layer 205 on which or in which an electronic structure 215 is formed, as in Fig. Figure 2A shows the electronic structure 215, which in some embodiments comprises a transistor, wiring, a contact, an intermediate connection, a via, and / or a diffusion region. The underlying layer 205 comprises, in some embodiments, a semiconductor substrate and / or an insulating layer.

[0023] Furthermore, as in Fig. Figure 2A shows a conductive structure 225 formed in the first dielectric layer 200, which in some embodiments is in contact with the electronic structure 215. In some embodiments, the first dielectric layer is made of silicon nitride. The conductive structure 225 comprises, in some embodiments, a contact, a via, a wire, an intermediate connection, and / or a rod. In some embodiments, an opening is formed in the first dielectric layer 200 by using one or more lithography and etching operations, and the opening is filled with one or more conductive materials by one or more film formation operations and one or more planarization operations, such as a chemical-mechanical polishing (CMP) operation.In some embodiments, the conductive structure comprises polysilicon, aluminum, aluminum silicon, titanium, titanium silicide, titanium nitride, tungsten, tungsten silicide, molybdenum, molybdenum silicide, copper, platinum, cobalt, cobalt silicide, tantalum, tantalum nitride, indium, gold, and silver, or an alloy thereof. In certain embodiments, the conductive structure comprises tungsten. When tungsten is used, one or more adhesive and / or barrier layers (not shown) are formed before a tungsten layer is formed. In some embodiments, the adhesive and / or barrier layer comprises titanium, titanium nitride, tantalum, and / or tantalum nitride.

[0024] Similar to in Fig. As shown in Figure 1B, an adhesion-enhancing layer 210 is formed on the surface of the first dielectric layer 200, as shown in Figure 1B. Fig. Figure 2B shows that in some embodiments, a thermal or plasma oxidation operation as described above is used to form the adhesion-enhancing layer 210. In some embodiments, no adhesion-enhancing layer is formed on the surface of the conductive structure 225. In some embodiments, an oxide of an element representing the conductive structure 225 is formed on the surface of the conductive structure 225.

[0025] Then, similar to what happens in Fig. 1C a second dielectric layer 220 is formed on the adhesion-enhancing layer 210 and the conductive contact 225 as in Fig. 2C shown. In some embodiments, the second dielectric layer is made of aluminum nitride.

[0026] The following will be similar to the one described in Fig. 1D, the second dielectric layer 220 is partially or completely oxidized to form the oxidized second dielectric layer 230, as in Fig. Shown in 2D.

[0027] Fig. 3A, Fig. 3B, Fig. 3C and Fig. The 3D figures illustrate various stages of a sequential fabrication operation of a semiconductor device according to this disclosure. It is understood that further operations may occur before, during, and after the operations described above. Fig. The embodiments shown in Figures 3A to 3D can be provided, and some of the operations described below can be replaced or eliminated for other embodiments of the method. The sequence of operations / processes can be interchangeable. Materials, configurations, dimensions, methods, and / or operations as explained with respect to the embodiments above can be used in the following embodiments; a detailed explanation thereof can be omitted.

[0028] After the structure from Fig. 2A is formed similarly to how in Fig. 1B an adhesion-enhancing layer 210 is formed on the surface of the first dielectric layer 200 and the surface of the conductive structure 225, as shown in Fig. 3A shown. In some embodiments, a deposition process, such as CVD, PVD or ALD as described above, is used to form the adhesion-enhancing layer 210.

[0029] Then, similar to what happens in Fig. 1C a second dielectric layer 220 is formed on the adhesion-enhancing layer 210 as in Fig. Figure 3B shows that in some embodiments the second dielectric layer is made of aluminum nitride.

[0030] The following will be similar to the one described in Fig. 1D, the second dielectric layer 220 is partially or completely oxidized to form the oxidized second dielectric layer 230, as in Fig. 3C shown. As in Fig. As shown in Figure 3C, the oxidized second dielectric layer 230 does not directly contact the conductive structure 225. In some embodiments, a first adhesion-enhancing layer is used, as shown in Figure 3C. Fig. 2B shown, and furthermore a second adhesion-enhancing layer is formed over the first adhesion-enhancing layer and the conductive structure 225, as shown in Fig. Shown in 3D.

[0031] In some embodiments, the first dielectric layer 200 comprises several dielectric layers. As in Fig. As shown in Figure 3E, a lower layer 200A, a middle layer 200B, and an upper layer 200C are successively formed over the underlying layer 205 and the electronic structure 215. In some embodiments, the lower layer 200A and the upper layer 200C are made of silicon nitride, and the middle layer 200B is made of silicon oxide. Then, an opening 201 is formed over the electronic structure 215 by using one or more lithography and etching operations, as shown in Figure 3E. Fig. 3F shown. Furthermore, a conductive material for the conductive structure 225 is formed in the opening and on the upper layer 200C, as shown in Fig. 3G shown. Then a planarization operation, such as chemical-mechanical polishing (CMP) and / or a re-etching process, is performed to obtain the conductive structure 225, as shown in Fig. 3H shown. The following are the operations relating to the Fig. 2B to 2D or 3A to 3D are explained and carried out.

[0032] Fig. Figures 4A to 8C illustrate various stages of a sequential fabrication operation of a semiconductor device according to this disclosure. It is understood that further operations may occur before, during, and after the operations described above. Fig. The materials shown in Figures 4A to 8C can be provided, and some of the operations described below can be substituted or eliminated for other embodiments of the method. The sequence of operations / processes can be interchangeable. Materials, configurations, dimensions, methods, and / or operations as explained with respect to the embodiments above can be used in the following embodiments; a detailed explanation thereof can be omitted.

[0033] Fig. 4A and Fig. Figure 4B shows one of the different stages of a sequential manufacturing process of a semiconductor device according to an embodiment of this disclosure. Fig. Figure 4A shows a plan view (top view) and Fig. 4B shows a cross-sectional view along line X1-X1 of Fig. 4A.

[0034] Fig. 4A and Fig. Figure 4B shows a structure of a semiconductor device after forming metal gate structures. 10. In Fig. 4A and Fig. 4B, metal gate structures 10 are formed over a channel layer 5, approximately a section of a fin structure, and cover insulation layers 20 are arranged over the metal gate structures 10. The thickness of the metal gate structures 10 is in some embodiments in the range of 15 nm to 50 nm. The thickness of the cover insulation layer 20 is in some embodiments in the range of approximately 10 nm to approximately 30 nm, and in other embodiments in the range of approximately 15 nm to approximately 20 nm. Sidewall spacers 30 are provided on the sidewalls of the metal gate structure 10 and the cover insulation layer 20. The film thickness of the sidewall spacers 30 at the bottom of the sidewall spacers is in some embodiments in the range of approximately 3 nm to approximately 15 nm and in other embodiments in the range of approximately 4 nm to approximately 8 nm.The combination of the metal gate structure 10, the cover insulation layer 20, and the sidewall spacers 30 can be collectively referred to as a gate structure. Furthermore, source / drain regions 50 are formed adjacent to the gate structures, and the gaps between the gate structures are filled with an interlayer dielectric (ILD) layer 40.

[0035] Fig. Figure 4C is a magnified view of the gate structure. The metal gate structure 10 comprises one or more layers 16 of metallic material, such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlC, TiAlN, TaN, NiSi, CoSi, or other conductive materials. A gate dielectric layer 12, located between the channel layer 5 and the metal gate, comprises one or more layers of metal oxides, such as a high k-value metal oxide. Examples of metal oxides used for high k-value dielectrics include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or mixtures thereof.

[0036] In some embodiments, one or more functional setting layers 14 (MG) are arranged between the gate dielectric layer 12 and the metal material 16. The functional setting layers 14 are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or multiple layers of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the functional setting layer, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the functional setting layer.

[0037] The cover insulation layer 20 comprises one or more layers of insulating material such as silicon nitride-based material, including SiN, SiCN, and SiOCN. The sidewall spacer 30 is made of a different material than the cover insulation layer 20 and comprises one or more layers of insulating material such as silicon nitride-based material, including SiN, SiON, SiCN, and SiOCN. The ILD layer 40 comprises one or more layers of insulating material such as silicon dioxide-based material, including silicon dioxide (SiO2) and SiON.

[0038] In some embodiments, no gate cover insulation layer is formed, as in Fig. Shown in 4D.

[0039] The material of the sidewall spacer 30, the material of the cover insulation layer 20, and the material of the ILD layer 40 differ from one another, so that each of these layers can be selectively etched. In one embodiment, the sidewall spacer 30 is made of SiOCN, SiCN, or SiON, the cover insulation layer 20 is made of SiN, and the ILD layer 40 is made of SiO2.

[0040] In this embodiment, Fin-field-effect transistors (Fin FETs) manufactured by a gate replacement process are used.

[0041] Fig. Figure 4E shows an exemplary perspective view of a Fin-FET structure.

[0042] First, a fin structure 310 is produced over a substrate 300. The fin structure comprises a lower region and an upper region as a channel region 315. The substrate is, for example, a p-silicon substrate with an impurity concentration in the range of approximately 1 × 10⁻⁶ 15 cm -3 up to approximately 1 × 10 18 cm -3 In other embodiments, the substrate is an n-silicon substrate with an impurity concentration in the range of approximately 1 × 10⁻⁶. 15 cm -3 up to approximately 1 × 10 18 cm -3Alternatively, the substrate can comprise another elemental semiconductor, such as germanium; a compound semiconductor, including group IV-IV compound semiconductors such as SiC and SiGe, group III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In one embodiment, the substrate is a silicon layer of an SOI (silicon-on-insulator) substrate.

[0043] After the formation of the fin structure 310, an insulating layer 320 is formed over the fin structure 310. The insulating layer 320 comprises one or more layers of insulating materials such as silicon oxide, silicon oxynitride, or silicon nitride, deposited by LPCVD (low-pressure chemical vapor deposition), plasma CVD, or flowable CVD. The insulating layer can be formed by one or more layers of spin-on glass (SOG), SiO₂, SiON₂, SiOCN₂, and / or fluorine-doped silicate glass (FSG).

[0044] After the formation of the insulating layer 320 over the fin structure, a planarization operation is performed to remove a portion of the insulating layer 320. This planarization operation may include chemical-mechanical polishing (CMP) and / or a back-etching process. The insulating layer 320 is then further removed (cut out), exposing the upper region of the fin structure.

[0045] A dummy gate structure is formed over the exposed fin structure. The dummy gate structure comprises a dummy gate electrode layer made of polysilicon and a dummy gate dielectric layer. Sidewall spacers 350, comprising one or more layers of insulating materials, are also formed on the sidewalls of the dummy gate electrode layer. After the dummy gate structure is formed, the fin structure 310 not covered by the dummy gate structure is cut out beneath the top surface of the insulating layer 320. Then, using an epitaxial growth technique, a source / drain region 360 is formed over the cut-out fin structure. The source / drain region may include a stress material to apply a load to the channel region 315.

[0046] Then, an intermediate dielectric layer (ILD) 370 is formed over the dummy gate structure and the source / drain region. After a planarization operation, the dummy gate structure is removed to create a gate space. A metal gate structure 330, comprising a metal gate electrode and a gate dielectric layer, such as a high k-value dielectric layer, is then formed in the gate space. Finally, the cover insulation layer 340 is formed over the metal gate structure 330 to obtain the Fin FET structure shown in Figure 1. Fig. 4E. In Fig. 4E sections of the metal gate structure 330, the cover insulation layer 340, side walls 330 and the ILD 370 are cut to show the underlying structure.

[0047] The metal gate structure 330, the cover insulation layer 340, side walls 330, source / drain 360 and the ILD 370 made of Fig. 4E essentially correspond to the metal gate structures 10, cover insulation layers 20, side wall spacers 30, source / drain regions 50 and the interlayer dielectric layer (ILD) 40. Fig. 4A to 4D. In some embodiments, one or more additional ILD layers are formed above ILD layer 40, thereby forming a first ILD layer 45, as shown in Fig. 5A to 8C shown.

[0048] The following explanation describes how in Fig. Figures 5A to 8C show four fin structures 5 formed over a substrate 1, but the number of fin structures 5 is not limited to four and can be one, two, three or five or more.

[0049] After the metal gate structure is formed, a first etch stop layer 60 is formed over the first ILD layer 45 (or 40), and a second ILD layer 65 is formed over the first etch stop layer 60, as shown in Fig. Figure 5A shows that the etch stop layer and the ILD layer are formed by suitable film formation processes, such as CVD, PVD, or ALD.

[0050] By using one or more lithography and etching operations, a contact hole (opening) 67 for the first contact 70 is formed in the first and second ILD layers 45, 65, as shown in Fig. 5B shown.

[0051] Then, a first contact lining layer 68 is conformally formed in the contact hole 67 and on the upper surface of the second ILD layer 65, and a conductive material is formed over the first contact lining layer 68. The contact lining layer 68 and the conductive material layer are formed by suitable film formation processes, such as CVD, PVD, ALD, or plating. Subsequently, a planarization operation, such as a back-etch operation or a chemical-mechanical polishing (CMP) operation, is performed to form the source / drain contact 70, as shown in Fig. 5C shown.

[0052] Subsequently, a second etch stop layer 75 and the third ILD layer 80 are formed, as shown in Fig. 5D shown. In some embodiments, the third ILD layer 80 comprises, similarly to the first dielectric layer 200, one or more layers of nitride-based insulating material. In some embodiments, the nitride-based insulating layer is silicon nitride or silicon germanium oxynitride (SiGe). In some embodiments, the nitride-based insulating material comprises silicon nitride and silicon oxynitride. In the case of silicon oxynitride, the amount of nitrogen is greater than the amount of oxygen (Si) in some embodiments. x O y N z , where y < z). In certain embodiments, silicon nitride is used as the third ILD layer 80.

[0053] As in Fig. Figure 5E shows that by using one or more lithography and etching operations a contact hole (opening) 82 for the first contact is formed in the third ILD layer 80 and the second etch stop layer 75.

[0054] Then, as in Fig. Figure 6A shows a second contact lining layer 90 conformally formed in the contact hole 82. The second contact lining layer 90 is formed by suitable film formation processes, such as CVD, PVD, ALD or plating.

[0055] Then, as in Fig. As shown in Figure 6B, one or more conductive material layers are formed in the contact hole 82 and the third ILD layer 80. The conductive layer is formed by suitable film formation processes, such as CVD, PVD, ALD, or plating. In some embodiments, the conductive material is formed at a temperature in the range of approximately 200 °C to approximately 400 °C. In some embodiments, the conductive material comprises, similar to the conductive structure 225, polysilicon, aluminum, aluminum silicon, titanium, titanium silicide, titanium nitride, tungsten, tungsten silicide, molybdenum, molybdenum silicide, copper, platinum, cobalt, cobalt silicide, tantalum, tantalum nitride, indium, gold, and silver, or an alloy thereof. In certain embodiments, the conductive material comprises tungsten. Then, a planarization operation, such as a back-etching operation or a CMP operation, is performed to form the second contact 100, as shown in Figure 6B. Fig. 6C shown.

[0056] The following will be similar to the one described in Fig. 1B, Fig. 2B and Fig. 3B, the surface of the third ILD layer is treated by an oxygen-containing gas and / or an oxygen-containing plasma to form an adhesion-enhancing layer 110, as in Fig. Figure 6D shows that in some embodiments a deposition process is used to form the adhesion-enhancing layer 110.

[0057] Furthermore, as in Fig. 7A shown, similar to in Fig. 1C, Fig. 2C and Fig. 3C, a third etch-stop layer 120 is formed on the adhesion-enhancing layer 110. In some embodiments, the third etch-stop layer 120 comprises, similar to the second dielectric layer 220, a nitride-based insulating material. In some embodiments, the third etch-stop layer 120 comprises an aluminum-based insulating material. In certain embodiments, the third etch-stop layer 120 comprises aluminum nitride and / or aluminum oxynitride (Al x O y N z In the case of aluminum oxynitride, the amount of nitrogen is greater than the amount of oxygen in some embodiments (Al x O y N z , where y < z).

[0058] Then, as in Fig. 7B shown, similar to in Fig. 1D, Fig. 2D and Fig. 3D, the third etch stop layer 120 is oxidized to an oxidized etch stop layer 125. The structure and / or configuration of the oxidized third etch stop layer 120 is the same or similar to that of the oxidized second dielectric layer 230 as described above.

[0059] Then, as in Fig. 7C, a fourth ILD layer 130 is formed above the oxidized etch stop layer 125. The material for the fourth ILD layer 130 comprises one or more silicon oxide, silicon nitride, SiOC, SiOCN, SiCN, SiON, a low k-value material, a porous material, or any other suitable dielectric. A low k-value material generally has a dielectric constant that is less than that of silicon dioxide (3.9). In some embodiments, a low k-value material has a dielectric constant that is less than 2.0.

[0060] Then, as in Fig. Figure 7D shows that, by using one or more lithography and etching operations, a contact hole (opening) 135 for a third contact is formed in the fourth ILD layer 130. The etch stops on the oxidized etch stop layer 125 in some embodiments as shown in Fig. 7D shown. Then another etching operation is performed to execute the oxidized etch stop layer at the bottom of aperture 135, as shown in Fig. 8A shown.

[0061] Furthermore, one or more conductive material layers are formed in the contact hole 135 and on the fourth ILD layer 130, and a planarization operation, such as a back-etch operation or a CMP operation, is performed to form the third contact 140, as shown in Fig. Figure 8B shows that in some embodiments, a third contact lining layer (not shown) is conformally formed in the contact hole 135. The conductive layers are formed by suitable film formation processes, such as CVD, PVD, ALD, or plating. In some embodiments, the conductive material for the third contact and / or the third lining layer comprises polysilicon, aluminum, aluminum silicon, titanium, titanium silicide, titanium nitride, tungsten, tungsten silicide, molybdenum, molybdenum silicide, copper, platinum, cobalt, cobalt silicide, tantalum, tantalum nitride, indium, gold, and silver, or an alloy thereof. If the lower region of the third contact 140 is smaller than the upper region of the second contact 100, a portion of the oxidized etch stop layer 125 remains on the upper surface of the second contact 100.

[0062] In some embodiments, when the adhesion-enhancing layer 110 is formed by a deposition process, the adhesion-enhancing layer 110 is formed on the upper surface of the second contact 100. If the lower region of the third contact 140 is smaller than the upper region of the second contact 100, a portion of the adhesion-enhancing layer 110 remains on the upper surface of the second contact 100, as shown in Fig. 8C shown.

[0063] After the formation of the gate electrodes, further CMOS processes are carried out to create various features, such as additional interlayer dielectric layers, contacts / vias, interconnect metal layers and passivation layers, etc.

[0064] Fig. 9A, Fig. 9B, Fig. 9C and Fig. Figure 9D shows different views of a semiconductor device according to one embodiment of this disclosure. Fig. 9A is a top view, Fig. 9B is a cross-sectional view (Y-section), Fig. 9C is a cross-sectional view (X-section 1) and Fig. Figure 9D is a cross-sectional view (X-section 2). Materials, configurations, dimensions, methods and / or operations as explained with respect to the above embodiments may be used in the following embodiments, so a detailed explanation of them can be omitted.

[0065] In Fig. In 9A, three gate structures 10 extending in the Y-direction are arranged over a fin structure 5 extending in the X-direction. Sections between the gate structures 10 are source / drain regions 50, and source / drain contacts 70 are arranged over the source / drain regions 50. In some embodiments, the source / drain regions 50 comprise one or more epitaxially formed semiconductor layers (epitaxial layers). In some embodiments, the source / drain contact 70 are contact rods extending in the Y-direction beyond the source / drain regions 50. Thus, the width of the epitaxial source / drain layer (source / drain region) 50 is smaller than the width of the contact rod 70 in the Y-direction. As in Fig. 9A and Fig. As shown in Figure 9B, the width of the source-drain contact 70 is, in some embodiments, greater than the width of the upper contact 100 in the Y-direction. In some embodiments, one or more gate contacts 71 are arranged over one or more gate electrodes of the gate structures 10. Furthermore, in some embodiments, upper contacts 100 and 102 are arranged over the source-drain contacts 70 and the gate contact 71, respectively.

[0066] As in Fig. As shown in Figures 9B to 9D, the source / drain regions 50 are formed in cutouts within the fin structure 5. The gate structure 10 comprises a gate dielectric layer formed over the fin structure 5, a gate electrode, and sidewall spacers 30. The gate structure 10 is embedded in a first interlayer dielectric (ILD) layer 45. The first ILD layer 45 comprises one or more dielectric layers. In some embodiments, a first etch stop layer 60 is arranged over the first ILD layer 45, and a second ILD layer 65 is formed over the first etch stop layer 60. Furthermore, a second etch stop layer 75 is arranged over the second ILD layer 65, and a third ILD layer 80 is formed over the second etch stop layer 75.

[0067] The first and second ILD layers 45, 65 comprise one or more layers of insulating material, for example, a silicon oxide-based material such as silicon dioxide (SiO2), SiOC, and SiOCN. In some embodiments, a material with a low k-value or an organic material is used for the ILD layers. The third ILD layer 80 comprises silicon nitride or nitrogen-rich silicon oxynitride. The first and second etch stop layers 60, 75 are made of a different material than the ILD layers and comprise one or more layers of insulating material, for example, a silicon nitride-based material such as silicon nitride and SiON.

[0068] The first source-drain contact 70 is formed in a contact hole that extends through the first and second ILD layers 45, 65 and the first and second etch stop layers 60, 75. In some embodiments, a first contact lining layer 68 is formed on the inner surface of the contact hole. In some embodiments, the first contact lining layer 68 comprises one or more conductive material layers, such as Ti, TiN, Ta, and TaN. In certain embodiments, a TiN layer is used as the first contact conduction layer 68.

[0069] The first source-drain contact 70 and the gate contact 71 comprise one or more conductive material layers, such as tungsten, cobalt, nickel, molybdenum, and an alloy thereof. In certain embodiments, the first source-drain contact 70 and the gate contact 71 are made of cobalt.

[0070] In some embodiments, a second source-drain contact 100 is formed above the first source-drain contact 70. A first gate contact 102 is formed in a contact hole extending through the second and third ILD layers 65, 80 and the first and second etch stop layers 60, 75. The second source-drain contact 100 and the first gate contact 102 comprise one or more conductive material layers, such as W, Co, Ni, Mo, Cu, Al, and an alloy thereof. In certain embodiments, the second source-drain contact 100 and the first gate contact 102 are made of W.

[0071] Furthermore, an adhesion-enhancing layer 110 and an oxidized etch-stop layer 120 are arranged on the surface of the third ILD layer 80, as shown in Fig. Figures 9B to 9D show a third source-drain contact 140, which is arranged on top of the second source-drain contact 100, as shown in Figure 9B to 9D. Fig. 9C is shown, and a second gate contact 142 is arranged at the first gate contact 102, as shown in Fig. 9D shown.

[0072] In this disclosure, an adhesion-enhancing layer is formed between a silicon nitride-based dielectric layer and an aluminum nitride-based dielectric layer, and it is therefore possible to suppress the detachment of the aluminum nitride-based dielectric layer during and after the oxidation of the aluminum nitride-based dielectric layer.

[0073] It is understood that not all advantages have necessarily been discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may offer different advantages.

[0074] According to one aspect of this disclosure, in a process for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion-enhancing layer is formed on an area of ​​the first dielectric layer, and a second dielectric layer is formed on the adhesion-enhancing layer. In one or more of the preceding and subsequent embodiments, the first dielectric layer is made of silicon nitride and the second dielectric layer is made of aluminum nitride. In one or more of the preceding and subsequent embodiments, the adhesion-enhancing layer is made of silicon oxide. In one or more of the preceding and subsequent embodiments, the second dielectric layer is oxidized. In one or more of the preceding and subsequent embodiments, the adhesion-enhancing layer is formed by treating the area of ​​the first dielectric layer with an oxygen-containing gas.In one or more of the preceding and following embodiments, the oxygen-containing gas comprises at least one gas from the group consisting of N₂O, O₂, ozone, and CO₂. In one or more of the preceding and following embodiments, the substrate is heated to a temperature in the range of 250 °C to 400 °C during the treatment of the surface of the first dielectric layer with the oxygen-containing gas, and the oxygen-containing gas is applied at a pressure in the range of 0.67 mbar to 26.67 mbar. In one or more of the preceding and following embodiments, the thickness of the adhesion-enhancing layer is in the range of 1 nm to 5 nm. In one or more of the preceding and following embodiments, the adhesion-enhancing layer is formed by treating the surface of the first dielectric layer with oxygen-containing plasma.In one or more of the preceding and following embodiments, the adhesion-enhancing layer is formed by a deposition process.

[0075] According to another aspect of this disclosure, in a process for manufacturing a semiconductor device, a first nitride-based dielectric layer is formed over a semiconductor device structure on a substrate, an adhesion-enhancing layer is formed over the first nitride-based dielectric layer, a second nitride-based dielectric layer is formed over the adhesion-enhancing layer, and the second nitride-based dielectric layer is at least partially oxidized. The first nitride-based dielectric layer is made of a different material than the second nitride-based dielectric layer. In one or more of the preceding and subsequent embodiments, a conductive structure is formed in the first nitride-based dielectric layer, and an upper surface of the conductive structure is exposed by the first nitride-based dielectric layer.In one or more of the preceding and subsequent embodiments, the conductive structure comprises tungsten. In one or more of the preceding and subsequent embodiments, the adhesion-enhancing layer is formed on the upper surface of the conductive structure. In one or more of the preceding and subsequent embodiments, the adhesion-enhancing layer is formed on the first nitride-based dielectric layer and not on the upper surface of the conductive structure. In one or more of the preceding and subsequent embodiments, the first nitride-based dielectric layer is made of silicon nitride, and the second nitride-based dielectric layer is made of aluminum nitride.

[0076] According to another aspect of this disclosure, in a process for manufacturing the semiconductor device, a first conductive contact is formed, embedded in a first insulating layer; a second insulating layer is formed over the first conductive contact; a first opening is formed in the second insulating layer to at least partially expose the first conductive contact; the first opening is formed by a first conductive material to form a second conductive contact in contact with the first conductive contact; an adhesion-enhancing layer is formed on the second insulating layer; a nitride-based insulating layer is formed on the adhesion-enhancing layer; the nitride-based insulating layer is oxidized; a third insulating layer is formed on the oxidized nitride-based insulating layer; a second opening is formed by etching the third insulating layer.The oxidized nitride-based insulating layer is removed, and the second opening is formed by a second conductive material. In one or more of the preceding and subsequent embodiments, the second insulating layer is made of silicon nitride, and the nitride-based insulating layer is made of aluminum nitride. In one or more of the preceding and subsequent embodiments, the first conductive contact is formed on an epitaxial source-drain layer. In one or more of the preceding and subsequent embodiments, the first conductive contact is formed on a gate electrode.

[0077] According to one aspect of this disclosure, a semiconductor device comprises a first dielectric layer arranged over a semiconductor device structure, an adhesion-enhancing layer arranged over the first dielectric layer, and a second dielectric layer arranged over the adhesion-enhancing layer. The first metal nitride layer and the second metal nitride layer comprise different metals. In one or more of the preceding and subsequent embodiments, the first dielectric layer is made of silicon nitride. In one or more of the preceding and subsequent embodiments, the second dielectric layer is made of aluminum oxynitride. In one or more of the preceding and subsequent embodiments, the second dielectric layer comprises an aluminum oxynitride layer on top of an aluminum nitride layer.In one or more of the preceding and following embodiments, the adhesion-enhancing layer is made of SiO. x manufactured, wherein 0 < x < 2. In one or more of the preceding and following embodiments, the adhesion-enhancing layer has a thickness of 0.5 nm to 10 nm.

[0078] According to another aspect of this disclosure, a semiconductor device comprises a first nitride-based dielectric layer arranged over a semiconductor device structure, a first conductive structure formed in the first nitride-based dielectric layer, an adhesion enhancer layer arranged over the first nitride-based dielectric layer, a second nitride-based dielectric layer arranged over the adhesion enhancer layer, a third dielectric layer arranged over the second nitride-based dielectric layer, and a second conductive structure formed in the third dielectric layer in contact with the first conductive structure.In one or more of the preceding and subsequent embodiments, the first nitride-based dielectric layer is made of silicon nitride, and the second nitride-based dielectric layer comprises at least one aluminum nitride layer and one aluminum oxynitride layer. In one or more of the preceding and subsequent embodiments, the first conductive structure comprises tungsten. In one or more of the preceding and subsequent embodiments, the first conductive structure is formed on a contact that is in contact with an epitaxial source-drain layer. In one or more of the preceding and subsequent embodiments, the first conductive structure is formed on a contact that is in contact with a gate electrode. In one or more of the preceding and subsequent embodiments, the third dielectric comprises a dielectric with a low k-value.In one or more of the preceding and following embodiments, the second nitride-based dielectric layer partially covers an upper surface of the first conductive structure. In one or more of the preceding and following embodiments, the adhesion-enhancing layer partially covers an upper surface of the first conductive structure, and the second nitride-based dielectric layer is not in contact with an upper surface of the first conductive structure.

[0079] According to another aspect of this disclosure, a semiconductor device comprises a gate electrode, a source-drain structure, a first conductive contact arranged in a first interlayer dielectric (ILD) layer and in contact with the source-drain structure, a second conductive contact that contacts the first conductive contact and is arranged in an opening formed in a second ILD layer arranged above the first ILD layer, a gate contact that contacts the gate electrode and is arranged in the first and second ILD layers, an adhesive insulation layer arranged above the second ILD layer, an etch stop layer arranged on the adhesive insulation layer, a third ILD layer arranged above the etch stop layer, and a third conductive contact that contacts either the second conductive contact or the gate contact and is arranged in the third ILD layer.In one or more of the preceding and subsequent embodiments, the adhesive insulation layer has a higher oxygen concentration than the second ILD layer. In one or more of the preceding and subsequent embodiments, the etch stop layer contains aluminum. In one or more of the preceding and subsequent embodiments, the semiconductor device further comprises a fourth conductive contact located in the third ILD layer. The third conductive contact contacts the second conductive contact, and the fourth conductive contact contacts the gate contact. In one or more of the preceding and subsequent embodiments, the second conductive contact and the gate contact comprise tungsten. In one or more of the preceding and subsequent embodiments, the thickness of the adhesive insulation layer is in the range of 1 nm to 5 nm, and the thickness of the etch stop layer is greater than the thickness of the adhesive insulation layer.

Claims

[1] Method for manufacturing a semiconductor device comprising: Forming a first dielectric layer (80, 200) over a substrate; Formation of an adhesion-enhancing layer (110, 210) on an area of ​​the first dielectric layer (80, 200); and Forming a second dielectric layer (120, 220, 230) on the adhesion-enhancing layer (110, 210), wherein the second dielectric layer (120, 220, 230) comprises an aluminium nitride-based material, wherein the adhesion improvement layer (110, 210) is formed by treating the surface of the first dielectric layer (80, 200) with an oxygen-containing gas. [2] Method according to claim 1, wherein: the first dielectric layer (80, 200) is made of silicon nitride, and the second dielectric layer (120, 220, 230) is made of aluminium nitride. [3] Method according to claim 2, wherein the adhesion-enhancing layer (110, 210) is made of silicon oxide or silicon oxynitride. [4] Method according to claim 3, further comprising oxidizing the second dielectric layer (120, 220, 230). [5] Method according to any of the preceding claims, wherein the oxygen-containing gas comprises at least one from the group consisting of N2O, O2, ozone and CO2. [6] Method according to one of the preceding claims, wherein during the treatment of the surface of the first dielectric layer (80, 200) with the oxygen-containing gas the substrate is heated to a temperature in a range of 250 °C to 400 °C, and the oxygen-containing gas is applied at a pressure in a range of 0.67 mbar to 26.67 mbar. [7] Method according to any one of the preceding claims 3 to 6, wherein the thickness of the adhesion-enhancing layer (110, 210) is in a range of 1 nm to 5 nm. [8] Method according to any one of the preceding claims 3 to 7, wherein the adhesion improvement layer (110, 210) is formed by treating the surface of the first dielectric layer (80, 200) with oxygen-containing plasma. [9] Method according to any one of the preceding claims 3 to 8, wherein the adhesion-enhancing layer (110, 210) is formed by a deposition process. [10] Method for manufacturing a semiconductor device, comprising: Formation of a first nitride-based dielectric layer (80, 200) over a semiconductor device structure on a substrate; Formation of an adhesion-enhancing layer (110, 210) over the first nitride-based dielectric layer (80, 200); Forming a second nitride-based dielectric layer (120, 220, 230) over the adhesion-enhancing layer (110, 210); at least partial oxidation of the second nitride-based dielectric layer (120, 220, 230), wherein the first nitride-based dielectric layer (80, 200) is made of a different material than the second nitride-based dielectric layer (120, 220, 230), further comprising forming a conductive structure (100, 225) in the first nitride-based dielectric layer (80, 200), wherein an upper surface of the conductive structure (100, 225) is exposed by the first nitride-based dielectric layer (200), wherein the conductive structure (100, 225) comprises tungsten, and wherein the adhesion enhancement layer (110, 210) is formed on the upper surface of the conductive structure (100, 225). [11] Method according to claim 10, wherein: the first nitride-based dielectric layer (80, 200) is made from silicon nitride, and the second nitride-based dielectric layer (120, 220, 230) is made of aluminum nitride. [12] Semiconductor device comprising: a first dielectric layer (80, 200) arranged over a semiconductor device structure; an adhesion-enhancing layer (110, 210) arranged above the first dielectric layer (80, 200); and a second dielectric layer (120, 220, 230) arranged above the adhesion-enhancing layer (110, 210), wherein the first dielectric layer (80, 200) comprises a first metal nitride and the second dielectric layer (120, 220, 230) comprises a second metal nitride which differs from the first metal nitride, and a nitrogen concentration of the second dielectric layer (120, 220, 230) is not uniform along a vertical direction, wherein a conductive structure (100, 225) is formed in the first nitride-based dielectric layer (80, 200), wherein an upper surface of the conductive structure (100, 225) is exposed in the first nitride-based dielectric layer (200), wherein the conductive structure (100, 225) comprises tungsten, and wherein the adhesion enhancement layer (110, 210) is formed on the upper surface of the conductive structure (100, 225). [13] Semiconductor device according to claim 12, wherein the first dielectric layer (80, 200) is made of silicon nitride. [14] Semiconductor device according to claim 12 or 13, wherein: the second dielectric layer (120, 220, 230) comprises aluminium oxynitride, and the nitrogen concentration of the second dielectric layer (120, 220, 230) increases along the vertical direction towards the first dielectric layer (80, 200) and the oxygen concentration of the second dielectric layer (120, 220, 230) decreases along the vertical direction towards the first dielectric layer (80, 200). [15] Semiconductor device according to any one of the preceding claims 12 to 14, wherein the second dielectric layer (120, 220, 230) comprises an aluminium oxynitride layer on an aluminium nitride layer.

Images