storage device

Abstract

comprising storage device (100): a cell arrangement (110) comprising several cells (202), each of the several cells (202) being configured to store a bit value; and a reset circuit (180) connected to the cell arrangement (110), wherein the reset circuit (180) is configured to simultaneously reset the bit value stored in each of the multiple cells (202) to a predetermined bit value; wherein the reset circuit (180) comprises a reset signal generator circuit (302) configured to generate a reset signal, wherein the reset signal is set up to trigger a parallel reset of the bit value stored in each of the multiple cells (202) to the specified bit value, wherein the feature that the reset signal generator circuit (302) is configured to generate the reset signal includes that the reset signal generator circuit (302) is configured to detect a logical disjunction between a first signal and a second signal, where the first signal indicates the initiation of a switch-on period for the multiple cells, and a second signal indicates the termination of the switch-on period for the multiple cells, wherein the reset signal generator circuit (302) includes an OR logic gate (306).

Description

BACKGROUND

[0001] A commonly used type of integrated circuit memory is a static random access memory (SRAM) device. A typical SRAM memory device has an array of memory cells. The memory cell uses six transistors connected between an upper reference potential and a lower reference potential (usually ground) such that one of two memory nodes can be occupied with the information to be stored, with the complementary information stored in the other memory node.

[0002] Power gating and voltage conservation techniques are frequently implemented in memory arrays to reduce power consumption. For example, power gates can be used to turn off memory peripherals in a deep sleep mode, and both the peripherals and the memory array are in a shutdown mode. Generally, an on-chip SRAM retains some of the bit values ​​stored in the SRAM when it exits power-down or shutdown mode. This can pose a security risk, as the contents could be read by malicious programs. Furthermore, some applications need to start an SRAM with all bit values ​​set to zero. For example, an application might need to start with an empty SRAM and set individual bits. A reset device and method for a static memory array are known from US Patent 4,928,266 A.From publication US 2018 / 0 358 084 A1, a system and a method for initializing a memory arrangement are known. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been enlarged or reduced arbitrarily for the sake of clarity. Fig. Figure 1 is a block diagram illustrating an exemplary storage device according to some embodiments. Fig. Figure 2 is a diagram illustrating an exemplary cell arrangement according to some embodiments. Fig. Figure 3A is a diagram illustrating a storage device with a reset circuit according to some embodiments. Fig. Figure 3B is a diagram illustrating a storage device with a different reset circuit according to some embodiments. Fig. Figure 3C is a diagram illustrating a storage device with multiple subblocks according to some embodiments. Fig. Figure 4 illustrates a time-lapse curve diagram of a reset circuit according to some embodiments. Fig. Figure 5 is a flowchart illustrating a procedure for resetting a memory device according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact.Furthermore, this disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically establish a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the FIGS. These spatially relative terms are also intended to encompass other orientations of the device in use or operation besides the orientation shown in the FIGS. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0006] Fig. Figure 1 discloses a block diagram of an exemplary storage device 100 according to some embodiments. The storage device 100 can be a random-access memory, such as a static random-access memory (SRAM) device. As shown in Fig. As shown in Figure 1, the storage device 100 includes at least one cell array 110 and several peripheral circuits, such as a decoder circuit 120, a local input / output (I / O) circuit 130, a local control circuit 140, a global I / O circuit 150, a global control circuit 160, a power control circuit 170, and a reset circuit 180. The storage device 100 may also include other components not shown in Figure 1. Fig. Figure 1 shows. In exemplary embodiments, the storage device 100 can be part of an integrated circuit (IC) chip.

[0007] The cell array 110 contains multiple memory cells (also called multiple bit cells) arranged in a matrix of m rows and n columns. Each of the multiple cells of the cell array 110 is configured to store a single bit of information (that is, 0 or 1). The multiple cells of the cell array 110 are accessed via multiple word lines and multiple bit line pairs. The cell array 110 is described with reference to Fig. 2 discussed in more detail. Although the storage device 100 contains only a single cell arrangement 110 for the sake of simplicity, the storage device 100 could also contain several cell arrangements 110.

[0008] The peripheral devices contain circuits that provide various functions to the storage device 100, which belongs to the cell array 110. For example, the decoder circuit 120 of the storage device 100 is configured to decode one or more address lines in order to select a word line (WL) of the cell array 110 and load the selected word line to a logic high. The logic high is approximately equal to a first predefined potential. In exemplary embodiments, the decoder circuit 120 includes several logic operators for decoding potentials on the address lines to identify a word line to be activated. The address lines are loaded to a logic high (that is, approximately equal to the first predefined potential) or to a logic low (that is, approximately equal to a second predefined potential).In exemplary embodiments, the second predetermined potential is approximately equal to ground potential or zero volts. In some embodiments, the number of output lines of the decoder circuit 120 is equal to the number of rows of the cell arrangement 110, with each output of a word line being assigned to a row.

[0009] The local I / O circuit 130 of the storage device 100 is configured to read data to and from the cell array 110. For example, the local I / O circuit 130 is configured to read potentials in the multiple bit line pairs and compare the potentials for each pair. In exemplary embodiments, if the potential of a first bit line is greater than the potential of a second bit line of a bit line pair, the local I / O circuit 130 reads the output as a bit value 1. Conversely, if the potential of a first bit line is less than the potential of the second bit line of the bit line pair, the local I / O circuit 130 reads the output as a bit value 0.

[0010] The local control circuit 140 of the storage device 100 is configured to control the local I / O circuit 130. For example, the local control circuit 140 is configured to put the local I / O circuit 130 into a read mode to read information from the cell array 110 or into a write mode to write information to the storage array 110. Furthermore, the local control circuit 140 is configured to put the local I / O circuit 130 into a hold mode in which no data is read from or written to the cell array 110.

[0011] The global I / O circuit 150 of the storage device 100 is configured to combine the input / output from local I / O circuits 130. For example, the storage device 100 can contain multiple cell arrays 110, each with its own local I / O circuit 130. The global I / O circuit 150 is configured to combine the information from multiple local I / O circuits 130 into a single global I / O of the storage device 100. For example, local I / O circuits 130 are configured to store the output of cell arrays 110 in a shift register, and the global I / O circuit 150 is configured to read the data from the shift register and provide the data as the output of the storage device 100.

[0012] The local control circuit 160 of the storage device 100 is configured to control the global I / O circuit 150. For example, the global control circuit 160 can be configured to direct the global I / O circuit 150 to select one or more local I / O circuits 130 for reading or writing data. In another example, the global control circuit 160 is configured to initiate a read sequence for the global I / O circuit 150 to read data from one or more local I / O circuits 130, or a write sequence to write data to one or more local I / O circuits 130.

[0013] The power control circuit 170 is configured to control and manage the power to one or more components of the storage device 100. For example, in some embodiments, the power control circuit 170 is configured to selectively connect one or more components of the storage device 100 to a voltage terminal. The power control circuit 170 contains several logic gates or power gates. Each of the several power gates is configured to turn an associated component of the storage device 100 on or off. For example, the power control circuit 170 is configured to generate a shutdown (SD) signal to turn off all components of the storage device 100.Furthermore, the power control circuit 170 is configured to generate a Deep Sleep Low Power (DSLP) signal to turn off one or more peripheral circuits to reduce the power consumption of the storage device 100. Additionally, the power control circuit 170 is configured to generate a Ready (RDY) signal indicating that the storage device 100 is being lowered into standby mode.

[0014] The reset circuit 180 is configured to reset the stored values ​​in each of the multiple cells of the cell array 110 to a predetermined value. For example, the reset circuit 180 is configured to reset the stored values ​​in each of the multiple cells of the cell array 110 to a bit value 0 or to a bit value 1. The reset circuit 180 is described with reference to Fig. 3 of Revelation discussed in more detail.

[0015] Fig. Figure 2 illustrates an exemplary cell arrangement 110 according to some embodiments. As shown in Fig. As shown in Figure 2, the cell array 110 contains several cells designated 202a1, 202a2, 202a2, ..., 202nm. Each cell of the cell array 110 is configured to store one bit (that is, 0 or 1) of information. An exemplary cell contains a pair of cross-coupled inverters (also designated Q and Q-bar, where Q-bar is complementary to Q) to store the one bit of information. The cross-coupled inverters are connected to a pair of access transistors that provide access to the information stored in the cross-coupled inverters. In exemplary embodiments, cells of the cell array 110 can be formed using four transistors, six transistors, or eight transistors. Furthermore, memory cells of the cell array 110 can be single-port cells or multi-port cells (e.g., two-port and three-port cells).

[0016] We'll stick with it Fig. 2. The multiple memory cells of the cell array 110 are arranged in a matrix of multiple rows (i.e., m rows) and multiple columns (i.e., n columns). Each of the m rows of the cell array 100 contains a first plurality of cells, and each of the n columns of the cell array 110 contains a second plurality of cells. The number of rows and the number of columns of the cell array 110 can depend on the size of the cell array 110. For example, with a bit size of 32 kilo, the cell array 110 can contain 256 rows and 128 columns.

[0017] For example, and how in Fig. As shown in Figure 2, the first row of cell arrangement 119 contains a first plurality of cells designated 202a1, 202a2, ..., 202an. Each row continues to the m-th row of cell arrangement 110, which contains the first plurality of cells designated 202m1, 202m2, ..., and 202mn. Similarly, the first column of cell arrangement 110 contains a second plurality of cells designated 202a1, ..., 202m1. Furthermore, the second column of the cell arrangement contains the second plurality of cells designated 202a2, ..., 202m2. Each column continues to the n-th column, which contains the second plurality of cells designated 202an, ..., and 202mn.

[0018] Each of the first multiple cells in the first row is associated with a word line, designated WL1. Each row can be continued with the m-th row, where each of the first multiple cells is associated with a word line designated WLm. The word lines WL1, ..., WLm control access to the respective cells. For example, WL1 controls access to cells 202a1, 202a2, 202a2, ..., and 202an. That is, to write data to or read data from cells 202a1, 202a2, 202a2, ..., and 202an, WL1 is loaded to a logical 1. To store data in cells 202a1, 202a2, 202a2, ..., and 202an, WL1 is loaded to a logical 0.

[0019] We'll stick with it Fig. 2. The second plurality of cells in each column of cell arrangement 110 is connected to a bit pair. For example, the second plurality of cells in the first column, designated 2a1, ..., 2m1, is connected to a first bit pair (that is, a first bit line BLo and a second bit line BLBo). Likewise, the second plurality of cells in the second column, designated 2a2, ..., 2m2, is connected to a second bit pair (that is, a first bit line BL1 and a second bit line BLB1). And each column can be continued to the nth column, with the second plurality of cells, designated 202an, ..., and 202mn, being connected to an nth bit pair (that is, a first bit line BLn and a second bit line BLBn). In exemplary embodiments, each of the second bit lines BLBo, BLB1, ..., BLBn is connected to a corresponding first line BLBo, BLB1, ...BLBn are complementary bit line pairs. The bit line pairs are used to read or write data to or from a cell.

[0020] The word lines WL1, ..., WLm are connected to the gates of the pair of access transistors of the corresponding cells. Therefore, when a word line is activated and loaded to a logic 1 (that is, loaded to the first predetermined potential), the respective cells are connected to a single bit line of the bit line pair. The corresponding cells are then accessed by comparing a potential difference between the bit lines of the bit line pair.

[0021] In some implementations, power gating and voltage conservation techniques are implemented in the memory array to reduce power consumption. For example, power gates can be used to turn off memory peripherals in a deep sleep mode, and both the peripherals and the memory array are in a shutdown mode. An SRAM may retain some of its stored bit values ​​when it exits power-down or shutdown mode. This can pose a security risk, as the contents could be read by malicious programs. Furthermore, some applications need to start an SRAM with all bit values ​​set to zero. For example, an application might need to start with an empty SRAM and set individual bits. SRAMs typically do not provide a way to reset their contents to zero upon shutdown.One way to reset the contents is to write zero to each corresponding address of the SRAM per cycle. For example, erasing an SRAM with 1024 addresses might require 1024 cycles. If there are multiple SRAM blocks, each block might need to be erased. Consequently, it could take too long (i.e., too many cycles) to erase all SRAM blocks. According to aspects of the present disclosure, a reset circuit is included to erase SRAM blocks efficiently and quickly.

[0022] Fig. Figure 3A is a partial block diagram and a partial circuit diagram illustrating the storage device 100 with a reset circuit, for example, the reset circuit 180, according to some embodiments. The reset circuit 180 may, in some examples, include a reset signal generator circuit 302, several bias circuits 304 (for example, a first bias circuit 304a, a second bias circuit 304b, ..., an nth bias circuit 304n), and several recovery circuits (that is, a first recovery circuit 308a, ..., an mth recovery circuit 308m). Other embodiments and components of the reset circuit 180 are also within the scope of this disclosure. For example, and as shown in Fig. As shown in Figure 3A, the storage device 100 contains a reset signal generator circuit 302 and several bias circuits 304, namely a first bias circuit 304a, a second bias circuit 304b, ..., and an nth bias circuit 304n. Each of the several bias circuits 304 is assigned to a column of the storage device 100. For example, the first bias circuit 304a is assigned to the first column, the second bias circuit 304b is assigned to the second column, and so on up to the nth bias circuit 304n, which is assigned to the nth column.

[0023] In exemplary embodiments, the reset signal generator circuit 302 is configured to generate a reset signal, also known as the Clear All (or CLRall) signal. As shown in Fig. As shown in Figure 3A, the reset signal generator circuit 302 implements a logic disjunction of the SD signal and the RDY signal. For example, the signal generator circuit 302 includes an OR logic gate 306. The SD signal is fed into a first input of the OR logic gate 306, and the RDY signal is fed into a second input of the OR logic gate 306. The CLRall signal is received at the output of the OR logic gate 306. Thus, if both the SD signal and the RDY signal are logic low, the CLRall signal is also logic low. If either the SD signal or the RDY signal is logic high, the CLRall signal is also logic high.

[0024] Each of the multiple bias circuits 304 is configured to set the bit pairs of the associated column to a desired signal level. For example, the multiple bias circuits 304 are configured to set the first bit lines BLo, BL1, ..., BLn of the associated bit pair to a logic low and the second bit lines BLBo, BLB1, ..., BLBn of the associated bit pair to a logic high.

[0025] In exemplary embodiments, each of the multiple bias circuits 304 can contain multiple transistors and an inverter. For example, the first bias circuit 304a contains a first transistor 312a1, a second transistor 312a2, and an inverter 312a3. Likewise, the second bias circuit 304b contains a first transistor 312b1, a second transistor 312b2, and an inverter 312b3, and so on up to the nth bias circuit 304n, which contains a first transistor 312n1, a second transistor 312n2, and an inverter 312n3. The first transistors 312a1, 312b1, ..., 312n1 of the multiple bias circuits 304 are also called pull-down transistors and can contain NMOS transistors. However, other types of transistors are also within the scope of the disclosure. The second transistors 312a2, 312b2, ...The 312n2 of the multiple bias circuits 304 are also called pull-up transistors and may contain PMOS transistors. However, other types of transistors are also within the scope of the disclosure. The inverters 312a3, 312b3, ..., 312n3 of the multiple bias circuits 304 may contain NOT logic gates. However, other types of logic gates are also within the scope of the disclosure.

[0026] A source / drain of each of the first transistors 312a1, 312b1, ..., 312n1 of the multiple bias circuits 304 is connected to one of the first bit lines BLo, BL1, ..., BLn of a corresponding column. Additionally, a drain / source of each of the first transistors 312a1, 312b1, ..., 312n1 of the multiple bias circuits 304 is connected to a second potential (i.e., ground). A gate of each of the first transistors 312a1, 312b1, ..., 312n1 of the multiple bias circuits 304 is connected to an output of a corresponding inverter 312a3, 312b3, ..., 312n3 of the multiple bias circuits 304.

[0027] A source / drain of each of the second transistors 312a2, 312b2, ..., 312n2 of the multiple bias circuits 304 is connected to one of the second bit lines BLBo, BLB1, ..., BLBn of a corresponding column. Additionally, a drain / source of each of the second transistors 312a2, 312b2, ..., 312n2 of the multiple bias circuits 304 is connected to a first potential (i.e., VCC). A gate of each of the second transistors 312a2, 312b2, ..., 312n2 of the multiple bias circuits 304 is connected to the output of the reset signal generator circuit 302. Furthermore, the output of the reset signal generator circuit 302 is connected to the gates of each of the first transistors 312a1, 312b1, ..., 312n1 and to an input of each of the inverters 312a3, 312b3, ..., 312n3.

[0028] The second transistors 312a2, 312b2, ..., 312n2 are configured to load the second bit line of each of the multiple columns of cell array 110 to a logic high when the CLRall signal is at a logic low. The inverters 312a3, 312b3, ..., 312n3 are configured to invert the CLRall signal and feed the inverted CLRall signal into a corresponding first transistor 312a1, 312b1, ..., 312n1. The inverted CLRall signal causes the first bit line of each of the multiple columns of cell array 110 to be loaded to a logic low when the CLRall signal is at a logic low.

[0029] Furthermore, the output of the reset signal generator circuit 302 is connected via several recovery circuits to each of the word lines WL1, ..., WLm of the cell arrangement 110. For example, the output of the reset signal generator circuit 302 is connected via a first recovery circuit 308a to the first word line WL1, which continues to the m-th word line WLm, which is connected via the m-th recovery circuit 308m to the output of the reset signal generator circuit 302.

[0030] Each of the multiple recovery circuits 308a, ..., 308m is configured to load a corresponding word line WL1, ..., WLm of cell array 110 to a logic high when triggered by the CLRall signal. Each of the multiple recovery circuits 308a, ..., 308m contains a first logic gate and a second logic gate. For example, the first recovery circuit 308a contains a first logic gate (that is, a NOT logic gate 314a) and a second logic gate (that is, a NAND logic gate 310a), and so on up to the m-th recovery circuit 308m, which contains a first logic gate (that is, a NOT logic gate 314m) and a second logic gate (that is, a NAND logic gate 310m). One input of each of the NOT logic gates 314a, ..., 314m is connected to a corresponding output of the decoder circuit 120. One output of each of the NOT logic gates 314a, ...314m is connected to the first input of a corresponding NAND logic gate 31oa, ..., 310m. The output of the reset signal generator circuit 302 is connected to the second input of each of the NAND logic gates 310a, ..., 310m. An output of each of the NAND logic gates 310a, ..., 310m is connected to a corresponding word line WL1, ..., WLm.

[0031] The output of the reset signal generator circuit 302 is connected to the gates of each of the second transistors 312a2, 312b2, ..., 312n2 of the multiple bias circuits 304. Furthermore, the output of the reset signal generator circuit 302 is connected to an input of each of the inverters 312a3, 312b3, ..., 312n3 of the multiple bias circuits 304. Each inverter 312a3, 312b3, ..., 312n3 is configured to invert the CLRall signal. An output of each inverter 312a3, 312b3, ..., 312n3 is connected to a gate of a corresponding second transistor 312a2, 312b2, ..., 312n2. In addition, the inverted CLRall signal is applied to the second transistors 312a2, 312b2, 312b2, ..., 312n2 of the several bias circuits 304.

[0032] During operation, each of the multiple recovery circuits 308a, ..., 308m is configured to load a corresponding word line WL1, ..., WLm to a logic high when both a signal from decoder 120 and the CLRall signal on the corresponding word line WL1, ..., WLm are at a logic low. For example, if the output of decoder 120 is at a logic low and the CLRall signal is also at a logic low, then the output of each of the multiple recovery circuits 308a, ..., 308m is at a logic high, thereby loading each of the word lines WL1, ..., WLm to a logic high. In addition, each of the multiple bias circuits 404 is configured to load first bit lines BLo, BL1, ..., BLn to a logic low and to load second bit lines BLBo, BLB1, ..., BLBn to a logic high when the CLRall signal is at a logic low.By loading each of the word lines WL1, ..., WLm to a logical high, a bit value of zero is forcibly written in parallel to each of the multiple cells of cell array 110 by loading the first bit lines BLo, BL1, ..., BLn to a logical low and the second bit lines BLBo, BLB1, ..., BLBn to a logical high. That is, for the "reset" operation, a first node (i.e., a Q-node) of a cross-coupled inverter of each of the multiple cells is set to a bit value of 0, and a complementary second node (i.e., a Q-node) of the cross-coupled inverter of each of the multiple cells is set to a bit value of 1.

[0033] In exemplary embodiments, the cell array 110 of the storage device 100 can be reset by writing a bit value of one to each of the multiple cells. Such a reset is also called a setting operation, since each of the multiple cells is overwritten or "set" with a bit value of one. In exemplary embodiments, a bit value of one can be written to each of the multiple cells by loading the first bit lines BLo, BL1, ..., BLn to a logic high and loading the second bit lines BlBo, BLB1, ..., BLBn to a logic low. For example, for the "setting" operation, a first node (that is, a Q node) of the cross-coupled inverter of each of the multiple cells is set to a bit value of 1, and a complementary second node (that is, a Q node) of the cross-coupled inverter of each of the multiple cells is set to a bit value of 0.

[0034] Fig. Figure 3B illustrates the memory device 100 with a different reset circuit configured to reset the cell array 110 by writing a bit value of one to each of the multiple cells. The reset circuit 180 of the memory device 100 of Fig. 3B contains a reset signal generator circuit 302 and several bias circuits 320, namely a first bias circuit 320a, a second bias circuit 320b, ..., and an nth bias circuit 320n. Each of the several bias circuits 320 is assigned to a column of the storage device 100. For example, the first bias circuit 320a is assigned to the first column, the second bias circuit 320b is assigned to the second column, and so on up to the nth bias circuit 320n, which is assigned to the nth column. The multiple bias circuits 320 are set up to set the first bit lines BLo, BL1, ..., BLn of the associated bit line pair to a logical low and the second bit lines BLBo, BLB1, ..., BLBn of the associated bit line pair to a logical high.

[0035] In exemplary embodiments, each of the multiple bias circuits 320 can contain multiple transistors and an inverter. For example, the first bias circuit 320a contains a first transistor 322a1, a second transistor 322a2, and an inverter 322a3. Likewise, the second bias circuit 320b contains a first transistor 322b1, a second transistor 322b2, and an inverter 322b3, and so on up to the nth bias circuit 320n, which contains a first transistor 322n1, a second transistor 322n2, and an inverter 322n3. The first transistors 322a1, 322b1, ..., 322n1 of the multiple bias circuits 320 are also called pull-up transistors and can contain PMOS transistors. However, other types of transistors are also within the scope of the disclosure. The second transistors 322a2, 322b2, ...The 322n2 of the multiple bias circuits 320 are also called pull-down transistors and may contain NMOS transistors. However, other types of transistors are also within the scope of the disclosure. The inverters 322a3, 322b3, ..., 322n3 of the multiple bias circuits 320 may contain NOT logic gates. However, other types of logic gates are also within the scope of the disclosure.

[0036] A source / drain of each of the first transistors 322a1, 322b1, ..., 322n1 of the multiple bias circuits 320 is connected to one of the first bit lines BLo, BL1, ..., BLn of a corresponding column. Additionally, a drain / source of each of the first transistors 322a1, 322b1, ..., 322n1 of the multiple bias circuits 320 is connected to a first potential (i.e., VDD). A gate of each of the first transistors 322a1, 322b1, ..., 322n1 of the multiple bias circuits 320 is connected to an input of a corresponding inverter 322a3, 322b3, ..., 322n3 of the multiple bias circuits 320. Furthermore, a gate of each of the first transistors 322a1, 322b1, ..., 322n1 of the several bias circuits 320 is connected to the output of the reset signal generator circuit 302. In addition, the output of the reset signal generator circuit 302 is connected to an input of each of the inverters 322a3, 322b3, ..., 322n3 connected.

[0037] A source / drain of each of the second transistors 322a2, 322b2, ..., 322n2 of the multiple bias circuits 320 is connected to one of the second bit lines BLBo, BLB1, ..., BLBn of a corresponding column. Additionally, a drain / source of each of the second transistors 322a2, 322b2, ..., 322n2 of the multiple bias circuits 320 is connected to a second potential (i.e., ground). A gate of each of the second transistors 322a2, 322b2, ..., 322n2 is connected to an output of each of the inverters 322a3, 322b3, ..., 322n3.

[0038] The first transistors 322a1, 322b1, ..., 322n1 are configured to load the first bit line of each of the multiple columns of the cell array 110 to a logic high in response to a reset signal (also called the SETall signal for the setting operation) that is at a logic low. The inverters 322a3, 322b3, ..., 322n3 are configured to invert the SETall signal and apply the inverted SETall signal to a gate of a corresponding second transistor 322a2, 322b2, ..., 322n2. The inverted SETall signal causes the second bit line of each of the multiple columns of the cell array 110 to be loaded to a logic high when the SETall signal is at a logic low.

[0039] During operation, the reset signal generator circuit 302 is configured to generate the SETall signal, which is at a logic low when both the SD signal and the RDY signal are at a logic low. Each of the multiple recovery circuits 308a, ..., 308m is configured to load a corresponding word line WL1, ..., WLm to a logic high when both a signal from decoder 120 and the SETall signal for one of the word lines WL1, ..., WLm are at a logic low. Furthermore, each of the multiple bias circuits 320 is configured to load first bit lines BLo, BL1, ..., BLn to a logic high and second bit lines BLBo, BLB1, ..., BLBn to a logic low when the SETall signal is at a logic low. By loading each of the word lines WL1, ...When WLm is set to a logical high, a bit value of one is forcibly written in parallel to each of the multiple cells of cell array 110 by setting the first bit lines BLo, BL1, ..., BLn to a logical high and the second bit lines BLBo, BLB1, ..., BLBn to a logical low. That is, for the "setting" operation, the first node (i.e., the Q node) of the cross-coupled inverter of each of the multiple cells is set to a bit value of 1, and the complementary second node (i.e., the Q node) of the cross-coupled inverter of each of the multiple cells is set to a bit value of 0.

[0040] In Fig. 3B Each memory cell of cell array 110 can be written to a logical low value or "reset" by writing a bit value of zero to each of the multiple cells. In exemplary embodiments, a bit value of zero can be written to each of the multiple cells by loading the first bit lines BLo, BL1, ..., BLn to a logical low and loading the second bit lines BlBo, BLB1, ..., BLBn to a logical high. That is, for the "reset" operation, the first node (i.e., the Q node) of the cross-coupled inverter of each of the multiple cells is set to a bit value of 0, and the complementary second node (i.e., the Q node) of the cross-coupled inverter of each of the multiple cells is set to a bit value of 1.

[0041] In exemplary embodiments, if the number of multiple cells in cell arrangement 110 exceeds a predetermined number, the multiple cells are segmented into subblocks for reset. For example, if the number of multiple cells in cell arrangement 110 exceeds 64k, the multiple cells are segmented into more than one subblock, each subblock containing a maximum of 64k cells. Furthermore, if the number of columns exceeds a predetermined number, the multiple cells are subdivided into multiple subblocks, each containing no more than the predetermined number of columns. Similarly, if the number of rows exceeds a predetermined number, the multiple cells are subdivided into multiple subblocks, each containing no more than the predetermined number of rows.

[0042] Fig. Figure 3C illustrates an exemplary storage device with multiple subblocks according to some embodiments. As in Fig. As shown in Figure 3C, the storage device 100 contains multiple subblocks (350a, ..., 350n). Each of the multiple subblocks can contain up to a predetermined number of cells, columns, or rows. The multiple cells in the subblocks are reset by means of a corresponding (that is, a dedicated) reset circuit (designated as 180a, ..., 180n). For example, the multiple cells of a first subblock 350a are reset using a first reset circuit 180a, which propagates to multiple cells of an nth subblock 350n, which is reset using an nth reset circuit 180n. In exemplary embodiments, a finite state machine 360 ​​is provided to coordinate the reset of multiple subblocks 350a, ..., 350n.For example, the finite state machine 360 ​​can determine that several cells of the first subblock 350a have been reset and triggers the resetting of the next subblock, continuing this process up to the nth subblock 350n. In other examples, the finite state machine 360 ​​is implemented as a counter that is incremented by 1 after each subblock is reset, until a total number of subblocks of cell array 110 of storage device 100 have been counted.

[0043] Fig. Figure 4 illustrates a timing diagram 400 for the storage device 100 according to some embodiments. Fig. Figure 4 illustrates, for example, timing diagrams of the SD signal (labeled 404), the RDY signal (labeled 406), and the CLRall signal (labeled 408). As shown in timing diagram 400, the SD signal is logical high during a shutdown period (labeled 410). During the shutdown period, there is no power supply to the storage device 100. Furthermore, the RDY signal is logical low during the shutdown period, indicating that the storage device 100 is not accessible.

[0044] The shutdown period ends when the DSLP signal changes from a logic high to a logic low. This change triggers the power-on of the peripheral components of the storage device 100. For example, the DSLP signal changing to a logic low triggers the power-on of the decoder circuit 120, the local input / output (I / O) circuit 130, the local control circuit 140, the global I / O circuit 150, the global control circuit 160, the power control circuit 170, and the reset circuit 180.

[0045] After an initial predetermined period, starting from the moment the DSLP signal transitions to a logic low, the SD signal also transitions from a logic high to a logic low. The transition of the SD signal from a logic high to a logic low also marks the beginning of a power-on period (designated as 412). The initial predetermined period between the transitions of the DSLP and SD signals is defined as sufficient to power on the peripheral component of the storage device 100. The transition of the SD signal to a logic low triggers the power-on of the cell array 110 of the storage device 100.

[0046] Furthermore, and as in Fig. As shown in Figure 4, the SD signal changes to a logic low at the end of the power-on process (or at the end of the power-off process), causing the CLRall signal to change from a logic high to a logic low. When the CLRall signal changes to a logic low, it triggers a reset of the multiple cells of cell array 110 to a predetermined bit value. The CLRall signal remains logic low for the power-on duration. The power-on duration is defined as the time sufficient to reset each of the multiple cells of cell array 110 to a predetermined bit value. At the end of the power-on duration, the RDY signal changes from a logic low to a logic high, indicating that the storage device 100 is ready for access. The change in the RDY signal causes the CLRall signal to switch to a logic high, thereby activating the first transistors 412a1, 412b1, ..., 412n1 and the second transistors 412a2, 412b2, ..., 412n2 will be switched off.

[0047] Fig.Figure 5 is a flowchart of a method 500 for resetting a memory device according to some embodiments. Steps of the method 500 can be stored as instructions that can be executed by a processor to implement the method 500. In block 510 of the method 500, a reset signal is generated as a logical disjunction of a first signal (that is, the SD signal), which indicates the initiation of a multi-cell on-duty period, and a second signal (that is, the RDY signal), which indicates the termination of the multi-cell on-duty period of the memory device 100.The multiple cells of the storage device 100 are arranged in a matrix of multiple rows and multiple columns, each of the multiple columns comprising a first plurality of cells, each of the first plurality of cells being connected to a first bit line and a second bit line, and each of the multiple rows comprising a second plurality of cells, each of the second plurality of cells of a row being connected to one of multiple word lines.

[0048] In block 520 of procedure 500, several first transistors (designated 312a1, 312b1, ..., 312n1) are triggered to load the first bit line of each of the several columns to a first predetermined potential, with each of the several first transistors (designated 312a1, 312b1, ..., 312n1) being connected to the first bit line of the respective of the several columns. In block 530 of procedure 500, several second transistors (designated 312a2, 312b2, ..., 312n2) are triggered to load a second bit line of the respective of the several columns to a second predetermined potential, with each of the several second transistors (designated 312a2, 312b2, ..., 312n2) being connected to the second bit line of the respective of the several columns. In block 540 of procedure 500, several recovery circuits (designated 308a, ..., 308m) are triggered to restore the several word lines (designated WL1, ...to charge ( , WLm) to a third predetermined potential, wherein each of the multiple recovery circuits (designated as 308a, ..., 308m) is connected to one of the multiple word lines (designated as WL1, ..., WLm).

[0049] According to one embodiment, a storage device comprises: a cell arrangement comprising multiple cells, each of the multiple cells being configured to store a bit value; and a reset circuit connected to the cell arrangement, the reset circuit being configured to reset the bit value stored in each of the multiple cells in parallel to a predetermined bit value, the reset circuit comprising a reset signal generator circuit being configured to generate a reset signal, the reset signal being configured to trigger a parallel reset of the bit value stored in each of the multiple cells to the predetermined bit value, the feature that the reset signal generator circuit is configured to generate the reset signal includes that the reset signal generator circuit is configured toto establish a logical disjunction between a first signal and a second signal, wherein the first signal indicates the initiation of an on-time of the multiple cells, and a second signal indicates the termination of the on-time of the multiple cells, wherein the reset signal generator circuit comprises an OR logic gate.

[0050] In one embodiment, a storage device comprises: a cell arrangement comprising multiple cells, each of the multiple cells being configured to store a single bit value; a power control circuit being configured to generate a first signal indicating the initiation of an on-time of the multiple cells, and a second signal indicating the termination of the on-time of the multiple cells; and a reset circuit being configured to reset the bit value stored in each of the multiple cells in parallel to a predetermined bit value during the on-time, the reset circuit comprising a reset signal generator circuit being configured to generate a reset signal, the reset signal generator circuit comprising an OR logic gate.

[0051] According to exemplary embodiments, a method for resetting a storage device comprises: generating a reset signal as a logical disjunction of a first signal indicating the initiation of a multi-cell power-on period and a second signal indicating the termination of the multi-cell power-on period of a storage device; and triggering, by means of the reset signal, a parallel reset of a bit value stored in each of the multi-cells of a cell array of a storage device to a predetermined bit value during the power-on period, wherein the reset signal is generated by a reset signal generator circuit, the reset signal generator circuit comprising an OR logic gate.

[0052] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure.

Claims

[1] comprising storage device (100): a cell arrangement (110) comprising several cells (202), each of the several cells (202) being configured to store a bit value; and a reset circuit (180) connected to the cell arrangement (110), wherein the reset circuit (180) is configured to simultaneously reset the bit value stored in each of the multiple cells (202) to a predetermined bit value; wherein the reset circuit (180) comprises a reset signal generator circuit (302) configured to generate a reset signal, wherein the reset signal is set up to trigger a parallel reset of the bit value stored in each of the multiple cells (202) to the specified bit value, wherein the feature that the reset signal generator circuit (302) is configured to generate the reset signal includes that the reset signal generator circuit (302) is configured to detect a logical disjunction between a first signal and a second signal, where the first signal indicates the initiation of a switch-on period for the multiple cells, and a second signal indicates the termination of the switch-on period for the multiple cells, wherein the reset signal generator circuit (302) includes an OR logic gate (306). [2] Storage device (100) according to claim 1, where the multiple cells are arranged in a matrix of multiple rows and multiple columns, where each of the multiple columns comprises a first plurality of cells, wherein each of the first plurality of cells is connected by a first bit line (BLn) and a second bit line (BLBn), where each of the multiple rows comprises a second plurality of cells, where each of the second plural cells of a row is connected to a word line (WLm). [3] Storage device (100) according to claim 2, wherein the feature that the reset circuit (180) is configured to reset each of the multiple cells to the predetermined value comprises that the reset circuit (180) is configured to load the first bit line (BLn) of each of the multiple columns to a first predetermined potential, to load the second bit line (BLBn) of each of the multiple columns to a second predetermined potential, and to load the word line (WLm) of each of the multiple rows to a third predetermined potential. [4] Storage device (100) according to claim 1, wherein the reset circuit (180) further comprises several bias circuits (304) and several recovery circuits (308), wherein the feature that the reset signal is set up to trigger the simultaneous resetting of the bit value stored in each of the multiple cells (202) to the specified bit value includes that the reset signal is set up to: - Triggering each of the multiple bias circuits (304) to load the first bit line (BLn) of each of the multiple columns to the first predetermined potential and to load the second bit line (BLBn) of each of the multiple columns to the second predetermined potential; and - Triggering the multiple recovery circuits (308) to load the word line (WLm) of each of the multiple rows to a third predetermined potential. [5] Storage device (100) according to claim 4, wherein each of the multiple bias circuits (304) has a first transistor (312n1) configured to load the first bit line (BLn) of the corresponding column of the multiple columns to the first predetermined potential, and a second transistor (312n2) configured to load the second bit line (BLBn) of the corresponding column of the multiple columns to the second predetermined potential. [6] Storage device (100) according to claim 4 or 5, wherein each of the multiple recovery circuits (308) has an inverter (312n3) and a NAND logic gate (310m), wherein an input of the NAND gate (310m) is connected to a respective output of a decoder circuit (120), wherein an output of the inverter (312n3) is connected to a first input of the NAND gate (310m), where the reset signal is fed into a second input, where one output of the NAND gate (310m) is connected to the word line (WLm). [7] comprising storage device (100): a cell arrangement (110) comprising multiple cells, each of the multiple cells being configured to store a single bit value; an energy control circuit (170) configured to generate a first signal indicating the initiation of a duty cycle of the multiple cells, and to generate a second signal indicating the termination of the duty cycle of the multiple cells; and a reset circuit (180) configured to simultaneously reset the bit value stored in each cell of the multiple cells to a predetermined bit value during the power-on time; wherein the reset circuit (180) comprises a reset signal generator circuit (302) configured to generate a reset signal, wherein the reset signal generator circuit (302) includes an OR logic gate (306). [8] Storage device (100) according to claim 7, wherein the reset circuit (180) is configured to generate a third signal, wherein the third signal is set up to trigger the resetting of the bit value stored in each cell of the multiple cells to the specified bit value during the power-on period. [9] Storage device (100) according to claim 8, wherein the reset circuit (180) is configured to generate the third signal as a logical disjunction of the first signal and the second signal. [10] Storage device (100) according to any one of the preceding claims 7 to 9, wherein the feature that the reset circuit (180) is configured to reset the bit value stored in each of the multiple cells to the predetermined bit value during the power-on time comprises that the reset circuit (180) is configured to: - Determine that the number of cells in a set is greater than a specified number; and - Dividing the multiple cells into a first sub-block and a second sub-block. [11] Storage device (100) according to claim 10, wherein the reset circuit (180) is configured to: - parallel reset of an initial plurality of cells in the first subblock; and - parallel reset of a second plurality of cells in the second subblock. [12] Storage device (100) according to claim 10 or 11, wherein the reset circuit (180) further comprises a finite state machine (360) configured to indicate a status of resetting the first plurality of cells in the first subblock and resetting the second plurality of cells in the second subblock. [13] Storage device (100) according to any one of the preceding claims 7 to 12, wherein the feature that reset circuit (180) is configured to reset the bit value stored in each of the multiple cells to the predetermined bit value during the power-on time comprises that the reset circuit (180) is configured to reset the bit value stored in each of the multiple cells to a bit value of zero during the power-on time. [14] Storage device (100) according to any one of the preceding claims 7 to 13, wherein the energy control circuit (170) is configured to generate a fourth signal before the first signal, wherein the fourth signal is configured to switch on several peripheral components of the storage device (100). [15] Method for resetting a storage device (100), comprising: Generating a reset signal as a logical disjunction of a first signal indicating the initiation of a multi-cell on-time and a second signal indicating the termination of the multi-cell on-time of a storage device (100); and by means of the reset signal, triggering a simultaneous reset of a bit value stored in each cell of the multiple cells of a cell arrangement (110) of a storage device (100) to a predetermined bit value during the on-time, wherein the reset signal is generated by a reset signal generator circuit (302), wherein the reset signal generator circuit (302) comprises an OR logic gate (306). [16] Method according to claim 15, wherein the triggering of the parallel reset of the bit value stored in each of the multiple cells of the cell arrangement (110) of the storage device (100) to the predetermined bit value during the switch-on period by means of the reset signal comprises: by the reset signal, triggering the parallel reset of a bit value stored in each of the multiple cells of a cell arrangement (110) of the storage device (100) to the predetermined bit value during the on-time, where the multiple cells are arranged in a matrix of multiple rows and multiple columns, where each of the multiple columns comprises a first plurality of cells (202), wherein each of the first plurality of cells (202) is connected to a first bit line (BLn) and a second bit line (BLBn), wherein each of the multiple rows comprises a second plurality of cells (202), wherein each of the second plurality of cells (202) of a row is connected to one of the multiple word lines (WLm). [17] Method according to claim 16, wherein the triggering of a parallel reset of a bit value stored in each of the multiple cells (202) of a cell arrangement (110) of a storage device (100) to a predetermined bit value during the power-on time by means of the reset signal comprises: Triggering several first transistors (312n1) to charge the first bit line (BLn) of each of the several columns to a first predetermined potential, wherein each of the several first transistors (312n1) is connected to the first bit line (BLn) of the respective of the several columns; Triggering several second transistors (312n2) to charge a second bit line (BLBn) of each of the several columns to a second predetermined potential, wherein each of the several second transistors (312n2) is connected to the second bit line (BLBn) of the respective of the several columns; and Triggering multiple recovery circuits (308) to charge the multiple word lines (WLm) to a third predetermined potential, each of the multiple recovery circuits (308) being connected to one of the multiple word lines (WLm).

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