Improved contacting of metal conductors in case of misalignment of BEOL vias

Abstract

Exhibiting a semiconductor structure: a first conductive line (112A) and a second conductive line (112B) in a first dielectric layer (110), wherein the first conductive line (112A) and the second conductive line (112B) extend along a first direction; a third conductive line (132) in a second dielectric layer (130) located above the first dielectric layer (110), wherein the third conductive line (132) extends along a second direction different from the first direction and over at least the first conductive line (112A) and the second conductive line (112B); a via (134) in the second dielectric layer (130) that electrically connects the second conductive line (112B) and the third conductive line (132), wherein the via (134) terminates at a section of the second conductive line (112B); and a dielectric cover (121) over the first conductive line (112A), wherein a lower surface of the dielectric cover (121) lies below an upper surface of the first dielectric layer (110), wherein the section of the second conductive line (112B) in which the via (134) terminates has an upper surface which lies above an upper surface of a section of the first conductive line (112A) under the dielectric cover (121) and which is coplanar with an upper surface of the dielectric cover (121).

Description

TECHNICAL BACKGROUND

[0001] Integrated circuits comprise numerous devices such as transistors, diodes, capacitors, and resistors, which are fabricated on and / or embedded in a semiconductor substrate. These devices are initially isolated from one another and later interconnected to form functional circuits in the back-end-of-line (BEOL) processing stage. As the components in integrated circuits become increasingly smaller, the impact of interconnect structures on the performance and reliability of the integrated circuits increases.

[0002] According to document US 2014 / 0342549A1, a stack consisting of a first metal conductor and a first dielectric cap material portion is formed within a conduction trench of the first dielectric material layer. A second layer of dielectric material is then formed. A conduction trench extending between the top and bottom surfaces of the second dielectric material layer is patterned. A photoresist layer is applied to the second dielectric material layer and a via pattern is applied. An underlying portion of the first dielectric cap material is removed by selectively etching the dielectric materials of the first and second dielectric material layers to form a through-hole that is bounded laterally along the width of the conduction trench and along the width of the first metal conductor.

[0003] Earlier application DE 11 2018 007 152 T5 describes etch-stop-layer-based methods for fabricating a through-hole plating. In particular, an integrated circuit structure has several conductive lines in an ILD layer, each of the several conductive lines having a ground part comprising a metal and a top surface comprising the metal and a non-metal.

[0004] Document US 2017 / 0186849A1 describes a semiconductor device containing a first gate structure mounted on a substrate and extending in a first direction. A first protective layer has a Pi (π) shape with a head and two legs in a cross-section along a second direction perpendicular to the first.

[0005] Document US 2014 / 0264902A1 relates to a semiconductor structure and a method for manufacturing a semiconductor structure in which a spacer element is formed next to a metal body embedded in a first dielectric layer of a first compound layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following detailed description is best understood in conjunction with the accompanying drawings. It should be noted that, according to industry practice, the various features in the drawings are not necessarily shown to scale. Rather, the dimensions and spatial relationships of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Reference symbols denote identical features throughout the description and drawings. Fig. Figure 1A is a top view of a semiconductor circuit structure according to some embodiments. Fig. 1B is a cross-sectional view of the semiconductor structure made of Fig. 1A along line B-B'. Fig. Figure 2 is a flowchart of a process for manufacturing a semiconductor structure according to some embodiments. Fig. Figure 3 is a cross-sectional view of an initial structure of a semiconductor structure comprising a substrate and several conductive lines at a lower level in a first dielectric layer above the substrate, according to some embodiments. Fig. Figure 4 is a cross-sectional view of the semiconductor structure. Fig. 3 after forming a structured photoresist layer to expose a non-via end section of each of a first lower-level conductive line and a third lower-level conductive line on opposite sides of a second lower-level conductive line according to some embodiments. Fig. Figure 5 is a cross-sectional view of the semiconductor structure. Fig. 4 after cutting out the non-via end sections of the first and third conductive lines of the lower plane to form cutouts according to some embodiments. Fig. Figure 6 is a cross-sectional view of the semiconductor structure. Fig. 5 after the deposition of a dielectric covering layer to fill the cutouts according to some embodiments. Fig. Figure 7 is a cross-sectional view of the semiconductor structure. Fig. 6 after forming dielectric covers in the cutouts according to some embodiments. Fig. Figure 8 is a cross-sectional view of the semiconductor structure made of Fig. 7 after forming an etch stop layer over the first dielectric layer, the several conductive lines of the lower level and the dielectric covers according to some embodiments. Fig. Figure 9 is a cross-sectional view of the semiconductor structure made of Fig. 8 after forming a second dielectric layer over the etch stop layer according to some embodiments. Fig. Figure 10 shows a cross-sectional view of the semiconductor structure. Fig. 9 after forming a trench and a via opening in the second dielectric layer and the etch stop layer to expose a via end section of the second conductive line of the lower level according to some embodiments. Fig. Figure 11 is a cross-sectional view of the semiconductor structure made of Fig. 10 after forming a conductive line of the upper level and a via in the trench or via opening according to some embodiments. Fig. Figure 12 is a cross-sectional view of a semiconductor structure that has the same structure as the semiconductor structure from Fig. 6, according to some embodiments. Fig. Figure 13 shows a cross-sectional view of the semiconductor structure. Fig. 12 after forming a second dielectric layer over the dielectric cover layer according to some embodiments. Fig. Figure 14 shows a cross-sectional view of the semiconductor structure. Fig. 13 after forming a trench and a via opening in the second dielectric layer and the dielectric cover layer to expose a via end section of the second conductive line of the lower level according to some embodiments. Fig. Figure 15 shows a cross-sectional view of the semiconductor structure. Fig. 14 after forming a conductive line of the upper level and a through-hole in the trench or through-hole according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing various functions of the presented content. Specific examples of components, values, operations, materials, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like are considered. For example, the formation of a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which further features can be formed between the first and second features, so that the first and second features do not have to be in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms such as "below," "underneath," "lower," "above," "upper," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms should encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative designators used herein may also be interpreted accordingly.

[0009] In a multilayer interconnect structure, metal conductors (e.g., copper conductors) are placed in stacked dielectric layers and connected between layers via vias. In some cases, the metal conductors and vias are fabricated using single or double damascus processes. In such processes, after forming the lower-layer metal conductors in a dielectric layer, another dielectric layer is formed and patterned over the first to create grooves and via openings. The grooves and via openings are then filled with a conductive metal to form the upper-layer metal conductors and vias, respectively. The multiple dielectric layers are patterned using lithography processes.Ideally, vias are formed to be perfectly aligned with corresponding lower-level metal conductors in an underlying dielectric layer by aligning the lithography masks. A certain amount of mask misalignment is unavoidable in lithography processes, and these superimposed defects often lead to misalignment of the vias with respect to the target metal conductors. A misaligned via sometimes results in a short circuit with an adjacent metal conductor, causing defects and reducing the reliability of integrated circuits. As semiconductor technologies have evolved toward more advanced nodes with smaller feature sizes, the spacing between adjacent metal conductors has decreased rapidly.Therefore, misalignment of a via increasingly affects the performance and reliability of integrated circuits.

[0010] This disclosure provides structures and methods to improve the via-hole plating at the metal conductor boundary in back-end-of-line (BEOL) processing. In some embodiments, a section of each lower-level conductive conductor on each side of a target lower-level conductive conductor adjacent to the misaligned via is recessed, and a dielectric cover is formed over each recessed section of the adjacent lower-level conductive conductors. The dielectric covers help extend the via to the conductor boundary, thus preventing a short circuit of the via with the adjacent lower-level conductive conductors. The dielectric covers also help reduce the parasitic conductivity of conductive conductors. As a result, the operating efficiency of the integrated circuit is improved.

[0011] Fig. Figure 1A is a top view of a semiconductor structure 100 according to some embodiments of this disclosure. Fig. 1B is a cross-sectional view of the semiconductor structure 100 from Fig. 1A along line B-B'. With reference to Fig. 1A and Fig. Figure 1B comprises the semiconductor structure 100, a substrate 102, and a multilayer interconnect structure 104 according to embodiments of this disclosure. The interconnect structure 104 is located above the substrate 102 and connects the various active and / or passive devices in the substrate 102 to form an integrated circuit. For the sake of simplicity, the interconnect structure 104 comprises two metallization layers, e.g., a first metallization layer 106 located above the substrate 102 and a second metallization layer 108 located directly above the first metallization layer 106. An ordinary person skilled in the art would understand that in some cases the interconnect structure 104 comprises more than two metallization layers, such as five, seven, or even more metallization layers in complex integrated circuits. Furthermore, although it comprises Fig. 1B The first metallization layer 106 is directly above and in contact with the substrate 102, but in some cases the intermediate structure 104 comprises one or more metallization layers arranged between the first metallization layer 106 and the substrate 102 or above the second metallization layer 108. The first metallization layer 106 is therefore an Mx-plane metallization layer, and the second metallization layer 108 is an M(x+1)-plane metallization layer.

[0012] The first metallization layer 106 comprises a first dielectric layer 110 and several lower-level conductive lines embedded in the first dielectric layer 110. For the sake of simplicity, the first metallization layer 106 comprises four conductive lines, e.g., a first lower-level conductive line 112A, a second lower-level conductive line 112B, and a third lower-level conductive line 112C. Fig. 1A), and a fourth lower-level conductive line 112D ( Fig. 1A) in the first dielectric layer 110. The second metallization layer 108 comprises a second dielectric layer 130 and several upper-level conductive lines embedded in the second dielectric layer 130. For simplicity, the second metallization layer 108 comprises a single conductive line, e.g., an upper-level conductive line 132 in the second dielectric layer 130. In some embodiments, the second dielectric layer 130 is separated from the first dielectric layer 110 by an etch stop layer 122. In some embodiments, the lower-level conductive lines 112A, 112B, 112C, and 112D extend in a Y-direction (or are oriented accordingly). The upper-level conductive line 132 extends in an X-direction. In some embodiments, the X-direction and the Y-direction are perpendicular to each other.In some embodiments, the X direction is a horizontal direction and the Y direction is a vertical direction. In some embodiments, the conductive line of the upper level 132 overlaps a section of each of the conductive lines of the lower level 112A, 112B, 112C and 112D (. Fig. 1A). In some embodiments, the upper layer conductive line 132 overlaps some of the lower layer conductive lines 112A, 112B, 112C, or 112D. In some embodiments, the electrical connection between the first metallization layer 106 and the second metallization layer 108 is made by connecting the upper layer conductive line 132 and the second lower layer conductive line 112B through a via 134. The via 134 extends through a lower portion of the second dielectric layer 130 and the etch stop layer 122, and overlaps a portion of the second lower layer conductive line 112B. The second lower layer conductive line 112B is also referred to as a lower layer conductive target line 112B.

[0013] In some embodiments, each of the lower-level conductive lines 112A, 112B, 112C, and 112D comprises a metal section 114 and a metal liner 116 surrounding the metal section 114. Similarly, the upper-level conductive line 132 and the via 134 comprise a metal section 136 and a metal liner 138 surrounding the metal section 136. Furthermore, a section of each of the first and third lower-level conductive lines 112A and 112C, adjacent to the via 134, has a cutout top surface with respect to a top surface of a section of the second lower-level conductive line 112B on which the via 134 terminates. A dielectric cover 121 is located over the cutout section of each of the first and third lower-level conductive lines 112A and 112C.The section of the second conductive line of the lower level 112B, above which the via 134 ends, is referred to herein as a via end section 117 (. Fig. 1A), while the cut-out section of each of the first and third conductive lines of the lower level 112A and 112C is referred to herein as a non-via end section 118 ( Fig. 1A). In some embodiments, the via end section 117 is at the interface of the upper level conductive line 132 and the lower level conductive destination line 112B, and the non-via end section 118 is at the interface of the upper level conductive line 132 and a corresponding lower level conductive line 112A or 112C adjacent to the lower level conductive destination line 112B.

[0014] The via 134 and the underlying lower-level conductive traces 112A, 112B, 112C, and 112D are formed in separate damascening processes, each of which includes the lithographic structuring of the corresponding first dielectric layer 110 and second dielectric layer 130. During the damascening process for forming the via opening for the via 134, a misalignment error occurs in some cases between the via opening and the lower-level conductive target trace 112B, leading to misalignment of the via 134 subsequently formed in the via opening with the lower-level conductive target trace 112B. Due to variations in the lithography conditions, the via 134 is misaligned on each side of the lower-level conductive target trace 112B. For example, the via 134 is misaligned in Fig. 1A and Fig. Via 134 is misaligned towards the right side of the lower-level conductive target line 112B. This misalignment causes the via to extend beyond the right edge of the lower-level conductive target line 112B. The misalignment of the via reduces the lateral distance between the via 134 and a lower-level conductive line adjacent to the lower-level conductive target line 112B, such as the first lower-level conductive line 112A. There is a risk that the via 134 will bridge the lower-level conductive target line 112B with the adjacent lower-level conductive line 112A, resulting in a short circuit.In some embodiments, a superposition defect also causes etching of the first dielectric layer 110 during the formation of the via opening, such that the via 134 is formed to contain a section 134A embedded in the first dielectric layer 110. Section 134A reduces the distance between the lower-level conductive target line 112B and the adjacent lower-level conductive line 112A, resulting in a current leakage. The leakage current increases over time, leading to dielectric breakdown and ultimately to failure of the integrated circuit.

[0015] By inserting a dielectric cover 121 over a non-via end section 118 of each of the adjacent conductive lines 112A and 112C of the lower level, which is adjacent to the via end section 117 of the conductive target line 112B of the lower level, when the misalignment of the via 134 occurs, the distance D1 between the via 134 and the non-via end section 118 of a corresponding adjacent conductive line of the lower level, e.g. the first conductive line 112A of the lower level, becomes larger than the corresponding distance D2 that would otherwise be formed if the non-via end section 118 of the first conductive line 112A of the lower level was not cut out and the dielectric cover 121 was not formed on it.The introduction of the dielectric covers 121 on adjacent conductive traces of the lower level 112A and 112C helps to increase the through-hole contact of the conductive trace, which in turn helps to prevent short circuits of the conductive target trace 112B of the lower level with the adjacent conductive trace 112A or 112C of the lower level. The dielectric covers 121 also help to eliminate the dielectric breakdown fault, which in turn helps to increase the reliability of the integrated circuit.

[0016] Fig. Figure 2 is a flowchart of a process 200 for manufacturing a semiconductor structure, e.g., the semiconductor structure 100 made of Fig. 1A and Fig. 1B, according to some embodiments. Fig. Figures 3 to 11 are cross-sectional views of the semiconductor structure 100 at various stages of the manufacturing process according to several embodiments. The process 200 is described in detail below with reference to the semiconductor structure 100 in Fig. Sections 3 to 11 are discussed. In some embodiments, further operations are performed before, during, and / or after the method 200, or some of the described operations are replaced and / or eliminated. In some embodiments, further features are added to the semiconductor structure 100. In some embodiments, some of the features described below are replaced or eliminated. An ordinary person skilled in the art would understand that although some embodiments are discussed in such a way that the operations are performed in a specific order, these operations can also be performed in a different logical order.

[0017] With reference to Fig. 2 and Fig. 3 includes the execution of procedure 200 and the performance of operation 202, wherein an initial structure of a semiconductor structure 100 is provided. In Fig. 3 The starting structure of the semiconductor structure 100 comprises a substrate 102. In some embodiments, the substrate 102 is a bulk semiconductor substrate comprising silicon. Alternatively or additionally, in some embodiments, the bulk semiconductor substrate comprises another elemental semiconductor such as germanium, a compound semiconductor comprising gallium arsenide, gallium, phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor comprising SiGe, GaAsP, AlNAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 may have an epitaxial layer superimposed on a bulk semiconductor substrate. Furthermore, in some embodiments, the substrate 102 is a semiconductor-on-insulator (SOI) substrate.For example, substrate 102 includes a recessed oxide (BOX) layer formed by a process such as implanted oxygen separation (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0018] In some embodiments, the substrate 102 further comprises active devices such as p-type field-effect transistors (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor (MOS) transistors, complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, and / or high-frequency transistors. In some embodiments, the transistors are planar transistors or three-dimensional fin-type transistors. In some embodiments, the substrate 102 further comprises passive devices such as resistors, capacitors, and / or inductors. The substrate 102 further comprises insulating structures such as shallow trench insulation (STI) structures for separating different active and / or passive devices from one another.

[0019] A first metallization layer 106 is formed over the substrate 102. The first metallization layer 106 comprises a first dielectric layer 110 and several lower-level conductive lines embedded in the first dielectric layer 110. For the sake of simplicity, four lower-level conductive lines are defined as a first lower-level conductive line 112A, a second lower-level conductive line 112B, a third lower-level conductive line 112C, and a fourth lower-level conductive line 112D. Fig. 3. The lower-level conductive lines 112A, 112B, 112C, and 112D are arranged in a Y-direction. In some embodiments, the Y-direction is vertical. The lower-level conductive lines 112A, 112B, 112C, and 112D are arranged in parallel and separated from each other by the first dielectric layer 110. In some embodiments, all adjacent lower-level conductive lines 112A, 112B, 112C, and 112D are spaced a minimum metal-conductor spacing permitted by the design rules according to a manufacturing process. The minimum spacing between adjacent lower-level conductive lines 112A, 112B, 112C, and 112D varies based on the technology node. In some embodiments, the distance between adjacent conductive lines of the lower plane 112A, 112B, 112C and 112D is from approximately 12 nm to approximately 32 nm.In some embodiments, each of the lower-level conductive lines 112A, 112B, 112C, and 112D comprises a metal section 114 and a metal lining 116 surrounding the metal section 114. The metal lining 116 separates the metal section 114 from the first dielectric layer 110, thus preventing metal (e.g., copper) in the metal section 114 from diffusing into the first dielectric layer 110.

[0020] In some embodiments, the first dielectric layer 110 comprises silicon oxide. In some embodiments, the first dielectric layer 110 comprises a low-k dielectric having a dielectric constant (k) of less than 4. In some embodiments, the low-k dielectric has a dielectric constant of approximately 1.2 to approximately 3.5. In some embodiments, the dielectric layer 110 comprises tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicate glass such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectrics. In some embodiments, the first dielectric layer 110 is deposited by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) or spin coating.In some embodiments, the first dielectric layer 110 is planarized by a planarization process or otherwise cut out to provide a planar top surface. In some embodiments, the top surface of the first dielectric layer 110 is planarized using a chemical-mechanical polishing (CMP) process.

[0021] The first dielectric layer 110 is subsequently structured by one or more lithography and etching processes to form trenches (not shown) within it. In some embodiments, the lithography process includes depositing a photoresist layer (not shown) over the first dielectric layer 110 to expose the photoresist layer to a structure, performing firing after exposure, and developing the resist to form a structured photoresist layer (not shown). The structured photoresist layer exposes sections of the first dielectric layer 110 in which the trenches are to be formed. Next, sections of the first dielectric layer 110 formed by the structured photoresist layer are etched to create the trenches.In some embodiments, the dielectric layer 110 is formed using a dry etching process such as reactive ion etching (RIE) or plasma etching. After the trenches have formed in the first dielectric layer 110, the structured photoresist layer is removed, for example, by wet stripping or plasma ash. Alternatively, in some embodiments, a hard mask is used, such that the trench structure is transferred from the structured photoresist layer to the hard mask by a first etching and then transferred to the first dielectric layer 110 by a second etching.

[0022] The conductive conductors of the lower level 112A, 112B, 112C, and 112D are then formed in the trenches. A first metal lining layer (not shown) is deposited on the side walls and bottoms of the trenches and on the upper surface of the first dielectric layer 110. In some embodiments, the first metal lining layer comprises a diffusion barrier material that prevents the metal in the metal section 114 from diffusing into the first dielectric layer 110. In some embodiments, the first metal lining layer comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), ruthenium nitride (RuN), or other suitable diffusion barrier materials. In some embodiments, the first metal lining layer comprises a stack of the aforementioned diffusion barrier materials, such as Ti / TiN or Ta / TaN.In some embodiments, the first metal lining layer is deposited using a conformal deposition process such as CVD, PECVD, PVD or atomic layer deposition (ALD).

[0023] A first metal layer (not shown) is subsequently deposited over the first metal lining layer to fill the trenches. In some embodiments, the first metal layer comprises copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), an alloy thereof, or other suitable conductive metals. In some embodiments, the first metal layer is deposited by a suitable deposition process, such as CVD, PECVD, sputtering, or plating. In some embodiments, particularly when Cu or a Cu alloy is used in the first metal layer, an optional plating seed layer (not shown) is formed on the first metal lining layer before the first metal layer is formed. In some embodiments, the optional plating seed layer is formed by a deposition process, including, for example, CVD, PECVD, ALD, and PVD.

[0024] Subsequently, sections of the first metal layer and the first metal lining layer located above the top surface of the first dielectric layer 110 are removed using a planarization process. In some embodiments, a CMP process is performed to remove excess diffusion barrier material and conductive metal from the top surface of the first dielectric layer 110. A remaining section of the first metal lining layer at the side walls and bottom of each trench constitutes the metal lining 116, and a remaining section of the first metal layer within each trench constitutes the metal section 114. After the CMP process, the lower-level conductive conductors 112A, 112B, 112C, and 112D each have top surfaces that are coplanar with each other and with the top surface of the first dielectric layer 110.

[0025] With reference to Fig. 2 and Fig. 4. Performing the procedure 200 includes carrying out operation 204, in which a structured photoresist layer 115 is formed over the first dielectric layer 110. The structured photoresist layer 115 exposes a non-via end section 118 of each of the first lower-level conductive line 112A and the third lower-level conductive line 112C. As used herein, a non-via end section refers to a portion of a lower-level conductive line that adjoins a portion of a lower-level conductive target line where a via terminates. The structured photoresist layer 115 is formed by a lithography process. For example, a photoresist layer (not shown) is first deposited over the first dielectric layer 110 and the lower-level conductive lines 112A, 112B, 112C, and 112D.The photoresist layer is then structured by exposing the photoresist in a structure, performing firing processes after exposure, and developing the photoresist, thereby forming the structured photoresist layer 115.

[0026] With reference to Fig. 2 and Fig. 5 comprises the execution of the procedure 200 operation 206, wherein the non-via end section 118 of each of the first conductive line 112A of the lower level and the third conductive line 112C of the lower level, which is exposed through the structured photoresist layer 115, is recessed to form a cutout 119 over the non-via end section 118 of each of the first conductive line 112A of the lower level and the third conductive line 112C of the lower level.In some embodiments, a back-etching process is performed to remove an upper portion of the non-plated-through end section 118 of each of the first conductive line 112A of the lower level and the third conductive line 112C of the lower level, such that the upper surface of the non-plated-through end section 118 of each of the first conductive line 112A of the lower level and the third conductive line 112C of the lower level lies below the upper surface of the first dielectric layer 110. In some embodiments, the back-etching process includes dry etching, wet etching, or a combination thereof. In some embodiments, the metal section 114 and the metal lining 116 in each of the first conductive line 112A of the lower level and the third conductive line 112C of the lower level are etched using separate etching processes.For example, a mixture of gases including SF6, nitrogen, and chlorine is used to etch the metal section 114, and a basic solution comprising an aqueous mixture of ammonium hydroxide and hydrogen peroxide is used to etch the metal lining 116. The cutout 119 is formed with a depth D that determines the thickness of a dielectric cover 121 ( ). Fig. 1A and Fig. 1B), which is subsequently formed in each section 119. In some embodiments, the depth D of each section 119 ranges from approximately 1 nm to approximately 20 nm. After forming the sections 119, the structured photoresist layer 115 is removed, for example, by wet stripping or plasma ash.

[0027] With reference to Fig. 2 and Fig. Section 6 comprises carrying out the method 200 and performing the operation 208, in which a dielectric cover layer 120 is applied to the cutouts 119 to fill them. The dielectric cover layer 120 covers the first dielectric layer 110 and the conductive lines of the lower layer 112A, 112B, 112C, and 112D. In some embodiments, the dielectric cover layer 120 comprises silicon carbide, silicon oxycarbide, silicon nitride, nitrogen-doped carbide (NDC), or a combination thereof. In some embodiments, the dielectric cover layer 120 comprises a dielectric with a high k-value, such as, for example, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, or Y2O3. In some embodiments, the dielectric cover layer 120 is deposited using CVD, PECVD, PVD, ALD, or other suitable deposition processes.In some embodiments, the dielectric cover layer 120 comprises the same material as the first dielectric layer 110. In some embodiments, the dielectric cover layer 120 comprises a material that differs from the first dielectric layer 110.

[0028] With reference to Fig. 2 and Fig. 7. Carrying out method 200 comprises performing operation 210, wherein the dielectric covers 121 are formed in cutouts 119 that cover the non-plated-through end sections 118 of the first and third conductive lines 112A and 112C of the lower layer. In some embodiments, the dielectric covers 121 are formed by removing a portion of the dielectric cover layer 120 above the top surface of the first dielectric layer 110. In some embodiments, the removal process includes performing a planarization process. In some embodiments, the planarization process includes a CMP process. After the planarization process, the dielectric covers 121 each have a top surface that is coplanar with the top surface of the first dielectric layer 110.The dielectric covers 121 in the cutouts 119 are configured to have sufficient thickness to prevent short circuits between the lower-level conductive target line 112B and the adjacent lower-level first conductive line 112A or third conductive line 112C. In some embodiments, each dielectric cover 121 has a thickness of approximately 1 nm to approximately 20 nm. If the dielectric cover 121 is too thin, it may not adequately insulate the lower-level conductive target line 112B from the adjacent lower-level first conductive line 112A or third conductive line 112C in some cases where a via misalignment occurs.On the other hand, if the dielectric cover 121 is too thick, the layer resistance of the dielectric cover 121 becomes too high, which in some cases negatively affects the RxC (resistance×capacitance) delay performance.

[0029] With reference to Fig. 2 and Fig. Section 8 of the implementation of method 200 comprises performing operation 212, wherein an etch stop layer 122 is deposited over the first dielectric layer 110, the lower-level conductive lines 112A, 112B, 112C, and 112D, and the dielectric covers 121. The etch stop layer 122 is used to control the endpoint during the subsequent damascening processes for forming trenches and vias. In some embodiments, the etch stop layer 122 comprises a dielectric with high etch selectivity with respect to the first dielectric layer 110. In some embodiments, the etch stop layer 122 comprises silicon carbide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, or other suitable dielectrics. In some embodiments, the etch stop layer 122 comprises a dielectric that differs from the dielectric that provides the dielectric covers 121.In some embodiments, the etch stop layer 122 comprises a dielectric that is the same as the dielectric that provides the dielectric covers 121. In some embodiments, the etch stop layer 122 is deposited using CVD, PECVD, PVD, ALD, or other suitable deposition processes. The etch stop layer 122 is optional and is omitted in some embodiments.

[0030] With reference to Fig. 2 and Fig. 9. Carrying out the process 200 includes performing operation 214, in which a second dielectric layer 130 is deposited over the first dielectric layer 122 or over the etch stop layer, if present. The second dielectric layer 130 comprises a dielectric that is the same as or different from the dielectric provided by the first dielectric layer 110. For example, the second dielectric layer 130 comprises a dielectric with a low k-value, such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, doped silicate glass such as borophosphosilicate glass (BPSG), molten silicon dioxide glass (FSG), phosphosilicate glass (PSG), or boron-doped silicon glass (BSG). In some embodiments, the second dielectric layer 130 is deposited using CVD, PECVD, PVD, spin coating, or other suitable deposition processes.In some embodiments, the second dielectric layer 130 is planarized by a planarization process or otherwise cut out to provide a planar top surface. In some embodiments, the second dielectric layer 130 is planarized using a CMP process. In some embodiments, the second dielectric layer 130 comprises the same material as the dielectric cover layer 120 and the first dielectric layer 110. In some embodiments, the second dielectric layer 130 comprises a different material than at least one of the dielectric cover layer 120 or the first dielectric layer 110.

[0031] With reference to Fig. 2 and Fig. 10. The execution of procedure 200 comprises performing operation 216, forming a trench 132' and a via opening 134' to expose a section of the second conductive trace of the lower level 112B. The trench 132' encloses the base of the via opening 134'.

[0032] In some embodiments, the trench 132' and the via opening 134' are formed using a double damascening process. In some embodiments, the trench 132' and the via opening 134' are formed using a trench-first scheme. For example, a first lithography and etching process is performed to define the trench 132' in an upper portion of the second dielectric layer 130. The first lithography process includes depositing a first photoresist layer (not shown) over the second dielectric layer 130 to expose the first photoresist layer to a radiation structure, performing a firing process after exposure, and developing the first photoresist layer to form a structured first photoresist layer (not shown).The second dielectric layer 130 is subsequently etched using the first structured photoresist layer as an etch mask to form the trench 132' in the upper portion of the second dielectric layer 130. The etching process involves anisotropic etching, such as RIE or plasma etching. After forming the trench 132', the structured first photoresist layer is removed, for example, by wet stripping or plasma ash. Next, a second lithography and etching process is performed to define the via opening 134' within the trench 132. The via opening 134' extends through the second dielectric layer 130 and the etch stop layer 122, if present. The second lithography process involves depositing a second photoresist layer (not shown) over the second dielectric layer 130 to fill the trench 132'.The second photoresist layer is then structured by exposing it in a radiation structure, performing post-exposure firing processes, and developing the second photoresist layer to form a structured second photoresist layer (not shown). Once the structured second photoresist layer is formed, one or more anisotropic processes are performed to use the second dielectric layer 130 and the etch stop layer 122 as an etch mask, forming the via hole 134' beneath the trench 132'. After the via hole 134' is formed, the structured second photoresist layer is removed, for example, by wet stripping or plasma ash. Alternatively, in some embodiments, the trench 132' and the via 134' are formed using a via-first scheme.The formation processes include performing a first lithography and etching process to form a first structured photoresist layer (not shown) and etching the second dielectric layer 130 using the first structured photoresist layer as an etch mask to form an initial via opening (not shown), the initial via opening extending from the top surface of the second dielectric layer 130 to an intermediate plane between the top and bottom surfaces of the second dielectric layer 130. Next, a second lithography and etching process is performed to form a second structured photoresist layer (not shown) to define the structure of the trench 132'.Anisotropic etching is then performed to create the trench 132' in an upper section of the second dielectric layer 130, using the second structured photoresist layer as an etch mask. As the trench 132' forms, the anisotropic etching used in its formation extends downwards through the initial via opening, through the remaining section of the second dielectric layer 130 and the etch stop layer 122, thus forming the via opening 134' below the trench 132'.

[0033] In some cases, superimposition errors occur during the formation of the via hole 134', leading to a misalignment of the via hole 134'. The via hole 134' is formed to extend over an edge of the second conductive trace of the lower layer 112B. In some embodiments, Fig. 10 Although the via opening 134' is shown as extending beyond a right edge of the second conductive line of the lower layer 112B, a situation in which the via opening 134' extends beyond the left edge of the second conductive line of the lower layer 112B is considered in this disclosure. Furthermore, in some embodiments, the superposition defects cause the etching of a section of the second dielectric layer 130, and the via opening 134' therefore includes a notch section 134A' in the first dielectric layer 110, which exposes a side wall of the second conductive line of the lower layer 112B.

[0034] With reference to Fig. 2 and Fig. Figure 11 comprises carrying out method 200 and performing operation 218, wherein a conductive upper-level conductor 132 and a via 134 are formed in the trench 132' and the via opening 134', respectively. In some embodiments, the via 134 comprises a section 134A embedded in the first dielectric layer 110. The via 134 connects the conductive upper-level conductor 132 and the second conductive lower-level conductor 112B. The conductive upper-level conductor 132 comprises a metal section 136 and a metal liner 138 surrounding the metal section 136. The metal liner 138 is optional and is omitted in some embodiments.

[0035] In some embodiments, the conductive trace of the upper level 132 and the via 134 are formed by depositing a second metal lining layer (not shown) on the sidewalls and bottoms of the trench 132' and the via opening 134' and on the upper surface of the second dielectric layer. In some embodiments, the second metal lining layer comprises a diffusion barrier material that prevents the metal in the metal sections 136 from diffusing into the second dielectric layer 130. In some embodiments, the second metal lining layer comprises the same material as the first metal lining layer, which is used to form metal linings 116 in the conductive traces of the lower level 112A, 112B, 112C, and 112D.In some embodiments, the second metal lining layer comprises a different material than the first metal lining layer used to form metal linings 116 in the conductive traces of the lower level 112A, 112B, 112C, and 112D. For example, in some embodiments, the second metal lining layer comprises Ti, TiN, Ta, TaN, Ru, RuN, or other suitable diffusion barrier materials. In some embodiments, the second metal lining layer comprises a stack of the aforementioned diffusion barrier materials, such as Ti / TiN or Ta / TaN. In some embodiments, the second metal lining layer is deposited using a conformal deposition process such as CVD, PECVD, PVD, or ALD.

[0036] A second metal layer (not shown) is subsequently deposited over the second metal lining layer to fill the trench 132' and the via opening 134'. In some embodiments, the second metal layer comprises the same material as the first metal layer, which is used to form metal sections 114 in the lower-level conductive traces 112A, 112B, 112C, and 112D. In other embodiments, the second metal layer comprises a different material than the first metal layer used to form metal sections 114 in the lower-level conductive traces 112A, 112B, 112C, and 112D. For example, in some embodiments, the second metal layer comprises Cu, Al, W, Co, an alloy thereof, or other suitable conductive metals. In some embodiments, the second metal layer is deposited by a suitable deposition process, such as CVD, PECVD, sputtering, or plating.The deposition process continues until the conductive material fills the trench 132' and the via opening 134' and extends over the second dielectric layer 130. In some embodiments, if Cu or a Cu alloy is used in the first metal layer, an optional plating seed layer (not shown) is formed on the second liner layer before the second metal layer is formed. In some embodiments, the optional plating seed layer is formed by a deposition process, including, for example, CVD, PECVD, ALD, and PVD.

[0037] Subsequently, sections of the second metal layer and the second metal liner layer located above the top surface of the second dielectric layer 130 are removed using a planarization process. In some embodiments, a CMP process is performed to remove excess diffusion barrier material and conductive metal from the top surface of the second dielectric layer 130. After planarization, a section of the second metal layer remaining in the trench 132' and the via opening 134' represents the metal section 136, and a section of the second metal liner layer remaining in the trench 132' and the via opening 134' represents the metal liner 138. After the CMP process, a top surface of the conductive conductor of the upper layer 132 is coplanar with the top surface of the second dielectric layer 130.

[0038] In some embodiments, due to the misalignment of the via opening 134', the via 134 subsequently formed within the via opening 134' extends beyond an edge of the second conductive line of the lower level 112B. The insertion of the dielectric covers 121 into the non-via end sections 118 of both adjacent conductive lines of the lower level, i.e., the first and third conductive lines of the lower level 112A and 112C, helps to increase the via to the edge of the conductive line, regardless of which side of the conductive target line 112B of the lower level the via 134 is misaligned. This prevents an accidental short circuit of the conductive target line 112B of the lower level with the adjacent conductive line 112A or 112C of the lower level.The dielectric covers 121 also help to eliminate the current leakage between the lower level conductive target conductor 112B and the adjacent lower level conductive conductor 112A or 112C, which helps to eliminate dielectric breakdown and improve wiring reliability.

[0039] Fig. Figures 12 to 15 are cross-sectional views of the intermediate stages in the formation of the semiconductor structure 100 according to alternative embodiments. Unless specifically noted otherwise, the materials and formation processes of the components in these embodiments are essentially the same as their equivalent components identified by the same reference numerals in the embodiments described in Fig. Figures 2 to 11 will be shown. Details regarding the formation processes and the materials of the components are provided below. Fig. Numbers 12 to 15 are found in the discussion of the embodiments from Fig. 2 to 11.

[0040] The initial steps of these embodiments are similar to those in Fig. 2 to 6, and Fig. 12 comprises a structure similar to the one in Fig. 6 is. After forming the dielectric cover layer 120 over the first dielectric layer 110 and the conductive lines of the lower layer 112A, 112B, 11C and 112C are cut off to fill the cutouts 119, in Fig. 12, will be in Fig. 13, instead of performing operation 210 to remove a section of the dielectric cover layer 120 that lies above the first dielectric layer 110 and subsequently performing operation 212 to form an etch stop layer 122 above the first dielectric layer 110, operations 210 and 212 are omitted in the implementation of method 200 in the alternative embodiments. Fig. 13 uses the procedure 200 ( Fig. 2) Operation 214 continues after the dielectric cover layer has been deposited in Operation 210, forming a second dielectric layer 130 over the dielectric cover layer 120. A section of the dielectric cover layer 120 located in each cutout 119 forms the dielectric cover 121, while a section of the dielectric cover layer 120 located over the first dielectric layer 110 serves as an etch stop layer and performs a function identical to that of the etch stop layer 122 in Operation 210. Fig. 8 is.

[0041] Fig. Figure 14 shows a view after forming a trench 132' in an upper section of the second dielectric layer 130 and a via opening 134' extending through a lower section of the second dielectric layer 130 and the dielectric cover layer 120. Fig. Figure 15 shows a view after the formation of a conductive trace of the upper layer 132 and a via 134 in the trench 132' and in the via 134', respectively. The formation processes are similar to those described above. Fig. 10 and Fig. The 11 processes described are therefore not described in detail.

[0042] One aspect of this description relates to a semiconductor structure. The semiconductor structure comprises a first conductive line and a second conductive line in a first dielectric layer. The first conductive line and the second conductive line extend along a first direction. The semiconductor structure further comprises a third conductive line in a second dielectric layer, which lies above the first dielectric layer. The third conductive line extends along a second direction, different from the first direction, and over at least the second conductive line. The semiconductor structure further comprises a via in the second dielectric layer and the electrical connection of the second conductive line and the third conductive line. The via terminates at a segment of the second conductive line.The semiconductor structure further comprises a dielectric cover over the first conductive trace. A lower surface of the dielectric cover lies beneath an upper surface of the first dielectric layer. In some embodiments, the first direction is perpendicular to the second direction. In some embodiments, the via extends beyond an edge of the second conductive trace in the second direction. The portion of the second conductive trace where a via terminates has an upper surface above an upper surface of a portion of the first conductive trace beneath the dielectric cover. In some embodiments, the dielectric cover has an upper surface that is coplanar with the upper surface of the first dielectric layer. In some embodiments, the dielectric cover comprises silicon carbide, silicon nitride, nitrogen-doped carbide, or a high k-value dielectric.In some embodiments, the semiconductor structure further comprises an etch stop layer between the first and second dielectric layers. The via extends through a lower portion of the second dielectric layer and the etch stop layer to contact a portion of the second conductive trace. In some embodiments, the etch stop layer comprises the same dielectric as the dielectric cover. In some embodiments, the etch stop layer comprises a different dielectric than the dielectric cover. In some embodiments, the dielectric cover has a thickness of 1 nm to approximately 20 nm. In some embodiments, a portion of the via is embedded in the first dielectric layer. In some embodiments, the first and second dielectric layers each comprise a dielectric with a low k-value.

[0043] Another aspect of this description relates to a semiconductor structure. The semiconductor structure comprises a substrate, a first dielectric layer over the substrate, several lower-level conductive lines in the first dielectric layer extending along a first direction, an etch stop layer over the first dielectric layer, a second dielectric layer over the etch stop layer, an upper-level conductive line in an upper portion of the second dielectric layer extending along a second direction perpendicular to the first direction, a via extending through a lower portion of the second dielectric layer and the etch stop layer, and coupling the upper-level conductive line to a lower-level conductive target line of the several lower-level conductive lines.and a dielectric covering over a section of each of the adjacent lower-level conductive lines of the multiple lower-level conductive lines on opposite sides of the lower-level conductive target line. Each dielectric covering is adjacent to the via and lies beneath the etch stop layer. In some embodiments, a minimum conductive line spacing is permitted according to the design rules of a manufacturing process between the lower-level conductive target line and each of the adjacent lower-level conductive lines of the multiple lower-level conductive lines.

[0044] Another aspect of this description relates to a method for forming a semiconductor structure. The method involves forming multiple lower-level conductive lines in a first dielectric layer. The multiple lower-level conductive lines include a first lower-level conductive line, a second lower-level conductive line adjacent to the first lower-level conductive line, and a third lower-level conductive line adjacent to the second lower-level conductive line.The method further comprises recessing sections of the first and third conductive lines of the lower level below an upper surface of the first dielectric layer to form depressions, forming dielectric covers in the depressions, depositing a second dielectric layer over the first dielectric layer, and forming a trench and a via opening in the second dielectric layer. The via opening exposes a section of the second conductive line of the lower level adjacent to the dielectric covers. The method further comprises forming an upper-level conductive line and a via in the trench and via opening, respectively.The via couples the upper-level conductive conductor to the second conductive conductor of the lower level, and the upper-level conductive conductor overlaps the dielectric covers. In some embodiments, forming the trench and via opening in the second dielectric layer includes creating a via opening that exposes a side wall of the exposed portion of the second conductive conductor of the lower level, adjacent to one of the dielectric covers. In some embodiments, forming the dielectric covers includes forming a dielectric cover layer over the first dielectric layer and the multiple conductive conductors of the lower level. Sections of the dielectric cover layer within the trenches provide the dielectric covers, and the second dielectric layer is formed over the dielectric cover layer.In some embodiments, forming the trench and the via opening involves etching the second dielectric layer and the dielectric cover layer. The trench extends through an upper portion of the second dielectric layer, and the via opening extends through a lower portion of the second dielectric layer and the dielectric cover layer. In some embodiments, forming the dielectric covers involves forming a dielectric cover layer over the first dielectric layer and the multiple conductive traces of the lower plane, such that the dielectric cover layer fills the depressions, and removing a portion of the dielectric cover layer from the upper surface of the first dielectric layer. Portions of the dielectric cover layer remaining in the depressions constitute the dielectric covers.In some embodiments, the method further comprises forming an etch stop layer over the first dielectric layer, the dielectric covers, and the multiple conductive traces of the lower layer. Forming the trench and the via opening comprises etching the second dielectric layer and the etch stop layer, wherein the trench extends through an upper portion of the second dielectric layer, and the via opening extends through a lower portion of the second dielectric layer and the etch stop layer.

[0045] The above describes features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should be aware that they can easily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same purposes and / or the same advantages as the embodiments presented herein.

Claims

[1] Having a semiconductor structure: a first conductive line (112A) and a second conductive line (112B) in a first dielectric layer (110), wherein the first conductive line (112A) and the second conductive line (112B) extend along a first direction; a third conductive line (132) in a second dielectric layer (130) located above the first dielectric layer (110), wherein the third conductive line (132) extends along a second direction different from the first direction and over at least the first conductive line (112A) and the second conductive line (112B); a via (134) in the second dielectric layer (130) that electrically connects the second conductive line (112B) and the third conductive line (132), wherein the via (134) terminates at a section of the second conductive line (112B); and a dielectric cover (121) over the first conductive line (112A), wherein a lower surface of the dielectric cover (121) lies below an upper surface of the first dielectric layer (110), wherein the section of the second conductive line (112B) in which the via (134) terminates has an upper surface which lies above an upper surface of a section of the first conductive line (112A) under the dielectric cover (121) and which is coplanar with an upper surface of the dielectric cover (121). [2] Semiconductor structure according to claim 1, wherein the first direction is perpendicular to the second direction. [3] Semiconductor structure according to claim 1 or 2, wherein the via (134) extends in the second direction beyond an edge of the second conductive line (112B). [4] Semiconductor structure according to one of the preceding claims, wherein the upper surface of the dielectric cover (121) is coplanar with the upper surface of the first dielectric layer (110). [5] Semiconductor structure according to any of the preceding claims, wherein the dielectric cover (121) comprises silicon carbide, silicon nitride, nitrogen-doped carbide or a dielectric with a high k-value. [6] Semiconductor structure according to one of the preceding claims, further comprising an etch stop layer (122) between the first dielectric layer (110) and the second dielectric layer (130), wherein the via (134) extends through a lower section of the second dielectric layer (130) and the etch stop layer (122) to contact a section of the second conductive line (112B). [7] Semiconductor structure according to claim 6, wherein the etch stop layer (122) has the same dielectric material as the dielectric cover (121). [8] Semiconductor structure according to claim 6, wherein the etch stop layer (122) has a different dielectric material than the dielectric cover (121). [9] Semiconductor structure according to any of the preceding claims, wherein the dielectric covering (121) has a thickness of about 1 nm to about 20 nm. [10] Semiconductor structure according to one of the preceding claims, wherein a section of the via (134) is embedded in the first dielectric layer (110). [11] Semiconductor structure according to one of the preceding claims, wherein the first dielectric layer (110) and the second dielectric layer (130) each comprise a dielectric material with a low k-value. [12] Having a semiconductor structure: a substrate (102); a first dielectric layer (110) over the substrate (102); several conductive lines of the lower plane (112A-D) in the first dielectric layer (110) extending along a first direction; an etch stop layer (122) over the first dielectric layer (110); a second dielectric layer (130) over the etch stop layer (122); a conductive line of the upper plane (132) in an upper section of the second dielectric layer (130) extending along a second direction, the second direction being perpendicular to the first direction; a via (134) extending through a lower section of the second dielectric layer (130) and the etch stop layer (122) and coupling the upper layer conductive line (132) to a lower layer conductive target line (112B) of the multiple lower layer conductive lines (112A-D); and a dielectric cover (121) over a section of each of the adjacent lower-level conductive lines (112A, 112C) of the multiple lower-level conductive lines (112A-D) on opposite sides of the lower-level conductive target line (112B), wherein an upper surface of the conductive target line (112B) lies over a lower surface of the dielectric cover (121) and wherein each dielectric cover (121) is adjacent to the via (134) and lies below the etch stop layer (122). [13] Semiconductor structure according to claim 12, wherein a distance between the conductive target line of the lower level and each of the adjacent conductive lines of the lower level (112A-D) of the multiple conductive lines of the lower level (112A-D) is a minimum distance of the conductive lines that is allowed by the design rules according to a manufacturing process. [14] Method (200) for forming a semiconductor structure, comprising: Forming several lower-level conductive lines in a first dielectric layer (110), wherein the several lower-level conductive lines (112A-D) comprise a first lower-level conductive line (112A), a second lower-level conductive line (112B) adjacent to the first lower-level conductive line (112A), and a third lower-level conductive line (112C) adjacent to the second lower-level conductive line (112B); Deepening sections of the first conductive line (112A) of the lower level and the third conductive line (112C) of the lower level below an upper surface of the first dielectric layer (110) to form depressions; Forming dielectric covers (121) in the recesses, wherein the respective upper surfaces of the dielectric covers (121) are coplanar to an upper surface of the second conductive line (112B); Deposition of a second dielectric layer (130) over the first dielectric layer (110); Forming a trench (132') and a via opening (134') in the second dielectric layer (130), wherein the via opening (134') exposes a section of the second conductive line (112B) of the lower layer, which is adjacent to the dielectric covers (121); and Forming an upper level conductive line (132) in the trench (132') and a via (134) in the via opening (134'), wherein the via (134) couples the upper level conductive line (132) with the second lower level conductive line (112B), and the upper level conductive line (132) overlaps the dielectric covers (121). [15] Method (200) according to claim 14, wherein forming the trench (132') and the via opening (134') in the second dielectric layer (130) comprises forming a via opening (134') which exposes a side wall of the exposed section of the second conductive line (112B) of the lower plane, which is adjacent to one of the dielectric covers (121). [16] Method (200) according to claim 14 or 15, wherein forming the dielectric covers (121) comprises forming a dielectric cover layer (120) over the first dielectric layer (110) and the multiple conductive lines of the lower level (112A-D), wherein sections of the dielectric cover layer (120) within the recesses provide the dielectric covers (121), and the second dielectric layer (130) is formed over the dielectric cover layer (120). [17] Method (200) according to claim 16, wherein forming the trench and the via opening (134') comprises etching the second dielectric layer (130) and the dielectric cover layer (120), wherein the trench extends through an upper section of the second dielectric layer (130) and the via opening (134') extends through a lower section of the second dielectric layer (130) and the dielectric cover layer (120). [18] Method (200) according to any one of the preceding claims 14 to 17, comprising forming the dielectric covers (121): Forming a dielectric cover layer (120) over the first dielectric layer (110) and the multiple conductive lines of the lower layer (112A-D), wherein the dielectric cover layer (120) fills the depressions; and Removing a section of the dielectric cover layer (120) above the upper surface of the first dielectric layer (110) from the upper surface of the first dielectric layer (110), wherein sections of the dielectric cover layer (120) remaining in the depressions constitute the dielectric covers (121). [19] Method (200) according to claim 18, further comprising forming an etch stop layer (122) over the first dielectric layer (110), the dielectric covers (121) and the multiple conductive lines of the lower level (112A-D), wherein forming the trench (132') and the via opening (134') comprises etching the second dielectric layer (130) and the etch stop layer (122), wherein the trench (132') extends through an upper section of the second etch stop layer, and the via opening (134') extends through a lower section of the second dielectric layer (130) and the etch stop layer (122).

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