Method and apparatus for using a substrate gate bias for power amplifiers for millimeter wave devices

Abstract

Device comprising: an input transformer (950); a first differential transistor pair (910) comprising a first transistor (911), a second transistor (912) and a first DC voltage source (971) configured to apply a first substrate gate voltage to the first transistor (911) and the second transistor (912); a second differential transistor pair (920) comprising a third transistor (923), a fourth transistor (924) and a second DC voltage source (972) configured to apply a second substrate gate voltage to the third transistor (923) and the fourth transistor (924); a neutralizing cap (930) comprising a fifth transistor (935), a sixth transistor (936) and a third DC voltage source (973), wherein the fifth transistor (935) and the sixth transistor (936) are cross-connected, the fifth transistor (935) is an NMOS transistor, the sixth transistor (936) is an NMOS transistor and the third DC voltage source (973) is configured to apply a third substrate-gate voltage to the fifth transistor (935) and the sixth transistor (936); and an output transformer (960).

Description

Background of the invention; Field of the invention

[0001] In general, the present invention relates to sophisticated semiconductor devices and, in particular, to power amplifiers for millimeter wave devices. Description of the state of the art

[0002] Power amplification is a necessity in virtually all electronic devices. Given the ongoing race to reduce device size and / or power consumption, known power amplifiers exhibit undesirably low efficiency and undesirably large dimensions for use in modern devices. In conjunction with this, known power amplifiers exhibit relatively poor linearity over various voltage ranges. These problems are particularly pronounced for millimeter-wave devices.

[0003] Different electronic devices may have different power amplification requirements, based on one or more of the intended uses of the device, its available power, its desired power consumption, and the like. Known power amplifiers are generally designed specifically for a single electronic device and must be redesigned for use in a different electronic device. The prior art generally lacks power amplifiers that can provide one or more with increased efficiency, increased linearity, reduced size, and / or increased ease of incorporation into one or more electronic devices.

[0004] The present invention can address and / or at least reduce one or more of the problems mentioned above.

[0005] A FDSOI power amplifier with bias voltages and a method for its manufacture are known from US 2018 / 0 167 038 A1, as well as a circuit structure and a method for power amplifier control with forward and reverse voltage bias voltages for transistor back-gate areas from US 2018 / 0 302 038 A1.

[0006] The following is a simplified summary of the invention to provide a basic understanding of some aspects of it. This summary does not constitute an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to define its scope. Its sole purpose is to present some concepts in simplified form as a prelude to the more detailed description that will be discussed later.

[0007] In general, the present invention relates to devices and methods for preparing the device for use. In one embodiment, the present invention provides a device comprising an input transformer; a first differential transistor pair comprising a first transistor, a second transistor, and a first direct current (DC) voltage source configured to apply a first substrate-gate bias to the first transistor and the second transistor; a second differential transistor pair comprising a third transistor, a fourth transistor, and a second DC voltage source configured to apply a second substrate-gate bias to the third transistor and the fourth transistor;a neutralizing capacitor comprising a fifth transistor, a sixth transistor, and a third DC voltage source, wherein the fifth and sixth transistors are cross-coupled, the fifth transistor is a PMOS transistor, the sixth transistor is a PMOS transistor, and the third DC voltage source is configured to apply a third substrate-gate bias to the fifth and sixth transistors; and an output transformer.

[0008] In one embodiment, the present invention provides a method comprising forming a device, as described herein; determining at least one first desired capacitance of a first differential transistor pair, a second desired capacitance of a second differential transistor pair, and a third desired capacitance of a neutralizing capacitor; determining at least one first desired substrate-gate bias which, when applied to a first transistor and a second transistor, imparts the first desired capacitance to the first differential transistor pair; and a second desired substrate-gate bias which, when applied to a third transistor and a fourth transistor, imparts the second desired capacitance to the second differential transistor pair.and a third desired substrate-gate bias which, when applied to a fifth transistor and a sixth transistor, imparts the third desired capacitance to the neutralizing capacitance; and fixing at least one first DC voltage source such that a first substrate-gate bias is equal to the first desired substrate-gate bias; a second DC voltage source such that a second substrate-gate bias is equal to the second desired substrate-gate bias; and a third DC voltage source such that a third substrate-gate bias is equal to the third desired substrate-gate bias.

[0009] The embodiments described herein can provide a power amplifier with improved linearity, improved performance, and / or reduced size. The embodiments described herein can also provide a "drop-in" amplifier whose performance and / or linearity can be adjusted to a desired value, based on the intended use and other parameters of an electronic device into which it is to be incorporated.

[0010] According to the invention, a device according to claim 1 or 8 and a method according to claim 14 are provided. Brief description of the drawings

[0011] The invention can be understood with reference to the following description in conjunction with the accompanying drawings, in which the same reference numerals denote the same elements and in which: Fig. 1 represents a stylized block diagram representation of a mm-wave communication system according to embodiments described herein; Fig. 2 represents a stylized block diagram description of the control unit 140 according to the embodiments described herein; Fig. 3 A stylized block diagram representation of the communication front-end unit of Fig. 1 according to the embodiments described herein; Fig. 4 a stylized block diagram of the transmitter unit of Fig. 3 according to the embodiments described herein; Fig. 5 a stylized block diagram of the receiver unit of Fig. 3 according to the embodiments described herein; Fig. 6 A stylized block diagram representation of the signal processing unit of Fig. 1 according to the embodiments described herein; Fig. 7 a stylized block diagram representation of the antenna unit of Fig. 1 according to the embodiments described herein; Fig. 8 A stylized block diagram representation of an exemplary communication application of the system of Fig. 1 according to the embodiments contained herein; Fig. 9 shows a first power amplifier according to the embodiments described herein; Fig. 10 represents a second power amplifier according to embodiments described herein; Fig. 11 illustrates a method according to the embodiments described herein; and Fig. 12 represents a stylized representation of a system for manufacturing a semiconductor device according to the embodiments described herein.

[0012] While the subject matter disclosed herein is accessible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are described in detail herein. Furthermore, the stylized representations shown in the drawings are not drawn to absolute scale. Detailed description

[0013] Several illustrative embodiments of the invention are described below. For the sake of clarity, not all features of an actual implementation are described in this specification. It is understood, of course, that developing such an actual embodiment requires numerous implementation-specific decisions to achieve the developers' specific objectives, such as adhering to system-related and business-related constraints, which may differ from one implementation to another. Furthermore, it is understood that such a development effort can be complex and time-consuming, but is a routine undertaking for the average person skilled in the art who benefits from this invention.

[0014] The present subject matter will now be described with reference to the accompanying figures. Various structures, systems, and devices are shown schematically in the drawings for explanatory purposes only, so as not to obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the accompanying drawings are included to describe and illustrate the present invention with examples. The words and expressions used herein should be understood and interpreted in such a way as to have a meaning corresponding to that understood by those skilled in the art. No special definition of any expression or phrase, i.e., a definition that differs from the ordinary and customary meaning as understood by those skilled in the art, should be implied by the consistent use of the expression or phrase herein.To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by experts, such a special definition is explicitly set forth in the description in a defined manner that directly and unambiguously provides the special definition for the term or phrase.

[0015] The embodiments described herein provide millimeter wave (mm-wave) power amplifiers with improved linearity and performance. Other embodiments herein allow for the tuning of various power amplifier characteristics to improve linearity and efficiency for specific intended uses of the power amplifier and of a device comprising the power amplifier.

[0016] For the sake of simplicity, embodiments are shown herein in connection with a 5G communication device; however, the person skilled in the art will readily recognize that the concepts disclosed herein can be implemented in other types of devices, such as radar devices, other high-speed communication devices, network devices, etc. Fig. Figure 1 is a stylized block diagram representation of a communication system according to the embodiments described herein.

[0017] A system 100 may comprise a millimeter-wave device (mm-wave device) 110 and a database 170. The mm-wave device 110 may be a communications device, such as a 5G or WiGig communications device, or, in alternative embodiments (not shown), a radar device, a data network device, a video device, or the like. For the sake of illustration, clarity, and ease of description, the mm-wave device 110 is described in the context of a 5G or WiGig communications application; as such, the mm-wave device 110 may often be referred to below as the communications device 110.However, the person skilled in the art who benefits from the present invention would recognize that the concepts described herein can be applied to a wide variety of mm-wave applications, including vehicle applications using radar signals, wireless network applications, data network applications, video and audio applications, etc.

[0018] The communication device 110 can send a first communication signal, receive a second communication signal and process the second communication signal.

[0019] The communication device 110 can comprise a communication front-end unit 120, an antenna unit 130, a control unit 140, and a signal processing unit 150. The communication front-end unit 120 can comprise a variety of components, circuits, and / or modules and is capable of transmitting, receiving, and processing communication signals. In one embodiment, the communication device 110 can be contained in a single integrated circuit (IC) chip. In some embodiments, the communication device 110 can be formed on several integrated circuits arranged on a single IC chip. In other embodiments, the communication device 110 can be formed on a single integrated circuit implemented in an IC chip.

[0020] The communication front-end unit 120 can provide an output signal, e.g., a first communication signal. In one embodiment, the frequency range of the communication signals processed by the communication device 110 can be in the range of approximately 10 GHz to approximately 90 GHz, such as 28 GHz or 40 GHz. A more detailed description of the communication front-end unit 120 is given in Fig. 3 and the following description.

[0021] In one embodiment, the communication front-end unit 120 can be a network communication front-end unit. In this embodiment, the communication device 110 can process network communication for various types of communication applications, such as packet data network communication, wireless communication (e.g., cellular communication, IEEE 802.11ad WiGig technology, etc.), data communication, etc. The concepts disclosed herein can also be used for other types of applications, such as network communication, wireless communication, high-definition video, etc.

[0022] Further referring to section 1, the antenna unit 130 may also include a transmitting antenna and / or a receiving antenna. Furthermore, each of the transmitting and receiving antennas may have subsections to form an antenna array. The transmitting antennas are used to transmit the first communication signal, while the receiving antennas are used to receive a second communication signal. A more detailed description of the antenna unit 130 is given in Fig. 7 and the following description.

[0023] Further with reference to 1, the communication device 110 can also include a signal processing unit 150. The signal processing unit is capable of performing various analog and / or digital processing operations on the signals sent and / or received by the communication device 110. For example, the first communication signal transmitted by the communication device can be amplified before transmission. Furthermore, the second communication signal received by the communication device 110 can be passed through one or more analog filter stages. The second communication signal can then be converted into a digital signal by one or more analog-to-digital converters (DACs) in the signal processing unit 150. Digital signal processing (DSP) can be performed on the digitized signal. A more detailed description of the signal processing unit 150 is given in Fig. 6 and the following description.

[0024] With further reference to Fig. 1. The communication device 100 can also include a control unit 140. The control unit 140 can perform various control operations of the communication device 110. These functions include generating a first communication signal, transmitting the first communication signal, receiving a second communication signal, and processing the second communication signal.

[0025] Now, with reference to Section 2, a stylized block diagram description of the control unit 140 is provided in accordance with embodiments herein. The control unit 140 may comprise a processor unit 230, which can control various functions of the communication device 110. The processor unit 230 may comprise a microprocessor, a microcontroller, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), and / or the like.

[0026] The control unit 140 can also include a logic unit 220. The logic unit 220 can comprise a circuit capable of performing various logic operations, receiving data, and / or executing interface functions with respect to input data (data_in) and output data (data_out). The data_in signal can represent data derived from the processing and analysis of the second communication signal. The data_out signal can represent data generated for the first communication signal.

[0027] The control unit 140 can also include a memory unit 210. The memory unit 210 can include non-volatile memory (NVM) 214 and random access memory (RAM) 212. The non-volatile memory 214 can include flash memory and / or programmable read-only devices (PROMs). The memory unit 210 can store operating parameters for controlling operations of the communication device 110. The memory unit 210 can also store data that can be used to program any FPGA devices in the communication device 110. Thus, the memory unit 210 can be divided into a program data memory, a status data memory, and a response data memory. This division can be logical or physical.

[0028] In Fig. Figure 3 is a stylized block diagram representation of the communication front-end unit 120 according to the embodiments described herein. The communication front-end unit 120 can comprise a signal generation unit 310, a transmitter unit 320, and a receiver unit 330. The signal generation unit 310 is capable of generating a communication signal at a predetermined frequency. For example, a signal in the range of approximately 28 GHz to approximately 40 GHz can be generated. The signal generation unit 310 can include a true difference frequency doubler (FD). The FD can be configured in a push-push configuration. The signal generation unit 310 can provide a communication signal for transmission. A more detailed description of the signal generation unit 310 is given below.

[0029] With further reference to 3, the signal generation unit 310 provides a signal for processing and transmission to the transmitting unit 320. The transmitting unit 320 may include several filters, signal conditioning circuits, buffers, amplifiers, etc., for transmitting the signal from the signal generation unit 310. The transmitting unit 320 provides a communication signal to be transmitted to the antenna unit 130.

[0030] Fig. Figure 4 shows a stylized block diagram of the transmitting unit 320 according to the embodiments described herein. With simultaneous reference to the Fig. 3 and Fig. 4. The transmitter unit 320 can comprise a plurality of similar transmitters, i.e., a first transmitter 410a, a second transmitter 410b, up to an Nth transmitter 410n (collectively, “410”). In one embodiment, the first to Nth transmitters 410 can each process a single signal from the signal generation unit 310 and provide an output transmission signal for one or more antennas. In another embodiment, the signal generation unit 310 can provide a plurality of signals to the up to Nth transmitters 410. For example, the signal generation unit 310 can provide a signal transmission signal for each transmitter 410, or alternatively, a first transmission signal for a first set of transmitters 410 and a second transmission signal for a second set of transmitters 410.

[0031] With further reference to Fig. 3. A received signal (i.e., a second communication signal) is provided to the receiver unit 330. The receiver unit 330 can receive the second communication signal from the antenna. The receiver unit 330 can perform analog-to-digital conversion (A / D conversion), signal buffering, DSP, etc. In some embodiments, the signal processing unit 130 can perform A / D conversions and DSP and provide the processed signal to the receiver unit 330; however, in other embodiments, these tasks can be performed by the receiver unit 330. The receiver unit 330 is capable of supplying data_out to the control unit 140.

[0032] Fig. Figure 5 shows a stylized block diagram of the receiver unit 320 according to the embodiments described herein. With simultaneous reference to the Fig. 3 and Fig. 5. The receiver unit 320 can comprise several similar receivers, i.e., a first receiver 510a, a second receiver 510b, up to an Nth receiver 510n (collectively “510”). In one embodiment, the first to Nth receiver 510 can each process a single signal from the signal generation unit 310 and provide the signal to the control unit 140. In another embodiment, the antenna unit 130 can provide a plurality of signals to the first to Nth receivers 510. For example, the antenna unit 130 can provide one signal to each receiver 510, or alternatively, a first receiver signal for a first set of receivers 510 and a second receiver signal for a second set of receivers 510.

[0033] In Fig. Figure 6 shows a stylized block diagram representation of the signal processing unit 150 according to the embodiments described herein. The signal processing unit 150 can comprise an analog filter unit 610, an A / D converter 620, a DSP unit 630, and a memory 640. The analog filter unit 610 can perform both filtering and amplification of the analog mm-wave signal received by the signal processing unit 150. Noise filtering can be performed by the analog filter unit 610 before amplification of the analog mm-wave signal.

[0034] The 620 A / D converter can convert the filtered and / or amplified analog signal into a digital signal. The 620 A / D converter can perform conversions with predetermined or variable accuracy. For example, the 620 A / D converter can provide an accuracy of 12 bits, 24 bits, 36 bits, 48 ​​bits, 64 bits, 96 bits, 128 bits, 256 bits, 512 bits, 1024 bits, or higher. The converted digital mmWave signal is provided to the 630 DSP unit.

[0035] The DSP unit 630 can perform various DSP operations on the digital mm-wave signal. For example, the digital mm-wave signal can be digitally filtered by the DSP unit 630. Signal components outside a predetermined frequency range, such as 70 GHz to approximately 85 GHz, can be filtered to have a lower amplitude. In other cases, mathematical functions, such as a fast Fourier transform (FFT), can be performed on the mm-wave signal. The processed digital output from the DSP unit 630 can be sent to the control unit 140 for analysis. In other cases, the digital output can be buffered or stored in a memory 640. In some cases, the memory 640 can be a FIFO (first-in, first-out) memory.In other cases, the processed digital output from the DSP unit 630 can be stored in the storage unit 210 of the control unit 140.

[0036] In Fig. Figure 7 is a stylized block diagram representation of the antenna unit of Fig. 1 as described in the embodiments shown here. Millimeter wave signals to be transmitted (e.g. network data signals, wireless communication signals, etc.) can be received by the transmitting unit 320 ( Fig. 3) are provided for the transmitting antenna 710. In one embodiment, the transmitting antenna 710 can comprise a plurality of transmitting antenna sections 715. The transmitting antenna sections 715 are arranged in a predetermined pattern, for example, an arrangement matrix, as shown in Fig. Figure 7 is shown as an example.

[0037] Millimeter wave signals to be received (e.g., network data signals, wireless communication signals, etc.) can be detected by the receiving antenna 720. The receiving antenna 720 presents the received mm wave signals to the receiver unit 330 ( Fig. 3) ready. In one embodiment, the receiving antenna 720 can comprise several receiving antenna sections 725. The receiving antenna sections 725 are also arranged in a predetermined pattern, e.g., an arrangement matrix, which is shown in Fig. Figure 7 is shown as an example.

[0038] In Fig. Figure 8 is a stylized block diagram representation of an exemplary communication application of System 100 according to the embodiments described herein. Fig. Figure 8 shows an exemplary implementation of the signal generation unit 310 ( Fig. 3) and exemplary parts of the transmitter unit 320 and the receiver unit 330.

[0039] The signal generation unit 310 generates a signal (e.g., a first communication signal) that is to be transmitted.

[0040] A reference signal is provided by a reference signal generator 812. The reference signal is sent to a digital phase-locked loop (DPLL) 820. The DPLL 820 blocks the phase of the reference signal. The output of the DPLL 820 is sent to a digital control oscillator (DCO) 825. The output of the DCO is fed back to the DPLL. Thus, the DCO 825 can provide a stable DCO signal. In one embodiment, the DCO signal is approximately 14 GHz.

[0041] A variety of 827 low-dropout (LDO) regulators, which may include a reference voltage, an error amplifier, a feedback voltage divider, and a variety of pass-through elements, such as transistors. The 827 LDO regulators are configured to provide a regulated voltage supply for the various parts of the circuit. Fig. 8 to provide. In general, this regulated voltage supply is lower than the supply voltage.

[0042] In some embodiments, it is desirable to transmit a 28 GHz or approximately 40 GHz signal, for example, in a communications application. The DCO 825 can provide a 14 GHz signal; therefore, frequency multiplication may be necessary to provide a 28 GHz or approximately 40 GHz signal for transmission. Accordingly, a frequency multiplier 830 can be used to multiply the frequency provided by the DCO 825 to obtain the desired output frequency. The output of the frequency multiplier 830 is mixed by the mixer 832 with a baseband path signal provided by the D / A converter 844 and the baseband amplifier 846. The output of the mixer 832 is provided to the preamplifier 834 and subsequently to a power amplifier 840. The output of the power amplifier 840 can be provided to the antenna for transmission.A power detector 842 can detect the power of the output of the power amplifier 840 and initiate feedback settings to maintain a predetermined power level of the transmitted signal.

[0043] A received signal can be processed by the Fig. The circuit shown in Figure 8 is used for processing. The received signal, e.g., from the signal processing unit 150, is supplied to a balun circuit 850. The balun may include a transformer and provides a differential output for a preamplifier 852. After pre-amplification of the received signal, the output of the preamplifier 852 is provided to the mixer 860.

[0044] The mixer 860 can combine the received signal from the preamplifier 852 with an output signal from the frequency multiplier 830. The output of the frequency multiplier 830 can be a reference signal with a desired reference frequency. The mixer 860 receives the reference signal and, in one embodiment, multiplies it with the received communication signal.

[0045] In one embodiment, the frequency multiplier 830 can be a fully differential push-push frequency doubler.

[0046] The mixer 860 is designed for a Fig. provided. The output of the Fig. The signal is supplied to an automatic gain control (AGC) and filter circuits 868. A saturation detection circuit 872 can detect any saturation of the processed signal by the AGC / filter circuits 868 and perform a corresponding adjustment. The output of the AGC / filter circuits 868 is provided to an analog-to-digital converter (ADC) 870. The output of the ADC 870 can be provided to the control unit 140 for further processing and corresponding actions.

[0047] Fig. Figure 9 shows a first power amplifier 900 according to the embodiments described herein. The first power amplifier 900 comprises an input transformer 950 and an output transformer 960. The input transformer 950 receives an input signal IN and converts it into differential signals VP and VM. The output transformer 960 receives amplified differential signals VOP and VOM and converts them into an output signal OUT. As shown, the input transformer 950 is connected to ground, and the output transformer 960 is connected to VDD. The output signal OUT can be used for the antenna unit 130 ( Fig. 1 and Fig. 7) be provided, whereby the output signal can be transmitted via the transmitting antenna 710.

[0048] The transistors provided herein, by various embodiments, can each comprise a front gate and a substrate gate. The substrate gates can be used to influence the bias of the transistor. In one embodiment, the transistors comprising the substrate gates can be formed using fully depleted silicon-on-insulator (FDSOI) processes.

[0049] The first power amplifier 900 also includes a first differential transistor pair 910. The first differential transistor pair 910 comprises a first transistor 911 and a second transistor 912. The first transistor 911 includes a front gate 911a and a substrate gate 911b. The second transistor 912 contains a front gate 912a and a substrate gate 912b. The first differential transistor pair 910 can be a class AB transistor pair, as is known in the field of power amplifiers. As shown, the gate of the first transistor 911 is controlled by a first differential signal VP from the input transformer 950, and the gate of the second transistor 912 is controlled by a second differential signal VM from the input transformer 950. The first transistor 911 passes the first differential signal along VD0P, and the second transistor 912 passes the second differential signal along VD0M.

[0050] The first differential transistor pair 910 also includes a first direct current (DC) voltage source 971. The first DC voltage source 971 is configured to apply a first substrate gate bias to the first transistor 911 (for substrate gate 911b) and to the second transistor 912 (for the rear side 912b). By setting the first DC voltage source 971 to a specific voltage, the reverse bias voltages provided to the substrate gates 911b and 912b of the first transistor 911 and the second transistor 912 can be adjusted to a value that provides improved linearity and / or performance for the power amplifier 900.In general, in embodiments where the first differential transistor pair 910 is a class AB transistor pair, adjusting the reverse bias voltages of the first transistor 911 and the second transistor 912 changes the bias point of the first power amplifier 900, improving performance and reducing power consumption. For example, the first DC voltage source 971 can be set to a voltage of approximately 0.2 V.

[0051] The first power amplifier 900 also includes a second differential transistor pair 920, comprising a third transistor 923 and a fourth transistor 924. The third transistor 923 includes a front gate 923a and a substrate gate 923b. The fourth transistor 924 includes a front gate 924a and a substrate gate 924b. The second differential transistor pair 920 can be a Class C transistor pair, as is common in the field of power amplifiers. As shown, the gate of the third transistor 923 is controlled by a first differential signal VP from the input transformer 950, and the gate of the fourth transistor 924 is controlled by a second differential signal VM from the input transformer 950. The third transistor 923 passes the first differential signal along VD0P, and the second transistor 924 passes the second differential signal along VD0M.

[0052] The second differential transistor pair 920 also includes a second DC voltage source 972, designed to apply a second substrate gate bias to the third transistor 923 (to substrate gate 923b) and to the fourth transistor 924 (to substrate gate 924b). By fixing the second DC voltage source 972 to a specific voltage, the reverse bias voltages provided to the substrate gates 911b and 912b of the third transistor 923 and the fourth transistor 924 can be set to a value that provides improved linearity and / or performance of the power amplifier 900, improves power output, and reduces current consumption. For example, the second DC voltage source 972 can be set to a voltage of approximately 0 V.

[0053] The first power amplifier 900 also includes a neutralizing capacitor 930, which comprises a fifth transistor 935 and a sixth transistor 936. The fifth transistor 935 comprises a front gate 935a and a substrate gate 935b. The sixth transistor comprises a front gate 936a and a substrate gate 935b. The neutralizing capacitor 930 also includes a third DC voltage source 973, which is configured to apply a third substrate gate bias to the fifth transistor 935 and the sixth transistor 936. By fixing the third DC voltage source 973 to a specific voltage, the reverse bias voltages of the fifth transistor 935 (to the substrate gate 935b) and the sixth transistor 936 (to the substrate gate 936b) can be set to a value that provides improved linearity and / or performance of the power amplifier 900.In general, in embodiments where the second differential transistor pair 920 is a class C transistor pair, an increase in input power increases the gain of the first power amplifier 900 at lower reverse bias voltages, compared to a class AB transistor pair, whose gain decreases with increasing input power. The gate bias of the class AB and class C pairs can help to increase the flat power gain range to a higher input power level, thereby minimizing AM-AM. Setting the current source 973 to a specific voltage can also minimize AM and PM in the power amplifier 900, since the capacitance of the PMOS pair is matched to the capacitance of the complementary input NMOS pair, thus reducing the variation in input capacitance. For example, the third DC voltage source 973 can be set to a voltage from about 1 volt (V) to about 5 V.

[0054] In the neutralizing capacitor 930, the fifth transistor 935 and the sixth transistor 936 are cross-coupled. In other words, the source of the fifth transistor 935 is connected to the same differential signal as the drain of the sixth transistor 936, and the source of the sixth transistor 936 is connected to the same differential signal as the drain of the fifth transistor 935.

[0055] In the neutralizing cap 930 of the present embodiment, the fifth transistor 935 and the sixth transistor 936 can both be NMOS transistors. In embodiments where the fifth transistor 935 and the sixth transistor 936 are both NMOS transistors, reducing the substrate gate voltage provided by the third DC voltage source 973 can reduce the capacitance of the first power amplifier 900.

[0056] In one embodiment, such as that found, for example, in Fig. As shown in Figure 9, the first power amplifier 900 can further comprise a first harmonic trap 981 connected to VP and a second harmonic trap 982 connected to VM. The first harmonic trap 981 and the second harmonic trap 982 can enable the power amplifier 900 to dampen fluctuations in the input voltages more effectively.

[0057] In one embodiment, such as in Fig. As shown in Figure 9, the first power amplifier 900 can further comprise a stacked transistor pair 940a and a stacked transistor pair 940b. The transistor pair 940a comprises a seventh transistor 947a and an eighth transistor 948a. The seventh transistor 947a comprises a front gate 947c and a substrate gate 947d. The eighth transistor 948a comprises a front gate 948c and a substrate gate 948d. The transistor pair 940b comprises a ninth transistor 947b and a tenth transistor 948b. The ninth transistor 947b comprises a front gate 947e and a substrate gate 947f. The tenth transistor 948b comprises a front gate 948e and a substrate gate 948f. Fig. Component 9 also includes a fourth DC voltage source 974, configured to provide a fourth substrate gate bias for the seventh transistor 947 and the eighth transistor 948. The substrate gates described here provide the substrate gate bias for the transistor with substrate gates.

[0058] By applying predetermined voltages from the voltage sources 974a, 974b to the substrate gates of at least one of the stacked transistor pairs 940a, 940b, the power amplifier 900 can be more efficient when handling higher voltage signals. By setting the fourth DC voltage sources 974a, 947b to a specific voltage, AM and PM in the power amplifier 900 can also be minimized.

[0059] The first transistor 911, the second transistor 912, the third transistor 923, the fourth transistor 924, the fifth transistor 935, the sixth transistor 936, the seventh transistor 947a, the eighth transistor 948a, the ninth transistor 947b, and the tenth transistor 948b can have any architecture known in the art. In one embodiment, the first transistor 911, the second transistor 912, the third transistor 923, the fourth transistor 924, the fifth transistor 935, the sixth transistor 936, the seventh transistor 947a, the eighth transistor 948a, the ninth transistor 947b, and the tenth transistor 948b each comprise an FDSOI transistor.

[0060] Fig. Figure 10 shows a second power amplifier 1000 according to the embodiments described herein. Many elements of the second power amplifier 1000 are similar to the elements of the first power amplifier 900. The reference numerals of similar elements have the same tens and units digits between 9 and 10 and differ in whether the leading digit(s) are "9" or "10". Where similar elements have similar structural features or perform similar functions, the reference numerals in Figure 10 are used to refer to the first power amplifier 900. Fig. The 10 elements presented are not described in detail, and the reader is directed to the discussion of Fig. 9 referred.

[0061] The second power amplifier 1000 comprises an input transformer 1050 and an output transformer 1060. As shown, the input transformer 1050 is connected to VG0, and the output transformer 1060 is connected to ground.

[0062] The second power amplifier 1000 also includes a first differential transistor pair 1010. The first differential transistor pair 1010 comprises a first transistor 1011 and a second transistor 1012. The first and second transistors 1011 each include a front gate and a substrate gate, enabling bias biasing.

[0063] The first differential transistor pair 1010 also includes a first DC voltage source 1071. The first DC voltage source 1071 is configured to provide a first substrate-gate bias for the first transistor 1011 and for the second transistor 1012. In one embodiment, the first DC voltage source 1071 can be set to a voltage of approximately 0 V.

[0064] The second power amplifier 1000 also includes a second differential transistor pair 1020, comprising a third transistor 1023 and a fourth transistor 1024. The third and fourth transistors 1011 each include a front gate and a substrate gate, thus enabling biasing of the substrate gate.

[0065] The second differential transistor pair 1020 also includes a second DC voltage source 1072, configured to provide a second substrate-gate bias for the third transistor 1023 and for the fourth transistor 1024. In one embodiment, the second DC voltage source 1072 can be set to a voltage of approximately 0 V.

[0066] The second power amplifier 1000 also includes a neutralizing capacitor 1030, which comprises a fifth transistor 1035 and a sixth transistor 1036. The fifth and sixth transistors 1011 each comprise a front gate and a substrate gate, allowing for biasing of the substrate gate. The neutralizing capacitor 1030 also includes a third DC voltage source 1073. In one embodiment, the third DC voltage source 1073 can be set to a voltage of approximately 1 V to approximately 5 V.

[0067] In the neutralizing cap 1030 of the present embodiment, the fifth transistor 1035 and the sixth transistor 1036 can both be PMOS transistors. In embodiments where the fifth transistor 1035 and the sixth transistor 1036 are both PMOS transistors, increasing the substrate gate voltage provided by the third DC voltage source 1073 can reduce the capacitance of the second power amplifier 1000.

[0068] In an embodiment as shown in 10, the second power amplifier 1000 may further comprise a first harmonic trap 1081 and a second harmonic trap 1082 connected to VM.

[0069] In one embodiment, as described in Fig. As shown in Figure 10, the second power amplifier 1000 can further comprise at least one stacked transistor pair 1040, wherein each stacked transistor pair 1040 comprises a seventh transistor 1047 and an eighth transistor 1048. The seventh and eighth transistors 1047, 1048 each have a front gate and a substrate gate. The amplifier 1000 can also include a fourth DC voltage source 1074, configured to provide a fourth substrate gate bias for the substrate gates of the seventh transistors 1047a, 1047b and the eighth transistors 1048a, 1048b. For example, Figure 10 shows... Fig. 10 two stacked transistor pairs 1040a, 1040b. The seventh transistors 1047a, 1047b and the eighth transistors 1048a, 1048b each comprise a front gate and a substrate gate, thus enabling substrate gate biasing.

[0070] In one embodiment, the first transistor 1011, the second transistor 1012, the third transistor 1023, the fourth transistor 1024, the fifth transistor 1035, the sixth transistor 1036 and the seventh transistors 1047a are each an FDSOI transistor.

[0071] Fig. Figure 11 provides a flowchart of a method 1100 according to embodiments described herein. As shown, the method 1100 comprises forming (at 1110) a device, such as a power amplifier 900, as shown in Figure 9, or a power amplifier 1000, as shown in Figure 9. Fig. 10 shown, or a device comprising a power amplifier 900 or 1000.

[0072] Method 1100 also includes determining (at 1120) a desired capacitance of a neutralizing cap (e.g., neutralizing cap 930, 1030) of the device (e.g., power amplifier 900, 1000). The average person skilled in the art, benefiting from the present invention, can routinely determine the desired capacitance of the neutralizing cap, taking into account the expected range of parameters of an input signal for the device, the desired parameter range of an output signal of the device, and other characteristics that are desirable based on the expected use of a device comprising the device.

[0073] Method 1100 also includes determining (at 1130) a desired substrate-gate bias voltage which, when applied to a fifth transistor and a sixth transistor, imparts the desired capacitance to the neutralizing capacitor. The average person skilled in the art, benefiting from the present invention and having determined the desired capacitance, can routinely determine the desired substrate-gate voltage.

[0074] In one embodiment, the desired substrate gate bias is approximately 1 V to approximately 5 V.

[0075] Method 1100 also includes selecting and / or specifying (at 1140) a third DC voltage source such that a third substrate gate bias applied to the fifth transistor and the sixth transistor is equal to the third desired substrate gate bias.

[0076] In a further embodiment, method 1100 can also include determining a desired performance level of the device. Method 1100 can subsequently include determining a desired substrate-gate bias voltage which, when applied to the first and second transistors, or the third and fourth transistors, or to all four of the first to fourth transistors, imparts the desired performance level to the device. Method 1100 can further include specifying the first DC voltage source, the second DC voltage source, or both, such that the substrate-gate bias voltage supplied to the various first to fourth transistors is equal to the desired substrate-gate bias voltage, imparting the desired performance level to the device.

[0077] In a further embodiment, wherein the device further comprises at least one stacked transistor pair, each stacked transistor pair comprising a seventh transistor, an eighth transistor, and a fourth DC voltage source configured to provide a fourth substrate-gate bias up to the seventh and eighth transistors, the method 1100 may further comprise determining a desired gain of the device. The method 1100 may subsequently comprise determining a desired substrate-gate bias which, when applied to the seventh and eighth transistors, imparts the desired gain to the device.Method 1100 can further include setting the fourth DC voltage source so that the substrate gate bias supplied to the seventh transistor and the eighth transistor is equal to the desired substrate gate bias which gives the device the desired gain.

[0078] In Fig. Figure 12 is a stylized representation of a system 1200 for manufacturing a semiconductor device housing with a power amplifier 900, 1000 according to the embodiments described herein. A system 1200 of Fig. The system can comprise a semiconductor device processing system 1210 and an integrated circuit design unit 1240. The semiconductor device processing system 1210 can produce integrated circuit assemblies based on one or more designs provided by the integrated circuit design unit 1240.

[0079] The semiconductor device processing system 1210 can include various processing stations, such as etching process stations, photolithography process stations, CMP process stations, etc. Each of the processing stations can include one or more processing tools 1214 and / or measuring tools 1216. Feedback based on data from the measuring tools 1216 can be used to change one or more process parameters used by the processing tools 1214 to perform process steps.

[0080] The semiconductor device processing system 1210 can also include an interface 1212 capable of providing communication between the processing tools 1214, the measuring tools 1216, and a controller such as the processing controller 1220. One or more of the processing steps performed by the semiconductor device processing system 1210 can be controlled by the processing controller 1220. The processing controller 1220 can be a workstation computer, a desktop computer, a laptop computer, a tablet computer, or any other type of computer device that includes one or more software products capable of controlling processes, receiving process feedback, receiving test result data, performing learning cycle adjustments, making process adjustments, etc.

[0081] The Semiconductor Device Processing System 1210 can fabricate integrated circuits on a medium such as silicon wafers. In particular, the Semiconductor Device Processing System 1210 can fabricate integrated circuits that include a power amplifier, as shown in Fig. 9 or Fig. 10 shown.

[0082] The fabrication of integrated circuits by the semiconductor device processing system 1210 can be based on circuit designs provided by the integrated circuit design unit 1240. The semiconductor device processing system 1210 can provide processed integrated circuits / devices 1215 on a transport mechanism 1250, such as a conveyor system. In some embodiments, the conveyor system can be a sophisticated cleanroom transport system capable of transporting semiconductor wafers. In one embodiment, the semiconductor device processing system 1210 can implement several processing steps, such as those described above and in Fig. 11 of the procedures shown 1100.

[0083] In some embodiments, the elements designated “1215” may represent individual wafers, and in other embodiments, the elements 1215 may represent a group of semiconductor wafers, e.g., a “set” of semiconductor wafers. The integrated circuit or device 1215 may comprise a transistor, a capacitor, a resistor, a memory cell, a processor, and / or the like.

[0084] The integrated circuit design unit 1240 of the system 1200 can provide a circuit design that can be manufactured by the semiconductor device processing system 1210. This can include information on whether a power amplifier, as in Fig. 9 or Fig. As shown in Figure 9, it is a power amplifier. Fig. Figure 10 shows which DC voltage is specified for one or more DC voltage sources of the power amplifier; etc.

[0085] The 1240 integrated circuit design unit can determine the number of devices (e.g., processors, memory devices, etc.) to be included in a device package. Based on these device details, the 1240 integrated circuit design unit can determine the specifications of the devices to be manufactured. Based on these specifications, the 1240 integrated circuit design unit can provide data for manufacturing a semiconductor device described herein.

[0086] The System 1200 is capable of analyzing and manufacturing various products using different technologies. For example, the System 1200 can receive design and manufacturing data for producing components using CMOS, flash, BiCMOS, power components, memory devices (such as DRAM), NAND flash memory devices, and / or various other semiconductor technologies. This data can then be used by the System 1200 to manufacture the semiconductor devices described herein.

Claims

[1] Device comprising: an input transformer (950); a first differential transistor pair (910) comprising a first transistor (911), a second transistor (912), and a first DC voltage source (971) configured to apply a first substrate gate voltage to the first transistor (911) and the second transistor (912); a second differential transistor pair (920) comprising a third transistor (923), a fourth transistor (924), and a second DC voltage source (972) configured to apply a second substrate gate voltage to the third transistor (923) and the fourth transistor (924); a neutralization cap (930) comprising a fifth transistor (935), a sixth transistor (936), and a third DC voltage source (973), wherein the fifth transistor (935) and the sixth transistor (936) are cross-connected, the fifth transistor (935) is an NMOS transistor, the sixth transistor (936) is an NMOS transistor, and the third DC voltage source (973) is configured to apply a third substrate gate voltage to the fifth transistor (935) and the sixth transistor (936); and an output transformer (960). [2] The apparatus of claim 1, further comprising a harmonic trap (981, 982). [3] The device of claim 1, further comprising at least one stacked transistor pair (940a, 940b), each stacked transistor pair (940a, 940b) comprising a seventh transistor (947a), an eighth transistor (948a), and a fourth DC voltage source (974) configured to apply a fourth substrate gate voltage to the seventh transistor (947a) and the eighth transistor (948a). [4] The device of claim 3, wherein the device comprises two stacked transistor pairs (940a, 940b). [5] The device of claim 3, wherein the first transistor (911), second transistor (912), third transistor (923), fourth transistor (924), fifth transistor (935), sixth transistor (936), seventh transistor (947a), and eighth transistor (948a) each comprise a front gate and a substrate gate configured to receive a substrate gate voltage. [6] The device of claim 1, further comprising: a harmonic trap (981, 982); and two stacked transistor pairs (940a, 940b), each stacked transistor pair (940a, 940b) comprising a seventh transistor (947a), an eighth transistor (948a), and a fourth DC voltage source (974) configured to apply a fourth substrate gate voltage to the seventh transistor (947a) and the eighth transistor (948a). [7] The device of claim 1, wherein the first transistor (911) and the second transistor (912), the third transistor (923), the fourth transistor (924), the fifth transistor (935) and the sixth transistor (936) are each an FDSOI transistor. [8] Device comprising: an input transformer (1050); a first differential transistor pair (1010) comprising a first transistor (1011), a second transistor (1012), and a first DC voltage source (1071) configured to apply a first substrate gate voltage to the first transistor (1011) and the second transistor (1012); a second differential transistor pair (1020) comprising a third transistor (1023), a fourth transistor (1024), and a second DC voltage source (1072) configured to apply a second substrate gate voltage to the third transistor (1023) and the fourth transistor (1024); a neutralization cap (1030) comprising a fifth transistor (1035), a sixth transistor (1036), and a third DC voltage source (1073), wherein the fifth transistor (1035) and the sixth transistor (1036) are cross-connected, the fifth transistor (1035) is a PMOS transistor, the sixth transistor (1036) is a PMOS transistor, and the third DC voltage source (1073) is configured to apply a third substrate gate voltage to the fifth transistor (1035) and the sixth transistor (1036); and an output transformer (1060). [9] The apparatus of claim 8, further comprising a harmonic trap (1081, 1082). [10] The device of claim 8, further comprising at least one stacked transistor pair (1040a, 1040b), each stacked transistor pair (1040a, 1040b) comprising a seventh transistor (1047), an eighth transistor (1048), and a fourth DC voltage source (1074) configured to apply a fourth substrate gate voltage to the seventh transistor (1047) and the eighth transistor (1048). [11] The device of claim 10, wherein the device comprises two stacked transistor pairs (1040a, 1040b). [12] The apparatus of claim 8, further comprising: a harmonic trap (1081, 1082); and two stacked transistor pairs (1040a, 1040b), each stacked transistor pair (1040a, 1040b) comprising a seventh transistor (1047), an eighth transistor (1048), and a fourth DC voltage source (1074) configured to apply a fourth substrate gate voltage to the seventh transistor (1047) and the eighth transistor (1048). [13] The device of claim 8, wherein the first transistor (1011), the second transistor (1012), the third transistor (1023), the fourth transistor (1024), the fifth transistor (1035) and the sixth transistor (1036) each represent an FDSOI transistor. [14] Method comprising: forming a device comprising: an input transformer (1050); a first differential transistor pair (1010) comprising a first transistor (1011), a second transistor (1012), and a first DC voltage source (1071) configured to apply a first substrate gate voltage to the first transistor (1011) and the second transistor (1012); a second differential transistor pair (1020) comprising a third transistor (1023), a fourth transistor (1024), and a second DC voltage source (1072) configured to apply a second substrate gate voltage to the third transistor (1023) and the fourth transistor (1024); a neutralization cap (1030) comprising a fifth transistor (1035), a sixth transistor (1036), and a third DC voltage source (1073), wherein the fifth transistor (1035) and the sixth transistor (1036) are cross-connected, the fifth transistor (1035) is a PMOS transistor, the sixth transistor (1036) is a PMOS transistor, and the third DC voltage source (1073) is configured to apply a third substrate gate voltage to the fifth transistor (1035) and the sixth transistor (1036); and an output transformer (1060); determining a desired capacity of the neutralization cap (1030); determining a desired substrate gate voltage that, when applied to the fifth transistor (1035) and the sixth transistor (1036), applies the desired capacitance to the neutralization cap (1030); and setting the third DC voltage source (1073) such that the substrate gate voltage is equal to the desired substrate gate voltage. [15] The method of claim 14, wherein the third DC voltage source (1073) provides a substrate gate voltage of 1 V to 5 V. [16] The method of claim 14, wherein the first transistor (1011), the second transistor (1012), the third transistor (1023), the fourth transistor (1024), the fifth transistor (1035) and the sixth transistor (1036) are each an FDSOI transistor. [17] The method of claim 14, further comprising: determining a desired efficiency of the device; determining a desired substrate gate voltage that, when applied to the first transistor (1011) and the second transistor (1012), applies the desired efficiency to the device; and setting the first DC voltage source (1071) such that the substrate gate voltage provided to the first transistor (1011) and the second transistor (1012) is equal to the desired substrate gate voltage that applies the desired efficiency to the device. [18] The method of claim 14, further comprising: determining a desired performance of the device; determining a desired substrate gate voltage that, when applied to the third transistor (1023) and the fourth transistor (1024), applies the desired performance to the device; and setting the second DC voltage source (1072) such that the substrate gate voltage provided to the third transistor (1023) and the fourth transistor (1024) is equal to the desired substrate gate voltage that applies the desired performance to the device. [19] The method of claim 14, wherein the apparatus further comprises: at least one stacked transistor pair (1040a, 1040b), each stacked transistor pair (1040a, 1040b) comprising a seventh transistor (1047), an eighth transistor (1048), and a fourth DC voltage source (1074) configured to apply a fourth substrate gate voltage to the seventh transistor (1047) and the eighth transistor (1048); and the method further comprising: determining a desired gain of the device; determining a desired substrate gate voltage that, when applied to the seventh transistor (1047) and the eighth transistor (1048), applies the desired gain to the device; and setting the fourth DC voltage source (1074) such that the substrate gate voltage provided to the seventh transistor (1047) and the eighth transistor (1048) is equal to the desired substrate gate voltage that applies the desired gain to the device. [20] The method of claim 19, wherein the device comprises two stacked transistor pairs (1040a, 1040b).

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