Uniplanar (single-layer) passive circuit

Abstract

Structure (10) comprising: a passive circuit (16a) with multiple components, each formed in the same wiring plane (16), wherein the multiple components have a resistor in a rod shape (50a) and / or serpentine shape (50b) and wherein a crystal lattice of the resistor is damaged to increase scattering and reduce mobility and conductivity; and connections in the same wiring plane (16) connecting the multiple components of the passive circuit (16a).

Description

Field of the InventionThe present invention relates to semiconductor structures and, more particularly, to a uni planar (e.g., single layer) combined passive circuit and fabrication method.BackgroundPassive circuits include components important for the functioning of a semiconductor device. The passive circuit may include, for example, devices such as inductors, resistors, capacitors, conductors, and transformers. The inductance suppresses a rapid change of a current by inducing a voltage proportional to an amount of a current change. A ratio of the counter electromotive force generated due to the electromagnetic induction according to the change in current flowing in a circuit is referred to as an inductance (L). A resistor is a device having resistance to passage of an electric current. On the other hand, a capacitor is an electric charge storage device that is composed of one or more pairs of conductors separated by an insulator. A power combiner couples a defined amount of electromagnetic power from multiple terminals to a single terminal, thereby increasing the power level of the signals. A transformer is a static electrical device that transfers electrical energy between two or more circuits by electromagnetic induction.The production of the passive circuit components in semiconductor devices consists of lithography, etching and deposition processes on a plurality of wiring levels. In order to connect the separate components and their constituent parts fabricated on different wiring levels to each other, via connections must be made through multiple wiring levels. The via connection structures provide electrical connection of the individual components of the components from one level to another level.For example, in the manufacture of an inductor, a first winding is formed in a first wiring plane and a second winding (or underpass connection) is formed in a second wiring plane. Then, a through connection is made in an intermediate wiring level to connect the first and second windings formed on different wiring levels. Similar processes are also required for other components of the passive circuit and the connection of each component to each other, for example, a resistor in a first wiring level and components of a capacitor formed in second and third wiring levels. These processes become very complex and result in significant process costs and variability. Moreover, the components and their constituent parts in different wiring levels use a considerable area of the semiconductor chip, which is of particular importance when technology nodes continue to scale down.US 6 329 715 B1 discloses passive electronic components with a passive circuit, wherein the passive circuit consists of a conductor track pattern and is mounted on a surface of the insulating layer, and the surface of the insulating layer is preferably polished to allow a smaller pattern area by finer conductor patterns. US 2003 / 0 006 478 A1 describes a method and structure for an integrated circuit chip having a logic core that includes a plurality of isolation and conduction planes, an outer conductor plane, and passive components with a conductive polymer directly connected to the outer conductor plane. US 2007 / 0 294 871 A1 mentions the production process of a semiconductor component in which a metal level is formed within an inter-level dielectric, wherein a first metal line is separated from a second metal line by a region of the inter-level dielectric. The portion of the inter-level dielectric is removed between the first and second metal lines. Subsequently, a high-k dielectric is formed between the first and second metal lines in the region where the inter-level dielectric has been removed, such that a capacitor is formed from the first metal line, the second metal line, and the high-k dielectric. US 2005 / 0 151 249 A1 discloses a chip scale package which contains an integrated passive component at a redistribution layer. U.S. Pat. No. 8,853,819 B2 describes a semiconductor component with an integrated passive network, consisting of a substrate with dielectric and conductive layers for forming passive electronic components such as resistors, inductors and capacitors, including a method for producing the same. US 2017 / 0 213 637 A1 mentions high performance vertically stacked inductors and transformers having a structure that includes a first conductor from a redistribution line, a second conductor from a back-end-of-line wiring layer, and a ferromagnetic material between the first and second conductors. US 6 114 756 A describes a semiconductor device having a two-part coplanar interdigitated decoupling capacitor as part of the conductive lead frame. EP 2 956 948 B1 mentions a coupled inductor structure integrated into a substrate, which has improved performance and efficiency by means of special layout and production processes.SummaryBy way of example, a structure includes: a passive circuit having multiple components each formed in a single wiring level; and interconnects in the same wiring level that connect the multiple components of the passive circuit.Further by way of example, a structure includes: a first passive component and its constituent structures that are composed of a metal wiring and formed exclusively in a single wiring plane; a second passive component and its constituent structures that are composed of a metal wiring and formed exclusively in the single wiring plane; and a metal connection structure that is disposed exclusively in the single wiring plane and that connects the first passive component to the second passive component, thereby forming a passive circuit in the single wiring plane.Further exemplarily, a method of manufacturing a passive circuit includes: forming a first passive component and its constituent structures that are made of a metal wiring and formed exclusively in a single wiring plane; forming a second passive component and its constituent structures that are made of a metal wiring and formed exclusively in the single wiring plane; and forming a metal connection structure exclusively in the single wiring plane and connecting the first passive component to the second passive component, thereby forming a passive circuit in the single wiring plane.According to the invention, a structure according to any one of claims 1 to 5 is provided.Brief Description of the DrawingsThe present invention will be described in the following detailed description with reference to the mentioned plurality of drawings by way of examples of exemplary embodiments of the present invention. FIG. 1 shows a schematic illustration of a passive device / circuit in a single metal layer. FIGS. 2A-2C show various inductor or resistor configurations (structures) implemented in a single redistribution layer in accordance with aspects of the present invention. FIG. 3 illustrates a capacitor configuration (structures) in accordance with aspects of the present invention. FIGS. 4A and 4B show various transformer configurations (structures) in accordance with aspects of the present invention. FIGS. 5A and 5B show various power combiner configurations (structures) in accordance with aspects of the present invention. FIGS. 6A-6C show various configurations of a resistor in accordance with aspects of the present invention. FIG. 7A illustrates a passive circuit including a resistor and an inductor according to aspects of the present invention. FIG. 7B illustrates a passive circuit including a capacitor and an inductor according to aspects of the present invention. FIG. 8 shows a schematic diagram and chip diagram of a passive circuit in a single wiring plane according to aspects of the present invention. FIG. 9 shows an exploded view of the passive circuit in a single wiring plane in accordance with aspects of the present invention. FIG. 10 illustrates simulations of the process variability of the passive circuit fabrication processes at a single wiring level, in accordance with aspects of the present invention. FIG. 11 illustrates a system level design in accordance with aspects of the present invention.Detailed DescriptionThe present invention relates to semiconductor structures and, more particularly, to uni planar passive circuits (e.g., having a single wiring level) and fabrication methods. More particularly, the present invention relates to uni planar (e.g., single layer) passive circuits, such as a combination of resistors, capacitors, inductors, and transformers. Advantageously, by implementing the structures and methods described herein, CMOS processes and related processing complications (e.g., process variances) are significantly reduced compared to conventional passive circuits provided on multiple wiring levels of a semiconductor chip. The passive circuit can also achieve higher power requirements in many different technologies, for example millimeter wave applications and control circuits implemented using SiGe or SOI technologies. For example, the passive circuit may be provided in the redistribution layer and an active circuit may be provided in SiGe / SOI layers of the chip, thereby reducing cost and complexity while achieving higher performance.In embodiments, the passive circuitry, such as resistors, capacitors, inductors, transformers, and power combiners, is provided in a single wiring level of the semiconductor chip, wherein no via connection structures are provided for connecting a single component or components. In embodiments, the passive circuit may be provided in a redistribution layer (redistribution layer) or a back-end-of-line layer of the semiconductor chip, for example. The passive circuitry may be formed by transferring a pattern (e.g., a single patterning process and a single etching process) to a copper sheet (copper sheet). The patterned copper layer may be a discrete part that may be attached to a CMOS chip.The passive circuit may be implemented by a plurality of different components having different shapes on the single wiring level. By way of non-limiting example, the following components and interconnections may be implemented in a single wiring level:(i) inductors may be circular, horseshoe-shaped, and have meandering lines (multiple turns and segments);(ii) capacitors may represent interdigitated metal-on-metal capacitors in a single wiring plane;(iii) coupled inductors may be shaped into a loop or hairpin to form transformers; and(iv) resistors can be formed in a rod-like or serpentine manner.Moreover, the inductors and transformers may be implemented in the redistribution layer using magnetic materials for reduced size when implemented. The capacitors may also be implemented in the redistribution layer with high-k dielectrics, for example, to form a smaller footprint. In further embodiments, any of the passive circuits may be provided in the redistribution layer and an active circuit may be provided in SiGe / SOI layers of the chip.Since the passive circuit is disposed on a single wiring level, there is only a need for a single lithography, etching and deposition process, which saves considerable cost and reduces process variability compared to conventional circuit processes. By implementing the passive circuit on a single layer, it is also possible to provide high μ selective materials and high-k materials for the inductor and the capacitor, respectively, to increase device performance. Moreover, by implementing the passive circuit on a single layer, considerable space on the chip is saved, e.g. the circuits are more compact than conventional circuits on multiple wiring levels.The passive circuit of the present invention can be manufactured in various ways using a number of different tools. Generally, however, the methodologies and tools are used to form structures having dimensions in the micrometer and nanometer range. The methods used to fabricate the passive circuit of the present invention, i.e., technologies, have been adopted by the integrated circuit (IC) technology. For example, the structures are formed on wafers and realized in material layers that are structured on the top side of a wafer by photolithographic processes. In the production of the passive circuit, three basic components are used in particular: (i) depositing thin material layers on a substrate, (ii) applying a patterned mask to the films by photolithographic imaging and (iii) etching the films selectively with respect to the mask.FIG. 1 shows a schematic illustration of a passive circuit on a single layer, among other features and respective fabrication processes, in accordance with aspects of the present invention. More specifically, the structure 10 of FIG. 1 includes back-end-of-line (BEOL) components represented by reference numeral 12. In embodiments, the insulator material 12 amay be an oxide material. An optional magnetic layer 14 is provided between the back end of line components 12 and a redistribution layer 16. In embodiments, the magnetic layer 14 may be used to reduce the inductor size.Redistribution layer 16 is representative of a single wiring layer, which may include any combination of the components of the passive circuitry described herein. For example, the metal material 16 aof the redistribution layer 16 may be representative of any combination of, for example, resistors, capacitors, inductors, transformers, and power combiners formed in a single wiring layer using a single lithography, etching, and metal deposition process. The single process described herein also includes associated interconnects in the single wiring layer to connect the various components and form the passive circuit. Accordingly, and advantageously, passive circuit 16 ain a single wiring level does not require via interconnect structures to connect components formed in different metal layers.The patterning process may be used to provide any desired shape of the components in a single wiring level (e.g., redistribution layer) that includes the passive circuit described herein. The passive circuitry may be fabricated by pattern transfer (e.g., a single patterning process and a single etching process) onto a copper layer, the copper layer being a discrete part that may be mounted on a CMOS chip.Alternatively, and according to an example, the metallization pattern, e.g., passive circuit 16 amay be formed by a resist formed over the insulator material 16 that is exposed to energy (light) to form any structure (opening). A selective chemical etch process, e.g., a reactive ion etch (RIE), is used to form one or more trenches in the insulator material 16 through the openings of the resist in a single wiring plane. The paint may then be removed by a conventional oxygen ashing process or other known removing means. After resist removal, a conductive material may be deposited by any conventional deposition processes, e.g., chemical vapor deposition (CVD) processes, within the trenches to form the components and interconnects of the passive circuitry. Accordingly, the conductive material is deposited on a single metal layer that is free of via structures. Any residual material on the surface of the insulator material 16 may be removed by conventional chemical mechanical polishing (CMP) methods.In this way, the entire passive circuit, e.g., any combination of the resistors, capacitors, inductors, transformers, and power combiners, may be interconnected without requiring additional interconnect structures. As the manufacturing complexity is greatly reduced, the process variability for each of the various passive components is also lower, resulting in robust circuit characteristics (compared to a conventional device). Moreover, by implementing an additional lithography, etching and deposition process, it is also possible to easily introduce other materials into the passive circuit to improve its performance. For example, the insulator material 16 around the inductor and capacitor may be removed and replaced with selective high μ and high-k materials to increase device performance.FIGS. 2A-2C show various inductor or resistor configurations (structures) in accordance with aspects of the present invention. For example, the inductor (or resistor) 18 ashown in FIG. 1 may be a toroidal coil (e.g., horseshoe shaped); whereas the inductor (or resistor) 18 bin FIG. 2B represents a meandering line (e.g., multiple turns / segments). FIG. 2C shows that the inductors 18 c, 18 c", 18 c" may have different thicknesses tailored to different powers. The inductors 18 c, 18 c", 18 c" of FIG. 3 may be implemented in many different forms, as shown in FIGS. 2A and 2B.More specifically, the inductor (or resistor) 18 aof FIG. 2A includes metal lines provided on a single metal layer formed in a ring shape with an opening 20 between the terminals P 1, P 2. In the inductor (or resistor) 18b of FIG. 2B, the metal lines are patterned in a stepped sinusoidal pattern with the terminals P1, P2 at each respective end. In embodiments, the distance between each successive segment in the meandering inductor / resistor 18 bmay be increased at a constant rate or any other monotone rate (including periodically constant) moving from one port P 1 to the other port P 2. The thickness of the meandering windings can be varied depending on the frequency band, wherein a higher thickness applies for low frequency bands and a lower thickness applies for high frequency bands. Also contemplated herein are some other shapes for the inductors (or resistors), e.g., circular loops, fractals, along with a meandering line.The inductors 18 c, 18 c', 18 c" shown in FIG. 3 may represent a single inductor or multiple inductors. In each of the various scenarios, the inductors 18 c, 18 c', 18 c" or segments thereof may have different thicknesses that are matched to different frequencies. In embodiments, the thicker inductor 18 cis used for a smallest frequency, freq 1, the thinnest inductor 18 c" is used for the highest frequency, freq 3, and the medium thickness inductor is used for a medium frequency, freq 2, where freq 1<freq 2<freq 3. freq 3 may be, for example, 5 GHz and freq 1 may be 1 GHz, where freq 2 may be between 5 GHz and 1 GHz. In this way, the inductors can be adjusted for different frequencies. In addition, a pitch of each successive segment of the meandering windings can be increased at a constant rate or another monotone rate with a narrower pitch for low frequency bands and a higher pitch for higher frequency bands.Still referring to FIGS. 2A-2C, to increase density, inductors 18A-18C" (or a transformer made of multiple inductors) may be embedded in either insulator material or a high μ material. In the case of a high μ material, this material may be selectively deposited around the coil windings (or transformers) in the same wiring plane. The high μ material may be, for example, a ferromagnetic alloy with very high permeability used to increase inductance density while shielding sensitive electronic devices from static or low frequency magnetic fields. The high μ material may be iron-nickel alloys and in particular about 77% nickel, 16% iron, 5% copper and 2% chromium or molybdenum. As another example, the high μ material may be formed of about 80% nickel, 5% molybdenum, minor amounts of various other elements such as silicon, and iron as the remaining 12 to 15%.FIG. 3 shows a capacitor configuration (structure) according to aspects of the present invention. As shown in FIG. 3, the capacitor 22 may represent a metal-insulator-metal capacitor with interdigitated fingers 22 a, 22 b(e.g., interdigitated comb structures) in a single wiring plane. In embodiments, the interdigitated fingers 22 a, 22 brepresent a first capacitor plate and a second capacitor plate, respectively, wherein the insulator material separates the two capacitor plates. The width and distance between the interdigitated fingers 22a, 22b may be varied to improve performance at different frequency bands. Additionally, the capacitor 22 may be surrounded by a high-k dielectric to improve performance. The high-k dielectric material is provided in the same wiring level and may be any high-k dielectric material, e.g., HfO 2, Al 2 O 3, Ta 2 O 3, TiO 2, La 2 O 3, SrTiO 3, LaAlO 3, ZrO2, Y2O3, Gd2O3, and combinations thereof, the plurality of layers.FIGS. 4A and 4B show various transformer configurations (structures) in accordance with aspects of the present invention. More specifically, the transformer 30a shown in Fig. 4A represents a loop transformer; the transformer 30b shown in Fig. 4B represents a meandering transformer. The loop transformer 30a includes two separate metal lines (e.g., the primary inductor 30a' and the secondary inductor 30a") formed in a single metal layer in annular form with an opening 20 between the terminals P+, P-, S+, S-. In FIG. 4A, the terminals P+, P-, S+, S- are on the same side, respectively. In embodiments, transformers 30 a, 30 bmay also be embedded in either an insulator material or a high μ material for increased density, as already described herein. Those skilled in the art should also understand that several other shapes are contemplated for the transformer here, e.g., a circular loop, along with a meandering line.Referring to FIG. 4B, the meandering transformer 30b includes two metal lines (e.g., the primary inductor 30b' and the secondary inductor 30b"), each of which is patterned in a stepped sinusoidal pattern in a single metal layer, with the terminals P+, P- being on a side opposite to the terminals S+, S-. In this embodiment, meandering transformer 30b includes a distance between each successive segment that can be increased at a constant rate or any other monotone rate (including periodically constant) moving from one terminal P1 to the other terminal P2.FIGS. 5A and 5B show various power combiner configurations (structures) in accordance with aspects of the present invention. More specifically, the power combiners 40a shown in Figs. 5A and 5B each include a plurality of ring coils 40a' and a meandering transformer 40a". As shown in each of these configurations, the respective ring coils 40a' are provided in a portion of the meandering transformer 40a". In FIG. 5A, the terminals P+, P-, S+, S- are each on the same side, while in FIG. 5B, the terminals P+, P- are on a side opposite to the terminals S+, S-. It should also be appreciated that the thicknesses of the various power combiner configurations may vary along their length, e.g., portions have a selectively thicker and thinner portion. In particular, the meandering transformer 40a" may include a variation in thickness based on the voltage inputs to the plurality of ring coils 40a'. For example, thicker portions may be used to handle higher currents (voltages) and electromigration problems occurring at higher currents (voltages).FIGS. 6A-6C show various configurations of a resistor in accordance with aspects of the present invention. More specifically, FIG. 6A shows a rod-shaped resistor 50a, and FIG. 6B shows a serpentine-shaped resistor 50b (stepped sinusoidal). FIG. 6C shows a slotted resistor 50c. Although two slots 50c' are shown in FIG. 6C, it should be appreciated that any number of slots 50c may be provided to reduce or increase the overall resistance of resistor 50c. Additionally, the slots 50c' may have different widths to reduce or increase the overall resistance of the resistor 50c. For example, a wider slot or slots increase the overall resistance of resistor 50 cbecause of less metal present in the resistor itself. Similarly, the resistance of the rod-shaped resistor 50 aor the serpentine resistor 50 bmay be increased or decreased by decreasing or increasing the thickness of the rod-shaped resistor 50 aand the serpentine resistor 50 b, respectively.In further embodiments, each of the resistors 50a, 50b, 50c shown in Figures 6A-6C may be subjected to high energy implantation to increase its resistivity. For example, the resistors 50 a, 50 b, 50 cmay be exposed to a high energy (e.g., 4-10 keV) He ion beam, thereby damaging the crystal lattice, resulting in increased scattering and lower mobility and conductivity (and thus higher resistance).FIG. 7A shows a combination of a passive circuit including a resistor 50 and an inductor 18 in accordance with aspects of the invention. In embodiments, the resistor 50 and the inductor 18 are formed in a single wiring layer, e.g., redistribution layer, without the need for via connections. The resistor 50 and the inductor 18 may also have different thicknesses, with the resistor 50 having a thickness T 1 that is less than the thickness T 2 of the inductor 18, e.g., T 1<T 2. It will be appreciated by those skilled in the art that reducing the thickness of resistor 50 results in a small width (e.g., less metal) and thus an increase in the resistance. The resistor 50 may also be exposed to a high energy (e.g., 4-10 keV) He ion beam that damage the crystal lattice, resulting in increased scattering and lower mobility and conductivity (and thus higher resistance). In embodiments, resistor 50 and inductor 18 may be formed by either a subtractive or additive process, as understood by those skilled in the art, and thus no further explanation is required herein.FIG. 7B shows a combination of a passive circuit including an inductor 18 and a capacitor 22, in accordance with aspects of the invention. In embodiments, the inductor 18 and the capacitor 22 are formed in a single wiring layer, e.g., redistribution layer, without the need for via connections. The inductor 18 and the capacitor 22 may also have different thicknesses, where the inductor 18 has a thickness T 3 that is less than the thickness of the capacitor 22 of T 4, T 3<T 4, for example. It will be appreciated by those skilled in the art that the increase in thickness of the capacitor 22 results in more metal and thus an increase in capacitance. In embodiments, capacitor 22 and inductor 18 may be formed by either a subtractive or additive process as understood by those skilled in the art, so no further explanation is required herein to fully understand the present structures.FIG. 8 shows both a schematic diagram 150 and a chip image of the passive circuit 160 at a single wiring level according to aspects of the present invention. More specifically, FIG. 8 shows multiple inductors L 1, L 2, L 3 and multiple capacitors C 1, C 2 interconnected in a single wiring plane in the chip image to form passive circuitry 100 (without requiring via structures). In this configuration, the inductors L 1, L 2, L 3 are illustrated as meandering lines and the capacitors C 1, C 2 are interdigitated metal-insulator-metal capacitors (e.g., a interdigitated finger comb structure) that are each interconnected by interconnects 250 in the same wiring plane (therefore, no via interconnects for forming the passive circuit).Accordingly, as shown, various components, e.g., inductors, capacitors, resistors, etc., may be embedded in a single wiring plane and interconnected by implementing the structures and processes described herein to reduce overall size. These various components may form passive circuits in the redistribution layer or in other device layers (including one or more of the back-end-of-line layers). Moreover, a single chip may include multiple different wiring levels with a combination of the individual wiring levels including the passive circuits described herein. The passive circuit may also be provided in the redistribution layer and each active circuit may be provided in SiGe / SOI layers of the chip.FIG. 9 shows a three-dimensional view of a passive circuit in a single wiring plane according to aspects of the present invention. In this illustration, the plurality of inductors L 1, L 2, L 3 are shown to have different sizes and are embedded in a selectively disposed high μ material 200. In addition, the plurality of capacitors C 1, C 2 are metal-insulator-metal interdigitated capacitors (e.g., a comb-structure with interdigitated fingers) of different sizes connected to the plurality of inductors L 1, L 2, L 3 through interconnects 250 on the same wiring level. The capacitors C 1, C 2 are shown embedded in a selectively placed high-k material 300.And, as also shown in the illustration of FIG. 9, by implementing the structures shown here, in a single wiring level, a first plate of the multi-finger capacitors C 1, C 2, a portion of the same wiring level that forms the second plate of the multi-finger capacitors C 1, C 2, and a first metal interconnect 250 that uses the same wiring level can be formed to connect a last winding / last winding segments of one of the plurality of inductors L 1, L 2, L 3 also in the same wiring level. A metal interconnect 250 using the same wiring level may also be connected to a primary wiring of a transformer 350 having one or more turns / segments, with a portion of the same wiring level forming the secondary wiring of the transformer 350 having one or more turns / segments. Additionally or alternatively, a metal interconnect 250 using the same wiring level may be connected to segments (the first and last segments) of a resistor 400 using the same wiring level, etc.FIG. 10 shows simulated results illustrating the effect of variability in manufacturing processes on the passive circuit implemented using a single wiring level in accordance with aspects of the present invention. In particular, the diagrams of FIG. 10 show that the process variability for the passive circuit fabrication is well centered, e.g., minimal process variability. Graph (a) shows a frequency centered primarily at about 61 GHz. Graph (b) shows a 3dB bandwidth centered primarily at about 22.5 GHz. Curve (c) shows an insertion loss centered primarily at about 1.4 dB; plot (d), on the other hand, shows a return loss centered primarily at about 18 dB. Accordingly, it is seen that the filter has a substantially lower process variability and is therefore more robust (compared to conventional circuits provided on multiple levels).FIG. 11 illustrates a system level design in accordance with aspects of the present invention. In particular, the system-level design includes the passive circuits 100 provided in the redistribution layer 16 and the active circuit 500 in the SiGe / SOI layers of the chip 510. As shown in FIG. 11, the passive circuits 100 may be high-power passive circuits 100 exclusively incorporated in the redistribution layer 16. In embodiments, the high-power passive circuit 100 may include filters, couplers, splitters, combiners in addition to or as an alternative to the passive circuit already described herein. The active circuit 500 may include, as examples, digital, analog, and RF blocks. For example, the active circuit may include MOS / NPN transistors built on the front-end-of-line (FEOL) using the back-end-of-line (BEOL) in the passive circuit SOI / SiGe chip 510. As shown in FIG. 11, the passive circuits 100 are connected to the active circuits 500 via via interconnects 550 that extend through a dielectric material 560 (where the redistribution layer 16 is bonded to one side of the dielectric material 560 and the chip 520 is bonded to another side of the dielectric material 560).The method or methods described above are used in the production of integrated circuit chips. The resulting integrated circuit chips may be sold by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare chip, or in packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier with terminals attached to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier with surface interconnections and / or buried interconnections). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The final product may be any product that includes integrated circuit chips, from toys and other low-end applications to advanced computer products with display, keyboard, or other input device and central processor.

Claims

A structure (10) comprising: a passive circuit (16a) having a plurality of components each formed in the same wiring plane (16), wherein the plurality of components have a resistance in a rod shape (50a) and / or serpentine shape (50b), and wherein a crystal lattice of the resistance is damaged to increase scattering and reduce mobility and conductivity; and interconnects in the same wiring plane (16) that connect the plurality of components of the passive circuit (16a).A structure (10) comprising: a passive circuit (16a) having a plurality of components each formed in the same wiring plane (16); and interconnects in the same wiring plane (16) connecting the plurality of components of the passive circuit (16a), the plurality of components representing a resistor (50) and an inductor (18) connected together in the same wiring plane (16), the inductor (18) having a thickness (T2) greater than a thickness (T1) of the resistor (50).A structure (10) comprising: a passive circuit (16a) having a plurality of components each formed in the same wiring plane (16), the plurality of components representing a plurality of inductors (18) having matched different thicknesses, a greater thickness matched to a lower frequency than a smaller thickness; and interconnects in the same wiring plane (16) connecting the plurality of components of the passive circuit (16a).A structure (10) comprising: a passive circuit (16a) having a plurality of components each formed in the same wiring plane (16), the plurality of components representing at least an inductor and a capacitor, the capacitor (22) having an adjusted thickness (T4) that is greater than a thickness (T3, T1) of the inductor (18); and interconnects in the same wiring plane (16) that connect the plurality of components of the passive circuit (16a).A structure (10) comprising: a passive circuit (16a) having a plurality of components each formed in the same wiring plane (16); and interconnects in the same wiring plane (16) connecting the plurality of components of the passive circuit (16a), wherein the plurality of components comprise one or more metal-insulator-metal capacitors (22) formed as interdigitated comb structures in the same wiring plane (16), and wherein a width and a distance between fingers (22a, 22b) of the interdigitated comb structures are varied for different frequency bands, wherein a thickness of a wiring is selectively increased, resulting in increased sidewall capacitance with the comb structure.The structure (10) of any of claims 1 to 5, wherein the plurality of components are formed exclusively in a redistribution layer (16) and do not have via connections.The structure (10) of any of claims 1 to 5, wherein the plurality of components are patterned on a copper layer that is a discrete part attached to a CMOS chip.The structure (10) of any of claims 1 to 5, wherein the plurality of components comprise one or more metal-insulator-metal capacitors (22) formed as interdigitated comb structures with a high-k dielectric material selectively disposed within the comb structures in the same wiring plane.The structure (10) of any of claims 1 to 5, further comprising an active circuit (500) in a front-end-of-line or back-end-of-line layer of a SiGe or SOI chip (510), wherein the passive circuit (100) is provided exclusively in a redistribution layer (16) and the passive circuit (100) is connected to the active circuit (500) by via connection structures (550) extending through a dielectric material (560).The structure (10) of any of claims 1 to 5, wherein the plurality of components comprises one or more inductors and / or transformers having a high μ material selectively disposed around the one or more inductors and / or transformers.The structure (10) of any of claims 1 to 5, wherein the plurality of components comprise one or more inductors (18b) consisting of meandering windings whose total width or length changes at a constant rate or at a monotone rate, wherein the thickness of the meandering windings varies depending on the frequency band, and wherein a distance from each consecutive segment of the meandering windings is increased at a constant rate or another monotone rate with a smaller distance for low frequency bands and a higher distance for higher frequency bands.

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