DIGITAL VOIDED NOISE INSUCTED BY TIME VOIDES

By digitally subtracting the drive signal from the rate signal to eliminate clock-induced noise, the noise performance of MEMS gyroscopes is enhanced, enabling a low-power phase-locked loop and improving signal quality.

DE102019209172B4Active Publication Date: 2026-05-07ROBERT BOSCH GMBH
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Patent Information

Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
ROBERT BOSCH GMBH
Filing Date
2019-06-25
Publication Date
2026-05-07

AI Technical Summary

Technical Problem

MEMS gyroscopes face significant noise issues due to large quadrature signals, which are folded into the signal band by clock fluctuations, necessitating stringent clock signal requirements and reducing noise performance.

Method used

A digital phase-correct demodulation technique is employed to subtract the sampled drive signal from the sampled rate signal, effectively canceling noise induced by clock fluctuations in the digital section, allowing for a low-power phase-locked loop implementation.

Benefits of technology

This approach reduces the need for a low-noise oscillator, achieving a better power-to-noise ratio and improving noise performance in gyroscopic sensors.

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Abstract

System for processing signals from a gyroscope (102), comprising: at least one drive channel (104) designed to receive an output from a drive axis (110) of the gyroscope (102), wherein the at least one drive channel (104) includes the following: a drive channel analog-to-digital converter (ADC) (112) which receives a drive signal from the drive channel (104) and outputs a digitized drive signal; a drive channel phase-correct demodulator (114) that receives the digitized drive signal and generates a phase-correct demodulated drive signal; at least one drive channel filter (118) that receives the phase-correct demodulated drive signal and outputs a filtered phase-correct demodulated drive signal; and a phase-locked loop (PLL); a detection channel (106) designed to receive an output from a detection axis (108) of the gyroscope (102), wherein the detection channel (106) includes the following: a capture channel ADW (124) that receives an analog rate signal from the capture channel (106) and outputs a digitized rate signal; and a digital signal processor (125) which includes the following: a detection channel phase-correct demodulator (126) that receives the digitized rate signal and generates a phase-correct demodulated rate signal; a capture channel quadrature-phase demodulator (128) that receives the digitized rate signal and generates a quadrature-phase demodulated rate signal; a first acquisition channel filter (130) that receives the phase-correct demodulated rate signal and outputs a filtered phase-correct demodulated rate signal; and a second acquisition channel filter (132) that receives the quadrature-phase demodulated rate signal and outputs a filtered quadrature-phase demodulated rate signal; and a digital subtraction circuit (134) that subtracts the filtered phase-correct demodulated drive signal from the filtered phase-correct demodulated rate signal to generate a sensing axis output signal.
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Description

TECHNICAL AREA

[0001] The present invention relates generally to gyroscopic sensors and in particular to circuits for error correction in an output signal from a gyroscopic sensor. GENERAL STATE OF THE ART

[0002] Gyroscopes are commonly used to detect the rotation or orientation of an object along one or more axes of rotation. For example, gyroscopes have long been used in ships, aircraft, and spacecraft to identify vehicle rotation and for use in stability control systems. More recently, gyroscopes have been incorporated into microelectromechanical devices, or MEMS devices. While classical gyroscopes rotate around an axis, MEMS gyroscopes typically incorporate vibrating elements formed using photolithographic processes within an integrated circuit suitable for mounting on a printed circuit board or with other electronic components.When the MEMS device rotates around an axis, the plane of oscillation of the vibrating element tends to remain constant, and a modulated electrical signal from the MEMS sensor corresponds to the position of the mounting for the MEMS device around the axis. Some MEMS devices incorporate multiple vibrating gyroscope elements, enabling the detection of rotation along multiple axes in three-dimensional space.

[0003] For the further expansion of gyroscopes into more demanding UE applications, a move towards smaller processing nodes for ASIC implementation and a shift towards more digitally centered designs can be observed. An efficient way to implement this shift to more digital is to digitize the signals coming from the gyroscope right at the beginning.

[0004] The output of a vibrational MEMS gyroscope has two main signal components: the desired rate signal and the quadrature signal. The latter is an unwanted error signal that has the same frequency but a 90° phase shift relative to the rate signal. This quadrature signal can be several times larger than the full rate signal that the system is intended to measure.

[0005] Since the quadrature signal has the same frequency as the rate signal, sampling the quadrature signal will fold the oscillator's near-phase noise into the signal band, thus reducing the system's noise performance. The larger the quadrature, the greater the noise disadvantage.

[0006] Due to the large quadrature signals of today's MEMS gyroscopes, directly sampling the gyroscope output requires a clock signal with very low clock fluctuations to avoid noise convolution of the fluctuations in the presence of a large quadrature signal.

[0007] Publication US 2015 / 0 057 959 A1 describes a system and procedure for zero-point shift drift reduction in a gyroscope by demodulation phase error correction. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 represents a first embodiment of a circuit for canceling noise induced by clock fluctuations in a digital gyroscope. Fig. Figure 2 represents a second embodiment of a circuit for canceling noise induced by clock fluctuations in a digital gyroscope. Fig. Figure 3 represents a third embodiment of a circuit for canceling noise induced by clock fluctuations in a digital gyroscope. DETAILED DESCRIPTION

[0008] For the purpose of promoting an understanding of the principles of the present invention, reference is now made to the embodiments illustrated in the drawings and described in the following written specification. It is understood that this is not intended to limit the scope of protection of the invention. It is further understood that the present invention includes any variations and modifications to the illustrated embodiments and further applications of the principles of the invention, such as would normally occur to a person skilled in the art in the field to which this invention belongs.

[0009] As used here, the term "phase-correct signal" refers to a signal from a sensor, such as a gyroscope, that carries information from the sensor corresponding to a property the sensor measures during operation. For example, the phase-correct signal from a vibrating gyroscope is a modulated signal that corresponds to the movement of a vibrating element within the gyroscope.

[0010] As used here, the term quadrature signal refers to a different signal from the sensor that exhibits a quadrature phase (90° phase shift) relative to the phase-correct signal. This quadrature signal is also called a quadrature error signal. Ideally, the phase-correct signal is completely separate from the quadrature phase signal. However, the phase shift error can make measuring the phase-correct signal alone difficult in practical circuits.

[0011] In a highly digital gyroscope, not only the rate signal (including the quadrature) but also the displacement signal of the drive section is sampled with an ADW. This displacement signal has the same frequency and phase as the quadrature signal sampled in the rate channels. Since the drive signal is sampled at the same clock, the sampled drive signal will exhibit the same near-phase noise folded into the signal band as the sampled quadrature in the rate signal. Therefore, we can subtract the sampled drive signal from the sampled rate signal to eliminate the noise in the rate signal induced by clock fluctuations. The advantage of this technique is that it reduces the near-phase noise requirement of the PLL, as it can eliminate this noise in the digital post-processing stage, thus enabling a low-power PLL implementation.

[0012] In contrast to building a very low-noise oscillator, which imposes severe limitations regarding the power-to-noise ratio, the technique presented here allows for the subsequent cancellation of noise induced by clock fluctuations in the digital section. Therefore, the noise requirement for the oscillator becomes less stringent, and a much better power-to-noise ratio can be achieved.

[0013] Fig. Figure 1 is a schematic diagram of an embodiment of an open gyroscope circuit 100 designed to cancel clock-induced noise in the output signal. The circuit 100 includes a gyroscope 102 and an integrated circuit 103, such as an application-specific integrated circuit (ASIC). The gyroscope 102 includes at least one sensing element 108 for sensing along at least one axis. The gyroscope 102 may include three sensing elements 108 for sensing along the three axes (e.g., x, y, z). The gyroscope also includes at least one drive axis 110.

[0014] In circuit 100, the gyroscope 102 is a vibrating gyroscope, such as a MEMS gyroscope used in mobile electronic devices, or any other suitable vibrating gyroscope. The sensing elements 108 detect rotation about three sensing axes, each designed to generate a signal corresponding to the movement of a vibrating element and each corresponding to a rotation of the gyroscope along each of the x, y, and z axes. The x, y, and z axes correspond to three orthogonal axes of rotation in the physical world. In another embodiment, the gyroscope includes only one axis or another configuration of multiple sensing elements arranged on multiple axes.

[0015] In Fig. Assembly 1 includes ASIC 103, acquisition channels 106, a drive channel 104, and digital processors 119 and 125. A separate acquisition channel 106 is electrically connected to an output of each acquisition axis 108. Each acquisition channel 106 includes an analog-to-digital converter (ADC) 124 and a digital processor 125 (i.e., the digital post-stage). The digital processors 119 and 125 are implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or any other digital processing device. The digital processor 125 is designed to implement a digital phase-correct demodulator 126, a digital quadrature-phase demodulator 128, and filters 130 and 132 for the demodulators.

[0016] The phase-correct demodulator 126 generates a demodulated signal that corresponds to the phase-correct component (I sense) of the digitized output signal from the associated acquisition channel 106 via the ADW 124. The quadrature-phase demodulator 128 generates a demodulated signal that corresponds to the quadrature-phase component (Q). sense ) of the digitized output signal from the ADW 124. The digital processor 125 applies at least one filter 130, e.g. a low-pass filter, to the phase-correct signal (I sense ) from the phase-correct demodulator 126 and at least one filter 132, e.g. a low-pass filter, to the quadrature signal (Q sense ) from the quadrature-phase demodulator 128.

[0017] The drive axis 110 receives a drive signal that generates a vibration in the vibrating elements of each of the sensing axes 108. The drive axis 110 drives the sensing mass at a predetermined frequency to enable each of the sensing axes 108 to vibrate at a predetermined frequency. The drive channel 104 is connected to the output of the drive axis 110. The drive channel 104 includes an ADW 112, a digital phase-correct demodulator 114 for demodulating a phase-correct component (I drive ) of the drive signal, a digital quadrature-phase demodulator 116 for demodulating a quadrature-phase component (Q drive ) of the drive signal and at least one filter 118, e.g. a low-pass filter, for filtering out the phase-correct component I drive of the drive signal.

[0018] The drive channel 104 can also include a phase-locked loop (PLL) controller 120 and an amplitude controller 122. The output of the quadrature-phase demodulator 116 (Q drive The input signal is received by the amplitude controller 122. The amplitude controller 122 generates the drive signal, which is fed back to the drive axis 110. The amplitude controller 122 regulates the amplitude of the drive signal to maintain the amplitude of the oscillation for the gyroscope 102 at a predetermined level. The demodulators 114, 116 and the filter(s) 118 can be implemented by the digital processor.

[0019] The PLL controller 120 receives the filtered phase-correct component (I drive) of the drive signal from filter 118 and generates a clock control signal, which is fed to a digitally controlled oscillator (DCO) 121. The DCO 121 outputs a clock signal based on the clock control signal to the demodulation clock signal generator 123, which generates the demodulation clock signals for the I / Q demodulators 114, 116, 126, 128.

[0020] To eliminate the noise induced by clock fluctuations, the filtered phase-correct component (I) is used. drive ) of the drive signal from filter 118 and the filtered phase-correct component (I sense ) of the rate signal from filter 130 is supplied as input to a digital adder / subtractor 134, where the digital phase-correct drive signal (I drive ) from the digital phase-correct rate signal I senseis subtracted to cancel out the noise induced by clock fluctuations in the rate signal. Before reaching the adder / subtractor 134, the phase-correct component (I) can be drive The drive signal is scaled in a multiplier 131 by a scaling factor. The scaling factor is set by the output of the quadrature-phase demodulator 128, which is fed to the multiplier 131 after being filtered by at least one filter 132, e.g., a low-pass filter. The output of the digital adder / subtractor 134 is the output signal for the associated gyroscope sensing axis.

[0021] Fig. 2 represents another embodiment of an open gyroscope readout circuit 100' designed to eliminate noise induced by clock fluctuations in a digital gyroscope. Fig. 2 represents a more general solution to the problem of canceling out noise induced by clock fluctuations. In Fig. 2 The circuit 100' includes a gyroscope 102 and an ASIC 103 with at least one drive channel 104 and at least one sensing channel 106. In the embodiment of Fig. 2 The drive channel 104 includes an ADW 112, a digital PLL controller 120, and a digital amplitude controller 122. The at least one sensing channel 106 includes an ADW 124 and digital signal processing 140. In this embodiment, the digital post-stage signal processing 140 is designed to subtract the sampled drive signal from the sampled rate signal in order to eliminate the noise in the rate signal induced by clock fluctuations.

[0022] The embodiment of Fig. 3 is the embodiment of Fig.1 similar, except that the quadrature-phase demodulator 114 and the filter 118 are for the phase-correct drive signal I drive are integrated into the digital processing circuits for the acquisition channel. In the embodiments described above, the acquisition and drive ADWs can be implemented by delta-sigma modulators. Additionally, in the embodiments described above, the digital filters can be implemented by decimation filters.

[0023] Although the invention has been illustrated and described in detail in the drawings and the preceding description, it should be regarded as being illustrative and not limiting in nature.

Claims

[1] System for processing signals from a gyroscope (102), comprising: at least one drive channel (104) designed to receive an output from a drive axis (110) of the gyroscope (102), wherein the at least one drive channel (104) includes the following: a drive channel analog-to-digital converter (ADC) (112) which receives a drive signal from the drive channel (104) and outputs a digitized drive signal; a drive channel phase-correct demodulator (114) that receives the digitized drive signal and generates a phase-correct demodulated drive signal; at least one drive channel filter (118) that receives the phase-correct demodulated drive signal and outputs a filtered phase-correct demodulated drive signal; and a phase-locked loop (PLL); a detection channel (106) designed to receive an output from a detection axis (108) of the gyroscope (102), wherein the detection channel (106) includes the following: a capture channel ADW (124) that receives an analog rate signal from the capture channel (106) and outputs a digitized rate signal; and a digital signal processor (125) which includes the following: a detection channel phase-correct demodulator (126) that receives the digitized rate signal and generates a phase-correct demodulated rate signal; a capture channel quadrature-phase demodulator (128) that receives the digitized rate signal and generates a quadrature-phase demodulated rate signal; a first acquisition channel filter (130) that receives the phase-correct demodulated rate signal and outputs a filtered phase-correct demodulated rate signal; and a second acquisition channel filter (132) that receives the quadrature-phase demodulated rate signal and outputs a filtered quadrature-phase demodulated rate signal; and a digital subtraction circuit (134) that subtracts the filtered phase-correct demodulated drive signal from the filtered phase-correct demodulated rate signal to generate a sensing axis output signal. [2] System according to claim 1, wherein the detection channel ADW (124) and the drive channel ADW (112) are implemented as delta-sigma modulators. [3] System according to claim 1, wherein the at least one drive channel filter (118), the first detection channel filter (130) and the second detection channel filter (132) are implemented by decimation filters. [4] System according to claim 1, wherein the PLL includes a PLL controller (120) and an amplitude controller (122), and wherein the PLL controller (120) receives the filtered phase-correct demodulated drive signal and outputs a clock control signal. [5] System according to claim 4, wherein the drive channel (104) further comprises a drive channel quadrature phase demodulator (116) which receives the digitized drive signal and generates a quadrature phase demodulated drive signal. [6] System according to claim 5, wherein the amplitude controller (122) receives the quadrature-phase demodulated drive signal and outputs the drive signal to the drive axis (110). [7] System according to claim 1, wherein the filtered phase-correct demodulated drive signal is multiplied by a scaling factor in a multiplier circuit (131) before being fed to the digital subtraction circuit (134), wherein the scaling factor depends on the quadrature-phase demodulated rate signal. [8] System according to claim 1, wherein the drive channel phase-correct demodulator (114) and the at least one drive channel filter (118) are implemented by the PLL. [9] System according to claim 1, wherein the drive channel phase correct demodulator (114) and the at least one drive channel filter (118) are implemented by the digital signal processor (125) or a further digital signal processor (119). [10] System for processing signals from a gyroscope (102), comprising: at least one drive channel (104) designed to receive an output from a drive axis (110) of the gyroscope (102), wherein the at least one drive channel (104) includes the following: a drive channel analog-to-digital converter (ADC) (112) which receives a drive signal from the drive channel (104) and outputs a digitized drive signal; and a phase-locked loop (PLL) that receives the digitized drive signal from the drive channel ADW (112); and a detection channel (106) designed to receive an output from a detection axis (108) of the gyroscope (102), wherein the detection channel (106) includes the following: a capture channel ADW (124) that receives an analog rate signal from the capture channel (106) and outputs a digitized rate signal; and a digital signal processor (125) designed to receive the digitized rate signal from the sensing channel ADW (124) and the digitized drive signal from the drive channel ADW (112) and to subtract a phase-correct component of the digitized drive signal from a phase-correct component of the digitized rate signal to generate a sensing axis output signal. [11] System according to claim 10, wherein the PLL includes a PLL controller (120) and an amplitude controller (122), and wherein the PLL controller receives the digitized drive signal from the drive channel ADW (112) and outputs a clock control signal. [12] System according to claim 11, wherein the amplitude controller (122) receives the digitized drive signal from the drive channel ADW (112) and outputs the drive signal to the drive axis (110).

Citation Information

Patent Citations

  • System And Method For Gyroscope Zero-Rate-Offset Drift Reduction Through Demodulation Phase Error Correction

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