Stacked high-blocking III-V semiconductor power diode

Abstract

Stacked high-blocking III-V semiconductor power diode (10) having in the layer sequence mentioned - a first metallic contact layer (20) that is at least partially formed, - a highly doped first semiconductor contact layer (16) of a first conductivity type, at least partially formed, with a dopant concentration of at least 1·10 18 cm -3 and with a first lattice constant, - a first semiconductor intermediate layer (24) of the first conductivity type, at least partially formed, with a dopant concentration of 1∙1014 cm-3 - 5∙1017 cm-3 and a layer thickness (D24) of at least 0.5 µm, - a drift region (12) of a second conductivity type or of the first conductivity type with a dopant concentration of 8·10 11 cm -3 - 1·10 15 cm -3, the first lattice constant, a first energy band gap and a layer thickness (D12) between 10 µm and 200 µm or from 25 µm - 100 µm, - a highly doped second semiconductor contact layer (14) of the second conductivity type with a dopant concentration of at least 1·10 17 cm -3 , - a second metallic contact layer (18) formed at least in certain areas, wherein - the stacked high-blocking III-V semiconductor power diode (10) has a III-V semiconductor passivation layer (22) with the first lattice constant and a second energy band gap that differs from the first energy band gap, - the first metallic contact layer (20) is arranged on a top side of the first semiconductor contact layer (16), wherein - the III-V semiconductor passivation layer (22) the first or the second conductivity type and a dopant concentration in a range between 1·10 14 cm -3 and 5·10 18 cm -3 exhibits - the III-V semiconductor passivation layer (22) is arranged on the top side of the drift region (12) and has a contact hole through-opening, - the first semiconductor intermediate layer (24) covers the area of ​​the contact hole opening as well as a surface edge region of the III-V semiconductor passivation layer (22) adjacent to the contact hole opening, and viewed in a cross-section of the layer sequence, the first semiconductor intermediate layer (24) protrudes above a top surface of the III-V semiconductor passivation layer (22) in the surface edge region, - the first semiconductor contact layer (16) is arranged on or above a top surface of the first semiconductor intermediate layer (24).

Description

[0001] The invention relates to a stack-shaped, high-blocking III-V semiconductor power diode.

[0002] From "GaAs Power Devices" by German Ashkinazi, ISBN 965-7094-19-4, pages 8 and 9, a high-voltage-resistant semiconductor power diode made of GaAs with p + - n - n + The structure is known. GaAs Schottky diodes are described on pages 23 to 26.

[0003] Further high-voltage resistant III-V semiconductor power diodes and corresponding manufacturing processes are also known from the publications DE 10 2016 013 540 A1, DE 10 2016 013 541 A1, DE 10 2016 015 056 A1, DE 10 2017 002 935 A1 and DE 10 2017 002 936 A1.

[0004] A III-V PIN diode is also known from the JP S62 - 160 775 A.

[0005] A disadvantage of the described structures are the residual or leakage currents that occur during operation in the blocking direction, especially across the edges of the planar pn junctions or the mesa structures.

[0006] Against this background, the object of the invention is to provide a device that further develops the state of the art.

[0007] The problem is solved by a stacked, high-blocking III-V semiconductor power diode with the features of claim 1. Advantageous embodiments of the invention are the subject of dependent claims.

[0008] According to the subject matter of the invention, a stack-shaped high-blocking III-V semiconductor power diode is provided.

[0009] The stacked high-blocking III-V semiconductor power diode has a first metallic terminal contact layer formed at least in some areas, a highly doped first semiconductor contact layer formed at least in some areas, a first semiconductor intermediate layer formed at least in some areas, a drift region, a highly doped second semiconductor contact layer and a second metallic terminal contact layer formed at least in some areas, wherein the aforementioned layers and regions follow one another or are arranged one below the other in the aforementioned order.

[0010] The first highly doped semiconductor contact layer exhibits a first conductivity type, a dopant concentration of at least 1·10 18 cm -3 and a first lattice constant.

[0011] The first semiconductor intermediate layer exhibits the first conductivity type, a dopant concentration of 1·10 14 cm -3 - 1·1016 cm -3 or of 1·10 14 cm -3 - 1·10 17 cm -3 or of 1·10 14 cm -3 - 5·10 17 cm -3 and a layer thickness of at least 0.5 µm or at least 5 µm and, for example, at most 30 µm.

[0012] The drift area exhibits the first or a second conductivity type, a dopant concentration of 8·10 11 cm -3 - 1·10 15 cm -3 or of 8·10 11 cm -3 - 5·10 14 cm -3 or of 8·10 12 cm -3 - 8·10 14 cm -3 or of 8·10 12 cm -3 - 1·10 15 cm -3 , the first lattice constant, a first energy band gap and a layer thickness between 10 µm and 200 µm or from 25 µm - 100 µm.

[0013] Furthermore, the stacked high-blocking III-V semiconductor power diode features a III-V semiconductor passivation layer. This III-V passivation layer exhibits the first lattice constant, a second energy band gap distinct from the first, the first or second conductivity type, and a dopant concentration in the range of 1 × 10⁻⁶. 14 cm -3 and 5·10 18 cm -3 on.

[0014] In a first embodiment, the second energy band gap of the III-V semiconductor passivation layer is larger than the first energy band gap of the drift region.

[0015] The III-V semiconductor passivation layer is arranged on the top side of the drift region and has a contact hole opening, with the semiconductor interlayer covering the area of ​​the contact hole opening as well as a surface area of ​​the III-V semiconductor passivation layer adjacent to the contact hole opening.

[0016] The first semiconductor contact layer is arranged on or above a top surface of the semiconductor intermediate layer, and the first metallic terminal contact layer is arranged on a top surface of the first semiconductor contact layer.

[0017] The contact hole opening has, for example, a diameter of at least 1 µm, or at least 50 µm, or at least 500 µm, or at least 2500 µm. The surface area of ​​the III-V semiconductor passivation layer covered by the semiconductor interlayer has, for example, a width of at least 100 nm, or at least 5 µm, or at least 150 µm.

[0018] The first semiconductor contact layer completely or partially covers the semiconductor intermediate layer, but does not extend beyond the semiconductor intermediate layer to the III-V semiconductor passivation layer. The semiconductor contact layer is metallurgically bonded to the semiconductor intermediate layer or to another semiconductor intermediate layer located between the semiconductor intermediate layer and the first semiconductor contact layer.

[0019] In another embodiment, the first semiconductor contact layer extends beyond the first semiconductor intermediate layer.

[0020] The semiconductor interlayer is metallurgically bonded in the area of ​​the contact hole opening to the exposed surface of the drift region or to another semiconductor interlayer covering the surface of the drift region. Furthermore, the semiconductor interlayer is metallurgically bonded above the surface area of ​​the III-V semiconductor passivation layer adjacent to the contact hole opening to the III-V semiconductor passivation layer or to the other semiconductor interlayer.

[0021] It is noted that the drift region is also a semiconductor layer.

[0022] It is understood that the high-blocking III-V semiconductor power diode can be configured with an n-on-p or a p-on-n structure. Accordingly, either the first conductivity type is n and the second conductivity type is p, or vice versa.

[0023] It should also be noted that the metallic contact layers are each highly electrically conductive. Preferably, the metallic contact layers consist of one or more metal layers, wherein the metal layers preferably comprise Ge and / or Au and / or Ag and / or Pd.

[0024] The metallic contact layers establish a low-resistance electrical contact with the highly doped first semiconductor contact layer or the second highly doped semiconductor contact layer.

[0025] It is also understood that the respective semiconductor layer is directly adjacent to the corresponding metallic contact layer.

[0026] According to alternative embodiments, the metallic contact layers are designed as flat surfaces, fingers, or points.

[0027] Furthermore, it is understood that the connection contact layers are preferably interconnected by means of bond wires with contact fingers, the so-called pins, by arranging the semiconductor power diodes on a carrier, for example in the form of a leadframe.

[0028] All semiconductor layers, in particular the drift region, the first semiconductor contact layer and the III-V semiconductor passivation layer of the III-V semiconductor power diode, are preferably epitaxially produced.

[0029] The drift region, the semiconductor intermediate layer and the semiconductor contact layers consist of, for example, GaAs or comprise, for example, GaAs.

[0030] The aforementioned layers are grown sequentially, for example, on a growth substrate with the first lattice constant or on a growth substrate with a second lattice constant and a buffer layer. For example, growth is performed on a GaAs substrate or on a Ge substrate, e.g., with an InGaP or InGaAs interlayer to compensate for the lattice constant difference between germanium and gallium arsenide.

[0031] The growth substrate, e.g. the GaAs substrate or the Ge substrate with the InGaP interlayer, is then completely or partially removed by grinding and / or etching and / or other processes, e.g. peeling.

[0032] In a further embodiment, an InGaP layer or InGaAs interlayer is grown on a Ge substrate to compensate for a lattice constant difference to subsequent GaAs layers of the III-V device, with the InGaP interlayer simultaneously serving as an etch stop layer. The semiconductor layers of the device, preferably made of GaAs, are then epitaxially produced. Subsequently, the Ge substrate is first removed by an etching process, and then the InGaP interlayer is removed from the GaAs power diode by a further etching process, e.g., wet chemical etching.

[0033] As an alternative to completely removing the growth substrate, possibly with a buffer layer, the growth substrate is only partially removed.

[0034] For example, a GaAs substrate doped with the second conductivity type is used, so that a remaining layer of the substrate forms the highly doped second semiconductor contact layer. Alternatively, a buffer layer or part of a buffer layer is not removed and forms the second semiconductor contact layer.

[0035] The contact hole opening of the III-V semiconductor passivation layer is created, for example, by means of a mask that excludes the area of ​​the contact hole opening and an etching process that removes the III-V semiconductor passivation layer in the area of ​​the recess.

[0036] It is understood that the etching step can also create a trench extending into the drift region, since according to preferred embodiments there is no or only very low etch selectivity between the material of the III-V semiconductor passivation layer and the material of the drift region.

[0037] In an alternative embodiment, there is a high etch selectivity between the material of the III-V semiconductor passivation layer and the material of the drift region, so that no or only a small trench extending into the drift region is formed.

[0038] After removing the mask, the semiconductor intermediate layer and the first semiconductor contact layer are grown one after the other, for example, and then removed again in an etching step on a surface section of the semiconductor passivation layer up to the semiconductor passivation layer.

[0039] Alternatively or additionally, one or more layers of the III-V semiconductor power diode are connected to each other by means of a wafer bond.

[0040] It is also understood that at least the semiconductor contact layers, the drift region formed as a semiconductor layer and the III-V semiconductor passivation layer of the stacked high-blocking III-V semiconductor power diode each contain at least one element of the III main group and at least one element of the V main group.

[0041] Preferably, the aforementioned layers or areas consist of III-V materials, e.g. GaAs, AlGaAs, InGaP, GaAsP, InGaAs or InP.

[0042] It is noted that an area or layer consisting of a III-V material need only consist essentially of a III-V material, or may, in addition to a III-V material (i.e., a material comprising one or more elements of the III and one or more elements of the V main group), possibly also contain impurities and / or dopants and / or defects.

[0043] The same applies to a semiconductor region or layer consisting of GaAs or another explicitly named material combination. If a layer has an explicitly named material combination, this means that the layer's material consists of a compound of the explicitly named materials and, if applicable, other elements from Group 3 and / or Group 5. A layer containing GaAs can therefore, for example, be an InGaAs layer.

[0044] In further developments, the III-V semiconductor power diode has additional semiconductor layers made of other semiconductor materials or additional layers made of other non-semiconductor materials, e.g. a nitride layer or an oxide layer or a polyimide layer as a further passivation layer.

[0045] In another embodiment, the drift region and the first semiconductor contact layer, as well as, optionally, the semiconductor layers below the drift region, consist of GaAs or InGaAs, or the semiconductor layers have an indium content of at most 30%. This is advantageous because GaAs and InGaAs exhibit high charge carrier mobility.

[0046] According to alternative embodiments, the III-V semiconductor passivation layer consists of InGaP, AlGaAs, InGaAsP, InAlP, or InAlGaP. In another embodiment, the III-V semiconductor passivation layer has a higher energy bandgap than the drift region.

[0047] III-V semiconductors, especially GaAs, provide a particularly high electron mobility of 8800 Vs / cm at a doping level of less than 1·10 15 cm -3For example, the electron mobility in InGaAs is less than 1 × 10⁻⁵ when doped. 15 cm -3 at approximately 12,000 Vs / cm.

[0048] Low-doped layers, such as the drift region according to the invention, can now be reliably deposited, for example, using MOVPE or LPE, thereby creating a layer stack appropriate to the component.

[0049] The III-V semiconductor passivation layer suppresses leakage currents in the edge region and across the surface of the semiconductor power diode or current paths running across the edge.

[0050] The high-blocking semiconductor power diode according to the invention enables breakdown field strengths of up to 40 V / µm and very reliable breakdown field strengths of over 20 V / µm. The semiconductor structure according to the invention is therefore particularly suitable as a freewheeling diode, i.e., for use as a so-called protection diode.

[0051] An advantage of the semiconductor structure according to the invention is a particularly low reverse current and a high breakdown voltage. In particular, the breakdown characteristic exhibits an ideal shape.

[0052] In the semiconductor structure according to the invention, significantly fewer recombinations occur at the interface between the drift region and the III-V semiconductor passivation layer compared to an interface between a drift region and a conventional passivation layer, such as Si3N4 or SiO2, thereby substantially reducing leakage currents. In particular, the III-V semiconductor passivation layer provides better saturation of surface states compared to a conventional SiN or SiO passivation layer.

[0053] Due to an increased energy band gap of the III-V semiconductor passivation layer compared to the drift region, additional charge carriers are kept away from the surface, thus effectively reducing leakage currents even further.

[0054] Furthermore, the semiconductor structure according to the invention can be used to produce, in particular, high-blocking diodes with significantly reduced capacitance compared to Si- or SiC-based solutions.

[0055] The lower capacity improves the behavior of the components in the application, especially during switching processes, which significantly improves the overall efficiency of power modules and, above all, allows for higher switching frequencies and smaller components and thus smaller power modules compared to Si solutions.

[0056] Furthermore, III-V semiconductor power diodes can withstand higher temperatures at the pn junction compared to silicon-based diodes without being destroyed. This allows III-V semiconductor power diodes to be used in hot environments with temperatures up to 300°C.

[0057] Another advantage compared to SiC components is that III-V semiconductor power diodes can be manufactured much more cost-effectively than semiconductor structures made of SiC with comparable electrical properties.

[0058] It is also noted that the terms "below" and "above" or "under" and "above" merely serve to describe the arrangement of the individual layers and areas relative to each other and do not indicate any absolute direction.

[0059] In a first embodiment, the III-V semiconductor passivation layer has a layer thickness of 10 nm - 3 µm or of 20 nm - 2 µm.

[0060] In another embodiment, the III-V semiconductor passivation layer comprises or consists of InGaP or AlGaAs or InGaAsP or InAlP or InAlGaP.

[0061] In a further training, the second semiconductor contact layer has a layer thickness of 0.5 µm - 600 µm or of 10 µm - 300 µm or of 10 µm - 200 µm.

[0062] In another embodiment, the drift region exhibits the first conductivity type and the semiconductor passivation layer the second conductivity type. Furthermore, a third metallic contact layer, formed at least in certain areas, is arranged at a first distance from the semiconductor intermediate layer on a top surface of the semiconductor passivation layer and is metallurgically bonded to the semiconductor passivation layer.

[0063] In another embodiment, the III-V semiconductor passivation layer is epitaxially produced on the drift region and / or the drift region on the second highly doped semiconductor contact layer or on a buffer layer or on a substrate layer.

[0064] In another advanced method, the first highly doped semiconductor contact layer on the semiconductor intermediate layer and / or the semiconductor intermediate layer on the III-V semiconductor passivation layer as well as on the drift region or on another semiconductor intermediate layer are epitaxially produced.

[0065] In another embodiment, the first semiconductor contact layer, the drift region and the second semiconductor contact layer have GaAs or consist of GaAs.

[0066] In a further development, the stack-shaped high-blocking III-V semiconductor power diode has an additional passivation layer, wherein the additional passivation layer covers at least one top surface of the III-V semiconductor passivation layer.

[0067] The further passivation layer comprises, in a first embodiment, Si x N y and / or Si x O y and / or SiNO xand / or polyimide or consists of Si x N y and / or Si x O y and / or SiNO x and / or polyimide.

[0068] In another embodiment, the stack-shaped high-blocking III-V semiconductor power diode has a buffer layer, wherein the buffer layer is arranged below the underside of the drift region and above the second metallic terminal contact layer and has the first grid constant on a top side facing the drift region and a second grid constant differing from the first grid constant on a bottom side.

[0069] In a further development, the second highly doped semiconductor contact layer is arranged between the buffer layer and the second metallic terminal contact layer and has the second lattice constant. Alternatively, the second semiconductor contact layer has the first lattice constant and is arranged between the buffer layer and the drift region.

[0070] In another embodiment, the high-blocking III-V semiconductor power diode has a substrate layer, wherein the substrate layer is arranged below the underside of the drift region and above the second metallic terminal contact layer and has the first grid constant or a second grid constant different from the first grid constant.

[0071] In another embodiment, the second semiconductor contact layer is configured as a substrate layer or as a buffer layer. That is, the substrate layer or a part of the substrate layer, or the buffer layer or a part of the buffer layer, also forms the second semiconductor contact layer, or a single semiconductor layer fulfills both functions.

[0072] In another embodiment, the stacked high-blocking III-V semiconductor power diode has a second semiconductor intermediate layer with a dopant concentration of 1·10 14 cm -3 - 1·10 16 cm -3 or of 1·10 14 cm -3 - 1·10 17 cm -3 or of 1·10 14 cm -3 - 5·10 17 cm -3and a layer thickness of at most 50 µm or at most 20 µm, wherein the semiconductor intermediate layer is located below the drift region and above the second highly doped semiconductor contact layer and has the second conductivity type.

[0073] The invention is explained in more detail below with reference to the drawings. Similar parts are labelled with identical designations. The illustrated embodiments are highly schematic; that is, the distances and the lateral and vertical extents are not to scale and, unless otherwise indicated, do not exhibit any derivable geometric relationships to one another. In these drawings, the Fig. 1 a cross-sectional view of a first embodiment of a stacked high-blocking III-V semiconductor power diode, Fig. 2 a cross-sectional view of a second embodiment of the stacked high-blocking III-V semiconductor power diode, Fig. 3 a cross-sectional view of a third embodiment of the stacked high-blocking III-V semiconductor power diode, Fig. 4 a cross-sectional view of a fourth embodiment of the stacked high-blocking III-V semiconductor power diode, Fig. 5 a cross-sectional view of a fifth embodiment of the stacked high-blocking III-V semiconductor power diode, Fig. 6 a top view of a top surface of the first embodiment of the stacked high-blocking III-V semiconductor power diode.

[0074] The illustration of Fig. Figure 1 shows a stacked high-blocking III-V semiconductor power diode 10 with a second metallic terminal contact layer 18, a second highly doped semiconductor contact layer 14, a drift region 12, a first semiconductor intermediate layer 24, a highly doped first semiconductor contact region 16, a first metallic terminal contact layer 20 and a III-V semiconductor passivation layer 22.

[0075] The drift region 12 is filled with dopants of a first or second conductivity type with a low to very low dopant concentration of 8·10 11 cm -3 - 8·10 14 cm -3 doped and has a first lattice constant and a layer thickness D12 of at least 10 µm, e.g. 30 µm or 90 µm.

[0076] Below the drift region 12, the second highly doped semiconductor contact layer 14 of the second conductivity type follows in a metallurgically bonded manner with a dopant concentration of at least 1·10 17 cm -3 .

[0077] The second metallic contact layer 18, which is designed as a planar, flat metal layer, follows on the underside of the highly doped semiconductor contact layer in a material-bonded manner.

[0078] The III-V semiconductor passivation layer 22 is arranged on a top surface of the drift region 12 and is metallurgically bonded to the top surface of the drift region 12. The III-V semiconductor passivation layer 22 has a contact hole opening with a width B22.

[0079] The semiconductor intermediate layer 24 exhibits the first conductivity type and a dopant concentration of approximately 10 15 cm -3The semiconductor intermediate layer extends over the contact hole opening and a surface edge region of the III-V semiconductor passivation layer 22 adjacent to the contact hole opening and is metallurgically bonded to the surface edge region and to the top of the drift region 12 in the contact hole opening.

[0080] The highly doped first semiconductor contact area 16 has dopants of the first conductivity type with a dopant concentration of at least 1·10 18 cm -3 on and covers a top surface of the first semiconductor intermediate layer 24 in a materially bonded manner.

[0081] The first metallic terminal contact layer 20 is arranged on a top surface of the first semiconductor contact layer 16, wherein the metallic terminal contact layer 20 covers a part of the top surface of the first semiconductor contact layer 16 that is arranged at least approximately concentrically.

[0082] Depending on the type of conductivity of the drift region 12, a pn junction is formed either between the drift region 12 and the second semiconductor contact region 14 or between the drift region 12 and the semiconductor intermediate layer 24.

[0083] The illustration of Fig. Figure 2 shows a cross-sectional view of the stacked, high-blocking III-V semiconductor power diode 10 in a second embodiment. The following only highlights the differences compared to the illustration of the Fig. 1 explained.

[0084] The III-V semiconductor power diode 10 has a further passivation layer 26, e.g. an oxide layer, wherein the further passivation layer 26 covers the otherwise exposed surface of the III-V passivation layer 22.

[0085] The second semiconductor contact layer 14 is formed by a substrate layer 36, e.g. a remaining part of a growth substrate.

[0086] The illustration of Fig. Figure 3 shows a cross-sectional view of the stacked, high-blocking III-V semiconductor power diode in a third embodiment. The following only highlights the differences compared to the figure of the Fig. 2 explained.

[0087] On a top side of the III-V semiconductor passivation layer 22 of the high-blocking III-V semiconductor power diode 10, a third metallic contact layer 30, at least partially formed, is arranged and is metallurgically connected to the top side of the III-V semiconductor passivation layer 22.

[0088] The third metallic contact layer is arranged at a first distance A1 to the first semiconductor intermediate layer 24.

[0089] Furthermore, the III-V semiconductor passivation layer 22 exhibits the second conductivity type and the drift region 12 exhibits the first conductivity type.

[0090] The illustration of Fig. Figure 4 shows a cross-sectional view of the stacked, high-blocking III-V semiconductor power diode in a fourth embodiment. The following only highlights the differences compared to the figure of the Fig. 2 explained.

[0091] The high-blocking III-V semiconductor power diode 10 additionally has a buffer layer 32, wherein the buffer layer 32 has the first grid constant on a top side and a second grid constant on a bottom side.

[0092] The top surface of the buffer layer 32 is metallurgically bonded to the bottom surface of the drift region 12, and the bottom surface of the buffer layer 32 is metallurgically bonded to the top surface of the highly doped second semiconductor contact layer 14. The second semiconductor contact layer 14 has the second lattice constant.

[0093] In an alternative embodiment not shown, the buffer layer 32 forms the second semiconductor contact layer 14, so that the first metallic terminal contact layer 18 is metallurgically bonded to the underside of the buffer layer 32.

[0094] The illustration of Fig. Figure 5 shows a cross-sectional view of the stacked, high-blocking III-V semiconductor power diode in a fifth embodiment. The following only highlights the differences compared to the figure of the Fig. 2 explained.

[0095] The stacked high-blocking III-V semiconductor power diode 10 additionally has a second semiconductor interlayer 34, wherein the second semiconductor interlayer 34 is arranged between the second semiconductor contact layer 14 and the drift region 12, a layer thickness of at most 50 µm or at most 20 µm, and the second semiconductor interlayer 34 has the second conductivity type and a dopant concentration between 1·10 14 cm -3 and 1·10 16 cm -3 exhibits.

[0096] In the illustration of the Fig. Figure 6 shows a top view of the first embodiment of the stacked high-blocking III-V semiconductor power diode. The following only highlights the differences compared to the figure of the Fig. 1 explained.

[0097] The III-V semiconductor power diode has a rectangular circumference, while the circumference of the first highly doped semiconductor contact layer 16 and the circumference of the underlying semiconductor intermediate layer 24 are round. The circumference of the first metallic terminal contact layer 20 is also round, with the first metallic terminal contact layer 20 being arranged concentrically to the highly doped first semiconductor contact layer 16.

[0098] It is understood that the aforementioned dimensions do not always have to have the shape shown here. While round circumferential shapes for the contact hole opening and the layers following the drift region can be easily produced using masking processes and exhibit advantageous electrical properties, an angular, especially rectangular or square, shape of the component can be easily achieved by a singulation step using saws.

Claims

[1] Stacked high-blocking III-V semiconductor power diode (10), in the said layer sequence comprising - a first metallic connection contact layer (20) formed at least in some regions, - a highly doped first semiconductor contact layer (16) of a first conductivity type formed at least in some regions and having a dopant concentration of at least 1·10 18 cm -3 and with a first lattice constant, - a first semiconductor intermediate layer (24) of the first conductivity type formed at least in some regions, with a dopant concentration of 1 1014 cm-3 - 5 1017 cm-3 and a layer thickness (D24) of at least 0.5 µm, - a drift region (12) of a second conductivity type or of the first conductivity type with a dopant concentration of 8·10 11 cm -3 - 1·10 15 cm -3, the first lattice constant, a first energy band gap and a layer thickness (D12) between 10 µm and 200 µm or from 25 µm - 100 µm, - a highly doped second semiconductor contact layer (14) of the second conductivity type with a dopant concentration of at least 1·10 17 cm -3 , - a second metallic connection contact layer (18) formed at least in some regions, wherein - the stacked high-blocking III-V semiconductor power diode (10) has a III-V semiconductor passivation layer (22) with the first lattice constant and a second energy band gap different from the first energy band gap, - the first metallic connection contact layer (20) is arranged on an upper side of the first semiconductor contact layer (16), wherein - the III-V semiconductor passivation layer (22) has the first or the second conductivity type and a dopant concentration in a range between 1 10 14 cm -3 and 5·10 18 cm -3 has, - the III-V semiconductor passivation layer (22) is arranged on top of the drift region (12) and has a contact hole through opening, - the first semiconductor intermediate layer (24) covers the region of the contact hole through-opening as well as a surface edge region of the III-V semiconductor passivation layer (22) adjacent to the contact hole through-opening, and viewed in a cross-section of the layer sequence, the first semiconductor intermediate layer (24) projects beyond an upper side of the III-V semiconductor passivation layer (22) in the surface edge region, - the first semiconductor contact layer (16) is arranged on or above an upper side of the first semiconductor intermediate layer (24). [2] Stacked high-blocking III-V semiconductor power diode (10) according to claim 1, wherein the III-V semiconductor passivation layer (22) has a layer thickness (D22) of 10 nm - 3 µm. [3] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the III-V semiconductor passivation layer (22) comprises InGaP or AlGaAs or InGaAsP or InAlP or InAlGaP or consists of InGaP or AlGaAs or InGaAsP or InAlP or InAlGaP. [4] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the second semiconductor contact layer (14) has a layer thickness of 0.5 µm - 600 µm. [5] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the drift region (12) has the first conductivity type and the III-V semiconductor passivation layer (22) has the second conductivity type and a third metallic connection contact layer (30) formed at least in regions is arranged in a material-locking manner at a first distance (A1) from the semiconductor intermediate layer (24) on an upper side of the semiconductor passivation layer (22) and is material-lockingly connected to the semiconductor passivation layer (22). [6] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the III-V semiconductor passivation layer (22) on the drift region (12) and / or the drift region (12) on the second highly doped semiconductor contact layer (14) or on a buffer layer (32) or on a substrate layer (36) is epitaxially produced. [7] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the first highly doped semiconductor contact layer (16) is epitaxially produced on the semiconductor intermediate layer (24) and / or the semiconductor intermediate layer (24) is epitaxially produced on the III-V semiconductor passivation layer (22) and on the drift region (12) or on a further semiconductor intermediate layer. [8] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the first semiconductor contact layer (16), the drift region (12) and the second semiconductor contact layer (14) comprise GaAs or consist of GaAs. [9] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the stacked high-blocking III-V semiconductor power diode (10) has a further passivation layer (26), wherein the further passivation layer covers at least an upper side of the III-V semiconductor passivation layer (22). [10] Stacked high-blocking III-V semiconductor power diode (10) according to claim 9, wherein the further passivation layer (26) comprises Si x N y and / or Si x O y and / or SiNO x and / or polyimide or Si x N y and / or Si x O y and / or SiNO x and / or polyimide. [11] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the first conductivity type is n and the second conductivity type is p or that the first conductivity type is p and the second conductivity type is n. [12] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the stacked high-blocking III-V semiconductor power diode (10) has a buffer layer (32), wherein the buffer layer (32) is arranged below the underside of the drift region (12) and above the second metallic terminal contact layer (18) and either above or below the second semiconductor contact layer (14) and has the first lattice constant on an upper side facing the drift region (12) and a second lattice constant deviating from the first lattice constant on an underside. [13] Stacked high-blocking III-V semiconductor power diode (10) according to claim 12, wherein the second highly doped semiconductor contact layer (14) having the second lattice constant is arranged between the buffer layer (32) and the second metallic terminal contact layer (18) or having the first lattice constant is arranged between the buffer layer (32) and the drift region (12). [14] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the stacked high-blocking III-V semiconductor power diode (10) has a substrate layer (36), wherein the substrate layer (36) is arranged below the underside of the drift region (12) and above the second metallic terminal contact layer (14) and has the first lattice constant or a second lattice constant deviating from the first lattice constant. [15] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the second semiconductor contact layer (14) is formed as a substrate layer (36) or as a buffer layer (32). [16] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the stacked high-blocking III-V semiconductor power diode (10) has a second semiconductor intermediate layer (34) with a dopant concentration of 1 10 14 cm -3 - 5·10 17 cm -3 and a layer thickness (D34) of at most 50 µm or at most 20 µm, wherein the second semiconductor intermediate layer (34) is arranged below the drift region (12) and above the second highly doped semiconductor contact layer (14) and has the second conductivity type. [17] Stacked high-blocking III-V semiconductor power diode (10) according to one of the preceding claims, wherein the second energy band gap of the III-V semiconductor passivation layer (22) is larger than the first energy band gap of the drift region (12).

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