Semiconductor devices

Abstract

Semiconductor device comprising: a substrate (210); a bitline (BL) on the substrate (210), wherein the bitline (BL) extends in a first direction (Y) which is parallel to an upper surface of the substrate (210), wherein the bitline (BL) has a lower conductive pattern (230B), a middle conductive pattern (232B) and an upper conductive pattern (234B) which are stacked sequentially along a vertical direction (Z) on the substrate (210), wherein the lower conductive pattern (230B) has doped polysilicon, the middle conductive pattern (232B) has titanium atoms, tungsten atoms and nitrogen atoms, and the upper conductive pattern (234B) has tungsten atoms; and an insulating cover structure (CSC3) on the bit line (BL), wherein the insulating cover structure (CSC3) has a first insulating cover pattern (336C), a second insulating cover pattern (238C), a third insulating cover pattern (244C) and a fourth insulating cover pattern (250C), which are stacked sequentially in the vertical direction (Z) on the bit line (BL), wherein the second insulating cover pattern (238C), the third insulating cover pattern (244C) and the fourth insulating cover pattern (250C) have substantially the same widths in a second direction (X) which is parallel to the upper surface of the substrate (210) and perpendicular to the first direction (Y), wherein the first insulating cover pattern (336C) has a lower surface which is in contact with an upper surface of the upper conductive pattern (234B) of the bit line (BL), wherein the lower surface of the first insulating cover pattern (336C) has a width which is less than the width of each of the second insulating cover pattern (238C), the third insulating cover pattern (244C) and the fourth insulating cover pattern (250C) in the second direction (X), and wherein the thickness of the third insulating cover pattern (244C) in the vertical direction (Z) is less than the thickness of each of the second insulating cover pattern (238C) and the fourth insulating cover pattern (250C) in the vertical direction (Z).

Description

BACKGROUND

[0001] The concept according to the invention relates to semiconductor devices and in particular to a semiconductor device comprising bit lines.

[0002] As integrated circuit devices have rapidly miniaturized, the distances between multiple wiring leads have decreased, as has the area occupied by these leads and the conductive structures interposed between them. Consequently, ensuring sufficient contact area among these leads and conductive structures has become challenging. Therefore, it is desirable to develop a structure capable of limiting the increase in resistance of densely packed wiring leads within a limited area, and to develop a method for implementing such a structure.

[0003] From US patent 2018 / 0158773A1, a semiconductor device is known that comprises a substrate with a cell array area containing an active cell region. An insulating structure is located on the substrate. The insulating structure includes a direct contact hole that exposes and extends into the active cell region. A conductive structure is located within the direct contact hole and is connected to the active cell region. A bit line is located on the insulating structure. The bit line is connected to the conductive structure of the direct contact and runs orthogonally to the top surface of the insulating structure. The insulating structure comprises an insulating structure made of a non-metal-based dielectric material and a second insulating structure on top of the first insulating structure.The second insulating structure comprises a metal-based dielectric material with a higher dielectric constant than the dielectric constant of the first insulating structure. SUMMARY

[0004] Semiconductor devices according to the invention are specified in the attached patent claims.

[0005] According to one aspect of the concept according to the invention, an integrated circuit device is provided which has a structure that is able to limit the increase in resistances of wiring lines that are densely arranged within a limited area in the integrated circuit device, which has a fine elementary cell size corresponding to the miniaturization of the integrated circuit device.

[0006] According to another aspect of the concept according to the invention, a manufacturing method is provided for an integrated circuit device which has a structure capable of limiting the increase in resistances of wiring leads that are densely arranged within a limited area in the integrated circuit device, which has a fine elementary cell size corresponding to the miniaturization of the integrated circuit device.

[0007] According to one embodiment, an integrated circuit device is provided comprising a conductive line formed on a substrate, wherein the conductive line comprises a metal layer and extends in a first horizontal direction with respect to an upper surface of the substrate, and an insulating cover structure covering the conductive line, wherein the insulating cover structure comprises a first insulating cover pattern having a first density, the first insulating cover pattern being adjacent to the metal layer, and a second insulating cover pattern being vertically spaced from the metal layer with the first insulating cover pattern between them, the second insulating cover pattern having a second density greater than the first density.

[0008] According to another embodiment, an integrated circuit device is provided comprising: a pair of bit lines running parallel to each other on a substrate in a first horizontal direction with respect to an upper surface of the substrate, wherein the pair of bit lines is adjacent to each other in a second horizontal direction with respect to the upper surface of the substrate; a pair of insulating cover structures, each covering the pair of bit lines;and a contact structure extending in a vertical direction from between the pair of bit lines to between the pair of insulating cover structures, wherein the pair of bit lines each comprise a metal layer and each pair of insulating cover structures comprises a first insulating cover pattern on the metal layer, the first insulating cover pattern having a first density, and a second insulating cover pattern spaced from the metal layer with the first insulating cover pattern in between, the second insulating cover pattern having a second density greater than the first density.

[0009] According to another embodiment, an integrated circuit device is provided comprising: a substrate comprising a cell array region and a peripheral circuit region, a bit line on the substrate in the cell array region, the bit line comprising a first metal layer, a first insulating cover structure covering the bit line in the cell array region, a gate electrode on the substrate in the peripheral circuit region, the gate electrode comprising a second metal layer, and a second insulating cover structure covering the gate electrode in the peripheral circuit region, each comprising a first insulating cover pattern having a first density and a second insulating cover pattern spaced from the substrate with the first insulating cover pattern between them, the second insulating cover pattern having a second density.which is greater than the first density, and the first metal layer is in contact with the first insulating cover pattern contained in the first insulating cover structure, and the first metal layer has a first region doped with nitrogen (N) atoms, the first region extending from an interface between the first metal layer and the first insulating cover pattern in the first insulating cover structure towards the second insulating cover pattern and having a partial thickness of the first metal layer.

[0010] According to another embodiment, a method is provided for manufacturing an integrated circuit device, wherein the method comprises forming a conductive line on a substrate, the conductive line comprising a metal layer. An insulating cover structure is formed on the conductive line, the insulating cover structure comprising multiple insulating cover patterns. Forming the insulating cover structure includes forming a first insulating cover layer directly on the metal layer, the first insulating cover layer having a first density. A second insulating cover layer is formed on top of the first insulating cover layer, the second insulating cover layer having a second density greater than the first density.

[0011] According to another embodiment, a method is provided for fabricating an integrated circuit device, wherein the method comprises forming multiple conductive layers stacked on a substrate, the multiple conductive layers having a metal layer as an uppermost layer. An insulating cover structure is formed on the metal layer, the insulating cover structure comprising a first insulating cover pattern having a first density and a second insulating cover pattern having a second density greater than the first density. Bit lines are formed by etching the multiple conductive layers using the insulating cover structure as an etching mask.

[0012] According to another embodiment, a method is provided for fabricating an integrated circuit device, wherein the method comprises forming multiple conductive layers on a substrate in a cell array region and a peripheral circuit region, the multiple conductive layers comprising a metal layer as an uppermost conductive layer of the multiple conductive layers. A first insulating cover structure, comprising a first insulating cover pattern having a first density, and a second insulating cover pattern having a second density greater than the first density, are formed on the multiple conductive layers in the cell array region.A second insulating cover structure, comprising a third insulating cover pattern (the third insulating cover pattern having the first density), and a fourth insulating cover pattern (the second density) are formed on the multiple conductive layers in the peripheral circuit region. Bit lines are formed by etching the multiple conductive layers using the first insulating cover structure as an etch mask in the cell array region. A gate electrode is formed by etching the multiple conductive layers using the second insulating cover structure as an etch mask in the peripheral circuit region. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Embodiments of the concept according to the invention will be better understood with reference to the following detailed description in conjunction with the associated drawings: Fig. Figure 1 is a block diagram of an integrated circuit device according to an embodiment of the concept according to the invention; Fig. Figure 2 is a top view showing an example of an arrangement in an integrated circuit device according to an embodiment of the concept according to the invention; Fig. 3 is a layout that places elements in a cell array area of ​​an integrated circuit device from Fig. 2 illustrated according to an embodiment of the concept according to the invention; Fig. 4A and Fig. 4B are cross-sectional views along lines AA' and BB' from Fig. 3 of an integrated circuit device according to an embodiment of the concept according to the invention; Fig. 4C is a cross-sectional view of a peripheral circuit area CORE / PERI of an integrated circuit device. Fig. 2 according to an embodiment of the concept according to the invention; Fig. Figure 5 is an enlarged cross-sectional view of the dashed area “Q1” in Fig. 4A; Fig. Figures 6A to 6C are cross-sectional views of the integrated circuit devices according to embodiments of the concept according to the invention; Fig. Figure 7 is an enlarged cross-sectional view of the dashed area “Q2” in Fig. 6A; Fig. Figures 8A to 8Q are cross-sectional views to describe, in a processing sequence, a manufacturing process for an integrated circuit device according to one or more embodiments; and Fig. Figures 9A to 9C are cross-sectional views to describe a manufacturing process for an integrated circuit device according to one or more embodiments in a processing sequence. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0014] One or more embodiments are described in detail below with reference to the accompanying drawings. The same reference numerals denote the same elements in the drawings, and detailed descriptions thereof have been omitted.

[0015] Fig. Figure 1 is a block diagram of an integrated circuit device 100 according to one or more embodiments. Fig. Figure 1 shows an example of the integrated circuit device 100, which includes a dynamic random access memory (DRAM) device.

[0016] With reference to Fig. The integrated circuit device 100 comprises a first area 22 and a second area 24. The first area 22 can be a memory cell area of ​​the DRAM device, and the second area 24 can be a peripheral circuit area of ​​the DRAM device. The first area 22 can include a memory cell array 22A. Multiple memory cells for storing data in row and column directions can be arranged in the memory cell array 22A. The second area 24 can include a row decoder 52, a read amplifier 54, a column decoder 56, a self-refresh control circuit 58, an instruction decoder 60, a mode register set / extended mode register set (MRS / EMRS) circuit 62, an address buffer 64, and a data input / output circuit 66.

[0017] Fig. Figure 2 is a top view showing an exemplary arrangement structure of the integrated circuit device 100. Fig. 1 illustrates.

[0018] With reference to Fig. 2 The integrated circuit device 100 comprises several first areas 22. Each of the several first areas 22 can be surrounded by the second area 24. Each of the several first areas 22 can comprise a cell array area MCA of the DRAM device, and the second area 24 can comprise an area for forming peripheral circuits of the DRAM device and a core area (hereafter referred to as the "peripheral circuit area"). In the several first areas 22, the cell array area MCA can comprise the memory cell array 22A, which was described above with reference to Fig. 1 has been described.

[0019] The second area 24 can comprise a subword line driver block (SWD), a read amplifier block (S / A), and a connection block (CJT). Multiple bit line read amplifiers can be arranged within the read amplifier block (S / A). The connection block (CJT) can be located at the point where the subword line driver block (SWD) and the read amplifier block (S / A) intersect. Power drivers for controlling the bit line read amplifiers and ground drivers can be alternately arranged within the connection block (CJT). Furthermore, peripheral circuits, such as an inverter chain, an input / output circuit, etc., can be formed within the second area 24.

[0020] Fig. 3 is a layout to arrange elements of the in Fig. 2 shown cell array area MCA to illustrate.

[0021] With reference to Fig. 3. The cell array area MCA can comprise multiple active cell areas A1. Each of the multiple active cell areas A1 can be arranged such that it has a principal axis in a diagonal direction with respect to a first horizontal direction (X-direction) and a second horizontal direction (Y-direction). Multiple word lines WL can run parallel to each other in the X-direction, intersecting the multiple active cell areas A1. Multiple bit lines BL can run parallel to each other in the second horizontal direction (Y-direction) on the multiple word lines WL. The multiple bit lines BL can be connected to the multiple active cell areas A1 via direct contacts DC. Multiple buried contacts BC can be formed between two adjacent bit lines from the multiple bit lines BL.The multiple buried contacts BC can be arranged in a row along the first horizontal direction (X-direction) and the second horizontal direction (Y-direction). Multiple conductive landing pads LP can each be formed on the multiple buried contacts BC. The multiple buried contacts BC and the multiple conductive landing pads LP can connect lower electrodes (not shown) of capacitors formed on the multiple bit lines to the active cell regions A1. Each of the multiple conductive landing pads LP can partially overlap a corresponding buried contact BC.

[0022] Fig. Figures 4A to 4C are cross-sectional views illustrating an integrated circuit device 200 according to one or more embodiments. Fig. 4A and Fig. Figure 4B shows cross-sectional views illustrating an exemplary structure of part of the cell array area MCA in the integrated circuit device 200, and Fig. Figure 4C is a cross-sectional view showing an exemplary structure of part of the peripheral circuitry CORE / PERI in the integrated circuit device 200. The cell array area MCA of the integrated circuit device 200 can have a layout as shown in Fig. 3 is shown. Fig. Figure 4A shows a cross-sectional view along line AA' in Fig. 3, and Fig. 4B shows a cross-section along line BB' in Fig. 3.

[0023] Fig. Figure 5 is an enlarged cross-sectional view of a dashed area “Q1” in Fig. 4A.

[0024] With reference to Fig. 4A to 4C and Fig. 5. The integrated circuit device 200 can be part of the in Fig. The integrated circuit device 100 shown in Figures 1 to 3 comprises a substrate 210 having the cell array region MCA and the peripheral circuit region CORE / PERI. An isolation trench T1 is formed in the substrate 210, and an isolation layer 212 is formed in the isolation trench T1. Each of the multiple active cell regions A1 is defined in the substrate 210 within the cell array region MCA of the substrate 210 by the isolation layer 212. An active peripheral region A2 can be defined in the substrate 210 within the peripheral circuit region CORE / PERI by the isolation layer 212.

[0025] The substrate 210 can comprise silicon, e.g., monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the substrate 210 can comprise at least one of the following selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 210 can comprise a conductive region (e.g., a trough region) doped with impurities or a structure doped with impurities. The insulating layer 212 can comprise an oxide layer, a nitride layer, or a combination thereof.

[0026] In the cell array region MCA, several word line trenches T2, running in the first horizontal direction (X-direction), are formed in the substrate 210, and several dielectric gate layers 216, several gate lines 218, and several buried insulating layers 220 are formed in the several word line trenches T2. The several gate lines 218 can correspond to the several word lines WL that are in Fig. Figure 3 shows that multiple recessed spaces 220R can be formed in the upper surfaces of the buried insulating layers 220. The multiple dielectric gate layers 216 can each comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, or a high-k dielectric layer with a dielectric constant greater than that of the silicon oxide layer. For example, the multiple dielectric gate layers 216 can each comprise HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2. The multiple gate lines 218 can each comprise Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. The multiple buried insulating layers 220 can each comprise a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, or a combination thereof.

[0027] In the cell array region MCA, a buffer layer 222 can be formed on the substrate 210. The buffer layer 222 can comprise a first insulating layer 222A and a second insulating layer 222B. Both the first insulating layer 222A and the second insulating layer 222B can comprise an oxide layer, a nitride layer, or a combination thereof. Several direct contacts DC can be arranged on the multiple active cell regions A1. Each of the direct contacts DC can comprise Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0028] Several bit lines BL can run in the second horizontal direction (Y-direction) on the substrate 210 and the several direct contacts DC. Each of the several bit lines BL can be connected to the active cell area A1 via a corresponding direct contact DC. Each of the several bit lines BL can comprise a lower conductive pattern 230B, a conductive intermediate pattern 232B, and an upper conductive pattern 234B, which are layered sequentially on the substrate 210. The upper conductive pattern 234B, that is, the topmost layer of the bit line BL, can comprise metal. The lower conductive pattern 230B can comprise doped polysilicon. The conductive intermediate pattern 232B can comprise TiN, TiSiN, W, tungsten silicide, or a combination thereof. In one or more embodiments, the conductive intermediate pattern 232B may comprise TiN, TiSiN or a combination thereof, and the upper conductive pattern 234B may comprise W.

[0029] In one exemplary embodiment, the multiple insulating cover structures (CSCs) can each be vertically stacked on the multiple bit lines (BLs). The multiple bit lines (BLs) can each be covered by multiple insulating cover structures (CSCs). For example, each of the multiple insulating cover structures (CSCs) can cover the upper surface of a corresponding multiple bit lines (BLs). The multiple bit lines (BLs) and the multiple insulating cover structures (CSCs) can run parallel to each other in the second horizontal direction (Y-direction).

[0030] Each of the multiple insulating cover structures (CSC) can comprise a first insulating cover pattern 236C, a second insulating cover pattern 238C, an insulating thin-film pattern 244C, and a third insulating cover pattern 250C, layered sequentially on top of the upper conductive pattern 234B of the bit line BL. In the multiple insulating cover structures (CSC), a lower surface of the first insulating cover pattern 236C can be in contact with an upper surface of the upper conductive pattern 234B. A lower surface of the second insulating cover pattern 238C can be in contact with an upper surface of the first insulating cover pattern 236C. The term "contact" or the phrase "in contact with," as used here, refers to a directional connection (i.e., touching), unless the context indicates otherwise.

[0031] In each of the multiple insulating cover structures CSC, the first insulating cover pattern 236C and the second insulating cover pattern 238C can have different densities. In one or more embodiments, the first insulating cover pattern 236C, which is closer to the upper conductive pattern 234B of the bit line BL, can have a first density, and the second insulating cover pattern 238C, which is located away from the upper conductive pattern 234B of the bit line BL, with the first insulating cover pattern 236C in between, can have a second density greater than the first density. The insulating thin-film pattern 244C and the third insulating cover pattern 250C can have the second density similar to that of the second insulating cover pattern 238C.In the first horizontal direction (X-direction), the first insulating cover pattern 236C, the second insulating cover pattern 238C, the insulating thin-film pattern 244C, and the third insulating cover pattern 250C can have substantially the same widths. The term "substantially" can be used here to emphasize this meaning unless the context or other statements indicate otherwise. For example, items described as "substantially the same" or "essentially identical" may be exactly the same or identical, or they may be the same or identical within acceptable variations that may occur, for example, due to the manufacturing processes.

[0032] In one or more embodiments, the first insulating cover pattern 236C and the second insulating cover pattern 238C can comprise the same material. In other embodiments, the first insulating cover pattern 236C and the second insulating cover pattern 238C can comprise different materials. The first insulating cover pattern 236C can comprise a silicon nitride layer, a silicon carbonitride layer, or a combination thereof. The second insulating cover pattern 238C, the insulating thin-film pattern 244C, and the third insulating cover pattern 250C can each comprise a silicon nitride layer. The thickness of the first insulating cover pattern 236C in a vertical direction (Z-direction) can be less than that of the second insulating cover pattern 238C in the vertical direction (Z-direction).For example, the first insulating cover pattern 236C may have a thickness of approximately 2.0 nm to approximately 40.0 nm, and the thickness of the second insulating cover pattern 238C may be greater than that of the first insulating cover pattern 236C. Terms such as "approximately" or "about" may represent quantities, sizes, orientations, or layouts that vary only slightly in a relative manner and / or in a manner that does not substantially alter the operation, functionality, or structure of certain elements. For example, a range of "approximately 0.1 to approximately 1" may include a range such as a 0%–5% deviation by 0.1 and a 0%–5% deviation by 1, particularly if such a deviation has the same effect as the specified range.

[0033] In one or more embodiments, the upper conductive pattern 234B can include a nitrogen atom diffusion region (i.e., a region doped with nitrogen atoms) in an upper area therein. The nitrogen atom diffusion region can extend from an interface between the upper conductive pattern 234B and the first insulating cover pattern 236C to a partial thickness of the upper conductive pattern 234B in the direction of the substrate 210 within the upper conductive pattern 234B. The thickness (length in the Z-direction) of the nitrogen atom diffusion region can be approximately 0.01% to approximately 10% of the total thickness (length in the Z-direction) of the upper conductive pattern 234B.For example, the nitrogen atom diffusion region can extend from a thickness of about 0.5 nm to about 4.0 nm from the interface between the upper conductive pattern 234B and the first insulating cover pattern 236C, or from a thickness of about 0.5 nm to about 4.0 nm within the upper conductive pattern 234B, but the thickness of the nitrogen atom diffusion region is not limited to this.

[0034] In the nitrogen atom diffusion region, nitrogen (N) atoms may be in a diffused state, without chemical bonding to other atoms contained in the upper conductive pattern 234B. If the upper conductive pattern 234B comprises a tungsten (W) layer and the first insulating cover pattern 236C comprises a silicon nitride layer, then in one or more embodiments, the nitrogen atom diffusion region in the upper conductive pattern 234B may contain the tungsten (W) layer formed from tungsten (W) atoms, nitrogen (N) atoms distributed between the tungsten crystal structures (i.e., between the tungsten (W) atoms) contained in the W layer without chemical bonding to the tungsten (W) atoms of the tungsten crystal structures of the W layer, and tungsten nitride particles diffused into the W layer. The tungsten nitride particles may include a chemical bond between W and N.In an exemplary embodiment, the nitrogen atom diffusion region can be an upper section of the W-layer, wherein the upper section of the W-layer is doped with nitrogen (N) atoms and comprises the tungsten nitride particles distributed within the upper section of the W-layer. The thickness of the first region can be approximately 0.01% to approximately 10% of the total thickness of the W-layer.

[0035] The sidewalls of the multiple bitlines BL and the sidewalls of the insulating cover structures CSC can be covered by multiple insulating spacers 252. The multiple insulating spacers 252 can run parallel to the multiple bitlines BL in the second horizontal direction (Y-direction). The multiple insulating spacers 252 can each comprise an oxide layer, a nitride layer, an air layer, or a combination thereof. In this specification, the term "air" can refer to the atmosphere or an interstitial space containing other gases that may be present during the manufacturing process.

[0036] Multiple insulating barriers 254 and multiple conductive contact plugs 256 can be arranged in a row between the multiple bit lines BL and between the multiple insulating cover structures CSC in the second horizontal direction (Y-direction). The multiple insulating barriers 254 fill the multiple recessed spaces 220R formed in the upper surface of the buried insulating layer 220, and each of the insulating barriers 254 can be arranged between two conductive contact plugs 256 spaced apart from each other in the second horizontal direction (Y-direction). Opposite walls of each of the multiple conductive contact plugs 256 in the second horizontal direction (Y-direction) can be covered by the multiple insulating barriers 254.The multiple conductive contact plugs 256, arranged in a row in the second horizontal direction (Y-direction), can be isolated from each other by the multiple insulating barriers 254. The multiple insulating barriers 254 can each comprise a silicon nitride layer. The multiple conductive contact plugs 256 can be the ones in . Fig. The 3 shown multiple buried contacts BC are formed. A direct contact DC and a pair of conductive contact plugs 256, which are opposite each other with the direct contact DC in between, can be connected to different active cell regions A1 of the multiple active cell regions A1.

[0037] Multiple metal silicide layers 258A and multiple conductive landing pads LP can be formed on the multiple conductive contact plugs 256. The metal silicide layer 258A and the conductive landing pad LP can be arranged to overlap the conductive contact plug 256 in the vertical direction. Each of the multiple conductive landing pads LP can be connected to the conductive contact plug 256 via the metal silicide layer 258A. The multiple conductive landing pads LP can at least partially cover an upper surface of the third insulating cover pattern 250C to vertically overlap some of the multiple bit lines BL. The conductive contact plug 256, the metal silicide layer 258A and the conductive landing pad LP can form a contact structure CST that connects a lower capacitor electrode (not shown) formed on the conductive landing pad LP to the active cell area A1.

[0038] The metal silicide layer 258A can comprise cobalt silicide, nickel silicide, or manganese silicide. Each of the conductive landing pads LP can comprise a conductive barrier layer 262 and a conductive main layer 264. The conductive barrier layer 262 can comprise Ti, TiN, or a combination thereof. The conductive main layer 264 can comprise metal, metal nitride, conductive polysilicon, or a combination thereof. For example, the conductive main layer 264 can comprise W. The multiple conductive landing pads LP can have an island-like pattern on a plane. The multiple conductive landing pads LP can be electrically isolated from each other by an insulating layer 270 that fills an insulating gap 270S around each of the multiple conductive landing pads. The insulating layer 270 can comprise a silicon nitride layer, a silicon oxide layer, or a combination thereof.

[0039] In the peripheral circuit area CORE / PERI, a gate structure PG can be formed on the substrate 210. The gate structure PG can comprise a dielectric gate layer 224, a gate electrode 240, and an insulating cover structure CSP, which are sequentially layered on the peripheral active area A2.

[0040] The dielectric gate layer 224 can comprise at least one of the following, selected from: a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and a high-k dielectric layer with a dielectric constant greater than that of the silicon oxide layer. The gate electrode 240 can comprise a lower conductive pattern 230P, an intermediate conductive pattern 232P, and an upper conductive pattern 234P. The lower conductive pattern 230P, the intermediate conductive pattern 232P, and the upper conductive pattern 234P can each comprise the same materials as those of the lower conductive pattern 230B, the intermediate conductive pattern 232B, and the upper conductive pattern 234B contained in the bit line BL in the cell array region MCA.

[0041] The insulating cover structure CSP can comprise a first insulating cover pattern 236P and a second insulating cover pattern 238P. In the insulating cover structure CSP, a lower surface of the first insulating cover pattern 236P can be in contact with an upper surface of the upper conductive pattern 234P of the gate electrode 240. A lower surface of the second insulating cover pattern 238P can be in contact with an upper surface of the first insulating cover pattern 236P. In the insulating cover structure CSP, the first insulating cover pattern 236P and the second insulating cover pattern 238P can have different densities. In one or more embodiments, of the first insulating cover pattern 236P and the second insulating cover pattern 238P, the first insulating cover pattern 236P, which is closer to the upper conductive pattern 234P of the gate electrode 240, can have a first density like the first insulating cover pattern 236C in the cell array area MCA.The second insulating cover pattern 238P, located away from the upper conductive pattern 234P of the gate electrode 240, with the first insulating cover pattern 236P in between, can have a second density greater than the first, as is the case with the second insulating cover pattern 238C in the cell array region MCA. In a horizontal direction parallel to a major surface 210M of the substrate 210, the width of the first insulating cover pattern 236P is essentially the same as that of the second insulating cover pattern 238P.

[0042] In one or more embodiments, the first insulating cover pattern 236P and the second insulating cover pattern 238P can comprise the same material. In another embodiment, the first insulating cover pattern 236P and the second insulating cover pattern 238P can comprise different materials. The first insulating cover pattern 236P can comprise a silicon nitride layer, a silicon carbonitride layer, or a combination thereof. The second insulating cover pattern 238P can comprise a silicon nitride layer.

[0043] In one or more embodiments, the upper conductive pattern 234P of the gate electrode 240 can include a nitrogen atom diffusion region in a portion of its upper region. The nitrogen atom diffusion region can extend from an interface between the upper conductive pattern 234P and the first insulating cover pattern 236P of the gate electrode 240 to a point within the thickness of the upper conductive pattern 234P in the direction of the substrate 210 within the upper conductive pattern 234P. The thickness (length in the Z-direction) of the nitrogen atom diffusion region can be approximately 0.01% to approximately 10% of the total thickness (length in the Z-direction) of the upper conductive pattern 234P.For example, the nitrogen atom diffusion region with a thickness of about 0.5 nm to about 4.0 nm can extend from the interface between the upper conductive pattern 234P and the first insulating cover pattern 236P, or with a thickness of about 0.5 nm to about 4.0 nm within the upper conductive pattern 234P, but the thickness of the nitrogen atom diffusion region is not limited to this.

[0044] In the nitrogen atom diffusion region, N atoms may be in a diffused state without chemical bonding to other atoms contained in the upper conductive pattern 234P. If the upper conductive pattern 234P includes a W layer and the first insulating cover pattern 236P includes a silicon nitride layer, then in one or more embodiments, the nitrogen atom diffusion region in the upper conductive pattern 234P may include the W layer formed from W atoms, N atoms distributed between the tungsten crystal structures (i.e., between the W atoms) contained in the W layer without chemical bonding to the W atoms of the tungsten crystal structures of the W layer, and tungsten nitride particles diffused into the W layer. The tungsten nitride particles may include a chemical bond between W and N.

[0045] Opposite sidewalls of the gate structure PG can be coated with the insulating spacer 242. The insulating spacer 242 can comprise an oxide layer, a nitride layer, or a combination thereof. The gate structure PG and the insulating spacer 242 can be coated with an insulating thin film 244. The insulating thin film 244 can comprise a silicon nitride layer. An intermediate insulating layer 246, which fills a space around the gate structure PG, can be formed on the insulating thin film 244. The intermediate insulating layer 246 can comprise, but is not limited to, clay silazanes (TOSZ). The gate structure PG, the insulating thin film 244, and the intermediate insulating layer 246 can be coated with a third insulating cover layer 250. The third insulating cover layer 250 can comprise a silicon nitride layer.

[0046] In the peripheral circuit region CORE / PERI, a contact gap CS2 extends vertically through the third insulating cover layer 250, the intermediate insulating layer 246, and the insulating thin film 244, and then into the peripheral active region A2 of the substrate 210. Multiple conductive patterns CNP can be formed on the third insulating cover layer 250. These multiple conductive patterns CNP can extend in various planar shapes on the third insulating cover layer 250. Each of the multiple conductive patterns CNP can act as a contact plug extending vertically through the third insulating cover layer 250, the intermediate insulating layer 246, and the insulating thin film 244, passing over the contact gap CS2.The multiple conductive patterns CNP can each comprise a conductive barrier layer 262 and a conductive main layer 264, like the multiple conductive landing pads formed in the cell array region MCA. A metal silicide layer 258B can be located between the peripheral active region A2 and each of the multiple conductive patterns CNP. The metal silicide layer 258B can comprise cobalt silicide, nickel silicide, or manganese silicide.

[0047] Fig. Figures 6A to 6C are cross-sectional views illustrating an integrated circuit device 300 according to one or more embodiments. Fig. 6A and Fig. Figure 6B shows cross-sectional views illustrating an exemplary structure of part of the cell array area MCA in the integrated circuit device 300, and Fig. Figure 6C is a cross-sectional view showing an exemplary structure of part of a peripheral circuit area CORE / PERI in the integrated circuit device 300. The cell array area MCA of the integrated circuit device 300 can have a layout as shown in Fig. 3 is shown. Fig. Figure 6A shows a cross-sectional view along line AA' in Fig. 3, and Fig. 6B shows a cross-section along line BB' in Fig. 3.

[0048] Fig. Figure 7 is an enlarged cross-sectional view showing some elements located in a dashed area “Q2” in Fig. 6A are included.

[0049] With reference to Fig. 6A to 6C and Fig. 7 The integrated circuit device 300 has a similar structure to that of the one above with reference to Fig. 4A to 4C and Fig. Figure 5 illustrated the integrated circuit device 200. The integrated circuit device 300 can comprise several insulating cover structures CSC3, which cover the multiple bit lines BL. The insulating cover structures CSC3 can have a similar structure to that of the integrated circuit device 200, which is illustrated in Figure 5 ... Fig. 4A and Fig. The five illustrated structures exhibit CSC. However, the insulating cover structure CSC3 includes a first insulating cover pattern 336C instead of the first insulating cover pattern 236C of the insulating cover structure CSC in Fig. 4A.

[0050] A lower surface of the first insulating cover pattern 336C can be in contact with the upper surface of the upper conductive pattern 234B. A lower surface of the second insulating cover pattern 238C can be in contact with an upper surface of the first insulating cover pattern 336C.

[0051] In each of the multiple insulating cover structures CSC3, the first insulating cover pattern 336C and the second insulating cover pattern 238C can have different densities. In one or more embodiments, the first insulating cover pattern 336C can have a first density, and the second insulating cover pattern 238C can have a second density that is greater than the first density.

[0052] In the first horizontal direction (X-direction), the first insulating cover pattern 336C and the second insulating cover pattern 238C can have different minimum widths. That is, in the first horizontal direction (X-direction), the minimum width of the first insulating cover pattern 336C is smaller than that of the second insulating cover pattern 238C. Due to the difference in width between the first insulating cover pattern 336C and the second insulating cover pattern 238C in the first horizontal direction (X-direction), an undercut area can form under the second insulating cover pattern 238C near the point where a side wall of the first insulating cover pattern 336C and the lower surface of the second insulating cover pattern 238C meet. The exact structure of the first insulating cover pattern 336C is similar to the structure of the first insulating cover pattern 236C, which is described in relation to Fig. 4A, Fig. 4B and Fig. 5 has been described.

[0053] The sidewalls of the multiple bit lines BL and the sidewalls of the insulating cover structures CSC3 can be covered by multiple insulating spacers 352. Each of the multiple insulating spacers 352 can include a projecting sidewall 352S that projects toward the first insulating cover pattern 336C. ​​The exact structures of the multiple insulating spacers 352 are similar to those of the multiple insulating spacers 252 described above with reference to Fig. 4A, Fig. 4B and Fig. 5 have been described.

[0054] The multiple conductive contact plugs 256 and multiple insulating barriers 354 can be arranged in a row in the second horizontal direction (Y-direction) between the multiple bit lines BL and between the multiple insulating cover structures CSC3. Each of the multiple insulating barriers 354 can include a projecting side wall 354S that projects toward the first insulating cover pattern 336C. ​​The exact structures of the multiple insulating barriers 354 are similar to those of the multiple insulating barriers 254 described above with reference to Fig. 4A, Fig. 4B and Fig. 5 have been described.

[0055] Multiple metal silicide layers 258A and multiple conductive landing pads LP3 can be formed on the multiple conductive contact plugs 256. The conductive landing pad LP3 can overlap the conductive contact plug 256 and the metal silicide layer 258A in the vertical direction. The conductive contact plug 256, the metal silicide layer 258A, and the conductive landing pad LP3 can form a contact structure CST3 that connects a lower capacitor electrode (not shown) formed on the conductive landing pad LP3 to the active cell region A1. Part of the contact structure CST3 can include a projecting sidewall that extends toward the first insulating cover pattern 336C. ​​As shown in Fig. As shown in Figure 6A, the multiple conductive landing pads LP3 can each, for example, include a projecting sidewall LP3S that projects toward the first insulating cover pattern 336C. ​​Each of the multiple conductive landing pads LP3 can include a conductive barrier layer 362 and a conductive main layer 364. The conductive barrier layer 362 and the conductive main layer 364 can each include a projecting sidewall that projects toward the first insulating cover pattern 336C at a section corresponding to the projecting sidewall LP3S. The conductive landing pad LP3 includes the projecting sidewalls LP3S on opposite sides in the first horizontal direction (X-direction), and thus the conductive landing pad LP3 can have a non-uniform width. For example, the conductive landing pad LP3 can have a first section with a first width and a second section with a second width.The first section is located between two adjacent first insulating cover patterns 336C, and the second section is located between two adjacent second insulating cover patterns 238C. The first and second widths are measured in the first horizontal direction (X-direction). The first width may be larger than the second width. Therefore, the volume of the conductive landing pad LP3 between two adjacent first insulating cover patterns 336C may be larger than that of the conductive landing pad LP3 that does not include the protruding sidewalls LP3S. Since, as described above, the conductive landing pad LP3 includes a section with an increased volume due to the protruding sidewalls LP3S, the resistance of the conductive landing pad LP3 may be reduced.

[0056] In Fig. 6A The side walls of the conductive landing pad LP3 in the contact structure CST3 face the first insulating cover patterns 336C, and accordingly the projecting side walls LP3S are formed on the conductive landing pad LP3, however, one or more embodiments are not limited to this. For example, if an upper surface of the conductive contact plug 256 contained in the contact structure CST3 has a higher level than that in Fig. 6A shows and the side walls of the conductive contact plug 256 are opposite the first insulating cover patterns 336C, the conductive contact plug 256 can have projecting side walls that project in the direction of the first insulating cover patterns 336C.

[0057] The exact structures of the multiple conductive landing pads LP3 are similar to those of the multiple conductive landing pads LP described above with reference to Fig. 4A, Fig. 4B and Fig. 5 have been described. The exact structures of the conductive barrier layer 362 and the conductive main layer 364 are similar to those of the conductive barrier layer 262 and the conductive main layer 264, which were described above with reference to Fig. 4A, Fig. 4B and Fig. 5 have been described.

[0058] In the peripheral circuit area CORE / PERI, a gate structure PG3 can be formed on the peripheral active area A2. The gate structure PG3 includes an insulating cover structure CSP3. The insulating cover structure CSP3 can have a similar structure to that of the one in Fig. The insulating cover structure CSP shown in Figure 4C is present. However, the insulating cover structure CSP3 includes a first insulating cover pattern 336P instead of the first insulating cover pattern 236P shown in Figure 4C. Fig. 4C.

[0059] In a horizontal direction, the minimum width of the first insulating cover pattern 336P is smaller than the minimum width of the second insulating cover pattern 238P. Due to the difference in width between the first insulating cover pattern 336P and the second insulating cover pattern 238P in the horizontal direction, an undercut area can form under the second insulating cover pattern 238P near the point where a side wall of the first insulating cover pattern 336P and the lower surface of the second insulating cover pattern 238P meet. The exact structure of the first insulating cover pattern 336P is similar to the structure of the first insulating cover pattern 236P, which is described with reference to Fig. 4C has been described.

[0060] Opposite side walls of the gate structure PG3 can be covered with the isolation spacer 342. The isolation spacer 342 can include a projecting side wall 342S that projects toward the first isolation cover pattern 336P. The exact structure of the isolation spacer 342 is similar to that of the isolation spacer 242, which is described above with reference to Fig. 4C has been described.

[0061] Fig. Figures 8A to 8Q are cross-sectional views used to describe, in a processing sequence, a manufacturing process for an integrated circuit device according to one or more embodiments. The method for manufacturing the integrated circuit device 200, which refers to Fig. As illustrated in sections 4A to 4C, the following will be explained with reference to Fig. Sections 8A to 8Q are described. Fig. 8A to 8Q denote (a) cross-sectional views along line AA' in Fig. 3 according to a manufacturing sequence, and (b) denotes cross-sectional views along the line BB' in Fig. 3 according to a production sequence.

[0062] With reference to Fig. In 8A, several isolation trenches T1 and several isolation layers 212, which fill the several isolation trenches T1, are formed in the substrate 210, which has the cell array region MCA and the peripheral circuit region CORE / PERI. The several isolation layers 212 can define the several active cell regions A1 in the cell array region MCA of the substrate 210 and the peripheral active region A2 in the peripheral circuit region CORE / PERI.

[0063] Several word-direction trenches T2 (see Fig. 4B), which run parallel to each other, can be formed in substrate 210 in the cell array region MCA. To form the multiple word conduction trenches T2 with steps on their lower surfaces, the insulating layer 212 and the substrate 210 are etched by separate etching processes to differentiate the etched depth of the insulating layer 212 from the etched depth of the substrate 210. After cleaning the resulting structure, which has the multiple word conduction trenches T2, the multiple dielectric gate layers 216, the multiple gate conductors 218, and the multiple buried insulating layers 220 can be sequentially formed in the multiple word conduction trenches T2. Impurity ions are implanted into opposite sides of the multiple gate conductors 218 in the multiple active cell regions A1 to form multiple source / drain regions on the multiple active cell regions A1.In one or more embodiments, the multiple source / drain regions can be formed before the multiple gate lines 218 are formed.

[0064] Then the buffer layer 222 is formed on the substrate 210 in the cell array area MCA, and the dielectric gate layer 224 is formed on the substrate 210 in the peripheral circuit area CORE / PERI.

[0065] With reference to Fig. 8B, the lower conductive layer 230 is formed on the buffer layer 222 in the cell array region MCA and on the dielectric gate layer 224 in the peripheral circuit region CORE / PERI. The lower conductive layer 230 may contain doped polysilicon.

[0066] With reference to Fig. In step 8C, a mask pattern M21 is formed on the lower conductive layer 230. Subsequently, the lower conductive layer 230, exposed through an opening M210 of the mask pattern M21, is etched in the cell array region MCA. Then, a portion of the substrate 210 exposed as a result of the etching and a portion of the insulating layer 212 are etched to form direct contact holes DCH, which expose the active cell regions A1 of the substrate 210. The mask pattern M21 can include an oxide layer, a nitride layer, or a combination thereof. A photolithographic process can be used to form the mask pattern M21.

[0067] With reference to Fig. 8D will be the mask pattern M21 (see Fig. 8C) removed, and a direct contact DC is formed in each of the direct contact holes DCH.

[0068] In an exemplary process for forming the direct contact DC, a conductive layer is formed in the direct contact hole DCH and on an upper portion of the lower conductive layer 230 to a thickness sufficient to fill the direct contact hole DCH, and the conductive layer can be etched back only to remain in the direct contact hole DCH. The conductive layer can comprise Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0069] With reference to Fig. In embodiment 8E, the conductive intermediate layer 232 and the upper conductive layer 234 are formed sequentially on the lower conductive layer 230 and the direct contact DC in the cell array region MCA and the peripheral circuit region CORE / PERI. Each of the conductive intermediate layers 232 and the upper conductive layer 234 can comprise TiN, TiSiN, tungsten silicide, or a combination thereof. In one or more embodiments, the conductive intermediate layer 232 comprises TiN, TiSiN, or a combination thereof, and the upper conductive layer 234 can comprise W.

[0070] With reference to Fig. 8F forms a first insulating cover layer 236 on the upper conductive layer 234 in the cell array area MCA and on the peripheral circuit area CORE / PERI.

[0071] To form the first insulating cover layer 236, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process can be carried out at a first temperature, which is a relatively low temperature. The first temperature can be selected within a range of approximately 500 °C to approximately 700 °C. For example, the first temperature can be selected within a range of approximately 600 °C to approximately 650 °C. The first insulating cover layer 236 can comprise a silicon nitride layer. In this case, in the CVD or ALD process for forming the first insulating cover layer 236, a gas comprising SiH4, Si2Cl2H2, SiH6, Si2H6, Si3H8 or a combination thereof is used as a Si-containing starting material, and a gas comprising NH3, N2, NO, N2O or a combination thereof can be used as an N-containing starting material.However, one or more embodiments are not limited to the examples mentioned above.

[0072] Since the deposition process takes place at the first temperature, which is relatively low, when the first insulating cover layer 236 is formed, the formation of WN can be limited due to a reaction between the nitrogen (N)-containing starting material and the metal contained in the upper conductive layer 234, e.g., W, during the formation of the first insulating cover layer 236, or due to unwanted diffusion of N atoms from the first insulating cover layer 236 into the upper conductive layer 234. Therefore, the formation of insulating metal nitride, e.g., WN, between the upper conductive layer 234 and the first insulating cover layer 236 can be limited or reduced.

[0073] In one or more embodiments, nitrogen atoms contained in the first insulating cover layer 236 can diffuse into the upper conductive layer 234 during the formation of the first insulating cover layer 236. As a result, after the formation of the first insulating cover layer 236, a nitrogen atom diffusion region can be formed from an interface between the first insulating cover layer 236 and the upper conductive layer 234 over a portion of the thickness of the upper conductive layer 234. The exact structure of the nitrogen atom diffusion region is described above with reference to Fig. 4A to 4C described.

[0074] With reference to Fig. 8G forms the second insulating cover layer 238 on the first insulating cover layer 236 in the cell array area MCA and the peripheral circuit area CORE / PERI.

[0075] To form the second insulating cover layer 238, a CVD or ALD process can be carried out at a second temperature, which is a relatively high temperature. The second temperature is higher than the first temperature. For example, the second temperature can be selected within a range of approximately 700 °C to approximately 800 °C. The second insulating cover layer 238 can comprise a silicon nitride layer. In this case, the process for forming the second insulating cover layer 238 is the same as the process for forming the first insulating cover layer 236, which was described above with reference to Fig. 8F has been described.

[0076] The above with reference to Fig. 8F described process of the formation of the first insulating cover layer 236 and the above with reference to Fig. The process for forming the second insulating cover layer 238 described in Figure 8G can be carried out in situ or ex situ. To successfully form the first insulating cover layer 236 and the second insulating cover layer 238 in situ in the same chamber, in one embodiment the first insulating cover layer 236 and the second insulating cover layer 238 can each be formed by the CVD process, and the deposition temperature of the first insulating cover layer 236 can be lower than the deposition temperature of the second insulating cover layer 238. To form the first insulating cover layer 236 and the second insulating cover layer 238 ex situ, in another embodiment the first insulating cover layer 236 can be formed by the ALD process at the first temperature, which is relatively low, and the second insulating cover layer 238 can be formed by the CVD process at the second temperature, which is relatively high.

[0077] Since the deposition temperature of the second insulating cover layer 238 is higher than the deposition temperature when the first insulating cover layer 236 is formed, the density of the second insulating cover layer 238 can be greater than the density of the first insulating cover layer 236.

[0078] With reference to Fig. In the peripheral circuit region CORE / PERI, the dielectric gate layer 224, the lower conductive layer 230, the conductive intermediate layer 232, the upper conductive layer 234, the first insulating cover layer 236, and the second insulating cover layer 238 are structured using a mask pattern (not shown) as an etching mask. Then, the gate structure PG, comprising the dielectric gate layer 224, the gate electrode 240, the first insulating cover pattern 236P, and the second insulating cover pattern 238P, is formed in the peripheral circuit region CORE / PERI. The gate electrode 240 can comprise a lower conductive pattern 230P, a conductive intermediate pattern 232P, and an upper conductive pattern 234P.

[0079] With reference to Fig. 8I the isolation spacers 242 are formed on opposite side walls of the gate structure PG in the peripheral circuit area CORE / PERI, and an ion implantation process is carried out to form the source / drain areas in the peripheral active area A2 on opposite sides of the gate structure PG.

[0080] The insulating thin film 244 is then formed to cover exposed surfaces of the active cell array region MCA and the peripheral circuit region CORE / PERI. The insulating thin film 244 can be in contact with the upper surface of the second insulating cover layer 238 in the cell array region MCA and can be in contact with the upper surface of the second insulating cover pattern 238P in the peripheral circuit region CORE / PERI. The insulating thin film 244 can be formed by a process that is the same as or similar to the process for forming the second insulating cover layer 238 described above. Fig. 8G has been described.

[0081] In the peripheral circuit region CORE / PERI, the insulating intermediate layer 246, which fills a space around the gate structure PG, and the insulating thin film 244 are formed. The insulating intermediate layer 246 can have a planarized upper surface.

[0082] With reference to Fig. 8J The third insulating cover layer 250 is formed on the insulating thin film 244 and the insulating intermediate layer 246, which is planarized, in the cell array region MCA and the peripheral circuit region CORE / PERI. The third insulating cover layer 250 can be formed by a process that is the same as or similar to the process for forming the second insulating cover layer 238, which is described above with reference to Fig. 8G has been described.

[0083] With reference to Fig. 8K are in a state in which the third insulating cover layer 250 in the peripheral circuit area CORE / PERI is covered with a mask pattern M22, the third insulating cover layer 250, the insulating thin film 244, the second insulating cover layer 238 and the first insulating cover layer 236 in the cell array area MCA are structured by a photolithographic process, and then several insulating cover structures CSC are formed, each comprising the first insulating cover pattern 236C, the second insulating cover pattern 238C, the insulating thin film pattern 244C and the third insulating cover pattern 250C, which are sequentially layered on the upper conductive layer 234.

[0084] With reference to Fig. In 8L, the third insulating cover layer 250 in the peripheral circuit area CORE / PERI is coated with the mask pattern M22. The upper conductive layer 234, the conductive intermediate layer 232, and the lower conductive layer 230 are etched in the cell array area MCA using the multiple insulating cover structures CSC as an etching mask. Then, the multiple bit lines BL are formed, each comprising the lower conductive pattern 230B, the conductive intermediate pattern 232B, and the upper conductive pattern 234B. The resulting multi-bit line BL structure can be cleaned and dried. In one or more embodiments, the cleaning process of the resulting multi-bit line structure can be carried out using dilute high-frequency radiofrequency (DHF). The drying process can be carried out using isopropyl alcohol (IPA).After the formation of the multiple bit lines BL, a gap LS may remain between the bit lines BL. The height of the third insulating cover pattern 250C in the insulating cover structures CSC may be reduced due to the etching process for the formation of the multiple bit lines BL.

[0085] With reference to Fig. The multiple insulation spacers 252 are formed to cover the sidewalls of the multiple bit lines BL and the multiple insulating cover structures CSC. The multiple insulation spacers 252 can fill the direct contact holes DCH around the direct contacts DC.

[0086] With reference to Fig. 8N are in a state in which the third insulating cover layer 250 is covered with the mask pattern M22 in the peripheral circuit area CORE / PERI, the several insulating barriers 254 (see Fig. 4B) Each of the multiple bit lines BL in the cell array region MCA is formed to subdivide the line spaces LS into multiple contact spaces CS1. The multiple insulating barriers 254 can each overlap the gate line 218 in the vertical direction. A line space LS can be subdivided by the multiple insulating barriers 254, so that the multiple contact spaces CS1 can each have a column shape. Subsequently, structures exposed by the multiple contact spaces CS1 can be partially removed to form multiple recessed spaces RS, each of which exposes the active cell regions A1 of the substrate 210 between the bit lines BL.While the multiple insulating barriers 254 and the multiple recessed spaces RS are formed, the third insulating cover pattern 250C and the insulating spacers 252 are exposed to different etching process atmospheres, and the heights of the third insulating cover pattern 250C and the insulating spacers 252 can be further reduced.

[0087] With reference to Fig. 8O are in a state in which the third insulating cover layer 250 with the mask pattern M22 (see Fig. 8M) in the peripheral circuit area CORE / PERI is coated, the multiple conductive contact plugs 256 are formed in the cell array area MCA, wherein the multiple conductive contact plugs 256 each fill the multiple recessed spaces RS between the bit lines BL and partially fill the contact spaces CS1 between the bit lines BL.

[0088] The mask pattern M22 (see Fig. 8N) is removed to expose the third insulating cover layer 250 in the peripheral circuit area CORE / PERI, and thereafter the third insulating cover layer 250, the insulating intermediate layer 246 and the insulating thin film 244 in the peripheral circuit area CORE / PERI are etched in a state in which a mask pattern (not shown) covers the cell array area MCA to form several contact gaps CS2 which expose the peripheral active area A2 on the substrate 210. Then the mask pattern (not shown) covering the cell array area MCA is removed, and then a metal silicide layer 258A is formed on the conductive contact plugs 256 exposed by the multiple contact gaps CS1 in the cell array area MCA, and a metal silicide layer 258B is formed on surfaces of the peripheral active area A2 exposed by the multiple contact gaps CS2 in the peripheral circuit area CORE / PERI.In one or more embodiments, the metal silicide layers 258A and 258B can be formed simultaneously. In another embodiment, the metal silicide layers 258A and 258B can be formed by separate processes.

[0089] With reference to Fig. 8P coats the conductive layer 260 on exposed surfaces on the substrate 210 in the cell array region MCA and the peripheral circuit region CORE / PERI. The conductive layer 260 can comprise a conductive barrier layer 262 and a conductive main layer 264.

[0090] With reference to Fig. In step 8Q, the conductive layer 260 is structured in the cell array region MCA and the peripheral circuit region CORE / PERI. Then, multiple conductive landing pads (LP) are formed from the conductive layer 260 in the cell array region MCA, and multiple conductive patterns (CNP) are formed from the conductive layer 260 in the peripheral circuit region CORE / PERI. The multiple conductive landing pads (LP) can be arranged on the metal silicide layer and can partially overlap the multiple bit lines (BL) in a vertical direction.

[0091] According to the above with reference to Fig. In the method for fabricating the integrated circuit device 200 described in sections 8A to 8Q, when the multiple insulating cover structures CSC, which cover the multiple bit lines, are formed, the first insulating cover layer 236, which is located directly on the bit lines BL in the insulating cover structure CSC, is formed at a relatively low temperature in order to limit or reduce the formation of an undesired metal nitride layer at the interface between the multiple bit lines BL and the insulating cover structures CSC. Therefore, the increase in the resistance of the multiple bit lines BL can be reduced.

[0092] Fig. Figures 9A to 9C are cross-sectional views to describe, in a processing sequence, a method for manufacturing the integrated circuit device 300 according to one or more embodiments. The method for manufacturing the integrated circuit device 300, which refers to Fig. The illustrations in sections 6A to 6C are described below with reference to Fig. Sections 9A to 9C are described. Fig. 9A to 9C denote (a) cross-sectional views along line AA' in Fig. 3 according to the manufacturing sequence, and (b) denotes cross-sectional views along line BB' in Fig. 3 according to the processing sequence.

[0093] With reference to Fig. 9A the gate structure PG3, which comprises the dielectric gate layer 224, the gate electrode 240, the first insulating cover pattern 236P and the second insulating cover pattern 238P, is formed in the peripheral circuit area CORE / PERI in the same way as described above with reference to Fig. 8A to 8H have been described. Subsequently, exposed sidewalls of the first insulating cover pattern 236P are partially removed by a selective etching process that utilizes a difference in density between the first insulating cover pattern 236P and the second insulating cover pattern 238P. Then, the first insulating cover pattern 336P is formed with a minimum width smaller than that of the second insulating cover pattern 238P. An etchant, such as DHF, can be used to perform the selective etching process for forming the first insulating cover pattern 336P.

[0094] With reference to Fig. 9B describes the processes for forming the multiple insulating cover structures CSC3 and the multiple bit lines in the cell array area MCA on a resulting structure in Fig. 9A according to the above with reference to Fig. The manufacturing process described in sections 8I to 8L is carried out. However, in the embodiment described above with reference to Fig. The process described in 8I formed the insulation spacer 342 with projecting side walls 342S that project towards the first insulating cover pattern 336P.

[0095] Then, in the cell array area MCA, the exposed side walls of the first insulating cover pattern 236C are in Fig. 8K partially removed to form the first insulating cover pattern 336C by a selective etching process, which results in a difference in density between the first insulating cover pattern 236C in Fig. The 8K and the densities of the second insulating cover pattern 238C, the insulating thin-film pattern 244C, and the third insulating cover pattern 250C in the insulating cover structures CSC are utilized. The first insulating cover pattern 336C has a minimum width that is smaller than that of the second insulating cover pattern 238C. An etchant, such as DHF, can be used to perform the selective etching process to form the first insulating cover pattern 336C.

[0096] With reference to Fig. 9C can be the one mentioned above with reference to Fig. The 8M process described on the resulting structure in Fig. 9B. However, in this embodiment, instead of the multiple insulation spacers 252, the following can be used: Fig. 8M several insulation spacers 352 are formed which have projecting side walls 352S that project in the direction of the first insulation cover pattern 336C.

[0097] After that, the in Fig. 8N to 8Q illustrated processes on the resulting structure in Fig. 9C carried out to determine the Fig. To manufacture the integrated circuit device 300 shown in sections 6A to 6C.

[0098] According to the above with reference to Fig.The method for fabricating the integrated circuit device 300 described in sections 9A to 9C involves the formation of the multiple insulating cover structures CSC3, which cover the multiple bit lines BL, as the first insulating cover pattern 336C in the insulating cover structure CSC3 is obtained from a film formed at a relatively low temperature, with the first insulating cover pattern 336C being in contact with the bit lines BL. Therefore, the formation of an undesirable insulating metal nitride layer at an interface between the multiple bit lines BL and the insulating cover structures CSC3 can be limited or reduced, and the increase in the resistance of the multiple bit lines BL can be prevented.In the insulating cover structure CSC3, a side wall profile of the insulating cover structure CSC3 can also be optimized by using the difference between the densities of the first insulating cover pattern 336C and the second insulating cover pattern 238C, and thus the volumes of several conductive structures, e.g. the several conductive landing pads LP3, between the bit lines BL can be increased to limit the increase in resistance of the several conductive structures and improve the reliability of the integrated circuit device.

Claims

[1] Semiconductor device comprising: a substrate (210); a bitline (BL) on the substrate (210), wherein the bitline (BL) extends in a first direction (Y) which is parallel to an upper surface of the substrate (210), wherein the bitline (BL) has a lower conductive pattern (230B), a middle conductive pattern (232B) and an upper conductive pattern (234B) which are stacked sequentially along a vertical direction (Z) on the substrate (210), wherein the lower conductive pattern (230B) has doped polysilicon, the middle conductive pattern (232B) has titanium atoms, tungsten atoms and nitrogen atoms, and the upper conductive pattern (234B) has tungsten atoms; and an insulating cover structure (CSC3) on the bit line (BL), wherein the insulating cover structure (CSC3) has a first insulating cover pattern (336C), a second insulating cover pattern (238C), a third insulating cover pattern (244C) and a fourth insulating cover pattern (250C), which are stacked sequentially in the vertical direction (Z) on the bit line (BL), wherein the second insulating cover pattern (238C), the third insulating cover pattern (244C) and the fourth insulating cover pattern (250C) have substantially the same widths in a second direction (X) which is parallel to the upper surface of the substrate (210) and perpendicular to the first direction (Y), wherein the first insulating cover pattern (336C) has a lower surface which is in contact with an upper surface of the upper conductive pattern (234B) of the bit line (BL), wherein the lower surface of the first insulating cover pattern (336C) has a width which is less than a width of each of the second insulating cover pattern (238C), the third insulating cover pattern (244C) and the fourth insulating cover pattern (250C) in the second direction (X), and wherein the thickness of the third insulating cover pattern (244C) in the vertical direction (Z) is less than the thickness of each of the second insulating cover pattern (238C) and the fourth insulating cover pattern (250C) in the vertical direction (Z). [2] Semiconductor device according to claim 1, further comprising: a contact plug (256) which is arranged adjacent to the bit line (BL); and a conductive landing pad (LP3) which is arranged on the contact plug (256), wherein the conductive landing pad (LP3) is opposite the insulating cover structure (CSC3) in the second direction (X). [3] Semiconductor device according to claim 1, further comprising an insulating spacer (352) which covers a side wall of the bit line (BL) and a side wall of the insulating cover structure (CSC3), wherein the insulating spacer (352) has a protruding side which projects towards the first insulating cover pattern (336C) along the second direction (X). [4] Semiconductor device according to claim 1, further comprising: a contact plug (256) which is arranged adjacent to the bit line (BL); and a conductive landing pad (LP3) which is arranged on the contact plug (256), wherein the conductive landing pad (LP3) is opposite the insulating cover structure (CSC3) in the second direction (X), wherein the conductive landing pad (LP3) has a conductive main layer (364) and a barrier layer (362) which surrounds the conductive main layer (364). [5] Semiconductor device according to claim 1, wherein each of the first to fourth insulating cover patterns (336C, 238C, 244C, 250C) of the insulating cover structure (CSC3) comprises silicon nitride. [6] Semiconductor device according to claim 1, further comprising an insulating spacer (352) which covers a side wall of the bit line (BL) and a side wall of the insulating cover structure (CSC3), wherein the insulating spacer (352) has a region which is in contact with the upper surface of the upper conductive pattern (234B) of the bit line (BL). [7] Semiconductor device according to claim 1, further comprising an insulating spacer (352) which covers a side wall of the bit line (BL) and a side wall of the insulating cover structure (CSC3), wherein the insulating spacer (352) comprises oxide and nitride. [8] Semiconductor device according to claim 1, wherein the thickness of the bit line (BL) in the vertical direction (Z) is less than the thickness of the insulating cover structure (CSC3) in the vertical direction (Z). [9] Semiconductor device according to claim 1, further comprising an insulating spacer (352) which covers a side wall of the bit line (BL) and a side wall of the insulating cover structure (CSC3), wherein the insulating spacer (352) is in contact with a side wall of each of the first to fourth insulating cover patterns (336C, 238C, 244C, 250C) of the insulating cover structure (CSC3). [10] Semiconductor device comprising: a substrate (210) which has a cell region (MCA) and a peripheral region (CORE / PERI); a bitline (BL) which is arranged in the cell region (MCA) of the substrate (210), wherein the bitline (BL) extends in a first direction (Y) which is parallel to an upper surface of the substrate (210), wherein the bitline (BL) has a lower conductive pattern (230B), a middle conductive pattern (232B) and an upper conductive pattern (234B) which are stacked sequentially along a vertical direction (Z) on the substrate (210), wherein the lower conductive pattern (230B) comprises doped polysilicon, wherein the middle conductive pattern (232B) comprises titanium atoms, tungsten atoms and nitrogen atoms, and the upper conductive pattern (234B) comprises tungsten atoms; a cell insulating cover structure (CSC3) on the bit line (BL), wherein the cell insulating cover structure (CSC3) has a first insulating cover pattern (336C), a second insulating cover pattern (238C), a third insulating cover pattern (244C) and a fourth insulating cover pattern (250C) which are stacked sequentially along the vertical direction (Z) on the bit line (BL); a peripheral conductive line (240) which is arranged in the peripheral area (CORE / PERI) of the substrate (210); and a peripheral insulating cover structure (CSP3) on the peripheral conductive line (240), wherein the second insulating cover pattern (238C), the third insulating cover pattern (244C) and the fourth insulating cover pattern (250C) of the cell insulating cover structure (CSC3) have substantially the same widths in a second direction (X) which is parallel to the upper surface of the substrate (210) and perpendicular to the first direction (Y), wherein the first insulating cover pattern (336C) of the cell insulating cover structure (CSC3) has a lower surface which is in contact with an upper surface of the upper conductive pattern of the bit line (BL), wherein the lower surface of the first insulating cover pattern (336C) has a width which is less than the width of each of the second insulating cover pattern (238C), the third insulating cover pattern (244C) and the fourth insulating cover pattern (250C) in the second direction (X), and wherein the thickness of the third insulating cover pattern (244C) in the vertical direction (Z) is less than the thickness of each of the second insulating cover pattern (238C) and the fourth insulating cover pattern (250C) in the vertical direction (Z). [11] Semiconductor device according to claim 10, wherein the peripheral conductive line (240) comprises a peripheral lower conductive pattern (230P), a peripheral middle conductive pattern (232P) and a peripheral upper conductive pattern (234P) which are stacked sequentially along the vertical direction (Z) on the substrate (210), and wherein the peripheral lower conductive pattern (230P) comprises doped polysilicon, the peripheral middle conductive pattern (232P) comprises titanium atoms, tungsten atoms and nitrogen atoms, and the peripheral upper conductive pattern (234P) comprises tungsten atoms. [12] Semiconductor device according to claim 10, further comprising a pair of insulation spacers (352) covering both side walls of the bit line (BL) and both side walls of the cell insulating cover structure (CSC3), each of the pair of insulation spacers (352) having a protruding side wall which protrudes towards the first insulating cover pattern (336C) along the second direction (X). [13] Semiconductor device according to claim 10, further comprising: a contact plug (256) which is arranged adjacent to the bit line (BL); and a conductive landing pad (LP3) which is arranged on the contact plug (256), wherein the conductive landing pad (LP3) is opposite the cell insulating cover structure (CSC3) in the second direction (X), wherein the conductive landing pad (LP3) has a conductive main layer (364) and a barrier layer (362) which surrounds the conductive main layer (364). [14] Semiconductor device according to claim 10, further comprising an insulating spacer (352) which covers a side wall of the bit line (BL) and a side wall of the cell insulating cover structure (CSC3), wherein the insulating spacer (352) has a region which is in contact with the upper surface of the upper conductive pattern (234B) of the bit line (BL). [15] Semiconductor device according to claim 10, wherein the thickness of the bit line (BL) in the vertical direction (Z) is less than the thickness of the cell insulating cover structure (CSC3) in the vertical direction (Z). [16] Semiconductor device according to claim 10, further comprising an insulating spacer (352) which covers a side wall of the bit line (BL) and a side wall of the cell insulating cover structure (CSC3), wherein the insulating spacer (352) is in contact with a side wall of each of the first to fourth insulating cover pattern (336C, 238C, 244C, 250C) of the cell insulating cover structure (CSC3). [17] Semiconductor device comprising: a substrate (210); a pair of bitlines (BL) extending parallel to each other on a substrate (210) in a first direction (Y) which is parallel to an upper surface of the substrate (210), each of the pair of bitlines (BL) having a lower conductive pattern (230B), a middle conductive pattern (232B) and an upper conductive pattern (234B) which are stacked sequentially along a vertical direction (Z) on the substrate (210), wherein the lower conductive pattern (230B) has doped polysilicon, the middle conductive pattern (232B) has titanium atoms, tungsten atoms and nitrogen atoms, and the upper conductive pattern (234B) has tungsten atoms; and a pair of insulating cover structures (CSC3) each covering the pair of bit lines (BL), each of the pair of insulating cover structures (CSC3) having a first insulating cover pattern (336C), a second insulating cover pattern (238C), a third insulating cover pattern (244C) and a fourth insulating cover pattern (250C) stacked sequentially on the bit line (BL) in the vertical direction (Z); and a contact structure (CST) extending in the vertical direction (Z) from a position between the pair of bit lines (BL) to a position between the pair of insulating cover structures (CSC3), wherein the second insulating cover pattern (238C), the third insulating cover pattern (244C) and the fourth insulating cover pattern (250C) have substantially the same widths in a second direction (X) which is parallel to the upper surface of the substrate (210) and perpendicular to the first direction (Y), wherein the first insulating cover pattern (336C) has a lower surface which is in contact with an upper surface of the upper conductive pattern (234B) of one of the pair of bit lines (BL), wherein the lower surface of the first insulating cover pattern (336C) has a width which is less than a width of each of the second insulating cover pattern (238C), the third insulating cover pattern (244C) and the fourth insulating cover pattern (250C) in the second direction (X), and wherein the thickness of the third insulating cover pattern (244C) in the vertical direction (Z) is less than the thickness of the second insulating cover pattern (238C) and the fourth insulating cover pattern (250C) in the vertical direction (Z). [18] Semiconductor device according to claim 17, wherein each of the first to fourth insulating cover patterns (336C, 238C, 244C, 250C) of each of the pair of insulating cover structures (CSC3) comprises silicon nitride. [19] Semiconductor device according to claim 17, further comprising a plurality of insulation spacers (352) which are each arranged between one of the pair of bit lines (BL) and the contact structure (CST) and between one of the pair of insulating cover structures (CSC3) and the contact structure (CST), wherein at least one of the plurality of insulation spacers (352) has a protruding side wall (352S) which protrudes in the direction of the first insulating cover pattern (336C) from one of the pair of insulating cover structures (CSC3) along the second direction (X). [20] Semiconductor device according to claim 17, further comprising a plurality of isolation spacers (352) which are each arranged between one of the pair of bit lines (BL) and the contact structure (CST) and between one of the pair of insulating cover structures (CSC3) and the contact structure (CST), wherein at least one of the plurality of isolation spacers (352) has a region which is in contact with the upper surface of the upper conductive pattern (234B) of one of the pair of bit lines (BL).

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