Digital mobile radio with improved transceiver

Abstract

Apparatus for performing signal detection, the apparatus being intended to be coupled to a baseband integrated circuit (BBIC) (216) of a mobile station radio (MS) (200), and comprising: a memory module (206) for storing data associated with a signal received by an antenna (202) of the MS; and a communication detection module (208) for: Generating a field strength indicator (RSSI - Received Signal Strength Indicator) for the signal while the BBIC (216) is in a sleep mode; and Providing the RSSI to a microcontroller unit (MCU) (214) of the MS (200), wherein the memory module (206) is to provide the data to the BBIC (216) based on the RSSI indicating that a field strength of the signal exceeds a threshold.

Description

Priority data

[0001] The present application is a non-provisional application and claims the benefit of PCT application filed on January 18, 2019, with serial number PCT / CN2019 / 072382, entitled “DIGITAL MOBILE RADIO WITH ENHANCED TRANSCEIVER,” which is hereby incorporated by reference in its entirety. Area of ​​Revelation

[0002] The present disclosure relates to radio technology. More particularly, the present disclosure describes apparatus and procedures related to improved transceivers for digital mobile radio. General state of the art

[0003] Digital Mobile Radio (DMR) has emerged as a popular radio protocol for land mobile radio. Mobile station radios (MS), also known as DMR radios or DMR walkie-talkies, often support both DMR and analog frequency modulation (FM). To support both DMR and FM, the MS determines whether it is receiving a DMR signal or an FM signal.

[0004] The MS contains a radio frequency (RF) transceiver (TRx) and a baseband integrated circuit (BBIC). In previous implementations, the TRx contains a TRx transmitter channel (RF-Tx) and a TRx receiver channel (RF-Rx) for transmitting and receiving signals via an antenna of the MS. The BBIC determines whether the received signals are a DMR signal or an FM signal.

[0005] Previous implementations of an MS switch between three states during operation. In a transmit state (TX state), the RF Tx and BBIC are in an active mode to provide for the transmission of signals via the antenna. In a receive state (RX state), the RF Rx and BBIC are in an active mode to provide for the reception of signals via the antenna. In an idle state, the MS is put into a sleep state to conserve power. However, the MS has wake periods during the idle state to detect incoming signals. During these wake periods, the RF Rx and BBIC in previous implementations are in an active mode to perform DMR signal detection. While the idle state conserves some power, keeping the RF Rx and BBIC in active mode during the wake periods causes both the RF Rx and BBIC to draw power during these time periods.Since the current in an MS is limited, drawing current can affect the MS's working time between required charges.

[0006] US 2006 / 0 240 798 A1 describes a method and device for controlling sleep modes in a wireless transceiver, in which energy efficiency is improved in particular by automatically controlling the switching on and off of certain components. A hardware-based control logic module ("sleep control logic") is responsible for the precise implementation of sleep phases independently of the main processor, which merely specifies the timing. This separation enables low-latency and power-saving control, particularly in OFDM reception systems with bursty communication in which subsystems are shut down during inactivity phases. In addition, a so-called "snooze" mode is introduced, in which only some of the components are switched off to enable a quick return to the active state as soon as the decoder has completed its tasks.

[0007] US 2006 / 0 252 448A1 describes a wireless communication system in which energy consumption is significantly reduced through intelligent interaction between a receiving unit and a control unit, particularly in battery-operated base and end stations such as those used in security networks. The control unit is only activated when a received signal exceeds a predetermined reception strength, which is controlled by an RSSI (Received Signal Strength Indicator) comparison at regular intervals. In addition, received data is only forwarded for processing if it matches predefined comparison data, further reducing the operating time of the control unit. Brief presentation of Revelation

[0008] Devices and methods relating to digital mobile radio (DMR) with an improved transceiver are disclosed herein. The transceiver detects signals received by a mobile station radio (MS). By detecting the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing the amount of power consumed by the entire MS while the signals are being detected.

[0009] According to one aspect, a device may perform signal detection. The device may be coupled to a baseband integrated circuit (BBIC) of a mobile station radio (MS). The device may include a memory module for storing data associated with a signal received by an antenna of the MS. The device may further include a communication detection module for generating a field strength indicator (RSSI) for the signal while the BBIC is in a sleep mode and may provide the RSSI to a microcontroller unit (MCU) of the MS, wherein the memory module provides the data to the BBIC based on the RSSI indicating that a field strength of the signal exceeds a threshold.

[0010] According to another aspect, an MS may include an antenna, wherein a BBIC is to be in a sleep mode during wake periods of an idle state of the MS. The MS may further include a transceiver coupled to the antenna and the BBIC, the transceiver comprising: a communications processing module for receiving data associated with signals from the antenna, the signals received by the antenna during the wake periods; and generating processed data from the received data. The transceiver may further include an MCU for identifying a digital mobile radio (DMR) signal or a frequency modulation (FM) signal from the processed data, wherein the MCU is to trigger a wake-up procedure of the BBIC in response to an identification of the DMR signal or the FM signal.

[0011] According to another aspect, instructions may be stored on one or more non-transitory computer-readable storage media, wherein the instructions, when executed by an MCU of a transceiver of a DMR MS, cause the MCU to perform one or more operations. The operations may include identifying a DMR signal or an FM signal from processed data retrieved by a communications processing module of the MS, wherein the processed data is associated with a signal received by the MS during a wake period of an idle state of the MS. The operations may further include initiating a baseband integrated circuit (BBIC) wake-up procedure in response to identifying the DMR signal or the FM signal and causing the communications processing module to provide the processed data to the BBIC. Short description of the drawings

[0012] For a more complete understanding of the nature and advantages of the disclosed subject matter, reference is now made to the following detailed description of embodiments and to the accompanying drawings, in which: Fig. 1 shows an exemplary environment that the MS can implement with an improved transceiver, according to some embodiments, Fig. 2 shows a portion of an exemplary MS with improved transceiver according to some embodiments, Fig. 3 is a diagram of a first portion of an exemplary communication processing module according to some embodiments, Fig. 4 is a diagram of a second portion of the exemplary communication processing module of Fig. 3 according to some embodiments, Fig. 5 is a diagram of a third portion of the exemplary communication processing module of Fig. 3 according to some embodiments, Fig. 6 shows an exemplary state diagram that may be used by an MS, according to some embodiments, Fig. 7 shows a first portion of an exemplary flowchart for an MS according to some embodiments, Fig. 8 illustrates a second portion of the exemplary flowchart for an MS according to some embodiments. Detailed description

[0013] The present disclosure relates to radio technology. More particularly, the present disclosure describes apparatus and procedures related to DMR (Digital Mobile Radio) communications using improved transceivers.

[0014] The following description and drawings set forth in detail certain illustrative implementations of the subject matter, indicating several ways in which the various principles of the subject matter may be carried out. However, the illustrative examples are not exhaustive of the many possible embodiments of the disclosure. Other objects, advantages, and features of the subject matter disclosed herein are set forth below in light of the drawings, where applicable.

[0015] With the advent of mobile communications devices, the goal of implementing systems that are both battery-efficient and support multiple signaling protocols has evolved. In particular, land mobile radio has seen the development of mobile station radios (MSs) that support multiple radio protocols while maintaining battery efficiency to provide longer battery life for battery-dependent MSs. Regarding radio protocols, MSs often support both DMR and frequency modulation (FM) communications.

[0016] Previous implementations of an MS included a transceiver for transmitting and receiving signals via an antenna of the MS and a baseband integrated circuit (BBIC) for performing radio control functions of the MS. Both the transceiver and the BBIC had to be in an active mode to detect signals received by the MS. One approach to conserving power in these previous implementations involved transitioning the MS to an idle state when certain elements were placed in sleep mode. To maintain proper detection of received signals by the MS during the idle state, periodic wake periods are implemented during the idle state, involving a transition of a subset of the elements (including the transceiver and the BBIC) back to active mode to detect incoming signals from the MS.

[0017] The subject matter disclosed herein, comprising the improved transceiver, allows for the detection of incoming signals while a BBIC or digital signal processor (DSP) (collectively referred to in this disclosure as a "BBIC") remains in a sleep mode. In particular, the transceiver may operate with a microcontroller unit (MCU) of the MS to detect whether signals are being received by the MS. Accordingly, the BBIC may remain in sleep mode during wake periods of the MS's idle state, rather than entering an active mode during wake periods to detect whether signals are being received by the MS. The BBIC's sleep mode draws less power than the BBIC's active mode.Accordingly, power is saved by keeping the BBIC in sleep mode for a longer period, thereby extending the battery life of the MS compared to the embodiments where the BBIC must be in active mode during the awake periods of the idle state.

[0018] Fig. Figure 1 illustrates an exemplary environment 100 that the enhanced transceiver MS may implement, according to some embodiments. In particular, the environment 100 illustrates components that may comprise a land mobile radio system. The land mobile radio system, or portions thereof, may support DMR communications, FM communications, or some combination thereof. For example, the land mobile radio system may support communications encoded according to DMR protocols or FM approaches.

[0019] The environment 100 may include one or more MSs 102. The MSs 102 may include DMR MSs in some embodiments. The MSs 102 may include enhanced transceivers according to the embodiments disclosed herein. The MSs 102 may support DMR communications and FM communications. In particular, the MSs 102 may be capable of receiving and / or transmitting signals encoded according to DMR protocols and FM approaches, and encoding and / or decoding signals according to DMR protocols and FM approaches. In other embodiments, each of the MSs 102 may support DMR communications, FM communications, or both DMR communications and FM communications.

[0020] One or more of the MSs 102 may be capable of establishing direct communication links with other MSs 102. For example, a first MS 102a may establish a communication link 104 with a second MS 102b. The communication link 104 may be a wireless connection and may be established when the first MS 102a and the second MS 102b are within a certain proximity of each other. The first MS 102a and the second MS 102b may exchange communications over the communication link 104 after the communication link 104 has been established.

[0021] The environment 100 may further include one or more base stations (BSs) 106, which may also be referred to as repeaters. The BSs 106 may receive communications from one remote device and transmit the communications to another remote device. For example, the BSs 106 may receive a communication from one of the MSs 102 and transmit the communication to one or more of the other MSs 102, may receive a communication from one of the MSs 102 and transmit the communication to a core infrastructure (as described below), may receive a communication from a core infrastructure and transmit the communication to one or more of the MSs 102, or some combination thereof.

[0022] Each of the BSs 106 may provide for the establishment of communication links by the MSs 102 when the MSs 102 are within a certain proximity of the BSs 106. For example, the first MS 102a may establish a communication link 108 with a first BS 106a, and the second MS 102b may establish a communication link 110 with the first BS 106a. The communication link 108 and the communication link 110 may be wireless connections. The first BS 106a may provide for communication between the first MS 102a and the second MS 102b when the first MS 102a and the second MS 102b are not within close enough proximity to each other to communicate directly. For example, the first MS 102a and the second MS 102b may use the communication link 108, the communication link 110, and the first BS 106a to exchange communications.

[0023] The environment 100 may further include one or more core infrastructures, such as a core infrastructure 112. The core infrastructure 112 may facilitate communication between multiple BSs 106. For example, the core infrastructure 112 may include a communication link 114 with the first BS 106a and a communication link 116 with a second BS 106b in the illustrated embodiment. The communication link 114 and the communication link 116 may include wireless connections, wired connections, or some combination thereof. The first BS 106a and the second BS 106b may exchange communications via the communication link 114, the communication link 116, and the core infrastructure 112. There is the capability of exchanging communications between MSs 102 having communication links to different BSs 106.For example, a third MS 102c may establish a communication link 118 with the second BS 106b. The first MS 102a and the third MS 102c may exchange communications via the communication link 108, the first BS 108a, the communication link 114, the core infrastructure 112, the communication link 116, the second BS 106b, and the communication link 118. The core infrastructure 112 may further generate communications that may be transmitted via the BSs 106 to one or more of the MSs 102, may provide for utilization of resources of the core infrastructure 112 by the MSs 102, or some combination thereof.

[0024] The environment 100 may further include a network entity 120. The network entity 120 may be coupled to the core infrastructure 112. The network entity 120 may include a local area network (LAN), a wide-area network (WAN), or another data transmission network. The network entity 120 may provide for the utilization of resources by the core infrastructure 112 and / or the MSs 102. Furthermore, the network entity 120 may generate communications that may be transmitted to one or more of the MSs 102.

[0025] The components within environment 100 may implement procedures for communication among the devices. For example, MSs 102 may switch between states during operation, where the different states may involve different operations of MSs 102. In particular, each MS 102 may switch between a transmit state (TX state), a receive state (RX state), and an idle state.

[0026] In the TX state, the MSs 102 may be configured to transmit communications. In particular, a radio frequency transceiver (RF-Tx) transmitter channel and a BBIC of the MSs 102 may be in an active mode to allow transmission of communications from the MSs 102. In some embodiments, the MSs 102 may be in the TX state for five percent of the MSs 102's operating time. In other embodiments, the amount of time the MSs 102 are in the TX state may differ from five percent.

[0027] In the RX state, the MSs 102 may be configured to receive communications. In particular, a radio frequency transceiver (RF-Rx) channel and the BBIC of the MSs 102 may be in an active mode to allow reception of communications by the MSs 102. In some embodiments, the MSs 102 may be in the RX state for five percent of the MSs 102's operating time. In other embodiments, the amount of time the MSs 102 are in the RX state may differ from five percent.

[0028] In the idle state, the MSs 102 may be configured to maintain one or more components of the MSs 102 in a sleep mode. When placed in sleep mode, each component in sleep mode may disable and / or suspend certain operations of the component. Power consumption of the components in sleep mode is lower than when the component is in active mode. Accordingly, maintaining the components in sleep mode reduces power consumption from a battery of the MSs 102, which may extend the operating time of the MSs 102 for a charge amount of the battery. In some embodiments, the MSs 102 may be in the idle state for 90 percent of the operating time of the MSs 102. In other embodiments, the amount of time the MSs 102 are in the idle state may differ from 90 percent.

[0029] While the MSs 102 are in the idle state, they may continue to receive communications from the other MSs 102 and / or the BSs 106. Missing received communications is undesirable, so certain components of the MSs 102 may switch to active mode for periods of time (referred to as "wake periods") to detect any communications received by the MSs 102. In particular, an MCU and transceiver of the MSs 102 may switch to active mode during the wake periods to detect any communications received by the MSs 102, while a BBIC of the MSs 102 may be maintained in sleep mode during the wake periods. Having the BBIC in sleep mode saves power compared to previous approaches to wake periods, where the MCU, transceiver, and BBIC of a previous MS had to be in active mode during wake periods to detect any communications received by the previous MS.The ability to maintain the BBIC in sleep mode during waking periods is facilitated by improved transceivers described throughout this disclosure.

[0030] While environment 100 illustrates an implementation of a land mobile radio system, it should be understood that other implementations of land mobile radio systems may include more or fewer components than illustrated in environment 100. For example, some other implementations of a land mobile radio system may omit the network entity 120, the core infrastructure 112, and / or the BSs 106. Furthermore, the implementation of the MSs 102 with the enhanced transceiver is not limited to land mobile radio systems and may be implemented in other radio communication systems, such as other radio communication systems that support DMR communications, FM communications, or both DMR and FM communications.

[0031] Fig. Figure 2 illustrates a portion of an exemplary MS 200 with enhanced transceiver according to some embodiments. In particular, Fig. 2 is a simplified diagram illustrating some components of the MS 200 related to the subject matter of the present disclosure. It is understood that the MS 200 may include additional components and connections implemented in wireless communication devices. Furthermore, the portion of the MS 200 may be included in any of the MS 102 ( Fig. 1).

[0032] The MS 200 may include an antenna 202. The antenna 202 may be used for the transmission and reception of signals by the MS 200. In other embodiments, the MS 200 may include more than one antenna, where some of the antennas may be used for the transmission of signals and others may be used for the reception of signals.

[0033] The MS 200 may further include a front-end module 220 coupled to the antenna 202. The front-end module 220 may include one or more discrete devices. For example, the front-end module 220 may include one or more power amplifiers (PAs), RF switches, bandpass filters, low-noise amplifiers, or some combination thereof. Signals received by the antenna 202 may propagate to the front-end module 220 for processing by the discrete devices.

[0034] The MS 200 may further include a transceiver 204 coupled to the front-end module 220. The transceiver 204 may manage the transmission and reception of signals via the antenna 202. For example, the transceiver 204 may schedule transmissions via the antenna 202. Furthermore, the transceiver 204 may detect signals received by the antenna 202.

[0035] Transceiver 204 may include a receiver channel. Specifically, transceiver 204 may include an RF Rx. The RF Rx may include a flexible-bandwidth direct conversion receiver. The flexible-bandwidth direct conversion receiver, in some embodiments, may include a highly linear quadrature downconverter, a pair of single-pole programmable low-pass filters, and a pair of high-dynamic-range sigma-delta analog-to-digital (AD) converters. Furthermore, the flexible-bandwidth direct conversion receiver may perform digital signal processing functions.

[0036] The transceiver 204 may further include a communications processing module 218. The communications processing module 218 may include a memory module 206. The memory module 206 may store data associated with signals received by the transceiver 204. For example, the memory module 206 may store data associated with signals received by the transceiver 204 from the antenna 202. In some embodiments, the memory module 206 may further store a test pattern, as described further throughout the present disclosure. The memory module 206 may operate as a buffer that stores the data to be accessed at some time after the signals are received.

[0037] The communication processing module 218 may further include a communication detection module 208. The communication detection module 208 may facilitate the detection of communications received by the transceiver 204. In particular, the communication detection module 208 may facilitate the detection of signals associated with communications received by the transceiver 204. The communication detection module 208 may facilitate the detection of DMR signals, other TDMA (Time Division Multiple Access)-FSK (Frequency Shift Keying) signals, analog FM signals, or some combination thereof. Detecting the signals may include calculating a field strength indicator (RSSI) and determining whether the field strength exceeds a threshold based on the RSSI. Furthermore, detecting the signals may include frame synchronization (SYNC) code correlation for DMR signals and other TDMA-FSK signals.Fast Fourier transform (FFT)-based spectrum estimation can be used to detect analog FM signals. Signal detection can be robust and immune to low signal-to-noise ratios (SNR), carrier frequency offsets, and adjacent-channel interference.

[0038] The communication detection module 208 may further include a demodulation module 210. The demodulation module 210 may facilitate the demodulation of signals received by the transceiver 204. In particular, the demodulation module 210 may apply demodulation methodologies and / or filtering to facilitate demodulation of the signals. The demodulation methodologies and / or filtering applied by the demodulation module 210 may depend on the type of signal to which the methodologies and / or filtering are applied. For example, an arctan-first methodology, a differentiator-first with phase increment over a sample methodology, or a differentiator-first with phase increment over a symbol duration methodology may be applied. Furthermore, low-pass filtering may be applied to analog FM signals in some embodiments.Pulse shape filtering may be applied to DMR signals and other TDMA-FSK signals in some embodiments. Pulse shape filtering may be programmable in some embodiments. For example, pulse shape filtering for DMR / 4FSK signals may load an SRRC (square root raised cosine) filter profile. Pulse shape filtering for P25 / C4FM may load an RRC (root raised cosine) filter profile. The slope of the filters may be 0.2.

[0039] The communication detection module 208 may further include an information module 212. The information module 212 may generate and / or store information associated with a signal received by the transceiver 204, which information may be used to process the signal. For example, the information module 212 may perform cross-correlation operations on data associated with a signal and store the result of the cross-correlation operations, may determine a timing error associated with the data and store the timing error, may store a digital processing (DP) output result, or some combination thereof. The memory module 206, the communication detection module 208, the demodulation module 210, and the information module 212 may be included in an RF Rx of the transceiver 204.

[0040] The transceiver 204 may further include an MCU 214. The MCU 214 may facilitate the performance of one or more of the operations performed by the transceiver 204. For example, the MCU 214 may operate with the communication detection module 208 to detect the signals. Furthermore, the MCU 214 may operate with the demodulation module to determine what methodology and / or filtering to apply to the data associated with the signals and may operate with the information module 212 to generate some of the information and use the information to process the signal. The MCU 214 may include or be coupled to one or more computer-readable media having instructions stored thereon, where the MCU 214 may perform one or more operations in response to execution of the instructions by the MCU 214.

[0041] The MS 200 may further include a BBIC 216. The BBIC 216 may be coupled to the transceiver 204. The BBIC 216 may perform signal conversion for signals received from the transceiver 204. For example, the BBIC 216 may decode signals received from the transceiver 204. The BBIC 216 may include an MCU 222 that facilitates signal conversion for the signals. The MCU 222 may include or be coupled to one or more computer-readable media having instructions stored thereon, where the MCU 222 may perform one or more operations in response to execution of the instructions by the MCU 222.

[0042] Fig. 3 illustrates a diagram of a first portion 300 of an exemplary communication processing module according to some embodiments. In particular, the components of the illustrated first portion 300 may be incorporated into the communication processing module 218 ( Fig. 2) within an RF-Rx of the transceiver 204 ( Fig. 2) can be implemented. For example, a first part of the components can be contained in the memory module 206, and a second part of the components can be contained in the communication detection module 208. Further illustrated Fig. 3 MS components 334 that can prepare data for the communication processing module. For example, the MS components 334 can be connected between one or more antennas (such as antenna 202 ( Fig. 2)) of an MS (such as the MSs 102 ( Fig. 1)) and the communications processing module. The MS components 334 can generate data for processing by the communications processing module based on signals received by the antenna.

[0043] The MS components 334 may include one or more analog-to-digital converters (ADCs) 336. The ADCs 336 may receive analog signals received by the antennas as input and output digital representations of the signals. The ADCs 336 may be coupled to receive paths 338 for receiving data from an antenna in the illustrated embodiment.

[0044] The MS components 334 may further include one or more decimation filters and a digital correction data path 342 (referred to as "decimation filters 342"). The decimation filters 342 may be coupled to the output of the ADCs 336 and may receive data output by the ADCs 336. The decimation filters 342 may reduce a sampling rate of the data received from the ADCs 336. The decimation filters 342 may further remove data corresponding to out-of-band signals and noise from the data received from the ADCs 336.

[0045] The first section 300 may include a multiplexer 302. Inputs of the multiplexer 302 may be coupled to an output of the decimation filters 342 and to an input 306 of the transceiver from an MCU (such as the MCU 214 ( Fig. 2)). Input 306 may receive a test pattern from the MCU. Multiplexer 302 may further receive a control signal from the MCU indicating which of the data from decimation filters 342 and data at input 306 should be propagated to an output of multiplexer 302.

[0046] The first section 300 may further include a memory device 308. The memory device 308 may be coupled to the output of the multiplexer 302 and may store data output by the multiplexer 302. The memory device 308 may, in some embodiments, include a FIFO (First-In, First-Out) memory device. The memory device 308 may receive write and read commands (such as a write enable trigger and a read enable trigger) from the MCU that indicate when the memory device 308 should store data and when the memory device 308 should output stored data to an output of the memory device 308.

[0047] The storage device 308 may further receive indications of a position where a read pointer should be located and / or indications of a position where a write pointer should be located. For example, the storage device 308 may receive indications that the read pointer should be positioned at a certain set of memory locations from the write pointer, the read pointer should be positioned a certain set of memory positions from a current position of the read pointer, or the read pointer and the write pointer should be positioned at the same location. In some embodiments, the indications may include an indication of a position for the read pointer relative to the current write pointer location, an indication of an amount of data to be bypassed by the read pointer, and an indication that the read pointer should be positioned at the same position as the current write pointer location.

[0048] In some embodiments, the memory device 308 may have a depth size of at least 4096. Accordingly, the memory device 308 may store an input stream of 24,000 samples per second (ksps) for more than 170 milliseconds (ms). The memory device 308 may include a write enable control bit and a read enable control bit that enable writing and reading, respectively, to the memory device 308. The memory device 308 may further include a status register that indicates how much data is buffered in the memory device 308. The data written to the memory device 308 may overflow, although the most recently received 4096 samples may be stored if the data limit of the memory device 308 is hit.

[0049] The memory device 308 may have a separate write clock and read clock. In some embodiments, the write clock may have a frequency of 24 kilohertz (kHz). The read clock may have a frequency greater than the write clock. For example, the read clock may have a frequency that is twice, four times, or eight times the frequency of the write clock. The read clock may be faster than an input data sampling rate of the memory device 308. The memory device 308 and the multiplexer 302 may be implemented in a memory module (such as the memory module 206 ( Fig. 2)) of the communication processing module.

[0050] The first section 300 may further include a multiplexer 310. The multiplexer 310 may have as inputs the output of the decimation filters 342 and the output of the memory device 308. The multiplexer 310 may further receive a control signal from the MCU indicating which of the data output by the decimation filters 342 and the data output by the memory device 308 should be propagated to an output of the multiplexer 310.

[0051] The first section 300 may further include a counter 312. The counter 312 may be coupled to an output of the multiplexer 310 and may count a data valid signal. For example, the counter 312 may count a number of edges or a number of a certain state of the data valid signal. The counter 312 may further receive a counter enable bit from the MCU indicating whether the counter 312 should be enabled or disabled. Furthermore, the counter 312 may receive a self-clear control bit from the MCU, which causes the counter 312 to clear its current value. A value of the counter 312 may be reset by the MCU or a BBIC (such as the BBIC 216 ( Fig. 2)) of the MS can be read.

[0052] Counter 312 may also receive an indication of a counter threshold from the MCU. If a value of counter 312 equals the threshold, an interrupt is triggered. Counter 312 may continue counting after the interrupt is triggered.

[0053] In some embodiments, counter 312 may comprise a 16-bit counter. The counter may be driven by the same read clock used by memory device 308. Counter 312 may continue to count the data valid signal until the counter value reaches 65535. After the value reaches 65535, counter 312 may maintain the value until the counter is cleared.

[0054] The first section 300 may further include converter components 314. The converter components 314 may, in some embodiments, include a digital downconverter. The converter components 314 may be coupled to the output of the multiplexer 310 and remove a carrier frequency offset from data received at the output of the multiplexer 310. A DDS (Direct Digital Synthesizer) FTW (Frequency Tuning Word) used by the converter components 314 may be 32 bits wide and may be set by the MCU. Furthermore, the data path in the converter may be reset under the control of the MCU.

[0055] The first section 300 may further include a multiplexer 316. The inputs of the multiplexer 316 may be coupled to the output of the multiplexer 310 and to the output of the converter components 314. The multiplexer 316 may receive a control signal from the MCU indicating which of the data received by the multiplexer 310 or the data received by the converter components 314 should be propagated to an output of the multiplexer 316. Accordingly, the data output by the multiplexer 310 may bypass the converter components 314 if the control signal from the MCU indicates that the data received by the multiplexer 310 should be propagated by the multiplexer 316. However, the MCU may avoid bypassing the converter components 314 if a propagation delay of the transceiver has been determined to avoid changes in the propagation delay.

[0056] The first section 300 may further include an Rx-programmable finite impulse response filter (RPFIR) component 324. An input of the RPFIR component 324 may be coupled to the output of the multiplexer 316. The RPFIR component 324 may stop adjacent-channel interference for data received from the multiplexer 316, may select a desired channel bandwidth for RSSI measurement, or some combination thereof.

[0057] The RPFIR component 324 can support at least two filter profiles that can be applied to data received by the RPFIR component 324. In some embodiments, the RPFIR component 324 can store four filter profiles. The RPFIR component 324 can receive a control signal from the MCU indicating which profile should be applied by the RPFIR component 324. The RPFIR component 324 can perform passband compensation, operate as a channel selection filter, or some combination thereof. The data path of the RPFIR component 324 can be reset under the control of the MCU.

[0058] The first section 300 may further include a multiplexer 326. The inputs of the multiplexer 326 may be coupled to the output of the multiplexer 316 and to an output of the RPFIR component 324. The multiplexer 326 may receive a control signal from the MCU indicating which of the data received from the multiplexer 316 or the data received from the RPFIR component 324 should be propagated to an output of the multiplexer 326. Accordingly, data from the multiplexer 316 may bypass the RPFIR component 324 if the control signal from the MCU indicates that the data received from the multiplexer 316 should be propagated.

[0059] The first section 300 may further include RSSI components 328. The RSSI components 328 may be coupled to an output of the multiplexer 326. The RSSI components 328 may accumulate filtered channel power from data received from the multiplexer 326 on a sample-by-sample basis. The duration of the accumulated samples may be programmed by the MCU. In particular, the duration may range from 100 microseconds to 10 milliseconds. The number of accumulated samples used may be based on an input sampling frequency, an RF bandwidth of the passband of the RPFIR component 324, a number of samples within a certain time period (such as 1.5 milliseconds), or some combination thereof.

[0060] The RSSI components 328 can provide an output in units of dBFS (Decibels Relative to Full Scale), which output indicates the received signal power within the assigned channel at the antenna coupled to the transceiver. The accumulated power level can be subtracted by the gain in units of decibels (dB) from an automatic gain control block to obtain the RSSI component output. The output of the RSSI components 328 can be accessed by the MCU when the accumulation is manually reset and / or restarted by the MCU. The RSSI output can be used to measure the noise floor at the antenna port during the initialization phase. In power detection mode, RSSI accumulation operations can be automatically restarted if the output of the RSSI components 328 does not reach a detection threshold stored by the MCU.The RSSI component 328 may be implemented in a communication detection module (such as the communication detection module 208). Fig. 2)) of the communication processing module. The counter 312, the converter components 314, the RPFIR component 324, and the RSSI components 328 may be included in the communication detection module 208 ( Fig. 2). An output 332 of the multiplexer 326 may be connected to a second section 400 (see Fig. 4) of the transceiver.

[0061] Fig. 4 illustrates a diagram of a second portion 400 of the exemplary communication processing module of Fig. 3 according to some embodiments. In particular, the second section 400 may be connected to the output 332 of the first section 300 ( Fig. 3) be coupled as an input to the second section 400.

[0062] The second section 400 may include a frequency discriminator component 402. The frequency discriminator component 402 may be coupled to the output 332. The frequency discriminator component 402 may perform operations that facilitate FM demodulation of data received via the output 332.

[0063] In the illustrated embodiment, the frequency discriminator component 402 may support two types of FM demodulators. For example, the two types of FM demodulators may comprise a differentiator-first methodology of FM demodulation, a normalizer-first methodology of FM demodulation, or some combination thereof. The frequency discriminator component 402 may receive an indication of which of the FM demodulators should be employed from the MCU. A data path of the frequency discriminator component 402 may be reset by the MCU. Furthermore, the frequency discriminator component 402 may output a sample power of the data received by the frequency discriminator component 402 in addition to the result of the FM demodulation applied to the data.

[0064] The second section 400 may further include a pulse RPFIR component 404. The pulse RPFIR component 404 may be coupled to the output of the frequency discriminator component 402. The pulse RPFIR component 404 may include a narrowband filter. The pulse RPFIR component 404 may be programmed by the MCU with several different filters to apply to data received from the frequency discriminator component 402. In particular, the pulse RPFIR component 404 may receive an indication from the MCU as to which filter should be applied. In cases where a DMR signal is detected, the pulse RPFIR component 404 may apply a pulse-shaping filter. In cases where an FM signal is detected, a low-power filter for FM demodulation to reject noise at higher bands may be applied by the pulse RPFIR component 404. A data path in the pulse RPFIR component 404 can be reset by the MCU.

[0065] The second section 400 may further include a multiplexer 406. The inputs of the multiplexer 406 may be coupled to the output 332, an output of the frequency discriminator component 402, and an output of the pulse RPFIR component 404. The multiplexer 406 may receive a control signal from the MCU indicating which of the data received from the output 332, the data received from the frequency discriminator component 402, or the data received from the pulse RPFIR component 404 should be propagated to an output of the multiplexer 406. Accordingly, data from the frequency discriminator component 402 may bypass the pulse RPFIR component 404 if the control signal from the MCU indicates that data received from the frequency discriminator component 402 should be propagated.Furthermore, data from output 332 may bypass both frequency discriminator component 402 and pulse RPFIR component 404 if the control signal from the MCU indicates that the data received from output 332 should be propagated.

[0066] The second section 400 may further include a resampler component 408. An input of the resampler component 408 may be coupled to the output of the multiplexer 406. The resampler component 408 may adjust the sampling phase of data received by the multiplexer 406. A resampling phase of the resampler component 408 may be programmable by the MCU.

[0067] The second section 400 may further include a multiplexer 410. The inputs of the multiplexer 410 may be coupled to an output of the resampler component 408 and an output of the multiplexer 406. The multiplexer 410 may receive a control signal from the MCU indicating which of the data received from the multiplexer 406 or the data received from the resampler component 408 should be propagated to an output of the multiplexer 410. Accordingly, data from the multiplexer 406 may bypass the resampler component 408 if the control signal from the MCU indicates that the data received from the multiplexer 406 should be propagated. In cases where an FM signal is detected, the resampler component 408 may be bypassed. In cases where a DMR signal or a P25 signal is detected, the data from the multiplexer 406 can be sent directly through the resampler component 408.The frequency discriminator component 402, the pulse RPFIR component 404, and the resampler component 408 may be incorporated in the demodulation module 210 (. Fig. 2). An output 414 of the multiplexer 410 may be connected to a third section 500 ( Fig. 5) of the transceiver.

[0068] Fig. 5 illustrates a diagram of a third portion 500 of the exemplary communication processing module of Fig. 3 according to some embodiments. In particular, the third section 500 may be connected to the output 414 of the second section 400 ( Fig. 4) be coupled as an input to the third section 500.

[0069] The third section 500 may include a correlator component 502. An input of the correlator component 502 may be connected to an output 414 of the multiplexer 410 ( Fig. 4). The correlator component 502 can perform cross-correlation operations on data received via output 414.

[0070] In particular, the correlator component 502 may have two different inputs flowing from the output 414. For example, the correlator component 502 may receive the data and the sample power of the data. The correlator component 502 may perform cross-correlation operations between the data and local sync codes. In some embodiments, the correlator component 502 may include 14 independent correlation processors operating in parallel. For each input sample of the data, 14 cross-correlation output samples may be generated by the 14 correlation processors. Each of the correlation processors may be enabled or disabled by the MCU. Each of the correlation processors may be independently loaded with a corresponding sync code by the MCU, where each sync code may have a length of 24 2-state {-1, +1} symbols.

[0071] The correlator component 502 may further include a moving average frequency deviation. The moving average may further sum the continuous 5x24 input samples (frequency deviation). In parallel, 24 samples of the power input may be summed with the sample size (I2+Q2) to generate a power sum, which may be the corresponding confidence factor for an output of the correlator component 502. The correlator component 502 may provide 16 outputs in parallel (or substantially parallel) at a sampling rate of 24 kHz. The 16 outputs may be 24-bit fixed-point symbols. The correlator component 502 may further receive a control, which is a self-clearing bit, to enable an entire correlator engine of the correlator component 502 based on an individual correlator enable bit pattern. The output of the correlator component 502 may not be applicable to FM signals.In some embodiments, the correlator component 502 may support some short SYNC code detection.

[0072] The third section 500 may further include a timing error detector (TED) component 504. An input of the TED component 504 may be coupled to the output 414. The TED component 504 may be enabled when a DMR signal is detected. The TED component 504 may track a sample timing error for data received via the output 414 based on Gardner algorithms. The TED component 504 may have an upsampling rate of five. In other embodiments, the TED component 504 may have an upsampling rate of four. Outputs of the TED component may be divided into five phases and may be provided with three bits of phase information. The TED component 504 may further receive a self-clearing control bit from the MCU that causes the TED component 504 to be cleared.

[0073] The third section 500 may further include a storage device 506. The storage device 506 may be partitioned into multiple areas (which may be referred to as "partitions"), where each of the areas may store data received from different components. The inputs of the storage device may be coupled to the output 414, outputs of the correlator component 502, and the output of the TED component 504. In other embodiments, the third section 500 may include multiple storage devices, where each of the storage devices may store data received from different components. If the third section 500 includes multiple storage devices, each of the storage devices may be coupled to the component that provides the data that the storage device is configured to store.

[0074] The storage device 506 may include a correlator partition 508. The correlator partition 508 may store data received from the correlator component 502. In particular, the correlation processor 508 may buffer the outputs of the correlator component 502. The correlation processor 508 may be arranged in a FIFO (First-In-First-Out) arrangement. The correlator partition 508 may support a maximum depth of 32.

[0075] A current buffered data count in the correlator partition 508 may be stored in an AHB (Advanced High-Performance Bus) status register. In some embodiments, the current buffered data count in the correlator partition 508 may be stored in an AXI (Advanced Extensible Interface) bus, another bus status register. If the buffered data count equals a configured threshold, an interrupt may be triggered. The value of the configured threshold may be programmed by the MCU.

[0076] An output port of the correlator partition 508 can occupy 16 32-bit AHB addresses. The MCU can read the oldest 24x16 data from the correlator partition 508 during the main routine or during the interrupt service routine (ISR) for the interrupt triggered by the buffered data count equal to the configured threshold. Reading all 16 24-bit data from the correlator partition 508 in one clock cycle can be an automatic transaction. When the MCU finishes reading the 16 24-bit data, a status of the correlator partition 508 can be updated with the current value minus 1. Furthermore, the correlator partition 508 can convert the 24-bit data to 32-bit data with an extended sign bit to correspond to the 32-bit AHB.

[0077] If writing to the correlator partition 508 fills the size of the correlator partition 508 before the MCU reads the data, writing to the correlator partition 508 may cause an overflow. If the correlator partition 508 is enabled, a data discard event may occur. A data discard indicator bit may be set in response to the data discard. The data discard indicator bit may be read and cleared by the MCU.

[0078] The memory device 506 may further include a TED partition 510. The TED partition 510 may store data received from the TED component 504. In particular, the TED partition 510 may buffer the outputs of the TED component 504. The TED partition 510 may be arranged in a FIFO arrangement. The TED partition 510 may support a maximum depth of 32.

[0079] A buffered data count in the TED partition 510 can be stored in an AHB status register. If the buffered data count equals a configured threshold, an interrupt can be triggered. The value of the configured threshold can be programmed by the MCU.

[0080] An output port of the TED partition 510 can occupy a 32-bit AHB address. The MCU can read the oldest 16-bit data from the TED partition 510 during the main routine or during the ISR for the interrupt triggered by the buffered data count equal to the configured threshold. When the MCU finishes reading the 16-bit data, a status of the TED partition 510 can be updated with the current value minus 1. Furthermore, the TED partition 510 can convert the 16-bit data to 32-bit data with an extended sign bit to conform to the 32-bit AHB.

[0081] If writing to the TED partition 510 fills the size of the TED partition 510 before the MCU reads the data, writing to the TED partition 510 may cause an overflow. If the TED partition 510 is released, a data discard event may occur. A data discard indicator bit may be set in response to the data discard. The data discard indicator bit may be read and cleared by the MCU.

[0082] The memory device 506 may further include a DP partition 512. The DP partition 512 may store data received from the output 414. The DP partition 512 may be arranged in a FIFO array. The DP partition 512 may support a maximum depth of 32.

[0083] The current buffered data count in DP partition 512 can be stored in an AHB status register. If the buffered data count equals a configured threshold, an interrupt can be triggered. The value of the configured threshold can be programmed by the MCU.

[0084] An output port of the DP partition 512 can occupy two 32-bit AHB addresses. The MCU can read the oldest two 22-bit data pieces from the DP partition 512 during the main routine or during the ISR for the interrupt triggered when the buffered data count equals the configured threshold. When the MCU finishes reading the two 22-bit data pieces, a status of the DP partition 512 can be updated with the current value minus 1. Furthermore, the DP partition 512 can convert the 22-bit data to 32-bit data with an extended sign bit to conform to the 32-bit AHB.

[0085] If writing to the DP partition 512 fills the size of the DP partition 512 before the MCU reads the data, writing to the DP partition 512 may cause an overflow. If the DP partition 512 is enabled, a data discard event may occur. A data discard indicator bit may be set in response to the data discard. The data discard indicator bit may be read and cleared by the MCU.

[0086] The memory device 506 may include an ARM (Advanced Reduced Instruction Set Computer Machine) partition 514. The ARM partition 514 may store data received from the MCU. In particular, the ARM partition 514 may buffer the outputs of the MCU. The ARM partition 514 may receive the data from the MCU via an ARM data master port 526 and an AHB slave port 528. The ARM partition 514 may be arranged in a FIFO arrangement. The ARM partition 514 may support a maximum depth of 32.

[0087] The MCU can write a 32-bit data value to ARM partition 514 during the main routine or in response to an ISR. A status of ARM partition 514 can be updated with the current value plus 1 when the MCU finishes writing the 32-bit data. The current buffered data count in ARM partition 514 is stored in an AHB status register.

[0088] The ARM partition 514 may feed the oldest 16x2 data into a data path of the transceiver via a multiplexer 516 if there is any valid data in the ARM partition 514. For all data output on the data path by the ARM partition 514, a status of the ARM partition is updated with the current value minus 1. A read clock for the ARM partition 514 may be the same as that provided by the memory device 308 ( Fig. 3) and the counter 312 ( Fig. 3) used read clock. If the status of the ARM partition drops to 0, an interrupt can be generated.

[0089] The third section 500 may further include a rounding component 520. The rounding component may support two rounding modes, which may be specified by a control bit of the MCU. A first mode may be an FSK demodulation mode, where each symbol is mapped to two bits for demodulation. In the first mode, the rounding component 520 may round the input 22-bit IQ data to 16-bit data, with the 16-bit output Q data set to zero. The second mode is the normal mode. In the second mode, the rounding component 520 rounds the input 22-bit IQ data to 16-bit IQ data. The correlator component 502, the TED component 504, the storage device 506, and the rounding component 520 may be located in the information module 212 ( Fig. 2) must be included.

[0090] The third section 500 may further include the multiplexer 516. The inputs of the multiplexer 516 may be coupled to the rounding component 520 and the ARM partition 514. The multiplexer 516 may receive a control signal from the MCU indicating which of the data received by the rounding component 520 or the data received from the ARM partition 514 should be propagated to an output of the multiplexer 516. An output of the multiplexer 516 may be coupled to a BBIC (such as the BBIC 216 ( Fig. 2)). In particular, the output of multiplexer 516 may be coupled to the BBIC via an SSI (Synchronous Serial Line Interface) port 524.

[0091] Fig. 6 illustrates an exemplary state diagram 600 that may be used by an MS, according to some embodiments. In particular, the state diagram 600 includes states that may be used by the MS 200 ( Fig. 2) which may comprise the sections of the communication processing module as shown in Fig. 3-5 shown.

[0092] The state diagram 600 may include an output stage mode 602. In the output stage mode 602, the rounding component 520 ( Fig. 5) are in normal mode and can be enabled to operate independently. The converter components 314 ( Fig. 3), the RPFIR component 324 ( Fig. 3) and the resampler component 408 ( Fig. 4) may be enabled as configured when the output stage mode 602 has been entered. The output stage mode 602 may be selected for both wideband cases (such as LTE (Long Term Evolution)) and narrowband cases (such as land mobile radio (LMR) with demodulation disabled).

[0093] While the communications processing module is in output stage mode 602, it can provide fine digital adjustment of the receiver channel center frequency, performed by the converter components 314. Furthermore, the communications processing module can provide adjacent channel rejection and roll-off compensation at the corner frequency, performed by the RPFIR component 324. The communications processing module can also provide fine digital adjustment of the receive channel sampling phase, performed by the resampler component 408. These three functions can be optional and can be manually controlled via SPI (Serial Peripheral Interface) registers. The other functional blocks of the communications processing module can be enabled independently of the SPI and can be independently configured by the SPI. Therefore, the output stage mode 602 can be fully subordinated to the BBIC via the SPI.

[0094] The states may further include a power detection mode 604. The power detection mode 604 may be enabled at the beginning of a detection cycle time of a wake period in the idle state of the MS. In the power detection mode 604, some of the components of the communication processing module are in a sleep mode or are turned off. For example, the demodulation module 210 ( Fig. 2) and the information module 212 ( Fig. 2) be in a sleep state or turned off in the power detection mode 604.

[0095] The storage device 308 ( Fig. 3) and the counter 312 ( Fig. 3) may be initially cleared during power detection mode 604. After memory device 308 and counter 312 have been cleared, write control of memory device 308 may be enabled. In particular, the write enable trigger of memory device 308 may be set.

[0096] The RPFIR component 324 ( Fig. 3) can be enabled in power detection mode 604. The RPFIR component 324 can be used to select the desired channel bandwidth in the frequency domain for RSSI. A filter profile loaded into the RPFIR component 324 can determine the bandwidth providing the sampling frequency. Accordingly, the input data stream can be input through the external input 322, filtered by the RPFIR component 324, and delivered to the RSSI components 328.

[0097] If the RSSI components 328 indicate that the received signal level is above the detection threshold, an interrupt is generated by the RSSI component 328 and transmitted to the MCU. In response to receiving the interrupt, the MCU can cause an ISR to be performed. Specifically, two optional operations can be applied in the ISR.

[0098] If the wake period for the first operation is configured to depend only on power detection, the MCU can wake up the BBIC if the measured channel power level is above the configured threshold. This operation can be applied to the FM, DMR, TETRA (Trans European Trunked Radio Access), and Broadband (LTE) cases. In other embodiments, this operation may not be applicable to the Broadband (LTE) cases.

[0099] If, for the second operation, the wake period is configured to depend on SYNC detection for DMR, the communication processing module may transition to DMR detection mode 606 if it has not already entered it. The data path of RPFIR component 324 may be reset.

[0100] The states may further include DMR detection mode 606. In DMR detection mode 606, the write control of the memory device 308 may be enabled. In particular, the write enable trigger of the memory device 308 may be set. Each input sample received by the communication processing module may be buffered by the memory device 308. The read control of the memory device 308 may be disabled in DMR detection mode 606.

[0101] The multiplexer 310 may select the data from the decimation filters 342 to be propagated to the output of the multiplexer 310. Accordingly, an input of the communication processing module may feed directly into the converter components 314 while setting the value of the FTW to zero. The output of the converter components 314 may be fed into the RPFIR component 324 to stop adjacent-channel interference. The output of the RPFIR component 324 may be fed into a component external to the communication processing module (such as a game slicer) that drives the frequency discriminator component 402. The frequency discriminator component 402 may output the FM demodulator output and the sample power of the data input to the frequency discriminator component 402.

[0102] The FM demodulator output and the sampling power are fed into the two paths of pulse RPFIR component 404. Pulse RPFIR component 404 may apply a single filter profile when a DMR signal has been detected and the input sampling rate is 24 ksps. The outputs of pulse RPFIR component 404 may be fed into resampler component 408, which may have a resampler timing phase set to zero.

[0103] The outputs of the resampler component 408 can be fed into the correlator component 502. The outputs of the correlator component 502 can be fed into the correlator partition 508 ( Fig. 5) to the memory device 506, which buffers the outputs. The output of the correlator partition 508 may not be fed to the SSI port 524 ( Fig. 5) in the DMR detection mode 606. However, the output of the correlator partition 508 can be formed through the SPI for debugging purposes.

[0104] During the DMR detection mode 606, operations are associated with the ISR that are triggered in the power detection mode 604. In the ISR, the MCU reads both the correlator partition 508 and the DP partition 512 ( Fig. 5). The MCU may compare the output to a configured threshold. The MCU will attempt to determine a correct sync and peak position for the output. If a correct sync and peak position are determined, the MCU may determine a carrier frequency offset (CFO) estimate, a sample timing error estimate, and a DMR burst head index estimate for the output. In some embodiments, the DMR burst head index may be determined indirectly based on a propagation delay between the memory device 308 and the correlator component 502. The propagation delay may be determined via a DMR propagation delay test mode of the communication processing module.

[0105] With the exception of the features described with respect to the DMR propagation delay test mode, the configuration of the components in the DMR propagation delay test mode may be the same as in the DMR detect mode 606. In the DMR propagation delay test mode, the MCU may assume control of the communication processing module and bypass the MS components 334 by causing the multiplexer 302 to propagate data received on the input 306 to an output of the multiplexer 302. Furthermore, the MCU may clear the read pointers of the memory device 308 and then load a test pattern into the memory device via the input 306 and the multiplexer 302. When the DMR propagation delay test mode is exited, the MCU may reset the counter 312 and the read pointer of the memory device 308 to the values ​​when the DMR propagation delay test mode 608 was entered.

[0106] After the initial configuration of the DMR propagation delay test mode has been completed, the MCU may release read control of the memory device 308. The correlator component 502 may perform the same operations on the data read from the memory device 308 that it performs during the DMR detection mode 606. The correlator component 502 feeds one sample at a time into the correlator partition 508, and the MCU searches for correlation peaks in the samples until an expected peak is located. After the MCU identifies the peak, the MCU may read the value of counter 312, which may be referred to as the SYNC index plus the propagation and detection delays. The SYNC index may implement subsequent configuration changes in the data path from the memory device 308 to the correlator component 502, such as changes to the interrupt threshold of the correlator partition.

[0107] The SYNC index plus the propagation and detection delays can be used to determine a location of the read pointer of the memory device 308. For example, the DMR burst head index estimate obtained in the DMR detection mode 606 can be equal to the SYNC index plus the propagation and detection delays, which can be applied to the memory device 308 as the buffer depth for positioning the read pointer relative to the write pointer.

[0108] After DMR SYNC is detected, the MCU may trigger a wake-up of the BBIC and prepare for transition to DMR Detected Mode 610. Before transitioning to DMR Detected Mode 610, the MCU may perform one or more operations. For example, the MCU may disable and / or mask a monitor detection timer timeout interrupt. Furthermore, the MCU may disable other SYNC code correlation engines in the correlator component 502, leaving the detected SYNC code enabled.

[0109] The MCU may further load the DMR burst head index estimate into the memory device 308 if the propagation delay from the multiplexer to the correlator partition 508 is known, where the DMR burst head index indicates a position at which the read pointer of the memory device 308 is to be located relative to the write pointer of the memory device 308. The read pointer may be moved to the indicated position on the next positive edge of the write clock of the memory device 308. The MCU may further load the CFO estimate as the FTW into the converter components 314 to remove the CFO from the data received by the converter components 314. Furthermore, the MCU may load the sample timing error estimate into the resampler component 408 to remove the timing error.

[0110] The MCU may further cause the multiplexer 310 to propagate the output of the memory device 308 to the output of the multiplexer 310. Furthermore, the MCU may reset the data path of the communication processing module, except for the memory device 308. The MCU may clear the value of the counter 312. Furthermore, the MCU may initiate a wake-up procedure of the BBIC by toggling a wake-up trigger of the BBIC. The MCU may monitor the BBIC to determine whether the communication processing module can switch to the DMR detected mode after the BBIC wake-up procedure has been completed.

[0111] If no DMR SYNC is detected when a monitor-detecting timeout interrupt is received, the MCU may transition the transceiver to sleep mode, which may indicate the idle state of the MS outside of the wake periods.

[0112] The states may further include DMR Detected Mode 610. DMR Detected Mode 610 may be entered after a DMR Detect Mode 606 cycle where a DMR SYNC was identified. The MCU may cause the reading of memory device 308 to begin at the beginning of DMR Detected Mode 610.

[0113] The data read from the storage device 308 may pass through components of the communications processing module, which may perform operations on the data. In particular, the converter components 314 may remove the CFO estimate from the data. Furthermore, the RPFIR component 324 may reject adjacent-channel interference from the data. The frequency discriminator component 402 may output the result of demodulating the data. The pulse RPFIR component 404 may filter the data received by the pulse RPFIR component 404. The resampler component 408 may resample the filtered data received by the pulse RPFIR component 404 with the resampling phase of the sample timing error estimate. The correlator component 502 may perform operations on the detected SYNC code and may generate an output sample for each corresponding input sample, with the outputs provided to the correlator partition 508.

[0114] The TED component 504 may be enabled in the DMR detected mode 610. The TED component 504 may detect a residual sampling timing error for the data. Furthermore, the TED component 504 generates an output sample for each corresponding input sample, which output samples are to be provided to the TED partition 510. The TED component 504 may further output five phase outputs for the 24 kilohertz sampling rate.

[0115] The DP partition 512 can buffer data received from the rounding component 520. Furthermore, the correlator partition 508 can buffer data received from the correlator component 502. The TED partition 510 can buffer data received from the TED component 504. The multiplexer 516 can propagate either the output of the ARM partition 514 or the output of the rounding component 520 to the output of the multiplexer 516 based on an indication received from the MCU, with the output of the multiplexer 516 being provided to the SSI port 524. The rounding component 520 can round inputs to 16 bits as signed data.

[0116] The MCU can read data from the DP partition 512, the correlator partition 508, and the TED partition 510 via the AHB. Based on the read data, the MCU can obtain a more accurate SYNC correlation peak, a more accurate residual CFO estimate, and a residual sample timing error. In some embodiments, the MCU can demodulate the current burst and generate demodulated bits via the ARM partition 514 to the SSI port 524.

[0117] The DMR detected mode 610 may be terminated while the BBIC's receive enable signal is cleared. Specifically, the transceiver exits the idle state with the DMR signal detected. When the receive enable signal is cleared again, the communication processing module may transition to the output stage mode 602 with the memory device 308 deactivated.

[0118] The stages may further include an FM detection mode 612. The FM detection mode may follow the power detection mode 604. The FM detection mode 612 may detect analog FM signals. Certain components of the communication processing module may be disabled in the FM detection mode. For example, the pulse RPFIR component 404 and the resampler component 408 may be disabled and bypassed in the FM detection mode. Furthermore, the correlator component 502, the correlator partition 508, the TED component 504, the TED partition 510, and the ARM partition 514 may be disabled.

[0119] In FM detection mode 612, multiplexer 302 may propagate data from decimation filters 342 to the output of multiplexer 302, where the data from decimation filters 342 is fed to memory device 308. Memory device 308 may buffer the data received from decimation filters 342. Multiplexer 310 may also propagate the data from decimation filters 342 to an output of the multiplexer, where the data is fed to converter components 314 set to an FTW value of zero. The output of converter components 314 may be provided to RPFIR component 324, which rejects adjacent-channel interference. The output of RPFIR component 324 can be provided to an external component (such as the gain slicer) that drives frequency discriminator component 402. Frequency discriminator component 402 outputs the result of demodulation of the data.The pulse RPFIR component 404 and the resampler component 408 may be bypassed, and the output of the frequency discriminator component 402 is fed into the DP partition 512. In some embodiments, only the DP partition 512 may be enabled in the FM detection mode 612. The DP partition 512 and the DP partition 512 interrupt may operate similarly to the DP partition 512 and the DP partition 512 interrupt from the DMR detection mode 606.

[0120] In FM detection mode 612, the MCU can read the data from the DP partition 512 after a frame of data is ready to be read. The MCU can perform a real FFT operation for every 16 data inputs received. The 16 data inputs can be conjugated with the previous 48 buffered data inputs to compile 64 FFT inputs. The MCU can determine the power of each FFT bin generated by the MCU FFT routine and process them as FM detection algorithm inputs.

[0121] After the MCU detects an FM signal received by the transceiver, the MCU may obtain the FM CFO estimate based on the averaging of 64x8 data inputs. Furthermore, the MCU may obtain a buffered data length from the memory device 308. In response to the MCU detecting an FM signal, the MCU may initiate a wake-up procedure of the BBIC and prepare to transition the communication processing module to an FM detected mode 614.

[0122] Before entering FM Detected Mode 614, the MCU may perform certain operations. For example, the MCU may load the CFO estimate into the converter components 314 as the FTW to remove the CFO. Furthermore, the MCU may load the buffered data length into the memory device 308 as the set of memory positions by which a read pointer of the memory device 308 should be moved from a current read pointer position. The read pointer position may be updated on the next positive edge of the data valid, as received by the counter 312.

[0123] The MCU may further switch the multiplexer 310 to propagate the output of the memory device 308 to the output of the multiplexer 310. The MCU may reset the data path of the communication processing module, except for the memory device 308, and clear the counter 312. Furthermore, the MCU may initiate a wake-up procedure of the BBIC by switching a wake-up procedure of the BBIC. The MCU may monitor the BBIC to determine whether the communication processing module can switch to the FM-detected mode after the BBIC wake-up procedure has been completed.

[0124] If no FM signal is detected when a monitor detection timeout interrupt is received, the MCU may transition the transceiver to sleep mode, which may indicate the idle state of the MS outside of wake periods.

[0125] The states may further include FM detected mode 614. Upon switching to FM detected mode 614, the MCU may initiate reading of the memory device 308. The read clock of the memory device 308 may be twice, four times, or eight times the frequency of the write clock of the memory device 308, where the write clock of the memory device may be 24 kilohertz, 48 kilohertz, or 96 kilohertz.

[0126] The data read from the memory device 308 may be passed through components of the communications processing module, which may perform operations on the data. For example, the converter components 314 may remove the CFO estimate from the data. Furthermore, the RPFIR component 324 may reject adjacent-channel interference. The frequency discriminator component 402 may output the result of the demodulation applied to the data. The pulse RPFIR component 404 may filter the data received from the frequency discriminator component 402 with a loaded low-pass filter profile. The rounding component 520 may round the data to 16 bits as signed data. The multiplexer 516 may propagate the data received from the output of the rounding component 520 to the output of the multiplexer 516, thereby delivering the data to the SSI port 524.

[0127] The FM detected mode 614 may be terminated while the BBIC's receive enable signal is cleared. Specifically, the transceiver exits the idle state with the FM signal detected. When the receive enable signal is cleared again, the communication processing module may transition to the output stage mode 602 with the memory device 308 deactivated.

[0128] If TRx is in the idle state with Rx and Tx enable low, the BBIC can warn of a monitor enable. Before this, the BBIC can provide all the configuration inputs required by TRx. Fig. 7 and Fig. 8 illustrate portions of an exemplary flowchart 700 for an MS according to some embodiments. In particular, the flowchart 700 indicates a flow of operations performed by the MS 200 ( Fig. 2) can be used, which includes the sections of the communication processing module, as in Fig. 3-5, for DMR signal detection.

[0129] The flow of operation may begin at stage 702, where an idle state of the TRx MCU (such as the MCU 214 ( Fig. 2)) is initiated. The idle state can be exited at any time by the BBIC clearing the monitor enable, which can occur in response to a change in an internal state of the MCU in step 726. For example, the BBIC can clear the monitor enable when a push-to-talk button of the MS is pressed and can proceed to step 724, where the idle state is exited.

[0130] Upon initiation of the idle state, operation flow may proceed to stage 728. In stage 728, according to the configuration provided by the BBIC, the TRx MCU may determine whether the communication processing module should initially enter a sleep state or initially enter a wake period of the idle state. Whether the communication processing module should initially enter the sleep state or the wake period may be preconfigured or programmed. In response to the TRx MCU determining that the communication processing module should enter the sleep state, flow may proceed to stage 706, where the communication processing module is placed into a sleep state. In response to the TRx MCU determining that the communication processing module should enter the wake period, flow may proceed to stage 730.

[0131] In stage 730, according to the configuration provided by the BBIC, the TRx MCU may determine whether RSSI power detection is enabled. If the TRx MCU determines that RSSI power detection is enabled, the flow may proceed to stage 704. If the TRx MCU determines that RSSI power detection is disabled, the flow may proceed to stage 736 (in Fig. 8 shown).

[0132] In response to determining that RSSI power detection is enabled, the MS may enter power detection mode 604 ( Fig. 6). In particular, the operation flow may proceed to stage 704, where the TRx may perform the RSSI power detection operation on data received from the TRx. The BBIC may be in sleep mode upon initiation of the idle state. Upon completion of the RSSI power detection, the flow may proceed to stage 708.

[0133] At stage 708, according to the configuration provided by the BBIC, the TRx can determine whether the field strength, as indicated by the RSSI generated by the RSSI power detection operation, of the data exceeds a threshold. If the field strength exceeds the threshold, flow proceeds to stage 732. If the field strength is below the threshold, flow returns to stage 704.

[0134] If the TRx does not detect a field strength that exceeds the threshold (as indicated by the flow continuously alternating between steps 704 and 708) during a detection time, the flow may proceed to step 706. In particular, if a detection time elapses before the detection of a field strength that exceeds the threshold, the flow proceeds to step 706.

[0135] In stage 706, the TRx (including the communications processing module) places itself into a sleep mode. The TRx may remain in the sleep mode until a sleep timer expires. In response to the expiration of the sleep timer while the flow is in stage 706, the flow may return to stage 704.

[0136] In stage 732, the TRx may determine whether a detected RSSI count is above a threshold. For example, the TRx may determine whether a frequency with which the RSSI exceeds a threshold is greater than a threshold frequency with which the field strength exceeds the threshold. If the detected RSSI count is below the threshold, flow may return to stage 704. If the detected RSSI count exceeds the threshold, flow may continue to stage 736.

[0137] If the TRx determines that the detected threshold does not exceed the threshold (as indicated by flow continuously alternating among steps 704, 708, and 732) for a detection time, flow may proceed to step 706. Specifically, if a detection time expires before detecting a field strength that exceeds the threshold, flow proceeds to step 706.

[0138] At stage 736, the TRx MCU may determine, based on the configuration provided by the BBIC, whether fine detection of the signal should be performed. For example, the TRx MCU may determine whether the signal's waveform (such as DMR or FM) should be processed by the communication processing module. If fine detection of the signal should be performed, flow may proceed to stage 710. If fine detection of the signal should not be performed, flow may proceed to stage 714.

[0139] The TRx MCU can access the DMR detection mode 606 ( Fig. 6) and / or the FM detection mode 612 ( Fig. 6) when flow proceeds to stage 710. For example, the TRx MCU may switch between DMR detect mode 606 and FM detect mode 612, or operate in DMR detect mode 606 and FM detect mode 612 simultaneously, depending on the configuration provided by the BBIC.

[0140] In DMR detection mode 606, at stage 710, the TRx MCU may perform a DMR SYNC detection operation. Flow may proceed to stage 712, where the TRx MCU determines whether a DMR SYNC has been detected by the DMR SYNC detection operation. If the TRx MCU determines that a DMR SYNC has been detected, flow proceeds to stage 714. If the TRx MCU determines that no DMR SYNC has been detected, flow returns to stage 710.

[0141] In FM detection mode 612 at stage 710, the TRx MCU may perform an FM detection operation. Flow may proceed to stage 712 if the TRx MCU determines whether an FM signal has been detected by the FM detection operation. If the TRx MCU determines that an FM signal has been detected, flow proceeds to stage 714. If the TRx MCU determines that no FM signal has been detected, flow returns to stage 710.

[0142] If the TRx MCU has not detected a DMR SYNC or FM signal (as indicated by the flow continuously alternating between step 710 and 712) for a detection time, the flow may proceed to step 706 (where step 706 refers to the same step in both Fig. 7 as well as Fig. 8). In particular, if a detection time expires before the DMR SYNC or FM signal is detected, flow proceeds to stage 706, where the TRx (including the communications processing module) is placed in a sleep mode.

[0143] The TRx can be switched to the DMR Detected Mode 610 ( Fig. 6) and / or FM Detected mode when the flow proceeds to step 714. In step 714, the MS's BBIC wake-up procedure may be initiated. The flow may proceed to step 716.

[0144] At stage 716, the TRx may wait for the BBIC to complete the wake-up procedure. Flow may proceed to stage 718, where the TRx determines whether the BBIC has completed the wake-up procedure based on whether the BBIC's receive enable has been alerted. If the receive enable has not been alerted, flow returns to stage 716. If the receive enable has been alerted, flow proceeds to stage 720.

[0145] If the TRx determines that the BBIC has not completed the wake-up procedure (as indicated by flow continuously alternating between steps 716 and 718) within a wake-up time period, flow may proceed to step 738. At step 738, the TRx may exit monitor mode and provide an indication that the BBIC has not completed the wake-up procedure within the wake-up time period. For example, the TRx may provide an indication that a digital baseband processor (DBB) of the BBIC is not operational.

[0146] In stage 720, the TRx may flush the data stored by the memory device 308 and the data received by the communication processing module to the BBIC. When the TRx completes flushing the data, flow may proceed to stage 722, where the DMR detected mode 610 is exited and the BBIC's receive enable is cleared. Furthermore, in stage 722, the idle state is exited with the detected DMR signal.

[0147] Therefore, the present invention should not be considered limited to the specific embodiments described above. Various modifications, equivalent processes, and numerous structures to which the present invention may be applied will be readily apparent to those skilled in the art to which the present invention pertains upon consideration of the present disclosure.

[0148] According to one aspect of the invention, digital mobile radio (DMR) devices and methods with an improved transceiver are provided. The transceiver detects waveforms of signals received by a digital mobile radio (MS). By detecting the waveforms of the signals, the transceiver allows a digital baseband processor of the MS to remain in a sleep state while the signals are being detected by the DMR, thereby reducing the amount of power consumed while the signals are being detected.

Claims

[1] Apparatus for performing signal detection, the apparatus being intended to be coupled to a baseband integrated circuit (BBIC) (216) of a mobile station radio (MS) (200), and comprising: a memory module (206) for storing data associated with a signal received by an antenna (202) of the MS; and a communication detection module (208) for: Generating a field strength indicator (RSSI - Received Signal Strength Indicator) for the signal while the BBIC (216) is in a sleep mode; and Providing the RSSI to a microcontroller unit (MCU) (214) of the MS (200), wherein the memory module (206) is to provide the data to the BBIC (216) based on the RSSI indicating that a field strength of the signal exceeds a threshold. [2] The apparatus of claim 1, further comprising an information module (212) for storing processed data, wherein the processed data is generated by processing the data associated with the signal, wherein the processed data is accessed by the MCU (214) to determine a waveform of the signal. [3] The apparatus of claim 2, wherein the memory module (206) comprises a memory device (308) configured as a FIFO (First-In-First-Out) in which the data is to be stored, the memory device (308) being to receive an indication of a position for a read pointer of the memory device (308) from the MCU (214), the position being based on the waveform of the signal. [4] The apparatus of claim 2 or 3, wherein the communication detection module (208) is to remove a carrier frequency offset and reject adjacent channel interference from the data to generate the processed data. [5] The apparatus according to any one of claims 2 to 4, further comprising a demodulation module (210), wherein the demodulation module (210) is to perform a demodulation operation on the data to generate the processed data. [6] The device of any one of claims 1 to 5, wherein the memory module (206) is further to store a test pattern, and wherein the device further comprises an information module (212) that: the test pattern is to be received from the memory module (206); and perform cross-correlation operations on the test pattern, using a result of the cross-correlation operations to determine a propagation delay of the device. [7] The device of any one of claims 1 to 6, wherein the memory module (206) is to store the data while the BBIC (216) is in the sleep mode, and wherein the memory module (206) is to provide the data to the BBIC (216) while the BBIC (216) is in an active mode. [8] The device of any one of claims 1 to 7, wherein the device comprises the MCU (214) and wherein the device is a transceiver (204) of the MS (200). [9] Mobile station radio (MS) (200), comprising: an antenna (202); a baseband integrated circuit (BBIC) (216) for being in a sleep mode during wake periods of an idle state of the MS (200); and a transceiver (204) coupled to the antenna (202) and the BBIC (216), the transceiver (204) comprising: a communication processing module (218) for: Receiving data associated with signals from the antenna (202), wherein the signals are received by the antenna (202) during the waking periods; and Generating processed data from the received data; and a microcontroller unit (MCU) (214) for identifying a digital mobile radio (DMR) signal or a frequency modulation (FM) signal from the processed data, wherein the MCU (214) is to trigger a wake-up procedure of the BBIC (216) in response to an identification of the DMR signal or the FM signal. [10] The MS of claim 9, wherein the communication processing module (218) is to generate a field strength indicator (RSSI) based on the data, and wherein the MCU (214) is to use the RSSI to identify the DMR or FM signal. [11] The MS of claim 9 or 10, wherein the MCU (214) is to identify a portion of the data associated with the DMR signal or the FM signal, and wherein the MCU is to cause the communication processing module (218) to provide the portion of the data to the BBIC (216) after the wake-up procedure of the BBIC (216) has been initiated. [12] The MS of claim 11, wherein the MCU (214) is to monitor the BBIC (216) for a receive enable warning, and wherein the MCU (214) is to cause the communication processing module (218) to deliver the portion of data in response to the receive enable warning. [13] The MS of claim 11 or 12, wherein the communication processing module (218) comprises a FIFO memory device (308) that stores the data associated with the signals, and wherein the MCU (214) provides an indication of a position of a read pointer for the memory device (308) for delivery of the portion of the data to the BBIC (216). [14] The MS of claim 13, wherein the indication of the position of the read pointer comprises an indication of a set of memory positions where the read pointer is to be located from a write pointer for the memory device (308). [15] MS according to claim 13 or 14, wherein the indication of the position of the read pointer comprises an indication of a set of memory positions from which the read pointer is to be moved from a current position of the read pointer. [16] MS according to one of claims 9 to 15, wherein the MCU (214): cause a test pattern to be stored within a memory device (308) of the communication processing module (218); cause the memory device (308) to deliver the test pattern to a correlator component (502) of the communication processing module (218); and to determine a propagation delay from the memory device (308) to the correlator component (502) based on the test pattern. [17] The MS of any one of claims 9 to 16, wherein identifying the DMR signal comprises identifying a frame synchronization (SYNC) code of the DMR signal from the processed data. [18] MS according to one of claims 9 to 17, wherein the MS (200) is a DMR-MS. [19] One or more non-transitory computer-readable storage media having instructions stored thereon, the instructions, when executed by a microcontroller unit (MCU) (214) of a transceiver (204) of a DMR (Digital Mobile Radio)-MS (Mobile Station Radio) (200), causing the MCU (214): identifies a DMR signal or a frequency modulation (FM) signal from processed data retrieved by a communications processing module (218) of the MS (200), the processed data being associated with a signal received by the MS (200) during a wake period of an idle state of the MS (200); triggers a wake-up procedure of a baseband integrated circuit (BBIC) (216) in response to an identification of the DMR signal or the FM signal; and causes the communication processing module (218) to deliver the processed data to the BBIC (216). [20] One or more non-transitory computer-readable media according to claim 19, wherein the instructions, when executed by the MCU (214), further cause the MCU (214): identifies a field strength indicator (RSSI) associated with the DMR signal or FM signal retrieved by the communications processing module (218) of the MS (200); and determines that the RSSI indicates that a field strength of the DMR signal or the FM signal exceeds a threshold.

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