SERDES RECEIVER WITH OPTIMIZED CDR PULSE SHAPING

Abstract

Clock data recovery system with: a feedforward equalizer configured to equalize a first input signal received from an analog-to-digital controller based on a plurality of received tap coefficients, thereby producing a first output signal; an adder configured to add the first output signal and a feedback signal from a decision feedback equalizer, thereby producing a second output signal; a double limiter configured to receive the second output signal and provide a first group of preliminary decisions to a decision feedforward equalizer, the decision feedforward equalizer providing an equalized output signal; a second adder configured to generate a first error signal based on the equalized output signal from the decision feedforward equalizer, wherein the plurality of received tap coefficients are based on the error signal; and a clock data recovery circuit configured to receive the first output signal and provide a setting signal for the analog-to-digital controller.

Description

background

[0001] Feedforward equalizers (FFEs) and decision feedback equalizers (DFEs) are among the most widely used equalizers in modern SerDes receivers (SerDes: parallel-to-serial converters / series-to-parallel converters) to compensate for intersymbol interference (ISI). Both equalizers have their respective advantages and disadvantages. The FFE can correct the precursor and postcursor ISI, but it also tends to amplify noise and crosstalk. The DFE corrects the postcursor ISI and does not amplify noise in the process, but it cannot correct the precursor ISI. The DFE is a powerful equalizer for postcursor ISI correction, but it has error propagation that the FFE does not have.For a DSP-based SerDes (DSP: digital signal processing), a parallel data path for these two equalizers is required. The FFE is well-suited for these implementations, while the DFE is unsuitable because its complexity increases exponentially with the number of taps. Although the DFE is preferred over the FFE due to its inherent ability to not amplify noise, it is impractical to implement it for postcursor ISI correction beyond the first few taps. Therefore, most DSP SerDes receivers use multiple FFE taps for precursor and postcursor ISI correction and then only one or two DFE taps for postcursor correction.

[0002] US 9 584 345 B1 discloses digital receiver systems and clock recovery techniques for implementing asynchronous baud rate clock recovery systems for multi-stage line modulation of high data rate serial receivers. A two-stage postcursor ISI equalization system is provided to efficiently emulate, for example, a four-stage DFE (Decision Feedforward Equalization) system while converting a four-stage equalized signal into a two-stage equalized signal. For example, a two-stage postcursor ISI equalization system comprises a DFE stage operating on a most significant component of a given four-stage data symbol, followed by a DFFE (Decision Feedforward Equalizer) stage operating on a least significant component of the given four-stage data symbol.In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol into a 2-level symbol.

[0003] US 8 615 062 B2 discloses a method for adapting impulse response taps of a receiver. An analog-to-digital converter (ADC) generates an ADC value for each bit sample of a received signal. An error signature analysis (ESA) module defines a window of bit samples and estimates, for the window, a bit value corresponding to each sample based on the ADC value. The ESA module generates (i) a reconstructed ADC value corresponding to an estimated cursor bit based on a number of estimated pre-cursor bits, the estimated cursor bit, and a number of estimated post-cursor bits, and (ii) an error signature value based on the reconstructed ADC value and the ADC value.Based on the error signature value and a minimum impulse response value, it is determined whether the cursor bit corresponds to residual intersymbol interference (ISI), and if so, the error signature value is accumulated and the tap values ​​for each impulse response tap are adjusted.

[0004] US 6 226 323 B1 describes a system for reducing the complexity of an adaptive decision-feedback equalizer for use in conjunction with a dual-mode QAM / VSB receiver system. QAM and VSB symbols, expressed in two's complement notation, contain an additional bit required to compensate for a fixed offset term introduced by the two's complement numbering system. A decision-feedback equalizer includes a decision-feedback filter section that operates with symbolic decisions represented by a word length that excludes the added bit representing the offset. The residual word is convolved with the decision-feedback filter coefficients, while a DC component corresponding to the excluded bit is convolved with the same coefficient values ​​in a correction filter.The two values ​​are summed to provide an ISI compensation signal at the input of a decision device such as a slicer. A DC component representing a pilot tone in VSB transmission systems also introduces a DC component and additional bits into a VSB word length. These additional bits are similarly excluded, and the residual representation is convolved with coefficient values ​​in a decision-feedback filter. The DC component, including the pilot tone representation, is convolved in a correction filter with the same coefficient values. Short description of the drawings

[0005] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 shows a block diagram of a transmission system according to examples of the present invention. Fig. 2 shows a block diagram of a SerDes receiver architecture according to examples of the present invention. Fig. 3 shows an exemplary signal representing a lock state, an early clock, and a late clock according to examples of the present invention. The Fig. 4A to 4C show exemplary waveforms identifying precursor, cursor, and postcursor positions according to examples of the present invention. Fig. 5 shows a block diagram of a SerDes receiver architecture according to examples of the present invention. Fig. 6 shows a block diagram of a feedforward equalizer (FFE) with m precursor and n postcursor taps according to examples of the present invention. The Fig. 7A and Fig. 7B show block diagrams of a decision feedback equalizer (DFE) according to examples of the present invention. Fig. Figure 8 shows a block diagram of a single-stage multi-tap decision feedforward equalizer (DFFE) according to examples of the present invention. Fig. 9 shows a conceptual block diagram of a DFFE according to examples of the present invention. Fig. 10 shows a conceptual block diagram of a two-stage DFFE according to examples of the present invention. Fig. 11 shows a linear model of an ideal feedback equalizer according to examples of the present invention. Fig. 12 shows a linear model of a DFFE according to examples of the present invention. Fig. Figure 13 shows a linear model of a two-stage DFFE according to examples of the present invention. Fig. 14 shows a single-stage DFFE for a cascade DFFE according to examples of the present invention. Fig. 15 shows a three-stage DFFE with DFE outputs as first preliminary decisions according to examples of the present invention. Fig. 16 shows a three-stage DFFE according to examples of the present invention. Fig. 17 shows a single-stage DFFE for a cascade DFFE according to examples of the present invention. Fig. 18 is a flowchart illustrating a method according to some embodiments. Detailed description

[0006] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] Examples described here focus on a digital signal processing (DSP) SerDes receiver architecture that includes a decision feedforward equalizer (DFFE) and equalization and clock data recovery (CDR) modules integrated with common automatic adaptation to optimally shape a signal for improved CDR and SerDes performance. SerDes is a device typically used in high-speed transmissions to compensate for limited inputs and outputs. A SerDes device converts data between parallel and serial interfaces using one or more differential lines to send data from point A to point B.

[0009] Fig. 1 shows a block diagram of a SerDes transmission system 100 according to examples of the present invention. In particular, the SerDes transmission system 100 includes a transmitter 104 communicatively coupled to a receiver 112 via a transmission channel 108. The transmitter 104 is configured to transmit one or more signals to the receiver 112 via the transmission channel 108. The transmitter 104 may include one or more non-recursive filters for conditioning data prior to transmission to the transmission channel 108. The transmission channel 108 may include a physical transmission medium, such as a backplane, a drive head in a magnetic recording system, copper cables, fiber optic cables, one or more coaxial cables and / or lines, or the transmission channel 108 may include one or more radio frequency (RF) channels.While it is stated herein that transmission channel 108 is used in a SerDes transmission system 100, examples of the present invention are not so limited, and some examples could be used in alternative transmission systems that utilize a transmitter and a receiver communicating over a transmission channel. Furthermore, it should be understood that each "bit" of a signal has a corresponding logical value, and that various signals described herein may utilize multi-bit data symbols based on various data coding schemes, such as pulse amplitude modulation (e.g., PAM-4).

[0010] The effect of intermittent crosstalk (ISI) generally increases with the transmission speed in the transmission channel 108. ISI is a form of signal distortion in which one symbol overlaps with subsequent symbols. This is an undesirable phenomenon because the preceding symbols have a similar effect to noise and therefore make the transmission less reliable. That is, the broadening of a pulse, which represents one or more parts of a transmission, beyond its allotted time interval causes it to overlap with neighboring pulses. ISI is most often caused by multiple transmissions or the linear and nonlinear natural frequency response of a transmission channel, which causes consecutive symbols to "blur" together. Therefore, the presence of ISI in a transmission system can introduce errors that propagate to the receiver output.Accordingly, the design of transmit and receive filters generally minimizes the effects of ISI, thereby sending digital data to its destination with the lowest possible error rate.

[0011] Conventional SerDes architectures are generally limited by the coupling problem between CDR and equalization adjustment. When the CDR and equalization are both adjusted by an equalized end node, the impulse response from the equalization is ideally flat. However, this flat impulse response makes it difficult for baud-rate CDRs, which are typically used in these architectures, to find a stable blocking point because multiple points on the impulse response satisfy the convergence criterion. To alleviate this problem, the CDR and equalization are adjusted using different nodes, with a partially equalized node being used for the CDR.This potentially decouples the CDR and equalization to avoid the problem of fully equalized link adaptation, but the impulse response at the partially equalized CDR node may not be symmetric, which can lead to a suboptimal CDR blocking point. Even if the CDR convergence point is optimal for the partially equalized CDR node, the CDR convergence point for the fully equalized end node may not be optimal. Thus, the conventional SerDes architecture usually requires CDR blocking point adjustment mechanisms to achieve better margins, which increases the complexity of the entire architecture. The CDR blocking point and BER (bit error rate) margins tend to be sensitive to the transmitter settings, as they play a large role in determining the shape of the impulse response, and therefore, link adaptation becomes a much more difficult task.And since the DFE is limited to the postcursor ISI alone, equalization tends to be dominated by the FFE, making it more sensitive to noise and crosstalk. Accordingly, the conventional SerDes architecture suffers from limitations such as the coupling between the CDR and equalization, which leads to uncertain CDR convergence points; an impulse response that may not be symmetric at the CDR node, resulting in a suboptimal CDR blocking point; conventional SerDes architectures typically require CDR blocking point adjustments for better margins; link spans of conventional SerDes architectures are sensitive to transmitter tuning values; and link adjustment tends to be a non-trivial task.

[0012] Fig. 2 shows an exemplary SerDes receiver architecture 200 having an equalization data path for implementing precursor and postcursor ISI correction through a combination of a feedforward equalizer (FFE), decision feedback equalizer (DFE), and a precursor tap-activated multi-tap decision feedforward equalizer (DFFE). The SerDes receiver architecture 200 may be implemented in the receiver 112 and may, as shown in Fig. 2, an analog front-end (AFE) circuit 204 including a continuous-time linear equalizer (CTLE) 208 and a variable gain amplifier (VGA) 212. Since a serial data channel tends to attenuate higher frequencies of a signal more than lower frequencies of the signal, the CTLE 208 is included to amplify high frequencies of a signal 202 received at the SerDes receiver architecture 200 to bring a majority of the frequency components of the received signal 202 to a similar or the same amplitude. However, amplifying signal frequencies also increases jitter and noise. The VGA 212 may be included to variably amplify signal amplitudes of the signal across the majority of frequencies.Accordingly, the AFE circuit 204 typically minimizes the ISI introduced by the combined characteristics of the transmitter and the channel, such as the ISI resulting from the impulse response of the channel, thereby reducing the ISI at the receiver.

[0013] The AFE circuit 204 may provide an equalized signal to an analog-to-digital converter (ADC) 216 to convert the received and equalized signal into a digital signal for subsequent digital signal processing at a digital signal processor (DSP) 218. The DSP 218 may include, among other things, an FFE 220, a clock data recovery (CDR) adjuster 224, a DFE 228, a DFFE 232, and an equalization adjuster 236. In particular, the CDR adjuster 224 may tap an intermediate node in the equalization data path between the FFE 220 and the DFE 228 for a reduced delay time, resulting in improved jitter tracking performance. The link adaptation (e.g., the CDR adaptation 224 and the equalization adaptation 236) implemented as part of the SerDes receiver architecture 200 eliminates potential negative interaction mechanisms between the CDR adaptation 224 and the equalization adaptation 236.That is, the unique combination of equalization provided by SerDes receiver architecture 200 and CDR matching 224 provides a symmetric impulse response at the CDR node that is optimal for a Müller-Muller baud rate CDR. The Müller-Muller CDR, sometimes referred to as MM-CDR, is a common and well-known type of baud rate CDR. Since the MM-CDR is typically sensitive to the shape of the impulse response, the proposed SerDes receiver architecture 200 addresses this limitation by "pulse shaping" the signal so that it is symmetric regardless of the real channel impulse response. The MM-CDR also has problems related to finding a stable blocking point when blocking to a fully equalized node, since any point on the impulse response can be a potential blocking point.However, the proposed SerDes receiver architecture 200 addresses this problem by introducing a residual ISI symmetric with the first tap's postcursor ISI, which is equal to the first tap's precursor ISI. This ensures a stable CDR convergence point with improved timing margins. The residual ISI is fully compensated by the final equalization stages and therefore does not affect the final bit error rate (BER) of the fully equalized signal used for decision making. Furthermore, due to the additional use of the DFFE 232 for precursor and postcursor ISI correction, the SerDes receiver architecture 200 has improved noise and crosstalk performance compared to a conventional FFE-dominant architecture.The SerDes receiver architecture 200 presented here achieves robust performance with a BER improvement over conventional architectures over a wider range of transmitter settings because it is largely insensitive to the channel impulse response due to its CDR pulse shaping capability.

[0014] In contrast to conventional SerDes architectures, in the SerDes receiver architecture 200, the DFE 228 does not need to be part of the main signal data path. That is, in an equalization data path 221, which is Fig. 2, the signal equalized by the DFFE 232 is actually the output of the FFE 220. The DFE 228 merely provides a first set of preliminary decisions corresponding to the output of the FFE 220 for processing by the DFFE 232. Thus, the DFE 228 may be omitted in some implementations. The DFE 228 may be used to start with a good BER at the input of the DFFE 232. If the DFE 228 is bypassed, further DFFE 228 stages, such as those shown in Fig. 5 can be used to achieve a desired BER. In principle, the DFE 228 can be bypassed, and its use can be determined by implementation cost trade-offs.

[0015] Similar to the DFE 228, the FFE 220 may also be omitted in some embodiments. The FFE 220 enables additional pre-equalization, resulting in a signal starting with a better signal-to-noise ratio (SNR), which enables a better BER for preliminary decisions, requiring fewer DFFE stages overall. The FFE 220 may amplify noise, which can be addressed by removing the FFE 220 entirely, but one or more additional DFFE stages may also be used to achieve a desired BER if the FFE 220 is not included in the architecture 200.

[0016] According to examples of the present invention, the SerDes receiver architecture 200 shown in Fig. 2, tap or utilize the FFE 220 node for CDR, which has the advantage of allowing sufficient equalization to reduce CDR noise and a shorter delay time to improve jitter tracking. Accordingly, CDR adjustment 224 is essentially decoupled from equalization adjustment 236 because they are tapped from different nodes; that is, CDR adjustment 224 utilizes FFE 220, while equalization adjustment 236 utilizes DFFE 232. Thus, the SerDes receiver architecture 200 is capable of adjusting the precursor and postcursor ISI correction at both the CDR FFE intermediate node, for example, the FFE node 220, and the equalized DFFE end node, for example, the DFFE node 232.As explained later, this implementation provides the flexibility to shape a symmetrical impulse response at the CDR node 224 independent of the transmitter settings, leveraging a residual ISI of the precursor and postcursor taps 220 and 232 that is fully compensated by subsequent DFFE stages. Since the SerDes receiver architecture 200 utilizes a multi-tap DFFE 232 topology with precursor taps, the precursor ISI can be utilized along with the postcursor ISI at the CDR node 224, so the impulse response is symmetrical and optimized for the MM-CDR.

[0017] The DFFE 232 removes the residual ISI present at the CDR node 224 because the DFFE 232 is capable of correcting the precursor and postcursor ISI. Furthermore, since significant signal equalization occurs after the FFE 220 with preliminary decisions based on the DFFE 232, the SerDes receiver architecture 200 is not FFE-dominant and exhibits better performance in the presence of noise and crosstalk than a conventional FFE-dominant architecture. Due to the aforementioned factors, robust performance is observed with an order of magnitude BER improvement over a conventional architecture.In summary, the SerDes receiver architecture 200 can optimize pulse shaping for the MM-CDR, reduce delay time and improve jitter tracking due to CDR tapping from an intermediate node in the equalization data path, reduce and / or eliminate coupling problems between the CDR adjustment and the equalization adjustment, enable a wider operating range for SerDes adjustment values, do not require special CDR blocking point adjustment, improve crosstalk performance over FFE-dominant SerDes architectures, and provide robust performance with improved BER over conventional SerDes architectures.

[0018] The CDR pulse shaping functions implemented by the SerDes receiver architecture 200 discussed above are described with reference to the Fig. 3 to 4C. According to the present invention, references to the MM-CDR and the baud rate CDR should be understood as references to a phase error detector (PED) used in a CDR loop 224 and should not be confused with the overall signal processing loop. For example, a PED can compare a phase between input data and a recovered clock and provide information for adjusting the phase of a sample clock. While the present invention primarily focuses on the MM-CDR, details discussed here can be generalized to other baud rate CDRs as well, as they have similar convergence characteristics.

[0019] The MM-CDR clock recovery can be explained using an impulse response as described in Fig. 3. A first precursor 304, a main cursor 308 and a first postcursor 312 are shown in Fig. 3 by h(τ k- T3), h(τ k ) or h(τ k + T b ), which can also be done using a simpler representation, namely h -1 , h0 or h1, respectively. The clock phase states can be defined as h -1 = h1 (blocking state), h -1 < h1 (early state) and h -1 > h1 (late state). An optimal scenario for the MM-CDR is a blocking at the peak value h0 of the impulse response, and since the blocking state is defined by h -1 = h1, an optimal impulse response at the CDR node is a symmetric impulse response with an initial state of h -1 = h1. For a Fig. 4A given asymmetric pulse with an initial state of h -1 < h1 and at a Fig. 4B shown given asymmetric impulse with an initial state of h -1> h1, the CDR is blocked after or before the given peak value of the impulse response to maintain a residual state of h -1 = h1, which after CDR convergence leads to a lower h0, eventually resulting in smaller margins.

[0020] For an ideal square wave response with h -1 = h1 = 0, as shown in Fig. However, as shown in Figure 4C, the MM-CDR has an unstable blocking point because every point at the peak of the impulse response is a potential convergence point. This is because even if the CDR shifts early or late, the CDR convergence criterion is met as long as the CDR samples the peak of the impulse response. The MM-CDR can effectively be regarded as a peak detector, similar to other baud-rate CDRs, but since a square wave response has multiple peaks, it is actually not an optimal impulse response for the MM-CDR, although jitter and noise can lead to a wide-open eye. Such a scenario can be encountered when a fully equalized node is sampled with an MM-CDR. Thus, an ideal node for the MM-CDR has partial equalization with a residual state of h -1 = h1.

[0021] Fig. 5 shows a SerDes receiver architecture 500 that incorporates further aspects of the SerDes receiver architecture 200 of Fig. 2 according to examples of the present invention. The SerDes receiver architecture 500 may first receive a digital signal from an ADC, such as the ADC 216 received. The digital signal y kmay be provided to an FFE 502, where the FFE 502 may be a finite element frequency (FIR) filter capable of correcting the precursor ISI and the postcursor ISI. From the FFE 502, a signal having a corrected precursor ISI and postcursor ISI may be forwarded to a junction 504, where it may be combined with a compensated postcursor ISI signal provided by a preliminary decision limiter 506 and a DFE FIR 508 to generate a further compensation signal. The signal provided to and equalized by a DFFE, such as DFFE 510, may be the output of an FFE, such as the FFE 502. The DFE FIR 508 provides a first group of preliminary decisions from the preliminary decision double limiter 506, corresponding to the output of the FFE 502, for processing with the DFFE 510.The DFE FIR 508 may be used to provide a first BER at the input of the DFFE 510. In some cases, the DFE FIR 508 may be bypassed or otherwise unused, and in these cases, additional DFFE 510 stages, such as a DFFE 512 and a DFFE 514, may be implemented to achieve a desired BER at the final output.

[0022] The multi-stage multi-tap DFFEs 510 to 514 can detect faults at a connection point 516 based on setpoints 518. In Fig. 5 shows DFFEs 510 to 514, but more or fewer DFFEs can be used. As also shown in Fig. 5, one or more LMS coefficients 520 (LMS: Least Mean Square) may be derived from the errors and data provided by the DFFE 514, and the one or more LMS coefficients 520 may then be provided again for each of the DFFEs 510 through 514. In addition, LMS coefficients 522 and / or 524 may be provided for the DFE FIR 508 and the FFE 502. A CDR adjustment may occur at 528 and may then be provided again to an ADC, such as the ADC 216. Further details of a DFFE are described in the Fig. 9 and Fig. 10 according to examples of the present invention.

[0023] Fig. 6 provides further details of an example of the FFE 502 according to examples of the present invention. In particular, the FFE 502 may be a finite element frequency (FIR) filter that can correct the precursor ISI and the postcursor ISI. As shown in Fig. 6, a block diagram shows an FFE for one symbol with m precursor taps (602A to 602D) and n postcursor taps (604A to 604D) and with a plurality of unit delays 606. The unit delays 606, for example -1 required for the FFE implementation can be implemented in a DSP SerDes architecture, such as the SerDes receiver architecture 200, in the digital domain. While the FFE can provide high-frequency gain to compensate for channel loss, correct the precursor and postcursor ISI, and provide a parallel data path implementation, the FFE can also amplify crosstalk and noise, and its implementation can be prohibitively expensive if multiple taps are required. However, the FFE 502 can provide an initial signal for the CDR and subsequent equalization stages. An initial signal x kcan be input, wherein one or more precursor signal components derived from the precursor taps 602A to 602D and, for example, -1 delayed, and one or more postcursor signal components derived from the postcursor taps 604A to 604D and delayed, for example, by z -1 delayed, can be provided to a summing component 608. The FFE 502 can provide a signal x_ffe k spend.

[0024] The Fig. 7A to 7C show further details of DFE implementations corresponding to the DFE FIR 508, the decision double limiter 506, and the junction 504 shown in Fig. 5, according to examples of the present invention. In particular, a DFE, such as the DFE-FIR 508, is a filter that can use feedback from detected symbols to generate an estimate of an output, such as a channel output. Detected symbols are input to the DFE, such as the DFE-FIR 508, so that the DFE generates an output that can be subtracted from the output of a linear equalizer, if present. The DFE, such as the DFE-FIR 508, can use the postcursor ISI, such as in Fig. 4B, by using an FIR filter in a feedback loop that utilizes real decisions from a decision double limiter. Because the DFE uses past decisions in a feedback path, it can only correct the postcursor ISI associated with those symbols. The DFE is unable to correct a precursor ISI, as this requires knowledge of future samples.

[0025] Fig. Figure 7A shows a block diagram of a DFE in a direct feedback configuration. That is, a signal y kcan be provided to a summing junction 702, and the signal resulting from the summing junction 702 is provided to a decision clipper 704, wherein the decision clipper 704 makes a symbol decision. The decision clipper 704 quantizes the input signal so that the ISI is derived directly from the incoming signal y by means of a feedback FIR filter 706. k can be subtracted.

[0026] In some topologies of the DFE, decisions are speculatively precomputed and one of the precomputed decisions is selected based on previous symbols to eliminate the feedback path at the decision double limiter 704. For example, in Fig. 7B shows a block diagram of a speculative DFE with only one tap for NRZ signaling (NRZ: Non Return to Zero), and in Fig. 7C shows a block diagram for a PAM-4 signaling system. Fig. The single-tap speculative DFE shown in Figure 7B includes summing junctions 708 and 710, decision limiters 712 and 714, a multiplexer 716, and a latch or flip-flop 718. The number of limiters for the single-tap DFE can be doubled for PAM-4 over NRZ along with changing an associated multiplexer from 2 to 1 to 4 to 1, as shown in Fig. 7C. That is, the number of double limiters 720 fed by input signals 722 can be increased by the NRZ signaling of Fig. 7B, which requires a multiplexer 724 with additional inputs that provide a selected signal for a flip-flop 726.

[0027] According to examples of the present invention, a configuration of an iterative DFE using preliminary decisions is provided that is less complex to implement than multi-tap DFEs and realizes multi-tap precursor and postcursor ISI correction. Preliminary decisions can be used such that multiple iterations improve the quality of the preliminary decisions.

[0028] Fig. 8 shows further aspects of a DFFE, such as the DFFE 510 of Fig. 5, according to examples of the present invention. In particular, Fig. 8 shows a basic iteration stage of a multi-tap DFFE configuration 800 with m precursor and n postcursor taps. The multi-tap DFFE configuration 800 shown in Fig. 8, does not exhibit any noise or crosstalk amplification like the FFE because, unlike the FFE, which uses real analog signal inputs, the DFFE uses decision outputs from double limiters as inputs to the FIR. The digital outputs of the preliminary decision double limiters are multiplied by the tap coefficients to reduce the amount of noise. And because digital outputs are used as the multiplier inputs, the multipliers are effectively converted into adders, which tend to be easier to implement. In particular, a signal x k into precursor taps 804A to 804C, a precursor tap 804D and postcursor taps 804E to 804H (collectively referred to as taps 804) and can be adjusted at each tap 804 by an amount z -1delayed, as shown at delay elements 806. Taps 804 are then each provided to a preliminary decision limiter 808. The outputs from preliminary decision limiters 808 may each be provided to multipliers 812, with each multiplier 812 multiplying the result of preliminary decision limiter 808 by a coefficient. For example, preliminary decision limiter 808 may quantize the sampled input from filter taps 804A through 804H, scaling the quantized value by a filter tap coefficient provided to multipliers 812. The outputs from the multipliers 812 may each be provided to an adder or combiner 816, with the outputs each effectively subtracted from the cursor tap 804D to provide an output that is precursor and postcursor ISI compensated.

[0029] A mathematical block diagram of a single-stage DFFE 902, which is similar to the exemplary DFFE 510 of Fig. 5 is in Fig. 9. As stated above, the decisions at the output of a first clipper 904 are only preliminary, and they are then used in an FIR filter 906 to equalize the signal at a junction 908, which is then input to the next stage clipper, such as clipper 910. It can be shown that the bit error rate (BER) of the decisions of the last stage, such as 910, is lower or better than the BER of the preliminary decisions of the previous stage, such as 904. This property of the DFFE can be used to cascade multiple stages and lower the BER to the desired level with each successive iteration. The lower the initial BER, the fewer DFFE stages are needed. And because decisions are preliminary and used as inputs in a feedforward path rather than the feedback path of the DFE, there is no error propagation in the DFFE.Furthermore, the complexity of the DFFE increases linearly with the number of taps, making it possible to implement a multi-tap DFFE for the precursor and postcursor ISI in a DSP SerDes architecture. Accordingly, higher-order floating taps can be implemented to handle non-ideal channel behavior, such as reflections. Advantages of the DFFE include ISI cancellation without amplifying crosstalk or noise; implementation complexity that increases linearly with the number of taps; a parallel datapath DSP implementation; reduced or no error propagation, as exhibited by the DFE; reduced or no critical feedback path timing issues, as encountered with the DFE; and the multipliers of the FFE can be replaced by adders in the DFFE.

[0030] It can be demonstrated that the quality of the decisions made by the output limiters, such as the output limiter 910, is better than the quality of the preliminary decisions made by the limiters of the previous stages, for example, the preliminary decisions made by the decision limiter 904. This is because when the first-stage limiters, such as the limiter 904, make the correct preliminary decisions, the output-stage limiters, such as the limiter 910, also make the correct decisions with an improved margin. However, when the preliminary decisions made by the limiter 904, for example, are erroneous, the output-stage limiters, such as the limiter 910, do not always make erroneous decisions.This means that the final stage's decisions can be correct even if the preliminary decisions are flawed, because incorrect preliminary decisions can sometimes allow for useful ISI compensation even if it is technically flawed. This is because the ISI is actually useful when there are no jumps in the data structure. For example, improved for a D data structure. k-1 = D k the ISI from a D k-1 -Symbol the signal levels for detecting a D k -symbol. And if D k-1 for this structure is faulty, carries the ISI compensation, which corresponds to the faulty D k-1 corresponds to, helps to determine the signal for the D k symbol. For example, a simplified analysis is provided as follows.

[0031] Consider an NRZ data transmission on a channel whose impulse response has a main cursor h0 and a first-tap postcursor h1. A signal level X k , which belongs to the D k -bit is provided in Equation 1: Xk=h0⋅sgn(Dk)+h1⋅sgn(Dk−1)

[0032] An output signal level Y k , which belongs to the D k -Bit after ISI compensation after a correct detection of D k-1 is given by equation 2: Yk=h0⋅sgn(Dk)+h1⋅sgn(Dk−1)−h1⋅sgn(Dk−1)⇒Yk=h0⋅sgn(Dk).

[0033] However, if there is an error in the detection of D k-1 the signal level Y k , which belongs to the D k -bit after ISI compensation with an erroneous preliminary decision, given by Equation 3: Yk=h0⋅sgn(Dk)+h1⋅sgn(Dk−1)+h1⋅sgn(Dk−1) ⇒Yk=h0⋅sgn(Dk)+2h1⋅sgn(Dk−1).

[0034] However, if D k-1 = D k is, a signal level Y k ' following an erroneous preliminary decision by D k-1 actually positive for the correct detection of the D k -bits are restored as given by Equation 4: Yk=h0⋅sgn(Dk)+2h1⋅sgn(Dk) ⇒Yk=(h0+2h1)⋅sgn(Dk).

[0035] It can thus be seen that there is a lower probability of error if the previous decision is incorrect. By extending the above analysis, we can conclude that with the DFFE topology described in the Fig. 8 and Fig. 9 is shown, the BER Dk1 the double limiter of the last stage is lower than the BER Dk0 the first stage double limiter.

[0036] The probability of detecting an error can be expressed as follows: Pe(Dk1)=Pe(Dk0)⋅Pe(Dk1, Dk0|e=1) where Pe(Dk1) for the error probability in Dk1 stands and Pe(Dk1, Dk0|e=1) for the error probability in Dk1 stands when there is an error in Dk0 From the above equation it can be seen that Pe(Dk1) <Pe(Dk0)⇒BER(Dk1)<BER(Dk0) This property of the DFFE can be used to cascade multiple stages of the DFFE and gradually lower the BER of each iteration until the desired BER level is reached or until a stage is reached where no further BER reduction is possible because the signal-to-noise ratio is limited by the noise and not by the ISI. A block diagram for a two-stage DFFE 1002 is shown in Fig. 10. In particular, a first stage 1004 may include a preliminary decision limiter 1006 that provides a preliminary decision to a first FIR filter 1008. An equalized signal from a first junction 1010 may be provided to a second stage 1012 that includes a decision limiter 1014, which may be considered a preliminary decision limiter. The quantized decisions from the decision limiter 1014 may be provided to a second FIR filter 1016. The equalized signal resulting from a second junction 1018 may be provided to a decision limiter 1020.

[0037] The BER relationships of each stage can be expressed as follows: BER(Dk2) <BER(Dk1)<BER(Dk0)

[0038] The above equation can be generalized and extended for several stages.

[0039] According to examples of the present invention, decision clippers, such as decision clippers 904 and / or 910, are nonlinear in nature, but based on some simplifying assumptions, a linear model can be constructed for analysis purposes. One potential disadvantage of using decision clippers, such as decision clippers 904 and / or 910, is that they prevent noise from passing through, and thus, the clipper can be considered an open circuit for noise analysis. It is clear that there is no noise amplification due to the use of clippers in the FIR, and thus, the signal equalization case can be considered for this analysis.

[0040] With full equalization, the signal levels before and after the double limiters are at their corresponding logical levels. Thus, in these cases, the double limiter can be considered a short circuit. To be more precise, a scaling factor α can be used, but for this analysis, α = 1.

[0041] Considering an ideal feedback equalizer with m precursor taps and n postcursor taps, one obtains the following equation 7 for an equalizer: yk=xk−∑i=−mi=mhi⋅Dk−i, i≠k

[0042] This is similar to that of a DFE, except that the above equation also includes precursor tap correction, whereas the DFE is limited to postcursor ISI correction. It should also be noted that there is no practical way to implement the above equalizer, as it requires the use of later symbols. This analysis simply compares the performance of the DFFE with that of such an ideal equalizer.

[0043] A linearized model for such an ideal feedback equalizer is given in Fig. 11. An FIR 1102 in the feedback path of this ideal equalizer is similar to the FIR shown in the Fig. 5 and Fig. 7A and given by Equation 8: FIR=∑i=−mi=nhi⋅z−i+m, i≠0

[0044] The transfer function Ideal_Feedback_Eq(z) of this ideal equalizer then follows from the linear model of Fig. 7A, as shown in Equation 9 below: Ideal_Feedback_Eq(z)=1 / (1+FIR)

[0045] Using the Taylor series expansion, the above equation can be expressed as Equation 10: Ideal_Feedback_Eq(z)=1−FIR+FIR2−FIR3+FIR4

[0046] Now, taking into account the linearized model of the DFFE (such as the DFFE 510 of Fig. 5), which in Fig. 12, the transfer function DFFE(z) of the DFFE can be expressed as DFFE(z) = 1 - FIR. Accordingly, the DFFE transfer function lacks the higher-order terms of the ideal equalizer. However, by cascading multiple DFFE stages, each higher-order term can be realized with each subsequent iteration stage. For example, a linearized model of a two-stage DFFE described in Fig. 13, a first stage 1302 and a second stage 1304. The transfer function DFFE2(z) of a two-stage DFFE is given by Equation 11: DFFE2(z)=1−FIR⋅(1−FIR)=>DFFE2(z)=1−FIR+FIR2.

[0047] Similarly, the transfer function DFFE3(z) of a three-stage DFFE is given by Equation 12: DFFE3(z)=1−FIR⋅(1−FIR+FIR2)=>DFFE3(z)=1−FIR+FIR2−FIR3.

[0048] The analysis can be extended to show that higher-order terms of an ideal equalizer can be realized by adding appropriate stages of the DFFE. For a practical application with an acceptable initial SNR, the DFFE can achieve the same performance as an ideal feedback equalizer using only precursor taps in a few initial iterations. Although the ideal feedback equalizer is not implementable, one advantage of the DFFE is its ease of implementation even when using precursor taps.

[0049] A DFFE, such as the DFFE 510 from Fig. 5, is an iterative equalizer that can be cascaded multiple times to realize a higher-order DFFE. To construct a higher-order multi-tap DFFE, the multi-tap DFFE can be used with a single-stage DFFE, such as the one described as DFFE 800 in Fig. 8, to provide a DFFE 1400 which is Fig. 14 by separating a cursor path 1402 from precursor taps 1404 and postcursor taps 1406. Accordingly, the cursor from the cursor path 1402 is provided to each subsequent stage unchanged from the previous stage. For example, a cursor path 1502 may be provided for a first stage 1504, a second stage 1508, and a third stage 1512. Returning to Fig. 14. The precursor taps 1404 and the postcursor taps 1406 may be provided to preliminary decision double limiters 1408 of the present DFFE, scaled, and summed at a junction 1410 to be provided as an output. As in Fig. 15, an output 1506 from the first stage 1504 is provided to the second stage 1508, and an output 1510 from the second stage 1508 is provided to the third stage 1512. Thus, by cascading three single-stage DFFE modules, as shown in Fig. 15, a third-order DFFE can be realized.

[0050] The number of required DFFE stages can be a function of the BER of the initial decisions. The better the initial BER, the fewer DFFE stages are required. To improve the quality of the initial preliminary decisions, instead of the raw double limiter outputs used in the Fig. 14 and Fig. 15, DFE double limiter outputs are used. That is, a three-stage DFFE 1600, which is Fig. 16, uses DFE outputs 1602 as initial preliminary decisions in a first stage 1604. To adapt the DFE double-limiter outputs 1602, single-stage DFFEs 1604, 1608, and 1612 have been modified to make decisions as inputs by utilizing double-limiters outside of DFFEs 1604, 1608, and 1612. Using this cascaded DFFE configuration, such as the three-stage DFFE 1600 shown, not only eliminates the residual ISI, but also enables optimized pulse shaping for the MM-CDR, resulting in robust performance with reduced sensitivity to SerDes adaptation. Accordingly, a single stage of the DFFE 1600, such as the DFFE 1604, 1608 and / or 1612, is referred to as a DFFE 1700 in Fig. 17. The DFFE 1700 is similar to the DFFE 1400 from Fig. 14, but differs in that the decision limiters 1408 of the DFFE 1400 are not included in the DFFE 1700. That is, decision limiters, such as decision limiters 1606 and 1610, are located outside the DFFE 1604 and 1608, respectively, as in Fig. 16. The DFFE 1700 also separates a cursor path 1702 from precursor taps 1704 and postcursor taps 1706.

[0051] One of the biggest challenges in integrating the MM-CDR with equalization blocks in the SerDes architecture is finding a joint matching solution that eliminates unwanted coupling mechanisms between the CDR and equalization matching. The proposed SerDes receiver architecture 500, with its unique combination of CDR, equalization, and joint matching, not only eliminates unwanted coupling between the CDR and equalization matching, but also shapes the impulse response at the CDR node to be optimal for the MM-CDR and all SerDes spans.

[0052] The adjustment of equalization blocks, such as FFE, DFE, and DFFE, is typically implemented using a Least Mean Square (LMS) algorithm, which minimizes the signal's error power compared to the nominal levels of the equalized signal. The goal of adjusting the equalization tap coefficients is to eliminate any residual ISI at these tap positions. The discussion focuses on h -1 and h1, i.e., the first precursor tap ISI and the first postcursor tap ISI, respectively, since the MM-CDR is primarily affected by these. The blocking state for the MM-CDR is determined by h -1 = h1. The MM-CDR PED, included here for completeness, is implemented using a PED equation based on a signal level y(k) (Equation 13): (k−1)⋅[k]−(k)⋅[k−1] or is implemented using a PED equation based on an error e(k) (Equation 14): [k−1]⋅[k]−[k]⋅[k−1]

[0053] To overcome coupling problems between the CDR and the equalization, various techniques have been used, such as introducing a residual ISI at the CDR node, but these techniques come at the expense of overall margins and the adjustment complexity in determining how much residual ISI should be introduced. The proposed SerDes receiver architecture 500 addresses these coupling problems by tapping the CDR from an intermediate node in the equalization data path and in subsequent equalization stages that compensate for the precursor and postcursor ISI. For example, let us return to Fig. 5, in which the CDR node 526 is tapped between the FFE 502 and the junction 504, while the equalization stages comprising the DFFE 510, the DFFE 512, and the DFFE 514 compensate for the precursor and postcursor ISI. Combined with the ability to add or subtract the ISI at the CDR node 526 and at the last equalized node, an impulse response is provided at the CDR node 526 such that it is optimal for the MM-CDR, but has no residual ISI at the last equalized node.

[0054] Below, attributes of the proposed SerDes receiver architecture that ensure optimized CDR pulse shaping are summarized. In particular, the CDR is tapped, for example, by the FFE node 526 and subsequently by one or more DFFEs, such as DFFEs 510, 512, and 514, capable of detecting the precursor ISI (h -1) and the postcursor ISI (h1) so that the MM-CDR-PED with a convergence condition of h -1 = h1 is used. Furthermore, the adaptation is controlled by the last equalized node, i.e., the LMS adaptation is used to control the FFE and DFFE equalization. Since the adaptation minimizes the ISI at the FFE node, for example, using the LMS coefficients 524, the impulse response becomes more symmetric, thus driving the MM-CDR to a better convergence point. Since the DFFE adaptation runs in parallel, providing LMS coefficients for the DFFEs 510, 512, and 514, for example, the multi-stage DFFE eliminates the residual ISI observed at the CDR node 526 and due to the MM-CDR adaptation with respect to h -1and h1 is symmetric. The net result is a symmetric impulse response at the CDR node 526 that is nearly optimal for the MM-CDR, but does not have the penalty of the residual ISI at the last equalized node.

[0055] For reliable convergence, the matching loop gain of the CDR is typically set higher than that of the FFE, which in turn is set higher than that of the DFFE. Further details of the CDR pulse shaping mechanism outlined above are discussed in more detail below.

[0056] The equalization is shared by the FFE and the DFFE, with their LMS coefficients being controlled by the adaptation, for example, such that the final ISI at the DFFE node is zero. That is, => h -1 (DFFE) = 0, h1(DFFE) = 0 → controlled by LMS adjustment.

[0057] This ensures that there is a residual ISI at the FFE node, which also happens to be the CDR node. The strength of the residual ISI at the FFE node 502 depends on the adjusted FFE coefficients 524 and the DFFE coefficients 520, which in turn are determined by the relative loop gains of the FFE and DFFE adjustments. With non-zero DFFE components and a final ISI at zero, there may be a residual ISI at the FFE node 502 that is DFFE-compensated. That is, => h -1 (FFE) ≠ 0, h1 (FFE) ≠ 0 → due to the joint DFFE adjustment.

[0058] Since the MM-CDR adapts in parallel, a blocking condition occurs in which h -1 = h1 at the CDR node 526. That is, => h -1 (FFE) = h1 (FFE) → controlled by MM-CDR.

[0059] Accordingly, there is a symmetrical impulse response with a non-zero ISI at the FFE node 502 or the CDR node 526, which is ensured by the joint adaptation of the MM-CDR, the FFE, and the DFFE. That is, => h -1 (FFE) = h1 (FFE) ≠ 0 → controlled by joint adjustment of the MM-CDR, the FFE and the DFFE.

[0060] This is an optimal condition for MM-CDR. Even if the impulse response is asymmetric before adjustment, the system is adjusted by adding or removing the ISI at the FFE node 502 (which is the CDR node 526) and the DFFE node (which is the last equalized node) such that there is a symmetric impulse response with a non-zero ISI at the CDR node 526. In some cases, the ISI is introduced at the FFE node 502 to make the impulse response symmetric and have an overall ISI of zero.

[0061] Symmetric CDR pulse shaping can be effectively used to simplify matching and increase the speed of convergence of the entire system by forcing the DFFE coefficients h -1 and h1 are equal, and by adjusting or fixing only one of them.

[0062] The advantage of this CDR pulse shaping method over conventional CDR adaptation mechanisms using the residual ISI is that the residual ISI at the CDR node 526 is fully compensated by the subsequent DFFE stages 510, 512, and 514 with little or no impact on the overall BER. Furthermore, the residual ISI is symmetrically adjusted with h -1= h1, which is optimal for the MM-CDR. Since the impulse response is largely symmetric regardless of the strength of the residual ISI at the CDR node 526, the CDR is blocked near the peak of the impulse response and is less sensitive to converged values ​​determined by the relative matching loop gains.

[0063] There is another advantage of a symmetrical impulse response at the CDR node 526. The CDR blocking point is determined by the impulse response at the CDR node 526, and therefore, even if the CDR node is blocked at an optimal point relative to the eye at the CDR node 526, it is not necessarily optimal relative to the eye at the fully equalized node, for example, at the output of the DFFE 514, potentially reducing timing margins at the fully equalized node, for example, at the output of the DFFE 514, even if the ISI is fully compensated. However, with a symmetrical impulse response at the partially equalized CDR node 526, the optimal CDR blocking point determined by the partially equalized eye tends to be quite close to the optimal blocking point relative to the fully equalized eye.This is because when a fully rectified eye is superimposed with a partially rectified eye, the zero-crossing points are similar. This can be inferred using a simplified analysis, as outlined below.

[0064] For a fully equalized eye, the zero crossing point is located halfway between the UI (Unit Interval) point before or after the peak of the eye. For a partially equalized signal with a symmetric impulse response, the impulse response value can be approximated to halfway between the UI point and the peak for a 0 → 1 transition, as shown in Equation 15: p0.5=h−0.5−h0.5(for the transition 0→1) where P 0,5 the signal value is halfway between the UI point and the peak value of the pulse, h -0,5 is half the UI precursor ISI value and h 0,5 is half the UI postcursor ISI value. For a symmetrical impulse response, h -0.5and h 0.5 be considered equal. Therefore, equation 16 applies: p0.5=h−0.5−h0.5(for the transition 0→1)

[0065] Similarly, p 0.5 = -h -0.5 + h 0.5 = 0 (for the transition 1 → 0).

[0066] Based on the above equations, the zero-crossing points for the partially rectified and fully rectified eyes are at the same position when they overlap. Therefore, the optimal CDR blocking points are similar for both eyes. This analysis is based on the simplified assumption that there is no ISI influence beyond the first precursor and first postcursor taps. However, since there are dominant ISI terms and the CDR is primarily influenced by them, the conclusions are still valid.

[0067] While LMS-based adaptation is described here and some embodiments may refer to LMS coefficients, coefficients derived by other means are also within the scope of the invention.

[0068] Fig. 18 is a flowchart illustrating a method 1800 according to some embodiments. The method 1800 may be implemented with the Fig. 5, but the presented method can also be used for other architectures. Fig. 5 and Fig.18, in a step 1810, an output of a feedforward equalizer 502 and a decision feedback equalizer 508 is received at a decision feedforward equalizer 510. The feedforward equalizer 502 equalizes an input signal based on a plurality of coefficients. In a step 1812, the plurality of coefficients are provided to the feedforward equalizer 502 based on an output of the decision feedforward equalizer 510.

[0069] In one example, a clock data recovery system is provided. The clock data recovery system may include: a feedforward equalizer configured to equalize a first input signal received from an analog-to-digital controller based on a plurality of received tap coefficients, thereby generating a first output signal; and an adder configured to add the first output signal and a feedback signal originating from a decision feedback equalizer, thereby generating a second output signal.The clock data recovery system may further include: a double limiter configured to receive the second output signal and provide a first group of preliminary decisions to a decision feedforward equalizer, wherein the decision feedforward equalizer provides an equalized output signal; and a second adder configured to generate a first error signal based on the equalized output signal from the decision feedforward equalizer, wherein the plurality of received tap coefficients are based on the error signal. Furthermore, the clock data recovery system may include a clock data recovery circuit configured to receive the first output signal and provide an adjustment signal to the analog-to-digital controller.

[0070] In another example, a SerDes receiver (SerDes: parallel-to-serial converter / serial-to-parallel converter) is provided. The SerDes receiver may include: a feedforward equalizer; a decision feedback equalizer; and a decision feedforward equalizer connected to the feedforward equalizer and the decision feedback equalizer, wherein an output of the decision feedback equalizer is provided to the decision feedforward equalizer and an output of the feedforward equalizer is provided to the decision feedforward equalizer and a clock data recovery unit.

[0071] In another example, a method is provided. The method may include the steps of: receiving, at a decision feedforward equalizer, an output of a feedforward equalizer and a decision feedback equalizer, wherein the feedforward equalizer equalizes an input signal based on a plurality of coefficients; and providing the plurality of coefficients based on an output of the decision feedforward equalizer to the feedforward equalizer.

Claims

[1] Clock data recovery system with: a feedforward equalizer configured to equalize a first input signal received from an analog-to-digital controller based on a plurality of received tap coefficients, thereby producing a first output signal; an adder configured to add the first output signal and a feedback signal from a decision feedback equalizer, thereby producing a second output signal; a double limiter configured to receive the second output signal and provide a first group of preliminary decisions to a decision feedforward equalizer, the decision feedforward equalizer providing an equalized output signal; a second adder configured to generate a first error signal based on the equalized output signal from the decision feedforward equalizer, wherein the plurality of received tap coefficients are based on the error signal; and a clock data recovery circuit configured to receive the first output signal and provide a setting signal for the analog-to-digital controller. [2] The clock data recovery system of claim 1, further comprising an analog front-end circuit connected to a channel, the analog front-end circuit configured to receive an input signal from the channel, the analog front-end circuit comprising a continuous-time linear equalizer and / or a variable gain amplifier. [3] The clock data recovery system of claim 1 or 2, wherein the decision feedforward equalizer receives the first output signal. [4] A clock data recovery system according to any preceding claim, wherein the decision feedforward equalizer is a first decision feedforward equalizer of a plurality of feedforward equalizers, and a second feedforward equalizer of the plurality of feedforward equalizers receives input signals from the feedforward equalizer and the first decision feedforward equalizer of the plurality of feedforward equalizers. [5] A clock data recovery system according to any preceding claim, wherein the plurality of received tap coefficients are based on an adaptation engine providing least mean square coefficients. [6] The clock data recovery system of claim 5, wherein the adaptation engine provides the least mean square coefficients to the decision feedback equalizer. [7] A clock data recovery system according to claim 5 or 6, wherein the adaptation engine provides the least mean square coefficients for the decision feedforward equalizer. [8] A clock data recovery system according to any preceding claim, wherein the decision feedforward equalizer comprises a plurality of precursor taps, a cursor tap, and a plurality of postcursor taps, the plurality of precursor taps and the plurality of postcursor taps providing a sample of the first output signal sampled at different times to a plurality of preliminary decision clippers. [9] The clock data recovery system of claim 8, wherein an output of each of the preliminary decision delimiters is scaled and combined with the output from the cursor tap. [10] SerDes receiver architecture (SerDes: parallel-to-serial converter / series-to-parallel converter) with: a feedforward equalizer; a decision feedback equalizer; and a decision feedforward equalizer connected to the feedforward equalizer and the decision feedback equalizer, wherein an output of the decision feedback equalizer is provided to the decision feedforward equalizer and an output of the feedforward equalizer is provided to the decision feedforward equalizer and a clock data recovery unit. [11] The SerDes receiver architecture of claim 10, wherein the decision feedforward equalizer comprises a plurality of postcursor taps, a cursor tap, and a plurality of precursor taps connected to an output of the feedforward equalizer. [12] The SerDes receiver architecture of claim 10 or 11, further comprising a cascade decision feedforward equalizer comprising the decision feedforward equalizer and a second decision feedforward equalizer, wherein an output from the decision feedforward equalizer is provided to the second feedforward equalizer. [13] The SerDes receiver architecture of any one of claims 10 to 12, further comprising an analog front-end circuit connected to a channel, the analog front-end circuit being configured to receive an input signal from the channel and comprising a continuous-time linear equalizer and / or a variable gain amplifier, and being configured to provide an output signal to an analog-to-digital converter between the analog front-end circuit and the feedforward equalizer. [14] SerDes receiver architecture according to one of claims 10 to 13, further comprising the clock data recovery unit. [15] The SerDes receiver architecture of claim 14, wherein the clock data recovery unit provides an adjustment signal to an analog-to-digital controller connected to the feedforward equalizer. [16] The SerDes receiver architecture of claim 14 or 15, wherein the clock data recovery unit receives an output of the feedforward equalizer. [17] SerDes receiver architecture according to one of claims 10 to 16, wherein the decision feedforward equalizer is a multi-stage multi-tap equalizer. [18] SerDes receiver architecture according to one of claims 10 to 17, further comprising: a channel; an analog front-end circuit; and an analog-to-digital controller connected to the feedforward equalizer, wherein the analog front-end circuit is arranged between the channel and the analog-to-digital controller. [19] Procedure with the following steps: Receiving, at a decision feedforward equalizer, an output of a feedforward equalizer and a decision feedback equalizer, wherein the feedforward equalizer equalizes an input signal based on a plurality of coefficients; and Providing the plurality of coefficients based on an output of the decision feedforward equalizer to the feedforward equalizer. [20] The method of claim 19, further comprising providing an adjustment signal for an analog-to-digital converter based on the output of the feedforward equalizer.

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