MAGNETIC DEVICE AND MAGNETIC DIRECT ACCESS MEMORY AND METHOD

Abstract

Magnetic storage device comprising: a magnetic tunnel junction stack, MTJ stack (100); a spin orbit torque induction wiring, SOT induction wiring (15) disposed above the MTJ stack (100); a first terminal coupled to a first end of the SOT induction wiring (15); a second terminal coupled to a second end of the SOT induction wiring (15) and to a source line (160); a selector layer (140) coupled to the first terminal and coupled to a word line (150); and a lower electrode (80) disposed below and coupled to the MTJ stack (100) and coupled to a switching device (110), where the MTJ stack (100) comprises: - a first magnetic layer (20) as a magnetic free layer; - a non-magnetic spacer layer (30) disposed beneath the first magnetic layer (20); and - a second magnetic layer (40) as a magnetic reference layer arranged under the spacer layer (30), wherein the SOT induction wiring (15) is arranged above the first magnetic layer (20), wherein the MTJ stack (100) further comprises an interface layer (50) disposed between the first magnetic layer (20) and the SOT induction wiring (15), the interface layer (50) comprising an MgO layer and a Co layer.

Description

BACKGROUND

[0001] Magnetic random-access memory (MRAM) offers comparable performance and density to volatile static random-access memory (SRAM) while maintaining the same low power consumption as volatile dynamic random-access memory (DRAM). Compared to non-volatile (NVM) flash memory, MRAM offers much faster access times and minimal degradation over time, whereas flash memory can only be rewritten a limited number of times. One type of MRAM is spin-transfer torque magnetic random-access memory (STT-MRAM). STT-MRAM uses a magnetic tunnel junction (MTJ) that is at least partially written by a current driven by the MTJ. Another type of MRAM is spin-orbit torque MRAM (SOT-MRAM), which generally requires a lower switching current than STT-MRAM. Patent application US 2019 / 0 386 203 A1 is known from the prior art.

[0002] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The following detailed description is best understood with reference to the accompanying drawings. Please note that, in accordance with industry practice, various features are not drawn to scale and are for illustrative purposes only. The dimensions of various features may, in reality, be arbitrarily enlarged or reduced to clarify the explanation. Fig. 1 is a schematic view of a SOT MRAM cell according to an embodiment of this disclosure. Fig. 2 is a schematic view of a SOT MRAM cell according to an embodiment of this disclosure. Fig. 3 is a schematic view of a SOT MRAM device according to an embodiment of this disclosure. Fig. 4 is a schematic view of SOT MRAM cells according to an embodiment of this disclosure. Fig. 5 is a schematic view of SOT MRAM cells according to an embodiment of this disclosure. Fig. 6 is a circuit diagram of a SOT MRAM device according to an embodiment of this disclosure. Fig. 7 is a circuit diagram of a SOT MRAM device according to an embodiment of this disclosure. Fig. 8 shows operations of a SOT MRAM cell according to an embodiment of this disclosure. Fig. 9 shows operations of a SOT MRAM cell according to an embodiment of this disclosure. Fig. 10A and Fig. 10B show structures of an SOT inductor wiring according to embodiments of this disclosure. Fig. 11A, Fig. 11B, Fig. 11C, Fig. 11D, Fig. 11E, Fig. 11F, Fig. 11G, Fig. 11H, Fig. 11I, Fig. 11 years and Fig. 11K show a sequential manufacturing operation for a SOT-MRAM device according to this disclosure. Fig. 12A, Fig. 12B and Fig. 12C show various structures for an SOT inductive wiring layer according to embodiments of this disclosure. Fig. 13A, Fig. 13B, Fig. 13C, Fig. 13D, Fig. 13E and Fig. 13F show a sequential manufacturing operation for a selector material layer according to this disclosure. Fig. 14 is a flowchart showing a sequential manufacturing operation of an SOT-MRAM device. DETAILED DESCRIPTION

[0004] It should be understood that the following disclosure provides many different embodiments or examples for implementing various functions of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the device. Furthermore, the formation of a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features need not be in direct contact.Various features may be arbitrarily labeled at different scales for simplicity and clarity. In the accompanying drawings, some layers / features may have been omitted for simplicity.

[0005] Furthermore, spatially relative terms such as "beneath," "underneath," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly. Furthermore, the term "made of" can mean either "comprising" or "consisting of."Furthermore, in the following manufacturing process, one or more operations may be present in / between the described operations, and the order of the operations may be changed. In this disclosure, unless otherwise described, the term "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), rather than one element of A, one element of B, and one element of C. Materials, configurations, dimensions, methods, and / or operations described with respect to one embodiment may be employed in the other embodiments, and the detailed explanation thereof may be omitted.

[0006] Spin torque transfer magnetic random access memory (STT MRAM) is one of the next-generation technologies for CMOS integrated circuits (ICs). Due to its non-volatile nature, it offers memory compatibility with Si-CMOS technology, fast read and write speeds, high data resilience and retention, a relatively small bit cell size, and environmental robustness. One emerging high-value application for STT MRAM is a low-level cache for a central processing unit (CPU) or microcontroller (MCU), which offers the attractive advantage of a system speed boost and faster power-up due to its non-volatile nature. However, this application has strict memory speed requirements, and more specifically, the write speed, which is much slower than the read speed.The cache application for a CPU and / or an MCU still demands low power consumption, which is difficult for STT MRAM because it requires a Western current to change the magnetization state during the write operation. At the current state of STT MRAM technology, improvements in write speed via a film stack and write scheme optimization and write current reduction via stack optimization and critical dimension (CD) reduction can stall due to unavoidable performance trade-offs in power handling and retention. New concepts, such as high-frequency assisted write operation, have been proposed, but are not feasible. A significant gap exists between the best reported STT MRAM write speed and power and those required by cache applications, which can lead to a showstopper.

[0007] An STT-MRAM cell generally comprises a magnetic tunnel junction (MTJ) film stack with a free magnetic layer, a reference or pinned magnetic layer, and a tunnel barrier layer made of a non-magnetic material such as MgO. The magnetization of the magnetic layers can be either in-plane or perpendicular to the plane. The free layer is the magnetic layer that has two energetically equivalent magnetic states, with the magnetization in the free layer being parallel or antiparallel to the magnetization of the reference layer. By applying a current perpendicular to the MTJ film stack, the magnetic orientation (moment) of the free magnetic layer can be changed, thereby writing data to the STT-MRAM cell.

[0008] In contrast, spin orbital transfer (or spin orbital torque) (SOT) magnetic switching is an emerging write concept that can potentially provide an order of magnitude improvement in write current and speed. SOT is considered a solution for high-speed, low-power cache applications.

[0009] In an SOT-MRAM, the magnetic moment of the free magnetic layer is switched using the spin orbit interaction effect caused by a current flowing parallel to the MTJ film stack. The magnetic moment of the free magnetic layer is switched using only the spin orbit interaction effect, or the magnetic moment of the free magnetic layer is switched using a combination of effects. An SOT device structure is a three-terminal device and generally requires two switching transistors (a 2T1R structure (two transistors, one resistor)). This results in a low cell density for an SOT-MRAM.

[0010] In this disclosure, a 1T1S1R (one transistor, one selector, and one resistor) SOT-MRAM design is proposed that can reduce a device footprint (cell size), reduce magnetic resistance, and increase a cell density.

[0011] Fig. 1 is a schematic view of a SOT MRAM cell according to an embodiment of this disclosure.

[0012] The SOT MRAM device includes an SOT inductor layer 15 as a spin orbit interaction active layer formed over an MTJ film stack 100. The MTJ film stack 100 includes a first magnetic layer 20, which is a free magnetic layer or a data storage layer, disposed beneath the SOT inductor layer 15, a non-magnetic spacer layer 30 disposed beneath the first magnetic layer 20, and a second magnetic layer 40, as a reference layer, disposed beneath the non-magnetic spacer layer 30. In some embodiments, an interface layer 50 is disclosed as a keeper layer between the SOT inductor layer 15 and the first magnetic layer 20. Further, the MTJ film stack 100 includes a third magnetic layer 60 as a hard bias layer disposed beneath the second magnetic layer 40.In some embodiments, a bottom electrode layer 80 is disposed beneath the MTJ film stack 100. In some embodiments, a seed layer 70 is formed on the bottom electrode layer 80. In some embodiments, an antiferromagnetic layer, such as a Ru layer, is disposed between the second magnetic layer 40 and the third magnetic layer 60. Furthermore, in some embodiments, the SOT inductor wire layer 15 includes an upper conductive layer 5, such as a top electrode, disposed on a main SOT inductor wire layer 10. In this disclosure, the bottom electrode 80 (and the seed layer 70) are not part of the MTJ film stack 100. However, it is possible to consider the bottom electrode 80 and / or the seed layer as a portion of the MTJ film stack 100.

[0013] The magnetic moment of the free layer 20 (first magnetic layer) is switched using the spin orbit interaction effect. In some embodiments, the magnetic moment of the first magnetic layer 20 is switched using only the spin orbit interaction effect. In other embodiments, the magnetic moment of the first magnetic layer 20 is formed using a combination of effects. For example, the magnetic moment of the first magnetic layer 20 is formed using a spin transfer torque as the primary effect, which may be assisted by a torque assisted by the spin orbit interaction. In other embodiments, the primary switching mechanism is induced by the spin orbit interaction. In such embodiments, another effect, including, but not limited to, spin transfer torque, may assist in switching.

[0014] The main SOT induction wire layer 10 is a spin-orbit active layer that exhibits strong spin-orbit interaction and can assist in switching the magnetic moment of the first magnetic layer 20. The main SOT induction wire layer 10 is used to generate a spin-orbit magnetic field H. More specifically, a current driven in-plane through the main SOT induction wire layer 10 and the associated spin-orbit interaction can lead to the spin-orbit magnetic field H. This spin-orbit magnetic field H corresponds to the spin-orbit torque T upon magnetization, where T = -γ[M×H], in the first magnetic layer 20. The torque and the magnetic field are thus interchangeably referred to as the spin-orbit field and the spin-orbit torque. This reflects the fact that the spin-orbit interaction is the origin of the spin-orbit torque and the spin-orbit field.The spin orbit torque occurs for a current driven in-plane in the main SOT inductor wire layer 10 and a spin orbit interaction. In contrast, the spin transfer torque is caused by a perpendicular-to-the-plane current flowing through the first magnetic layer 20, the non-magnetic spacer layer 30, and the second magnetic layer 40 (reference layer), and the spin-polarized charge carrier injected into the first magnetic layer 20. The spin orbit torque T can quickly deflect the magnetic moment of the first magnetic layer 20 from its equilibrium state parallel to the easy axis. The spin orbit torque T can tilt the magnetization of the first magnetic layer 20 significantly faster than the conventional maximum amplitude STT torque. In some embodiments, switching can be completed using the spin orbit torque.In other embodiments, a different mechanism, such as spin transfer, may be used to complete the switching. The generated spin orbit field / spin orbit torque can thus be used to switch the magnetic moment of the first magnetic layer 20.

[0015] In some embodiments, the interaction of the main SOT induction wire layer 10 includes the spin Hall effect. For the spin Hall effect, a current Je is driven in the plane of the main SOT induction wire layer 10 (i.e., current-in-plane, substantially in the xy plane in Fig. 1). In other words, the current Je is driven perpendicular to the stacked direction of the film comprising the main SOT induction wire layer 10 and the first magnetic layer 20 (i.e., perpendicular to the normal of the surface, the z-direction in Fig. 1). Charge carriers with spins of a specific orientation perpendicular to the current direction and the surface normal (z-direction) accumulate on the surfaces of the SOT induction wire layer 10. A large portion of these spin-polarized carriers diffuse into the first magnetic layer 20 (free layer). The diffusion leads to the torque T upon magnetization of the first magnetic layer 20. Since the torque upon magnetization corresponds to the effective magnetic field upon magnetization, as explained above, the spin accumulation accordingly leads to the field H at the first magnetic layer 20. The spin orbit field for the spin Hall effect is the cross product of the spin orbit polarization and the magnetic moment of the first magnetic layer 20. Thus, the magnitude of the torque is proportional to the in-plane current density Je and the spin polarization of the carriers. The spin Hall effect can be used to switch the magnetically stacked layer of Fig. 1, where the polarization induced by the spin Hall effect runs parallel to the simple axis of the first magnetic layer 20. To obtain the spin orbit torque T, the current pulse is driven in-plane through the SOT induction wire layer 10. The resulting spin orbit torque T counteracts the damping torque, resulting in switching of the magnetization of the first magnetic layer 20 in a manner analogous to conventional STT switching.

[0016] As stated above, the main SOT induction wire layer 10 is a spin orbit-active layer that triggers a strong spin orbit interaction with the first magnetic layer 20 (free layer). In some embodiments, the main SOT induction wire layer 10 comprises one or more heavy metals or materials doped with heavy metals. In certain embodiments, Pt, α-W, β-W, Mo, Ru, and / or β-Ta are used as the SOT induction wire layer 10. A thickness of the main SOT induction wire layer 10 is in a range of approximately 2 nm to 20 nm in some embodiments and in a range of approximately 5 nm to 15 nm in other embodiments. In some embodiments, an antiferromagnetic layer, for example, made of IrMn, is arranged between the main SOT induction wire layer 10 and the upper conductive layer 5. In other embodiments, instead of the heavy metal layer, the antiferromagnetic layer (e.g.IrMn) is used as the SOT induction wire layer 10.

[0017] The first magnetic layer 20, as a data storage layer, is a free layer with a switchable magnetic moment. In some embodiments, the first magnetic layer 20 is a cobalt iron boron (CoFeB) layer, a cobalt / palladium (CoPd) layer, and / or a cobalt iron (CoFe) layer with a thickness in a range of approximately 0.6 nm to approximately 1.2 nm in some embodiments. In certain embodiments, the first magnetic layer 20 is made of Fe x Co y B 1-x-y, where 0.50 : 5 x ≤ 0.70 and 0.10 ≤ y ≤ 0.30. In other embodiments, 0.55 ≤ x ≤ 0.65 and 0.15 ≤ y ≤ 0.25. In some embodiments, the free layer 20 (a memory layer) is either perpendicular magnetic anisotropic (PMA) or parallel magnetic anisotropic (IMA). The spin polarization can be controlled by changing the thickness of the free layer 20. In some embodiments, where the thickness of a free layer, e.g., of CoFeB, is less than about 1.3 nm, the free layer 20 is PMA, and when the thickness is greater than about 1.3 nm, the free layer 20 is IMA.

[0018] The non-magnetic spacer layer 30 is made of a dielectric material and acts as a tunnel barrier. In some embodiments, a non-magnetic spacer layer 30 comprises a crystalline or amorphous magnesium oxide (MgO) layer. In other embodiments, the non-magnetic spacer layer 30 is made of aluminum oxide or a conductive material such as Cu. In some embodiments, the non-magnetic spacer layer 30 has a thickness in a range of about 0.3 nm to about 3 nm, and in other embodiments, the thickness of the non-magnetic layer 30 is in a range of about 0.5 nm to about 1.0 nm. In this disclosure, an "element layer" or a "compound layer" generally means that the content of the element or compound is more than 99%.

[0019] The second magnetic layer 40 is a reference layer whose magnetic moment does not change. In some embodiments, the second magnetic layer 40 is made of the same material as the first magnetic layer 20, as set forth above. In some embodiments, the second magnetic layer 40 comprises one or more layers of magnetic materials. In some embodiments, the second magnetic layer 40 comprises a layer of cobalt (Co), iron (Fe), and boron (B), or a layer of Fe and B. In some embodiments, a thickness of the second magnetic layer 40 is in a range of about 0.2 nm to about 2.5 nm, and in a range of about 1.0 nm to about 1.5 nm, in other embodiments.

[0020] The third magnetic layer 60 is a hard bias layer whose magnetic moment does not change. In some embodiments, the third magnetic layer 60 comprises a multilayer structure of cobalt (Co) and platinum (Pt). In some embodiments, a thickness of the third magnetic layer 60 is in the range of about 0.2 nm to about 2.0 nm, and in other embodiments, it is in the range of about 0.3 nm to about 1.0 nm.

[0021] In some embodiments, the seed layer 70 comprises Ta. In some embodiments, the bottom electrode layer 80 comprises Ti, TiN, Ta, and / or TaN. In some embodiments, the CoHf buffer layer is disposed between the third magnetic layer 60 and the bottom electrode layer 80.

[0022] The upper conductive layer 5 is an electrode comprising one or more layers of Ta, TiN, TaN, Ru, Au and Al.

[0023] In some embodiments, the interface layer 50 comprises at least one of an MgO layer and a Co layer. The interface layer 50 can minimize the magnetic interference between the first magnetic layer 20 and the SOT inductor wire layer 10 while maintaining the magnetic coupling therebetween.

[0024] Fig. Figure 2 shows a schematic view of a SOT MRAM cell according to an embodiment of this disclosure. Materials, configurations, dimensions, processes, and / or operations related to Fig. 1 can be used in the following embodiments, and their detailed explanation may be omitted.

[0025] In some embodiments, the bottom electrode layer 80 is coupled to a switching device (e.g., a field-effect transistor (FET)) 110. In some embodiments, the bottom electrode 80 is coupled to a drain (or source) of the FET 110 through one or more conductive structures, such as a via, a wiring, and / or a pad, and a gate of the FET is coupled to a first word line (WL) 120. A source (or drain) of the FET 110 is coupled to a bit line (e.g., read bit line RBL) 130 through one or more conductive structures, such as a via, a wiring, and / or a pad.

[0026] In some embodiments, the SOT inductor wire layer 15 is disposed above the MTJ film stack along the vertical direction (film stacking direction) (Z-direction). One end of the SOT inductor wire 15 is coupled to the bottom of a selector material layer 140 through one or more conductive structures, such as a via, a wiring, and / or a pad. The other end of the SOT inductor wire 15 is coupled to a source line (SL) 160 through one or more conductive structures, such as a via, a wiring, and / or a pad. The source line 160 is coupled to a current source circuit 165 in some embodiments. The top of the selector material layer 140 is coupled to a second word line 150 (e.g., write word line) through one or more conductive structures, such as a via, a wiring, and / or a pad.

[0027] Selector material layer 140 is a switching device used to reduce or prevent leakage current from an operating memory cell or other memory cells flowing along the resistive network. In some embodiments, selector material 140 is an ovonic boundary switching (OTS) material, which is an amorphous material.

[0028] In some embodiments, the selector material layer 140 comprises one or more elements selected from the group consisting of GeSe doped with one or more elements selected from the group consisting of N, P, S, Si, and Te; AsGeSe doped with one or more elements selected from the group consisting of N, P, S, Si, and Te; and AsGeSeSi doped with one or more elements selected from the group consisting of N, P, S, Si, and Te. In certain embodiments, the selector material layer 140 is a chalcogenide or a solid electrolyte material containing one or more of Ge, Sb, S, and Te. In other embodiments, the selector material layer 140 is made of a material comprising SiO x , TiO x , AlO x , WHERE x , Ti x N y O z , HfO x , TaO x , NbO xor the like or suitable combinations thereof, where x, y, and z are non-stoichiometric values. In some embodiments, the selector material layer 140 comprises an oxygen-deficient transition metal oxide. In certain embodiments, the selector material layer 140 is made of a material comprising HfO x where 0 < x < 2. In some embodiments, the thickness of the selector material layer 140 is in the range of about 2 nm to about 20 nm, and in other embodiments, it is in the range of about 5 nm to about 15 nm.

[0029] Fig. 3 is a schematic cross-sectional view of an SOT-MRAM device according to an embodiment of this disclosure. Materials, configurations, dimensions, processes, and / or operations related to Fig. 1 and Fig. 2 can be used in the following embodiments, and their detailed explanation may be omitted.

[0030] In some embodiments, the SOT-MRAM device includes a layered structure with a multi-wiring layer structure. In some embodiments, the multi-wiring layer structure includes "Mx" (x=0, 1, 2, 3, ...) metal wiring layers located at respective stages disposed above a substrate, and "Vy" (y=0, 1, 2, 3, ...) vias (contacts) connecting the My metal wiring layer to the My+1 metal wiring layer. In some embodiments, the even-numbered metal wiring layers extend in one direction (e.g., X) and the odd-numbered metal wiring layers extend in another direction (e.g., Y) that crosses the one direction. In some embodiments, spacings for metal wirings in M3 and M4 are the same and spacings for the metal wirings in M5 or higher are the same and larger than the spacings for the metal wirings in M3 and M4.The adjacent metal wiring layers are separated by one or more interlayer dielectric (ILD) layers, and the vias are disposed within the ILD layers. In some embodiments, the metal wiring and vias are made of one or more of Al, Cu, a Cu alloy, W, Ti, TiN, Ta, TaN, or suitable conductive materials. In some embodiments, the ILD layers are made of one or more dielectrics, such as silicon oxide, SiOC, SiOCN, SiCN, or any other suitable material.

[0031] In some embodiments, bit line 130 is located at an M1 metal interconnect layer, which is the lowest metal interconnect layer above FETs 110. In some embodiments, bottom electrode layer 80 and / or MTJ film stack 100 are located at an M2 metal interconnect layer, which is located above bit line 130. In some embodiments, SOT inductor interconnect 15 is located at an M3 metal interconnect layer. In some embodiments, selector material layer 140 is located at an M3 or M4 metal interconnect layer. In some embodiments, source line 160 is located at the same metal interconnect layer as selector material layer 140. In other embodiments, source line 160 is located at a deeper metal interconnect layer than selector material layer 140.In some embodiments, the second word line (write word line (WWL)) 150 is located above the source line 160 and the selector material layer 140 and at the M4, M5, or M6 metal interconnect layers. In other embodiments, the source line 160 is located between the selector material layer 140 and the second word line 150.

[0032] In some embodiments, the FET 110 is a planar FET, a fin FET, or a gate-all-around FET. As in Fig. 3, the bottom electrode 80 is coupled to a drain of a FET 110, and a source of the FET 110 is coupled to the bit line 130. In some embodiments, the source is shared by two adjacent FETs 110, as shown in Fig. 3. In some embodiments, a pair of FETs 110 sharing the source is separated from another pair of FETs sharing a source by a dummy gate structure 122.

[0033] Fig. Figure 4 is a three-dimensional schematic view of a SOT-MRAM device according to an embodiment of this disclosure. Materials, configurations, dimensions, processes, and / or operations related to Fig. 1 to 4 can be used in the following embodiments, and their detailed explanation may be omitted.

[0034] In some embodiments, a first word line 120 (a gate of an FET) extends in the X-direction, and a bit line 130 extends in the Y-direction. The bit line 130 is located above the first word line 120 and is coupled to the source of the FET through a via 173 made of a conductive material. The bottom electrode 80, in some embodiments, is coupled to the drain of the FET through a via 171, a conductive pad 180, and a via 172. In some embodiments, the conductive pad 180 is on the same plane as the bit line 130 and is made of the same material. In some embodiments, the via 171 and the via 173 are made of the same material.

[0035] As in Fig. 4, the MTJ film stack 100 is disposed over the bottom electrode 80, and the SOT inductor wiring 15 is disposed over the MTJ film stack 100. One end of the SOT inductor wiring 15 is coupled to the bottom of the selector material layer 140 by a via 174 in some embodiments, and the other end of the SOT inductor wiring 15 is coupled to the source line 160 by a via 176. In some embodiments, the via 174 and the via 176 are made of the same material. In some embodiments, the height of the via 174 is the same as the height of the via 176. In other embodiments, the height of the via 174 is less than or greater than the height of the via 176.In some embodiments, the selector material layer 160 is disposed over a bottom electrode (not shown) formed on the via 174. In such a case, the bottom electrode 160 is made of the same material as the source line 160 in some embodiments. In some embodiments, the source line 160 extends in the Y direction.

[0036] Furthermore, as in Fig. 4, the second wordline 150 is arranged above the selector material layer 140 and the source line 160. In some embodiments, the second wordline extends in the X-direction. The second wordline 150 is coupled to the top surface of the selector material layer 140 with a via 175. In some embodiments, a top electrode (not shown) is formed on top of the selector material layer 160, and the via 175 is connected to the top electrode. In this embodiment, the SOT inductor wiring 15 extends in the Y-direction, and the vias 174 and 176 are arranged such that the SOT current flows along the Y-direction or across the SOT inductor wiring 15.

[0037] Fig. Figure 5 is a three-dimensional schematic view of an SOT-MRAM device according to another embodiment of this disclosure. The configuration of the SOT-MRAM shown in Fig. 5 is substantially the same as the configuration of the SOT MRAM shown in Fig. 4. In this embodiment, the SOT inductor wiring 15 extends in the X direction, and the vias 174 and 176 are arranged so that the SOT current flows along the X direction. The source line 160 extends in the Y direction and is connected to the SOT inductor wiring 15 through the via 176.

[0038] Fig. 6 is a circuit diagram of a SOT-MRAM device according to an embodiment of this disclosure. Materials, configurations, dimensions, processes, and / or operations related to Fig. 1 to 5 can be used in the following embodiments, and their detailed explanation may be omitted.

[0039] In some embodiments, bit lines, such as read bit lines RBL, and source lines SL, both extend in a row direction, and the first word line WL and the second word line (write word line) WWL extend in a column direction. SOT MRAM cells are arranged at locations defined, in some embodiments, by a read bit line RBL, a write word line WWL, a word line WL, and a source line SL. The number of memory cells coupled to the same word lines and / or the same bit lines is not limited to two or three and may be more than three, e.g., 4, 8, 16, 32, 64, 128, 256, 512, or 1024 or more.The word lines WL are coupled to a word driver circuit (row decoder), the source lines SL are coupled to a current source circuit, the read bit lines RBL are coupled to a read driver circuit (read circuit or column decoder), and the write word lines WWL are coupled to a write driver circuit (write circuit or row decoder). One end of the solid-state transistor (SOT) inductance wiring 15 is coupled to a corresponding source line SL, and the other end of the SOT inductance wiring SOT is coupled to a corresponding write word line WWL through a selector. One end of the MTJ film stack MTJ is coupled to a corresponding read bit line through an FET, whose gate is coupled to a corresponding word line.

[0040] Fig. 7 is a circuit diagram of an SOT-MRAM device according to another embodiment of this disclosure. Materials, configurations, dimensions, processes, and / or operations related to Fig. 1 to 6 can be used in the following embodiments, and their detailed explanation may be omitted.

[0041] In this embodiment, adjacent MRAM cells along the column direction are coupled to the same read bit line RBL and to two different word lines WL. Compared with the configuration of Fig. 6 the circuit can be Fig. 7 reduce the cell size in the column direction.

[0042] Fig. 8 and Fig. 9 illustrate operations of a SOT MRAM cell according to an embodiment of this disclosure.

[0043] During a write operation, a write current flows through the SOT induction wiring SOT. When a first data type (e.g., "0") is written to the MTJ film stack 100, the word line WL and the write word line WWL are set to a first potential (e.g., ground or 0 V), and the source line SL is set to a write voltage Vw that is higher than a threshold voltage of the selector material layer 140. With this write voltage, the selector material layer 140 is turned on to allow a current to flow from the source line SL to the write word line WWL through the SOT induction wiring SOT and the selector material layer 140. Since the FET 110 is off, no current flows through the MTJ film stack 100.

[0044] When writing a second data type (e.g., "1") to the MTJ film stack 100, the word line WL is set to a second potential (e.g., Vdd) higher than the first potential, the source line SL is set to the first potential (e.g., ground or Vss), and the write word line WWL is set to the high voltage Vw. With this high voltage, the selector material layer 140 is turned on to allow a current to flow from the write word line WWL to the source line SL through the SOT inductor wiring SOT and the selector material layer 140. In other words, the current flow directions in the SOT inductor wiring SOT are opposite for writing the first-type data and the second-type data. Since the FET 110 is off, no current flows through the MTJ film stack 100. During write operations, the read bit line RBL floats in some embodiments. The operation table from Fig. 9 can also be inverted in some embodiments according to the polarity of the spin Hall angle. Specifically, the spin Hall angle can be either positive or negative, and the write operations are opposite.

[0045] When reading data from the MTJ film stack 100, the word line WL is set to the second potential, the source line SL is set to the first potential, and the read bit line RBL is set to the read voltage Vread. The amplitude of Vread is approximately 1 / 2 to approximately 1 / 50 of Vw in some embodiments. In other embodiments, the source line SL is set to the second potential. As the FET 110 turns on, the read current flows from the source line SL to the read bit line RBL through the SOT induction wiring SOT and the MTJ film stack 100. In such a case, Vread is less than the source line voltage (e.g., Vread is negative). In other embodiments, the read current flows from the MTJ film stack 100 to the SOT induction wiring 15, in other words, from the read bit line RBL to the source line SL, so that the electrons flow from the free layer to the reference layer.The MTJ film stack 100 is more robust against read disturbances when electrons flow from the free layer to the reference layer. In such a case, Vread is higher than the source line voltage (e.g., Vread is positive). During read operations, the write word line WWL floats, and the selector material layer is not turned on. In some embodiments, substantially no leakage current flows through the selector material layer 140 during the read operation. The leakage current is below approximately 10 pA per cell in some embodiments.

[0046] In some embodiments, in the read operation, the source line SL connected to the target cell is set to Vdd, and the source lines connected to the other cell are set to Vdd / 2. The word line connected to the target cell is set to 0 V, and the word lines connected to the other cells are set to Vdd / 2. With this configuration, the leakage current can be further reduced.

[0047] Fig. 10A is a cross-sectional view of a SOT MRAM cell according to an embodiment of this disclosure.

[0048] In some embodiments, the upper conductive layer 5 has a recess (a thin portion) above the MTJ film stack 100, where a thickness of the upper conductive layer 5 is less than the remaining portion of the upper conductive layer 5. This structure allows an increase in the current flowing through the main SOT inductor wire layer 10 to trigger a sufficient SOT effect while allowing low resistance between adjacent cells. In some embodiments, a thickness of the upper conductive layer 5 is in a range of about 2 nm to 20 nm in some embodiments and in a range of about 5 nm to 15 nm in other embodiments, and the thickness of the thin portion of the upper conductive layer 5 is about 40% to about 80% of the thickness of the upper conductive layer 5 at a portion other than the thin portion.

[0049] Fig. 10B is a plan view of an SOT MRAM cell according to an embodiment of this disclosure. In other embodiments, a narrow portion where the width of the upper conductive layer 5 above the MTJ film is smaller than the remaining portion of the upper conductive layer 5 is provided adjacent to or instead of the recess. The width of the narrow portion of the upper conductive layer 5 is approximately 50% to approximately 90% of the width of the upper conductive layer 5 in areas other than the narrow portion.

[0050] Fig. 11A to 11K show a sequential manufacturing operation for a SOT-MRAM cell according to this disclosure. It is understood that in the sequential manufacturing process, one or more further operations may be performed before, during, and after the steps described in Fig. 11A to 11K, and that some of the operations described below may be replaced or eliminated for further embodiments of the method. The order of operations / processes may be interchangeable. Materials, configurations, dimensions, processes, and / or operations described with respect to Fig. 1 to 10B can be used in the following embodiments, and their detailed explanation may be omitted.

[0051] As in Fig. 11A, a hard mask structure 220 is formed over an n-th wiring layer comprising a metal wiring 210 embedded in an interlayer dielectric (ILD) layer 200. In some embodiments, n is 3, 4, 5, or 6. In some embodiments, the metal wiring 210 is made of Cu or a Cu alloy. In some embodiments, the hard mask layer 220 includes a first layer 222, a second layer 224, and a third layer 226. In some embodiments, the first through third layers are made of one of silicon oxide, silicon nitride, SiC, SiCN, alumina, zirconium oxide, or another suitable dielectric. In certain embodiments, the first and third layers 222 and 226 are made of SiC, and the second layer 224 is made of silicon oxide.

[0052] Then, the hard mask layer 220 is patterned to form an opening to at least partially expose the upper surface of the metal wiring 210 using one or more lithography and etching operations. A liner layer 230 is formed in the opening, and a conductive layer 240 is formed over the liner layer 230, as shown in Fig. 11B. In some embodiments, the liner layer 230 is made of Ti, Ta, or TaN, and the conductive layer 240 is made of TiN. After the conductive layer 240 is formed, a planarization operation, such as chemical mechanical polishing (CMP), is performed to form an electrode 240, as shown in Fig. 11C. The electrode 240 corresponds to the via 172 of Fig. 4 and Fig. 5 in some embodiments.

[0053] Subsequently, layers for the MTJ film stack 100 are formed over the electrode 240 as shown in Fig. 11D. In Fig. In FIGS. 11D to 11K, the electrode 240, the metal wiring 210, and the ILD layer 200 are omitted. The layer for the MTJ film stack includes layers for a bottom electrode BE, a seed or buffer layer, a hard bias layer, a reference layer, a non-magnetic spacer layer 30 (e.g., an MgO layer), a free layer, and an interface layer. In some embodiments, a CMP stop layer and a hard mask layer HM are formed over the interface layer.Each of the layers of the MTJ film stack can be formed by suitable film formation processes, which may include physical vapor deposition (PVD), including sputtering; molecular beam epitaxy (MBE); pulsed laser deposition (PLD); atomic layer deposition (ALD); electron beam (e-beam) epitaxy; chemical vapor deposition (CVD); or derivative CVD processes, which may further include low-pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD); electroplating, or combinations thereof.

[0054] Then, the stacked layers for the MTJ film are patterned into an MTJ film stack using one or more lithography and etching operations as shown in Fig. 11E. In some embodiments, as shown in Fig. 11E, the cross-sectional view of the MTJ film stack 100 has a tapered (mesa) shape. Then, one or more dielectric layers 205, such as silicon oxide, SiOC, SiOCN, SiCN, are formed to completely cover the MTJ film stack 100, as shown in Fig. 11F. A planarization operation such as CMP is performed to expose the top layer of the MTJ film stack, as shown in Fig. 11G. Then, a conductive layer 250 for the main SOT induction wire layer 10 and conductive layers 260 for the upper conductive layer 5 (see Fig. 1, Fig. 10A and Fig. 10B) as in Fig. 11H. In some embodiments, the conductive layers 260 include a first conductive layer 262, a second conductive layer 264 as an etch stop layer, and a third conductive layer 266. The second conductive layer 264 is made of a different material than the first and third conductive layers. In some embodiments, no first conductive layer is formed.

[0055] Furthermore, as in Fig. 11I, a photoresist pattern 270 is formed over the conductive layers 260 and the conductive layers 260 are patterned using one or more lithography and etching operations, as shown in Fig. 11J. Then, the photoresist pattern 270 is removed as shown in Fig. 11K. In some embodiments, the etching stops at the second conductive layer 264. In other embodiments, a further etch is performed such that the first conductive layer is partially etched. In some embodiments, before or after the patterning operations, Fig. 11I to 11K, the conductive layers 250 and 260 are patterned to form a line-shaped structure, and the thickness of the conductive layers 260 is determined by the operations of Fig. 11I to 11K reduced.

[0056] Fig. 12A to 12C show various structures for the SOT induction wire layer. In some embodiments, the main SOT induction wire layer 10 is a single layer of heavy metal, such as Pt, W, Ta, and Mo, as shown in Fig. 12A. In other embodiments, the SOT inductor wire layer 10' is a single layer of antiferromagnetic material, such as IrMn, as shown in Fig. 12B. In other embodiments, the SOT induction wire layer 10" is a bi-layer of heavy metal layer 11 and an antiferromagnetic material layer 12, wherein the heavy metal layer 11 is in contact with the MTJ film stack, as shown in Fig. 12C is shown.

[0057] Fig. 13A to 13F show a sequential manufacturing operation for a SOT-MRAM according to this disclosure. It is understood that in the sequential manufacturing process, one or more further operations may be performed before, during, and after the steps described in Fig. 13A to 13F, and that some of the operations described below may be replaced or eliminated for further embodiments of the method. The order of operations / processes may be interchangeable. Materials, configurations, dimensions, processes, and / or operations described with respect to Fig. 1 to 12B can be used in the following embodiments, and their detailed explanation may be omitted.

[0058] As in Fig. 13A, a first via 310 is formed in a first ILD layer 300. In some embodiments, the first via 310 corresponds to the via 174 of Fig. 4 and Fig. 5. Then, a second ILD layer 320 is formed over the via 310 and the first ILD layer 300, as shown in Fig. 13B. Furthermore, as shown in Fig. 13C, a hole or opening 325 is formed using one or more lithography and etching operations. Next, as shown in Fig. 13D, the opening 325 is filled with a selector material. In some embodiments, the selector material is formed by CVD, PVD, and / or ALD in the opening 325 and over the upper surface of the second ILD layer 320, and then a CMP operation is performed to remove the excess layer formed on the upper surface of the second ILD layer 320. The selector material layer 330 corresponds to the selector material layer 140 of Fig. 4 and Fig. 5. Subsequently, a third ILD layer 340 is formed, as in Fig. 13E, and then a second via 350 is formed as shown in Fig. 13F. In some embodiments, the second via 350 corresponds to the via 175 of Fig. 4 and Fig. 5.

[0059] Fig. Figure 14 is a flow diagram illustrating a sequential manufacturing operation of a SOT-MRAM device. It should be understood that in the sequential manufacturing process, one or more additional operations may be provided before, during, and after the stages described in Fig. 14, and that some of the operations described below may be replaced or eliminated for further embodiments of the method. The order of operations / processes may be interchangeable. Materials, configurations, dimensions, processes and / or operations described with respect to Fig. 1 to 13F can be used in the following embodiments, and their detailed explanation may be omitted.

[0060] In S1410 from Fig. 14, transistors such as FETs are formed. The transistors include switching transistors for SOT MRAM cells and logic transistors for control and operational circuits. After one or more ILD layers are formed over the transistors, bitlines are formed in S1420. The bitlines are made of one or more conductive materials, such as Cu, W, Ni, Co, Ti, or another suitable material. In some embodiments, the bitlines are formed from local interconnects in direct contact with the source / drain regions of the transistors. After one or more ILD layers are formed over the bitlines, MTJ film stacks are formed in S1430, for example, by the operations described with reference to Fig. 11A to 11G. Furthermore, in S1440, SOT induction wirings are respectively formed by the operations over the MTJ film stacks, which are Fig. 11H to 11K. After one or more ILD layers are formed over the SOT induction interconnections, selector material layers are formed in S1450, for example, by the operations described with reference to Fig. 13A to 13F. Furthermore, the source lines are formed in S1460. In some embodiments, the source lines are formed after forming one or more ILD layers over the selector material layers. In other embodiments, the source lines are formed on the same level as the selector material layers. Subsequently, write word lines are formed in S1470 after forming one or more ILD layers over the selector material layers and the source lines.

[0061] In this disclosure, a selector material layer is used as a switching device coupled to the SOT induction wiring, while an FET is used as a switching device coupled to the bottom of the MTJ film stack 100. Compared with the structure in which a selector material layer is coupled to the bottom of the MTJ film stack and an FET is coupled to the SOT induction wiring, it is possible to suppress the degradation of a tunneling magnetic resistance effect on the MTJ film stack and suppress read disturbance problems.

[0062] It should be understood that not all advantages have necessarily been discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0063] According to one aspect of this disclosure, a magnetic memory device comprises a magnetic tunnel junction (MTJ) stack, a spin orbit torque (SOT) induction wiring disposed above the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal. In one or more of the preceding and following embodiments, the magnetic memory device further comprises a bottom electrode disposed below and coupled to the MTJ stack and coupled to a switching device.In one or more of the preceding and following embodiments, the MTJ stack comprises a first magnetic layer as a magnetic free layer, a non-magnetic spacer layer disposed beneath the first magnetic layer, and a second magnetic layer as a magnetic reference layer disposed beneath the spacer layer. The SOT inductor wiring is disposed above the first magnetic layer. In one or more of the preceding and following embodiments, the MTJ stack further comprises an interface layer disposed between the first magnetic layer and the SOT inductor wiring. In one or more of the preceding and following embodiments, the first magnetic layer is Fe. x Co y B 1-x-y, 0.50 ≤ x ≤ 0.70 and 0.10 ≤ y ≤ 0.30. In one or more of the preceding and subsequent embodiments, the second magnetic layer comprises at least one of a layer of Co, Fe and B, and a layer of Fe and B. In one or more of the preceding and subsequent embodiments, the MTJ stack further comprises a third magnetic layer below the second magnetic layer, wherein the third magnetic layer has a different composition than the second magnetic layer. In one or more of the preceding and subsequent embodiments, the SOT inductor wiring comprises one or more layers of W, Ta, Mo and IrMn. In one or more of the preceding and subsequent embodiments, the SOT inductor wiring comprises a lower layer of W, Ta or Mo and an upper layer of IrMn. In one or more of the preceding and subsequent embodiments, the selector layer comprises HfOx , where 0 < x< 2.

[0064] According to another aspect of this disclosure, a magnetic memory device comprises a first word line, a bit line, a second word line, a source line, and a memory cell. The memory cell includes a magnetic tunnel junction (MTJ) stack, a spin orbit torque (SOT) induction wiring coupled to one end of the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring and coupled to the source line, a third terminal coupled to another end of the MTJ stack, a selector layer coupled to the first terminal and coupled to the second word lines, and a switching transistor coupled to the third terminal and the bit line, wherein a gate of the switching transistor is coupled to the first word line.In one or more of the preceding and subsequent embodiments, the source line is coupled to a current source. In one or more of the preceding and subsequent embodiments, the SOT inductor wiring is disposed above the MTJ stack, the third terminal is disposed below the MTJ stack, and the switching transistor is disposed below the third terminal. In one or more of the preceding and subsequent embodiments, the bit line is located between the switching transistor and the third terminal along a vertical direction. In one or more of the preceding and subsequent embodiments, the selector layer is located between the SOT inductor wiring and the second word line along a vertical direction.In one or more of the preceding and subsequent embodiments, the source line is located along a vertical direction between the SOT inductor wiring and the second word line. In one or more of the preceding and subsequent embodiments, the source line is located between the selector layer and the second word line along the vertical direction.

[0065] According to another aspect of this disclosure, a magnetic memory comprises a first word line, a second word line, a bit line, a write word line, a first source line, a second source line, a first memory cell, and a second memory cell.Each of the first and second memory cells includes a magnetic tunnel junction (MTJ) stack, a spin orbit torque (SOT) induction wiring coupled to one end of the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, a third terminal coupled to another end of the MTJ stack, a selector layer coupled to the first terminal and coupled to the write word line, and a switching transistor having a drain coupled to the third terminal and a source coupled to the bit line.The second terminal of the first memory cell is coupled to the first source line, and the second terminal of the second memory cell is coupled to the second source line, and a gate of the first switching transistor is coupled to the first word line, and a gate of the second switching transistor is coupled to the second word line. In one or more of the preceding and subsequent embodiments, the SOT inductor wiring is disposed above the MTJ stack, the third terminal is disposed below the MTJ stack, and the switching transistor is disposed below the third terminal.In one or more of the preceding and following embodiments, the MTJ stack comprises a first magnetic layer as a magnetic free layer, a non-magnetic spacer layer disposed beneath the first magnetic layer, and a second magnetic layer as a magnetic reference layer disposed beneath the spacer layer. The SOT induction wiring is disposed above the first magnetic layer.

[0066] According to another aspect of this disclosure, in a method of operating the magnetic memory device as set forth above, a first type of data is written to the MTJ film stack by flowing a current from the source line to the second word line via the selector material layer while the switching transistor is turned off.

[0067] According to another aspect of this disclosure, in a method of operating the magnetic memory device as set forth above, a second type of data is written to the MTJ film stack by flowing a current from the second word line to the source line via the selector material layer while the switching transistor is turned off.

[0068] According to another aspect of this disclosure, in a method of operating the magnetic memory device as set forth above, data is read from the MTJ film stack by turning on the switching transistor so that a current flows from the source line to the read bit line while turning off the selector material layer.

[0069] According to one aspect of this disclosure, in a method of fabricating a magnetic memory, a switching transistor is formed over a substrate, a bit line is formed, an MTJ film stack is formed, an SOT inductor wiring is formed over the MTJ film stack, a selector material layer is formed over the SOT inductor wiring such that the selector material layer is coupled to one end of the SOT inductor wiring, a source line is formed such that the source line is coupled to another end of the SOT inductor wiring, and a second word line is formed over the selector material layer and the source line.In one or more of the preceding and following embodiments, the MTJ film stack comprises a first magnetic layer as a magnetic free layer, a spacer layer disposed beneath the first magnetic layer, and a second magnetic layer as a magnetic reference layer disposed beneath the spacer layer. In one or more of the preceding and following embodiments, the SOT induction wiring comprises a bottom layer comprising one or more layers of W, Ta, Mo, and IrMn, and an upper layer made of one or more of TiN, Ru, Ti, TaN, and Al, and a portion of the top layer located above the MTJ film stack is trimmed.

Claims

[1] Magnetic storage device comprising: a magnetic tunnel junction stack, MTJ stack (100); a spin orbit torque induction wiring, SOT induction wiring (15) disposed above the MTJ stack (100); a first terminal coupled to a first end of the SOT induction wiring (15); a second terminal coupled to a second end of the SOT induction wiring (15) and to a source line (160); a selector layer (140) coupled to the first terminal and coupled to a word line (150); and a lower electrode (80) disposed below and coupled to the MTJ stack (100) and coupled to a switching device (110), where the MTJ stack (100) comprises: - a first magnetic layer (20) as a magnetic free layer; - a non-magnetic spacer layer (30) disposed beneath the first magnetic layer (20); and - a second magnetic layer (40) as a magnetic reference layer arranged under the spacer layer (30), wherein the SOT induction wiring (15) is arranged above the first magnetic layer (20), wherein the MTJ stack (100) further comprises an interface layer (50) disposed between the first magnetic layer (20) and the SOT induction wiring (15), the interface layer (50) comprising an MgO layer and a Co layer. [2] A magnetic memory device according to claim 1, wherein the first magnetic layer (20) comprises Fe x Co y B 1-x-y where 0.50 ≤ x ≤ 0.70 and 0.10 ≤ y ≤ 0.

30. [3] A magnetic memory according to claim 2, wherein the second magnetic layer (40) comprises at least one of: a layer of Co, Fe and B; and a layer of Fe and B [4] Magnetic storage device according to one of the preceding claims 1 to 3, wherein the MTJ stack (100) further comprises a third magnetic layer below the second magnetic layer (40), wherein the third magnetic layer has a different composition than the second magnetic layer (40). [5] A magnetic memory device according to any one of the preceding claims, wherein the SOT induction wiring (15) comprises one or more layers of W, Ta, Mo and IrMn. [6] A magnetic memory device according to any one of the preceding claims, wherein the SOT induction wiring (15) has a lower layer made of W, Ta or Mo and an upper layer made of IrMn. [7] Magnetic memory device according to one of the preceding claims, wherein the selector layer (140) HfOx where 0 < x < 2. [8] Magnetic memory comprising: a first word line (120); a bit line (130); a second word line (150); a source line (160); and having a memory cell: - a magnetic tunnel junction stack, MTJ stack (100); - a spin orbit torque induction wiring, SOT induction wiring (15) coupled to one end of the MTJ stack (100); - a first terminal coupled to a first end of the SOT induction wiring (15); - a second terminal coupled to a second end of the SOT induction wiring (15) and to the source line (160); - a third terminal coupled to another end of the MTJ stack (100); - a selector layer (140) coupled to the first terminal and coupled to the second word line (150); and - a switching transistor (110) coupled to the third terminal and the bit line (130), wherein a gate of the switching transistor (110) is coupled to the first word line (120), where the MTJ stack (100) comprises: - a first magnetic layer (20) as a magnetic free layer; - a non-magnetic spacer layer (30) disposed beneath the first magnetic layer (20); and - a second magnetic layer (40) as a magnetic reference layer arranged under the spacer layer (30), wherein the SOT induction wiring (15) is arranged above the first magnetic layer (20), wherein the MTJ stack (100) further comprises an interface layer (50) disposed between the first magnetic layer (20) and the SOT induction wiring (15), the interface layer (50) comprising an MgO layer and a Co layer. [9] The magnetic memory of claim 8, wherein the source line (160) is coupled to a current source. [10] Magnetic memory according to claim 8 or 9, wherein the SOT induction wiring (15) is arranged above the MTJ stack (100), wherein the third terminal is arranged below the MTJ stack (100), wherein the switching transistor (110) is arranged below the third terminal. [11] The magnetic memory of claim 10, wherein the bit line (130) is located along a vertical direction between the switching transistor (110) and the third terminal. [12] A magnetic memory according to claim 10 or 11, wherein the selector layer (140) is located along a vertical direction between the SOT induction wiring (15) and the second word line (150). [13] A magnetic memory according to any one of claims 10 to 12, wherein the source line (160) is located along a vertical direction between the SOT induction wiring (15) and the second word line (150). [14] The magnetic memory of claim 13, wherein the source line (160) is located along a vertical direction between the selector layer (140) and the second word line (150). [15] A method of manufacturing a magnetic memory, comprising: Forming a switching transistor (110) over a substrate; 8Forming a bit line (130) over the substrate; Forming an MTJ film stack (100) over the substrate; Forming an SOT induction wiring (15) over the MTJ film stack (100); Forming a selector material layer (140) over the SOT induction wiring (15) such that the selector material layer (140) is coupled to one end of the SOT induction wiring (15); Forming a source line (160) such that the source line (160) is coupled to another end of the SOT induction wiring (15); and Forming a word line (150) over the selector material layer (140) and the source line (160) such that the selector material layer (140) is coupled to the word line (150), wherein the MTJ film stack (100) comprises: a first magnetic layer (20) as a magnetic free layer; a spacer layer (30) disposed beneath the first magnetic layer (20); and a second magnetic layer (40) as a magnetic reference layer arranged under the spacer layer (30), wherein the SOT induction wiring (15) is arranged above the first magnetic layer (20), wherein the MTJ stack (100) further comprises an interface layer (50) disposed between the first magnetic layer (20) and the SOT induction wiring (15), the interface layer (50) comprising an MgO layer and a Co layer. [16] Method of claim 15, wherein the SOT induction wiring (15) has a lower layer (10) comprising one or more layers of W, Ta, Mo and IrMn, and an upper layer (5) made of one or more of TiN, Ru, Ti, TaN and Al, the method further comprising cutting a portion of the upper layer (5) located above the MTJ film stack (100).

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