Three-dimensional semiconductor storage device

Abstract

Semiconductor storage device, comprising: horizontal structures (100a, 100b) arranged on a peripheral circuit structure (PS) and spaced apart from each other in a first direction (D1); Storage structures (MS) arranged on the horizontal structures (100a, 100b), wherein the storage structures (MS) comprise source structures (SC) and electrode structures (ST); a partitioning structure (DIT) arranged between electrode structures (ST) of adjacent memory structures (MS) spaced apart in the first direction (D1), wherein the partitioning structure (DIT) is configured to separate the source structures (SC) of adjacent memory structures (MS) from each other; and an etch stop structure (ES) that is arranged between the horizontal structures (100a, 100b) and is located on a level that is lower than a level of the source structures (SC), wherein the etch stop structure (ES) is connected to a lower section of the division structure (DIT) and wherein the storage structures (MS) also contain vertical structures (VS) that penetrate the electrode structures (ST), and wherein the vertical structures (VS) are jointly connected from one of the storage structures (MS) to one of the source structures (SC), and wherein the etch stop structure (ES) is formed from a non-metallic material which has etch selectivity with respect to a silicon oxide layer and a silicon nitride layer.

Description

TECHNICAL AREA

[0001] The inventive concepts discussed here relate to a three-dimensional semiconductor storage device and a method for its manufacture, and in particular to a highly integrated three-dimensional semiconductor storage device and a method for its manufacture. DISCUSSION OF THE STATE OF THE TECHNOLOGY

[0002] Consumer demand for electronic devices that offer superior performance at relatively low cost has driven the need for higher integration of semiconductor devices. Since integration in two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a unit memory cell, it is highly influenced by the state of fine-structure fabrication technology. However, increasing the feature size requires very expensive equipment, and there is a practical limit to the feature size achievable. Therefore, three-dimensional semiconductor memory devices with three-dimensionally arranged memory cells have recently been proposed.

[0003] US 2018 / 0366486A1 discloses a planar stack of material layers comprising a lower dielectric etch stop layer, a sacrificial semiconductor layer, and an upper dielectric etch stop layer, formed over a source semiconductor layer on a substrate. An alternating stack of insulating and spacer material layers is formed. The spacer material layers are formed as electrically conductive layers or subsequently replaced by them. An array of storage stack structures is formed. A source cavity is formed by removing the sacrificial semiconductor layer and portions of the storage films. Source band structures are formed by a selective semiconductor deposition process on the vertical semiconductor channels and the source semiconductor layer. A dielectric filler material layer fills any remaining volume of the source cavity.

[0004] US 2017 / 0092733A1 discloses that an alternating stack of insulating and sacrificial material layers can be formed over a substrate. Storage stack structures and a backside trench are formed by the alternating stack. Backside recesses are formed by removing the sacrificial material layers from the backside trench, selectively for the insulating layers. In each backside recess, a cobalt-semiconductor alloy section is formed by converting cobalt and a semiconductor material. Conductive material in the backside trench can be removed by etching to electrically insulate cobalt-containing alloy sections located in different backside recesses. Electrically conductive layers containing a respective cobalt-semiconductor alloy section can be used as word conductors of a three-dimensional storage device.

[0005] US 9,978,771 B2 discloses a manufacturing process for a semiconductor device. A manufacturing process for a semiconductor device comprises forming a preliminary source stack structure comprising a first source layer, a first protective layer, a sacrificial layer, a second protective layer, and a second source layer, which are stacked successively in the specified order and form channel layers extending through the second source layer and partially within the first source layer, and growing a first region of an interlayer source layer from each channel layer, the first region of the interlayer source layer surrounding each channel layer in a region between the first and second protective layers.

[0006] US 2018 / 0247951A1 discloses a semiconductor storage device comprising a semiconductor substrate, a first insulating film provided over the semiconductor substrate, a first conductive film provided over the first insulating film, a plurality of first electrode films provided over the first conductive film and stacked so as to be separated from one another, a semiconductor element extending in a stacking direction of the plurality of first electrode films, and a charge storage element provided between the semiconductor element and one of the plurality of first electrode films. The first conductive film comprises a main section arranged at least beneath the plurality of first electrode films and a fine conducting section extending from the main section toward an end-surface face of the semiconductor substrate.The width of the fine line section is less than the width of the main section.

[0007] US 2018 / 0366487A1 discloses a method for forming a three-dimensional storage device comprising forming at least one lower-level dielectric layer over a semiconductor substrate, forming a buried source conductor over the at least one lower-level dielectric layer and over the semiconductor substrate such that the buried source conductor is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source conductor such that the sacrificial material layers are subsequently replaced by electrically conductive layers, forming storage openings through the alternating stack by etching through the alternating stack after the buried source conductor is electrically connected to the semiconductor substrate, and forming storage stack structures in the storage openings.Each memory stack structure comprises a vertical semiconductor channel that is electrically connected to the buried source lead, and a memory film that laterally surrounds the vertical semiconductor channel.

[0008] US 2016 / 0225714A1 discloses a semiconductor device that may include a conductive cell gate pattern in a cell array region extending to a step region, a vertical cell structure in the cell array region extending through the conductive cell gate pattern, a cell gate contact structure on the conductive cell gate pattern in the step region, a cell gate contact region in the conductive cell gate pattern aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the conductive cell gate pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region below the first peripheral contact structure, and a second peripheral contact region below the second peripheral contact structure.The cell gate contact area may contain a first element, and the remainder of the conductive cell gate pattern may not substantially contain the first element.

[0009] US 2018 / 0 122 906 A1 discloses that the contact area between a source-strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial sockets of semiconductors can be formed in memory openings at the source level before a vertically alternating stack of insulating and sacrificial material layers is formed. Memory openings can include convex sections created by removing the semiconductor sacrificial sockets. Memory stack structures can be formed with a larger sidewall surface in the convex sections to provide a larger contact area with the source-strap structure.Alternatively, lower sections of the storage openings can be selectively extended to upper sections during or after the formation of the storage openings to provide convex sections and increase the contact area with the source strap structure. SUMMARY

[0010] An exemplary embodiment of the inventive concepts discussed here provides a three-dimensional semiconductor memory device with an increased integration density.

[0011] An exemplary embodiment of the inventive concepts discussed here provides a method for reducing process failure in a process for manufacturing a three-dimensional semiconductor storage device.

[0012] According to an exemplary embodiment of the inventive concepts discussed here, a semiconductor memory device comprises horizontal structures arranged on a peripheral circuit structure and spaced apart from one another in a first direction. The memory structures are arranged on the horizontal structures. The memory structures comprise source structures and electrode structures. A partitioning structure is arranged between electrode structures (ST) of adjacent memory structures spaced apart from one another in a first direction and is configured to separate the source structures of adjacent memory structures from each other. An etch stop structure is arranged between the horizontal structures at a lower level than a level of the source structures.The etch stop structure is connected to a lower section of the partition structure, and the storage structures also contain vertical structures that penetrate the electrode structures, and the vertical structures are connected by one of the storage structures together with one of the source structures, and the etch stop structure is formed from a non-metallic material that has an etch selectivity with respect to a silicon oxide layer and a silicon nitride layer.

[0013] According to an exemplary embodiment of the inventive concepts discussed here, a semiconductor memory device comprises horizontal structures arranged on a peripheral circuit structure and spaced apart from one another, with a partition region arranged between them in a first direction. The partition region includes a first insulating intrusion layer. The memory structures are arranged on the horizontal structures. The memory structures comprise source structures and electrode structures on the source structures. Vertical structures penetrate the electrode structures and are connected to the source structures. A partition structure is arranged in the partition region and is configured to separate the source structures of adjacent memory structures from one another.An etch stop structure is positioned between the horizontal structures and is located on a plane lower than any of the horizontal structures. The etch stop structure is connected to a lower section of the partition structure. Penetrating plugs are provided to connect the memory structures to the peripheral circuit structure. The source structures comprise primary conductive source structures located on top of the horizontal structures and secondary conductive source structures located between the primary conductive source structures and the horizontal structures. The primary conductive source structures extend to the partition region and are connected to the partition structure's sidewalls. The etch stop structure is formed from a non-metallic material exhibiting etch selectivity with respect to a silicon oxide layer and a silicon nitride layer.

[0014] According to an exemplary embodiment of the inventive concepts discussed here, a semiconductor memory device comprises horizontal structures arranged on a peripheral circuit structure and spaced apart from one another in a first direction. The memory structures are arranged on the horizontal structures. The memory structures comprise source structures and electrode structures on the source structures. A partition structure is arranged between the electrode structures of adjacent memory structures that are spaced apart from one another in a first direction. The partition structure is configured to separate the source structures of adjacent memory structures from one another. An etch stop structure is arranged between the horizontal structures and is connected to a lower section of the partition structure. Penetrating plugs connect the memory structures to the peripheral circuit structure.The etch stop structure is arranged on the same plane as a plane of the horizontal structures, and the storage structures also contain vertical structures that penetrate the electrode structures, and the vertical structures are connected by one of the storage structures together with one of the source structures, and the side walls of the source structures contact the side walls of the partition structure, and the etch stop structure is formed from a non-metallic material that has an etch selectivity with respect to a silicon oxide layer and a silicon nitride layer.

[0015] The invention is defined in the attached independent claims. Further developments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Exemplary embodiments are better understood by referring to the following brief description in conjunction with the accompanying drawings. The accompanying drawings represent non-limiting, exemplary embodiments as described in this text. Fig. Figure 1 is a top view illustrating a substrate on which three-dimensional semiconductor storage devices are integrated, according to an exemplary embodiment of the inventive concepts discussed here. Fig. Figure 2 is a perspective view illustrating a three-dimensional semiconductor device according to an exemplary embodiment of the inventive concepts discussed here. Fig. Figure 3 is a top view illustrating a three-dimensional semiconductor storage device according to an exemplary embodiment of the inventive concepts discussed here. Fig. 4A and Fig. Figure 4B are top views illustrating a cell array structure of a three-dimensional semiconductor storage device according to exemplary embodiments of the inventive concepts discussed here. Fig. Figure 5 is an enlarged top view of a region “Q” of Fig. 4A according to an exemplary embodiment of the inventive concepts discussed here. Fig. Figures 6 to 8 are cross-sectional views along lines I-I', II-II' and III-III' respectively. Fig. 5 according to exemplary embodiments of the inventive concepts discussed here. Fig. 9A is an enlarged cross-sectional view showing section “P” of Fig. Figure 8 illustrates an exemplary embodiment of the inventive concepts discussed here. Fig. 9B is an enlarged cross-sectional view showing section “R” of Fig. Figure 7 illustrates an exemplary embodiment of the inventive concepts discussed here. Fig. Figures 10 to 12 are top views illustrating cell array structures of a three-dimensional semiconductor storage device according to exemplary embodiments of the inventive concepts discussed here. Fig. 13 and Fig. Figure 14 shows cross-sectional views of a three-dimensional semiconductor storage device along lines II' and II-II' of Fig. 5 according to exemplary embodiments of the inventive concepts discussed here. Fig. 15, Fig. 18, Fig. 21 and Fig. Figure 24 are cross-sectional views illustrating a method for fabricating a three-dimensional semiconductor storage device along line II' of Fig. 5 according to exemplary embodiments of the inventive concepts discussed here. Fig. 16, Fig. 19, Fig. 22 and Fig. Figure 25 are cross-sectional views illustrating a method for fabricating a three-dimensional semiconductor storage device along line II-II' of Fig. 5 according to exemplary embodiments of the inventive concepts discussed here. Fig. 17, Fig. 20, Fig. 23 and Fig. Figure 26 shows cross-sectional views illustrating a method for fabricating a three-dimensional semiconductor storage device along line III-III' of Fig. 5 according to exemplary embodiments of the inventive concepts discussed here. Fig. Figure 27 is a cross-sectional view of a three-dimensional semiconductor memory device along line II-II' of Fig. 5 according to an exemplary embodiment of the inventive concepts discussed here.

[0017] It should be noted that these figures are intended to illustrate the general features of the processes, structure, and / or materials used in certain exemplary embodiments and to supplement the following written description. However, these drawings may not be to scale and may not accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values ​​or properties encompassed by exemplary embodiments of the inventive concepts discussed herein. For example, the relative thicknesses and positions of molecules, layers, regions, and / or structural elements may have been reduced or enlarged for clarity.The use of similar or identical reference numerals in the different drawings is intended to indicate the presence of a similar or identical element or feature. DETAILED DESCRIPTION OF THE INVENTION

[0018] Fig. Figure 1 is a top view illustrating a substrate on which three-dimensional semiconductor storage devices are integrated, according to an exemplary embodiment of the inventive concepts discussed here.

[0019] As in Fig. As shown in Figure 1, a semiconductor substrate 1 (for example, a wafer, etc.) can comprise chip regions 10 on which semiconductor chips are formed, and a scribing region 20 located between the chip regions 10. In an exemplary embodiment, the semiconductor substrate 1 can comprise several discrete chip regions arranged two-dimensionally in two different directions (for example, a first direction D1 and a second direction D2). Each of the chip regions 10 can be surrounded by the scribing region 20. In other words, the scribing region 20 can be located between each adjacent pair of chip regions 10 that lie next to each other in the first and / or second direction D1 and D2. Although the chip regions 10 in the exemplary embodiment of Fig. While the exemplary embodiments of the inventive concepts discussed here are shown to comprise several square chip regions arranged in rows and columns, they are not limited to such examples. For instance, the chip regions 10 may have different shapes in a top view (for example, viewed from the third direction D3), and the multiple chip regions may have different arrangements.

[0020] In an exemplary embodiment, the semiconductor substrate 1 can be a bulk silicon wafer, a silicon-on-insulator (SOI) wafer, a germanium wafer, a germanium-on-insulator (GOI) wafer, a silicon-germanium wafer, a thin wafer with an epitaxial layer formed by a selective epitaxial growth (SEG) process, etc. In the three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concepts discussed herein, memory cells can be arranged three-dimensionally on each of the chip regions 10 of the semiconductor substrate 1.

[0021] Fig. Figure 2 is a perspective view that schematically illustrates a three-dimensional semiconductor device according to one embodiment of the inventive concept.

[0022] As in Fig. As shown in Figure 2, a three-dimensional semiconductor storage device according to an exemplary embodiment of the inventive concept discussed here can comprise a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS. The cell array structure CS can be overlapped with the peripheral circuit structure PS in the top view. For example, as in the exemplary embodiment of Fig. As shown in Figure 2, the cell array structure CS can be arranged directly on the peripheral circuit structure (for example, in the third direction D3).

[0023] In one exemplary embodiment, the peripheral circuit structure PS can comprise row and column decoders, a side buffer, control circuits, and peripheral logic circuits. However, exemplary embodiments of the inventive concepts discussed here are not limited to this, and the peripheral circuit structure PS need not include one or more of these components or may include additional components. The peripheral logic circuits of the peripheral circuit structure PS can be integrated on the semiconductor substrate.

[0024] The cell array structure CS can comprise multiple memory cells arranged three-dimensionally. The cell array structure CS can comprise one or more mats, each of which contains multiple memory blocks BLK0-BLKn. Each of the memory blocks BLK0-BLKn can contain multiple memory cells arranged three-dimensionally.

[0025] In one exemplary embodiment, for example, each of the memory blocks BLK0-BLKn can comprise multiple electrode structures, vertical structures that vertically intersect the electrode structures, and memory elements arranged between the side walls of the electrode structures and the vertical structures. Each of the electrode structures can be formed from or comprise at least one conductive material, such as doped silicon or metallic materials, and can be provided in the form of a conductor or a plate. However, exemplary embodiments of the inventive concepts discussed here are not limited to these.

[0026] The peripheral circuit structure PS and the cell array structure CS can be formed sequentially on the same wafer. However, in other exemplary embodiments, a first wafer with the peripheral circuit structure PS and a second wafer with the cell array structure CS can be produced separately, and then the first wafer can be bonded to the second wafer to form the semiconductor device.

[0027] Fig. Figure 3 is a top view that schematically illustrates a three-dimensional semiconductor storage device according to an exemplary embodiment of the inventive concepts discussed here.

[0028] As in Fig. 1 and Fig. Figure 3 shows the peripheral circuit structure PS and the cell array structure CS, which are related to Fig. 2 are described, arranged on each of the chip regions 10 of the semiconductor substrate 1.

[0029] In each of the chip regions 10, the peripheral circuit structure PS (see for example) can be Fig. 2) are arranged on the semiconductor substrate 1. As in the exemplary embodiment of Fig. As shown in Figure 3, the peripheral circuit structure PS can comprise row and column decoders ROW DEC and COL DEC, a side buffer PBR, and control circuits CTRL. However, exemplary embodiments of the inventive concepts discussed here are not limited to these.

[0030] Several MTR mats forming the CS cell array structure (see, for example, Fig. 2) can be arranged in each chip region 10. The multiple mat regions MTR can be arranged in the first direction D1 and in the second direction D2. The multiple mats MTR can be arranged so that they overlap with the peripheral circuit structure PS (see, for example, Fig. 2) For example, the multiple mats MTR can be arranged on the peripheral circuit structure PS in the third direction D3. The components of the peripheral circuit structure PS, such as the row and column decoders ROW DEC and COL DEC, the side buffer PBR, and the control circuits CTRL, can be arranged under each of the mat regions MTR, as in the exemplary embodiment of Fig. Figure 3 shows that in other exemplary embodiments, several mat regions MTR can share a single peripheral circuit structure. According to one exemplary embodiment of the inventive concepts discussed here, the peripheral logic circuits forming the peripheral circuit structure PS can be freely arranged below the mat regions MTR (for example, in the third direction D3).

[0031] Fig. 4A and Fig. Figure 4B are top views, each schematically illustrating a cell array structure of a three-dimensional semiconductor storage device according to exemplary embodiments of the inventive concepts discussed here. Fig. 5 is an enlarged view of region “Q” from Fig. 4A.

[0032] As in the Fig. 4A and Fig. As shown in Figure 5, the cell array structure CS can comprise several horizontal structures 100a and 100b. The horizontal structures 100a and 100b can be provided in respective regions corresponding to the mat regions MTR of Fig. 3. For example, a memory structure MS on each of the horizontal structures 100a and 100b can correspond to a single mat region MTR. Alternatively, a pair of first horizontal structures 100a adjacent to each other in the second direction D2 and the memory structures MS located on them can together form a first mat region MTR, and a pair of second horizontal structures 100b adjacent to each other in the second direction D2 and the memory structures MS located on them can together form a second mat region MTR. In an exemplary embodiment, the first horizontal structures 100a can form the peripheral circuit structure of Fig. 2 share, and the second horizontal structure 100b can share another peripheral circuit structure.

[0033] The multiple horizontal structures 100a and 100b can be spaced apart from each other in the first direction D1 and / or in the second direction D2. In the following, regions encompassing the horizontal structures 100a and 100b are referred to as mat regions MTR, and a region between mat regions MTR is referred to as a division region DV.

[0034] In one exemplary embodiment, a single chip region 10 can comprise four or more mat regions MTR. In another exemplary embodiment, a single chip region 10 can comprise eight mat regions MTR. As in the exemplary embodiment of Fig. As shown in Figure 4B, a single chip region 10 can comprise four mat regions MTR. In this exemplary embodiment, the reference to Fig. 1. The described scribed line region 20 is formed in a region corresponding to an edge region of the chip, as in Fig. 4B shown, and therefore, in contrast to the structure of Fig. 4A Some structures near the edge region of the chip are removed. The following description refers to an example of Fig. 4A.

[0035] Source structures SC, which are separate from each other, can be provided on either of the horizontal structures 100a and 100b. For example, as in the exemplary embodiment of the Fig. As shown in Figures 6-7, separate source structures SC can be arranged directly on the horizontal structures 110a (for example, in the third direction D3). The source structures SC can be part of a storage structure, which is described below. Each of the source structures SC can include projecting structures PP that project from the mat regions MTR and extend to the partition region DV. The source structures SC can be separated from each other by partition structures DIT, which are arranged in the partition region DV and inserted between the source structures SC. For example, the projecting structures PP of the source structures SC can directly touch the lateral sides of a partition structure DIT opposite adjacent mat regions MTR. An etch stop structure ES can be arranged in the partition region DV. The etch stop structure ES can be arranged below the partition structures DIT (for example, in the third direction D3).As in the exemplary embodiment of . Fig. As shown in Figure 4A, the etch stop structure ES can comprise first substructures ES1 extending in the first direction D1 and second substructures ES2 extending in the second direction D2. The first substructures ES1 can extend along the first edges EG1 of the horizontal structures 100a and 100b, which are parallel to the first direction D1, and the second substructures ES2 can extend along the second edges EG2 of the horizontal structures 100a and 100b, which are parallel to the second direction D2. In an exemplary embodiment, the etch stop structure ES can be a lattice-like structure in which the first substructures ES1 and the second substructures ES2 are arranged to intersect.

[0036] Fig. Figures 6 to 8 are cross-sectional views along lines I-I', II-II' and III-III' respectively. Fig. 5. Fig. 9A is an enlarged cross-sectional view showing section “P” of Fig. 8 illustrates. Fig. 9A is an enlarged cross-sectional view showing section “R” of Fig. Figure 7 illustrates this. In the following, a three-dimensional semiconductor storage device according to exemplary embodiments of the inventive concepts discussed here is described using the following examples: Fig. 4A, 5 to 8, 9A and 9B are described in more detail.

[0037] As in the Fig. In 4A, 5 to 8, 9A and 9B, the peripheral circuit structure PS, including the peripheral logic circuits PTR, can be arranged on the semiconductor substrate 1, and the cell array structure CS can be arranged on the peripheral circuit structure PS. The peripheral circuit structure PS can comprise the peripheral logic circuits PTR integrated on the semiconductor substrate 1 and a lower, interlayered insulating layer 50 arranged to cover the peripheral logic circuits PTR.

[0038] In an exemplary embodiment, the semiconductor substrate 1 can be a silicon wafer, a silicon germanium wafer, a germanium wafer, or a single-crystal epitaxial layer grown on a single-crystal silicon wafer.

[0039] The peripheral logic circuits PTR can be, as described above, the row and column decoders, the side buffer, and the control circuit. The peripheral logic circuits PTR can include NMOS and PMOS transistors, low- and high-voltage transistors, and resistors integrated on the semiconductor substrate 1. The peripheral circuit lines 33 can be electrically connected to the peripheral logic circuits PTR via peripheral contact connectors 31. For example, the peripheral contact connectors 31 and the peripheral circuit lines 33 can be coupled to the NMOS and PMOS transistors.

[0040] The lower interlayer insulating layer 50 can cover the peripheral logic circuits PTR, the peripheral contact connectors 31, and the peripheral circuit lines 33. In an exemplary embodiment, the lower interlayer insulating layer 50 can comprise several stacked insulating layers. For example, the lower interlayer insulating layer 50 can comprise at least one layer selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low k-value dielectric layer.

[0041] The etch stop layer 60 and an intermediate insulating layer 65 can be stacked successively onto the lower intermediate insulating layer 50. For example, as in the exemplary embodiment of Fig. As shown in Figure 6, the underside of the etch-stop layer 60 can be in direct contact with an upper side of the lower intermediate insulating layer 50. Similarly, an underside of the intermediate insulating layer 65 can be in direct contact with an upper side of the etch-stop layer 60. In an exemplary embodiment, the etch-stop layer 60 can be formed from (or comprise) an insulating material that has etch selectivity with respect to the lower intermediate insulating layer 50. For example, the etch-stop layer 60 can comprise a silicon nitride layer or a silicon oxynitride layer. However, exemplary embodiments of the inventive concepts discussed here are not limited to these. In an exemplary embodiment, the intermediate insulating layer 65 can be formed from (or comprise) the same material as the lower intermediate insulating layer 50.

[0042] The cell array structure CS can comprise the mat regions MTR, which are arranged on the horizontal structures 100a and 100b, respectively, and the dividing region DV, which is arranged between the mat regions MTR (for example, in the first direction D1). Each of the mat regions MTR can comprise electrode structures ST and vertical structures VS that penetrate the electrode structures ST. The electrode structures ST can comprise a cell array region CAR and a junction region CNR, as shown in Fig. 5, include. For example, as in the exemplary embodiment of Fig. As shown in Figure 5, the cell array region CAR and the connection region CNR can be spaced apart in the first direction D1. The connection region CNR can border the split region DV in the first direction D1.

[0043] The horizontal structures 100a and 100b can be arranged on the interlayered intermediate insulating layer 65. For example, as in the exemplary embodiment of Fig. As shown in Figure 6, the horizontal structures 100a and 100b can be arranged directly on the interlayered insulating layer 65 (for example, in the third direction D3). In an exemplary embodiment, the horizontal structures 100a and 100b can be formed from or comprise at least one semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or combinations thereof. The horizontal structures 100a and 100b can have at least one single-crystal, amorphous, or polycrystalline structure. As an example, the horizontal structures 100a and 100b can be formed from a polysilicon layer doped with n-type impurity atoms. The horizontal structures 100a and 100b can also comprise a metal layer.The horizontal structures 100a and 100b can be arranged on the cell array region CAR and the connection region CNR. A first insulating intrusion layer 105 can be arranged in the division region DV between the horizontal structures 100a and 100b (for example, in the first direction D1). In an exemplary embodiment, the first insulating intrusion layer 105 can be formed from or comprise silicon oxide.

[0044] Each of the electrode structures ST can comprise insulating layers ILD and electrodes EL, which are stacked alternately in the third direction D3 (for example, a vertical direction) perpendicular to the first and second directions D1 and D2. In each of the electrode structures ST, the electrodes EL can exhibit a step structure in a boundary region of the mat region MTR (for example, in the connection region CNR).

[0045] The electrodes EL of each electrode structure ST can have a length (for example, a length in the first direction D1 extending towards the division region DV) that decreases with increasing distance from the horizontal structure 100a or 100b. Each of the electrodes EL can have pad sections located at the end closest to the division region DV, and the pad section of each electrode EL can be exposed by another electrode of decreasing length (for example, in the first direction D1) located directly on top of it. The pad sections of the electrodes EL can be arranged at various positions in the horizontal and vertical directions. In an exemplary embodiment, the electrodes EL can be formed from or comprise at least one conductive material, such as doped semiconductor materials, metal silicides, metallic materials, metal nitrides, etc.The insulating layers (ILDs) can consist of or comprise silicon oxide. However, exemplary embodiments of the inventive concepts discussed here are not limited to this.

[0046] The vertical structures VS can be configured to penetrate the electrode structure ST in each mat region MTR and can be connected to the horizontal structures 100a and 100b. Viewed from above, the vertical structures VS can be arranged in a specific direction or in a zigzag pattern. For example, the vertical structures VS can extend in the third direction D3 to the horizontal structures 100a and 100b and penetrate the electrodes of the electrode structure ST, which extend in the first direction D1. The vertical structures VS can comprise a semiconductor material, such as silicon (Si), germanium (Ge), or combinations thereof. In an exemplary embodiment, the vertical structures VS can be formed from or comprise a doped semiconductor material or an intrinsic semiconductor material.The vertical structures VS, which comprise the semiconductor material, can be used as channel regions of transistors forming NAND cell strings. Gap-filling structures VI can be formed to fill the interiors of the vertical structures VS. The gap-filling structures VI can, for example, consist of or comprise silicon oxide. Contact pads 128 can be formed on or in the upper sections of the vertical structures VS. The contact pads 128 can, for example, be formed of or comprise doped polysilicon.

[0047] The source structure SC can be positioned between the electrode structure ST and the horizontal structures 100a and 100b (for example, in the third direction D3). The source structure SC can comprise first and second conductive source structures SCP1 and SCP2. As in the exemplary embodiment of Fig. As shown in Figure 6, the undersides of the second conductive source structure, SCP2, can be in contact with the topsides of the horizontal structures 100a and 100b. Similarly, the undersides of the first conductive source structure, SCP1, can be in contact with the topsides of the second conductive source structure, SCP2.

[0048] In one exemplary embodiment, the first and second conductive source structures SCP1 and SCP2 can be formed from (or comprise) a doped semiconductor material doped with different dopants, such as phosphorus (P) or arsenic (As), than the semiconductor substrate 1, thus exhibiting a second conductivity type that differs from that of semiconductor substrate 1. In another exemplary embodiment, the first and second conductive source structures SCP1 and SCP2 can be formed from an n-doped polysilicon layer. In this exemplary embodiment, the concentration of n-doped dopants in the second conductive source structure SCP2 can be higher than in the first conductive source structure SCP1.Sidewalls of the second conductive source structures SCP2 can be arranged on the horizontal structures 100a and 100b, and sidewalls of the first conductive source structures SCP1 can be in direct contact with sidewalls of the dividing structures, as described below.

[0049] The second conductive Source structures SCP2 can be in direct contact with sections of the side walls of the vertical structures VS. For example, as in the exemplary embodiments of the Fig. 9A and Fig. As shown in Figure 9B, the second conductive source structures SCP2 can include a sidewall section SP that is in contact with the vertical structures VS and encloses sections of the sidewalls of the vertical structures VS. For example, as in the exemplary embodiment of FIG. Fig. As shown in Figure 9A, the sidewall section SP can include lateral ends extending in the third direction D3, which are in direct contact with the outer wall surfaces of the vertical structures VS. The second conductive source structures SCP2 can further include a horizontal section HP, which can extend in the second direction D2 and is located below the electrode structures ST (for example, in the third direction D3). In the second conductive source structures SCP2, an upper surface of the horizontal section HP can be in contact with the undersides of the first conductive source structures SCP1.The sidewall section SP of the second conductive source structure SCP2 may have a greater width (for example, length in the third direction D3) than the width of the horizontal section HP and may extend in such a way that it covers sections of sidewalls (for example, sidewalls extending in the third direction D3) of the first conductive source structure SCP1 and sections of sidewalls (for example, sidewalls extending in the third direction D3) of the horizontal structures 100a and 100b.At least one of the electrodes EL adjacent to the source structure SC (for example, adjacent to D3 in the third direction) can serve as an extinguishing control gate electrode, and an electrode located directly on the extinguishing control gate electrode (for example, located directly above the insulating layer ILD located on the extinguishing control gate electrode in the third direction D3) can serve as an earth selection gate electrode.

[0050] The aforementioned structures PP project (for example, in the first direction D1) from the source structure SC to the division region DV. In an exemplary embodiment, the aforementioned structures PP can be segments of the first conductive source structures SCP1 that extend within the division region DV. In an exemplary embodiment, the second conductive source structures SCP2 need not extend into the division region DV. For example, the second conductive source structures SCP2 can terminate at or near the edge of the mat region MTR adjacent to the division region DV. Remaining potting structures RM can be arranged between the aforementioned structures PP and the first insulating intrusion layer 105 (for example, in the third direction D3). For example, as in the exemplary embodiment of Fig. As shown in Figure 9B, the remaining potting structures RM can comprise the first to third remaining sacrificial structures 52, 54, and 56. The first to third remaining sacrificial structures 52, 54, and 56 can be stacked directly on top of each other (for example, in the third direction D3). The first remaining sacrificial structure 52 can be placed directly on the first insulating penetrant layer 105 (for example, in the third direction D3). The aforementioned structures PP can be placed directly on the third remaining sacrificial structure 56 (for example, in the third direction D3). The second remaining sacrificial structure 54 can be placed between the first remaining sacrificial structure 52 and the third remaining sacrificial structure 56 (for example, in the third direction D3). In an exemplary embodiment, the first and third remaining sacrificial structures 52 and 56 can be formed from or comprise silicon oxide.The second remaining sacrificial structure 54 may be made of or comprise silicon nitride or polysilicon. The remaining encapsulation structures RM may be located on the same plane (for example, at a distance from substrate 1 in the third direction D3) as the plane of the second conductive source structures SCP2 in the mat region MTR. Top surfaces of the remaining encapsulation structures RM (for example, a top surface of the third remaining sacrificial structure 56) may be in contact with the bottom surfaces of the first conductive source structures SCP1.

[0051] A second insulating intrusion layer 107 can be arranged in a region between adjacent source structures SC. For example, as in the exemplary embodiment of Fig. As shown in Figure 6, the second insulating intrusion layer 107 in the division region DV can be formed directly between the source structures SC (for example, in the first direction D1) in adjacent mat regions MTR. As in the exemplary embodiment of Fig. As shown in Figure 6, the second insulating indentation layer 107 can have the same width (for example, length in the third direction D3) as the adjacent source structures SC. In an exemplary embodiment, the second insulating indentation layer 107 can, for example, be formed from or comprise silicon oxide. The second insulating indentation layer 107 can fill a region in which the protruding structures PP, which project from the source structures SC to the division region DV, are not arranged.

[0052] As in the exemplary embodiment of Fig. As shown in Figure 9A, a data storage structure DSP can be arranged between the electrode structure ST and the vertical structures VS. The data storage structure DSP can extend in the third direction D3 to enclose a side wall (for example, an inner side wall) of each vertical structure VS. In an exemplary embodiment, the data storage structure DSP can, for example, be a tubular structure with an open top and an open bottom. A bottom side of the data storage structure DSP can be in direct contact with the side wall section SP of the second conductive source structure SCP2. For example, as in the exemplary embodiment of Fig. As shown in Figure 9A, the underside of the data storage structure DSP can be in direct contact with an upper edge (for example, in the third direction D3) of the side wall section SP. In an exemplary embodiment, a lower section of the data storage structure DSP can be arranged between the vertical structure VS and the first conductive source structure SCP1 (for example, in the second direction D2).

[0053] The data storage structure DSP can consist of one or more layers. In one exemplary embodiment, the data storage structure DSP can be part of a data storage layer. For example, as in the exemplary embodiment shown in FIG. Fig. As shown in Figure 9A, the data storage structure DSP can comprise a tunnel insulating layer (TIL), a charge storing layer (CIL), and a blocking insulating layer (BLK), which are stacked sequentially onto the sidewall of the vertical structure VS to serve as the data storage layer of a NAND flash memory device. In an exemplary embodiment, the charge storing layer (CIL) can be a trap insulating layer, a floating-gate electrode, or an insulating layer with conductive nanodots. In an exemplary embodiment, the charge storing layer (CIL) can comprise at least one silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a laminated trap layer.The tunnel insulating layer (TIL) can be formed from at least one material with band gaps larger than the band gaps of the charge storage layer (CIL), and the barrier insulating layer (BLK) can be formed from a dielectric material with a high k-value (for example, aluminum oxide, hafnium oxide, etc.).

[0054] According to an exemplary embodiment of the inventive concepts discussed here, a dummy data storage structure DSPa can be arranged in the horizontal structures 100a and 100b and can be vertically spaced from the data storage structure DSP with the side wall section SP in between (for example, in the third direction D3). The dummy data storage structure DSPa can essentially have a "U"-shaped cross-section. The dummy data storage structure DSPa can be arranged between a bottom surface of the vertical structure VS and the horizontal structures 100a and 100b. For example, as in the exemplary embodiment of Fig. As shown in Figure 9A, a top surface of the dummy data storage structure DSPa can be in direct contact with a lower edge of the sidewall section SP of the second conductive source structure SCP2. Horizontal structures 100a and 100b can surround the dummy data storage structure DSPa in the second direction D2 and in the third direction D3. The dummy data storage structure DSPa can have essentially the same layered structure as the data storage structure DSP. For example, the dummy data storage structure DSPa can include a tunnel insulating layer TILa, a charge storage layer CILa, and a barrier insulating layer BLKa, stacked sequentially.

[0055] In an exemplary embodiment, the three-dimensional semiconductor memory device can be a three-dimensional NAND flash memory device and can comprise NAND cell strings integrated onto the horizontal structures 100a and 100b. In other words, the electrode structure ST, the vertical structures VS, and the data storage structure DSP can form memory cells arranged three-dimensionally on the horizontal structures 100a and 100b.

[0056] An upper intermediate insulating layer 150 can cover end sections of the electrodes EL, which are arranged to form the stepped structure, and can cover the horizontal structures 100a and 100b, the second insulating penetrant layer 107, and the protruding structures PP. A first intermediate insulating layer 160 can be arranged on top of the upper intermediate insulating layer 150 to cover the top surfaces of the vertical structures VS.

[0057] As in the Fig. 8 and Fig. As shown in Figure 9A, a common source electrode CSP can penetrate into the electrode structure ST in the third direction D3, extend into itself in the first direction D1, and connect to the horizontal structures 100a and 100b. The common source electrode CSP can penetrate into the entire source structure SC in the third direction D3 and then extend to the horizontal structures 100a and 100b. A first insulating spacer SS1 can be inserted between the common source electrode CSP and the electrode structures ST (for example, in the second direction D2). In an exemplary embodiment, the first insulating spacer SS1 can be made of or comprise silicon oxide.

[0058] In the partitioning region DV, the partitioning structures DIT can be arranged between the preceding structures PP of adjacent source structures SC. In an exemplary embodiment, the partitioning structures DIT can have a bar or rectangular shape. As in Fig. As shown in Figure 5, the width w1 of the partition structures DIT in the second direction D2 can be greater than the width w2 of the preceding structure PP. In an exemplary embodiment, the partition structures DIT can be formed from or comprise at least one of silicon oxide, silicon nitride, or silicon oxynitride. As shown in Figure 5, the partition structures DIT can be formed from or comprise at least one of silicon oxide, silicon nitride, or silicon oxynitride. Fig. As shown in Figure 4A, the partition structures DIT can be arranged next to four edges of each of the horizontal structures 100a and 100b. However, exemplary embodiments of the inventive concepts discussed here are not limited to this.

[0059] As in Fig. As shown in Figure 9B, the width (for example, the distance in the first direction D1 between lateral faces) of the division structure DIT can vary depending on the layer with which the division structure DIT is in contact. For example, the division structure DIT may have a first width t1 on a layer of the upper interlayered insulating layer 150 and may have a second width t2, which is smaller than the first width t1, on a layer of the first conductive source structure SCP1. Furthermore, the division structure DIT may have a third width t3, which is smaller than the second width t2, on a layer of the etch stop structure ES.In an exemplary embodiment, the partitioning structures DIT may have a first stair structure TS1 at or near an interface between the upper interlayer insulating layer 150 and the first conductive source structures SCP1, and may have a second stair structure TS2 at or near an interface between the interlayer intermediate insulating layer 65 and the etch stop structure ES.

[0060] The etch stop structure ES, which is connected to a lower section of the partition structure DIT, can be arranged between the peripheral circuit structure PS and the source structure SC. As in the exemplary embodiment of the Fig. 7 and Fig. As shown in Figure 9B, the top surfaces of the etch-stop structure ES can be positioned at a lower level than the bottom surfaces of the horizontal structures 100a and 100b. For example, the etch-stop structure ES can be arranged within the interlayered intermediate insulating layer 65, and the interlayered intermediate insulating layer 65 can cover the top and side surfaces of the etch-stop structure ES. In an exemplary embodiment, the etch-stop structure ES can be formed from (or comprise) a material selected to have etch selectivity with respect to the insulating layers ILD and sacrificial layers, as described below. For example, the etch-stop structure ES can be formed from (or comprise) a material that has etch selectivity with respect to silicon oxide and silicon nitride. The etch-stop structure ES can be formed from non-metallic elements (for example, an essentially metal-free material).As an example, the etch stop structure ES can comprise a semiconductor material such as polysilicon. The etch stop structure ES does not need to be electrically connected to adjacent interconnect lines and contacts and can be in an electrically isolated state.

[0061] As in the exemplary embodiment of Fig. As shown in Figure 5, the width w4 of the etch stop structure ES in the first direction D1 can be greater than the width w3 of the division structure DIT in the first direction D1. As in the exemplary embodiment of Fig. As shown in Figure 4A, the etch stop structure ES can comprise the first substructures ES1, extending in the first direction D1, and the second substructures ES2, extending in the second direction D2. In one exemplary embodiment, the etch stop structure ES can be thinner (for example, in length in the first direction D1) than the horizontal structures 100a and 100b. In another exemplary embodiment, the thickness of the etch stop structure ES can be about 1 / 6 to 1 / 2 times that of the horizontal structures 100a and 100b. In another exemplary embodiment, the thickness of the etch stop structure ES can be, for example, in the range of about 80 nm to about 200 nm. In another exemplary embodiment, the thickness of the etch stop structure ES can be in the range of about 110 nm to about 170 nm. In an exemplary embodiment, the thickness of the horizontal structures 100a and 100b can be in the range of about 300 nm to about 700 nm.In another exemplary embodiment, the thickness of the horizontal structures 100a and 100b can be in the range of approximately 450 nm to approximately 550 nm. The etch stop structure ES can be thicker than the etch stop layer 60. In one exemplary embodiment, the thickness of the etch stop structure ES can be approximately 10 to 90 times the thickness of the etch stop layer 60.

[0062] A second intermediate insulating layer 165, a third intermediate insulating layer 170, and a fourth intermediate insulating layer 175 can be stacked successively on top of the first intermediate insulating layer 160. As in the exemplary embodiment of Fig. As shown in Figure 3, cell contact connectors PLG can run vertically (for example, in the third direction D3) and can penetrate the first and second intermediate insulating layers 160 and 165, as well as the upper intermediate insulating layer 150, and can each be coupled to end sections of the electrodes EL. Bit lines BL can be arranged on the second intermediate insulating layer 165 such that they cross the electrode structures ST and extend in the second direction D2. The bit line BL can be electrically connected to the vertical structure VS by a bit line contact connector BPLG that extends through the first and second intermediate insulating layers 160 and 165. The third intermediate insulating layer 170 can cover the bit lines BL. Upper interconnect connecting lines TW can be arranged on the third intermediate insulating layer 170.For example, as in the exemplary embodiment of . Fig. As shown in Figure 6, lower sections of the upper interconnect lines TW can be in direct contact with an upper section of the third intermediate insulating layer 170. The upper interconnect lines TW can be connected to the bit lines BL or interconnect lines CL via vias. In an exemplary embodiment, at least one of the first to fourth intermediate insulating layers 160, 165, 170, and 175 can be made of or comprise silicon oxide.

[0063] An intrusion plug region TVS comprises several intrusion plugs TPLG. The intrusion plugs TPLG can extend vertically (for example, in the third direction D3) to penetrate the first and second intermediate insulating layers 160 and 165, the upper intermediate insulating layer 150, the first and second insulating intrusion layers 105 and 107, the intermediate intermediate insulating layer 65, and the etch stop layer 60, and can be coupled to the peripheral circuit lines 33. Each of the intrusion plugs TPLG can be surrounded by a second insulating spacer SS2 made of an insulating material. The intrusion plugs TPLG can each be connected to the cell contact plugs PLG via the connecting lines CL on the second intermediate insulating layer 165, which can extend from the mat region MTR to the intrusion plug TPLG (for example, in the first direction D1).The TPLG penetration plugs can electrically connect the electrodes EL of the electrode structures ST to the peripheral circuit lines 33. The TPLG penetration plugs, the PLG cell contact plugs, and the BPLG bit line contact plugs can be made of or comprise at least one metallic material (for example, tungsten, aluminum, etc.). The TPLG penetration plugs can be horizontally spaced (for example, in the first direction D1) from the etch stop structure ES and the partition structure DIT. In an exemplary embodiment, a bottom surface of the partition structure DIT can be positioned at a higher level than the bottom surfaces of the TPLG penetration plugs. Bottom surfaces of the vertical structures VS can be positioned at a higher level than the bottom surface of the partition structure DIT.In an exemplary embodiment, the underside of the partition structure DIT can be arranged between the undersides of the penetration plugs TPLG and the undersides of the vertical structures VS.

[0064] As in the exemplary embodiment of Fig. As shown in Figure 5, the penetration plug region TVS can be arranged in a section of the division region DV in which the etch plug structure ES and the source structure SC are not arranged, as shown in Figure 5. Fig. Figure 5 shows exemplary embodiments of the inventive concepts discussed here. However, these are not the only examples. For instance, in some exemplary embodiments, the intrusion plug region TVS can be located in the connection region CNR, or the cell array region CAR can be located in the mat region MTR.

[0065] Fig. Figures 10 to 12 are top views, each schematically illustrating a cell array structure of a three-dimensional semiconductor memory device according to exemplary embodiments of the inventive concept discussed here. For the purpose of concise description, a previously described element can be identified by the same reference numeral without repeating an overlapping description.

[0066] As in the Fig. As shown in Figures 10 to 12, the etch stop structure ES can be provided in various forms. Fig. Figure 10 shows an island type of the etch stop structure ES, in which all first and second substructures ES1 and ES2, extending in the first and second directions D1 and D2, are spaced apart from each other. Alternatively, the Fig. 11 and Fig. 12 Two structures of the etch stop structure ES, wherein one of the first substructures ES1 and the second substructure ES2 have a line shape. In the Fig. In the exemplary embodiment shown in Figure 11, for example, the first substructure ES has a linear shape and extends continuously in the first direction D1. The second substructure ES2 has an island configuration in which every second substructure (for example, in the first direction D1 and / or the second direction D2) is separated from the others. In the exemplary embodiment of Fig. 12 The second substructure ES2 has a linear shape and extends continuously in the second direction D2, and the first substructure ES1 has an island configuration in which each substructure (for example, in the first direction D1 and / or the second direction D2) is separated from the other. However, exemplary embodiments of the inventive concepts discussed here are not limited to these exemplary structures of the etch stop structure ES, and the structure of the etch stop structure ES can be modified in various ways depending on the arrangement and shapes of the partition structures DIT.

[0067] Fig. 13 and Fig. 14 are cross-sectional views along lines II' or II-II' of Fig. 5, to illustrate a three-dimensional semiconductor storage device according to exemplary embodiments of the inventive concepts discussed herein. For the purpose of a concise description, a previously described element can be identified by the same reference numeral without repeating an overlapping description.

[0068] As in the Fig. 13 and Fig. As shown in Figure 14, the etch stop structure ES, which is connected to a lower section of the partition structure DIT, can be arranged between the peripheral circuit structure PS and the source structure SC. In the exemplary embodiments shown in the Fig. 13 and Fig. As shown in Figure 14, the etch stop structure ES can be arranged on the same plane as the horizontal structures 100a and 100b. For example, the etch stop structure ES can have a top surface located on the same plane as the top surfaces of the horizontal structures 100a and 100b, and it can have a bottom surface located on the same plane as the bottom surfaces of the horizontal structures 100a and 100b. A bottom surface of the etch stop structure ES can be arranged on a top surface of the interlayered intermediate insulation layer 65 (for example, in the third direction D3), in contrast to the exemplary embodiment of Fig. 6, wherein the etch-stop structure ES is arranged directly on a top surface of the etch-stop layer 60, and the interlayered intermediate insulating layer 65 covers the top and side surfaces of the etch-stop structure ES. In an exemplary embodiment, the etch-stop structure ES and the horizontal structures 100a and 100b can be formed simultaneously from the same material and can be structured to form separate structures. In an exemplary embodiment, the etch-stop structure ES can have the same thickness (for example, length in the third direction D3) as the horizontal structures 100a and 100b. For example, the thicknesses of the etch-stop structure ES and the horizontal structures 100a and 100b can be in the range of about 300 nm to about 700 nm.

[0069] Fig. 15, Fig. 18, Fig. 21 and Fig. 24 are cross-sectional views along line II' of Fig. 5, to illustrate a method for manufacturing a three-dimensional semiconductor storage device according to exemplary embodiments of the inventive concept discussed here. Fig. 16, Fig. 19, Fig. 22 and Fig. 25 are cross-sectional views along line II-II' of Fig. 5. Fig. 17, Fig. 20, Fig. 23 and Fig. 26 are cross-sectional views along line III-III' of Fig. 5.

[0070] As in the Fig. As shown in Figures 15 to 17, the peripheral circuit structure PS can be formed on the semiconductor substrate 1. The semiconductor substrate 1 can include chip regions and a scribing line region, as previously described with reference to Fig. 1 described. The semiconductor substrate 1 can be a silicon wafer. The formation of the peripheral circuit structure PS can include: forming the peripheral logic circuits PTR on the semiconductor substrate 1, forming the peripheral interconnect connection structures, such as the peripheral contact connectors 31 and the peripheral circuit leads 33, which are connected to the peripheral logic circuits PTR, and forming the lower interlayer insulating layer 50. In an exemplary embodiment, a first wafer comprising the peripheral circuit structure PS can be fabricated separately, and the cell array structure CS, to be described below, can be formed on a second wafer. Subsequently, a bonding process can be performed to join the first and second wafers together to form the semiconductor device.

[0071] The row and column decoders, the side buffers, and the control circuits, which serve as the peripheral logic circuits (PTRs), can be formed on any chip region of the semiconductor substrate 1. In an exemplary embodiment, the formation of the peripheral logic circuits (PTRs) can include: forming the device isolation layer 11 in the semiconductor substrate 1 to define active regions, and subsequently forming peripheral gate electrodes on the semiconductor substrate 1.

[0072] The formation of the peripheral interconnect connection structures can include: forming the peripheral contact plugs 31 to penetrate sections of the lower interlayer insulating layer 50, and forming the peripheral circuit leads 33 that are connected to the peripheral contact plugs 31. After forming the peripheral logic circuits PTR and the peripheral interconnect connection structures 31 and 33, the lower interlayer insulating layer 50 can be formed to cover the entire top surface of the semiconductor substrate 1 (for example, in the third direction D3). The lower interlayer insulating layer 50 can comprise a single insulating layer or multiple stacked insulating layers.In an exemplary embodiment, the lower intermediate insulating layer 50 may comprise at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and a dielectric layer with a low k-value.

[0073] The etch stop layer 60 and the intermediate insulating layer 65 can be formed sequentially on the lower intermediate insulating layer 50. For example, the etch stop layer 60 can be formed directly on the lower intermediate insulating layer (for example, in the third direction D3). The intermediate insulating layer 65 can be formed directly on the etch stop layer 60 (for example, in the third direction D3). In an exemplary embodiment, the etch stop layer 60 can be formed from (or comprise) an insulating material that has etch selectivity with respect to the lower intermediate insulating layer 50. For example, the etch stop layer 60 can comprise a silicon nitride layer or a silicon oxynitride layer.In an exemplary embodiment, the intermediate intermediate insulating layer 65 can be formed from (or comprise) the same material as the lower intermediate insulating layer 50.

[0074] The etch stop structure ES can be formed on the etch stop layer 60. For example, the etch stop structure ES can be formed by forming a polysilicon layer directly on a top surface of the etch stop layer 60 and structuring the polysilicon layer. Subsequently, the intermediate insulating layer 65 can be formed on the etch stop layer 60, which is provided with the etch stop structure ES. In an alternative embodiment, the etch stop layer 60 can be formed simultaneously with the horizontal structures described below and can then be structured to create separate structures.

[0075] After forming the peripheral circuit structure PS, the horizontal structures 100a and 100b can be formed such that the peripheral circuit structure PS (for example, in the third direction D3) is covered. In an exemplary embodiment, the horizontal structures 100a and 100b can be formed by forming a semiconductor layer on the interlayered insulating layer 65 and structuring the semiconductor layer. In an exemplary embodiment, the horizontal structures 100a and 100b can be formed by depositing a polysilicon layer such that the entire top surface of the semiconductor substrate 1 (for example, in the third direction D3) is covered. In an exemplary embodiment, the polysilicon layer can be doped with impurity atoms of the first conductivity type during the deposition of the polysilicon layer.

[0076] In an exemplary embodiment, the horizontal structures 100a and 100b can be formed such that they are spaced apart from each other in the first and second directions D1 and / or D2, as shown in Fig. Figure 4A shows that the first insulating intrusion layer 105 can be formed to fill a region between the horizontal structures 100a and 100b. In an exemplary embodiment, the first insulating intrusion layer 105 can be formed from or comprise silicon oxide. Subsequently, a planarization process can be performed to expose the top surfaces of the horizontal structures 100a and 100b. In an exemplary embodiment, the horizontal structures 100a and 100b can form the mat regions MTR, and the first insulating intrusion layer 105 can form the partition region DV between the mat regions MTR (for example, in the first direction D1 and / or the second direction D2).

[0077] A first sacrificial structure 51 and a second sacrificial structure 53 can be formed successively on the horizontal structures 100a and 100b, and an opening OP1 can be formed such that it penetrates the second sacrificial structure 53. As in the exemplary embodiment of Fig. As shown in Figure 17, the opening OP1 can expose the first sacrificial structure 51 (for example, a top surface of the first sacrificial structure). A third sacrificial structure 55 can then be formed such that the opening OP1 is filled and the second sacrificial structure 53 is covered. In an exemplary embodiment, the first sacrificial structure 51 and the third sacrificial structure 55 can be made of or comprise silicon oxide. The second sacrificial structure 53 can, for example, be made of or comprise silicon nitride or polysilicon.

[0078] A preliminary conductive source structure PSC can be formed on the third sacrificial structure 55. The preliminary conductive source structure PSC can be formed such that it covers the horizontal structures 100a and 100b in the mat regions MTR. The preliminary conductive source structure PSC can extend to the partition region DV to form protruding structures PP. In an exemplary embodiment, the preliminary conductive source structures PSC in adjacent mat regions MTR can be interconnected by the protruding structures PP extending to the partition region DV. The first to third sacrificial structures 51, 53, and 55 can also be structured by a structuring process to form the preliminary conductive source structure PSC, and thus the first to third sacrificial structures 51, 53, and 55 can have essentially the same planar shape as the preliminary conductive source structure PSC.

[0079] In an exemplary embodiment, the preliminary conductive source structure PSC can cover the top surface of the edge of the semiconductor substrate 1 at the edge of the wafer. In other words, the preliminary conductive source structure PSC can be in direct contact with the semiconductor substrate 1 at the edge of the wafer.

[0080] The second insulating intrusion layer 107 can be formed on top of the first insulating intrusion layer 105 to fill a region where the preliminary conductive source structure PSC and the first to third sacrificial structures 51, 53, and 55 are not formed. The second insulating intrusion layer 107 can, for example, be made of or comprise silicon oxide.

[0081] As in the Fig. As shown in Figures 18 to 20, the potting structures 120 can be formed on the preliminary conductive source structure PSC. The potting structures 120 can be formed on the horizontal structures 100a and 100b, respectively. Each of the potting structures 120 can comprise sacrificial layers SL and insulating layers ILD, which are stacked alternately and repeatedly (for example, in the third direction D3).

[0082] In an exemplary embodiment, the sacrificial layers SL and the insulating layers ILD can be formed by a thermal chemical vapor deposition (TCD) process, a plasma-enhanced chemical vapor deposition (PE-CVD) process, or an atomic layer deposition (ALD) process. The sacrificial layers SL can be formed from a material that can be etched with etch selectivity with respect to the insulating layers ILD. For example, the sacrificial layers SL can be formed from a material that can be selectively etched without excessively etching the insulating layers ILD.In an exemplary embodiment, the sacrificial layers SL and the insulating layers ILD can exhibit high etch selectivity in a wet etching process using a chemical solution and low etch selectivity in a dry etching process using an etching gas. In another exemplary embodiment, the sacrificial layers SL and the insulating layers ILD can be formed from different insulating materials that exhibit etch selectivity with respect to each other. For example, the sacrificial layers SL can be formed from a silicon nitride layer, and the insulating layers ILD can be formed from a silicon oxide layer.

[0083] The formation of the potting structures 120 can include performing a trimming process. In an exemplary embodiment, the trimming process can include the following steps: forming a mask structure on a layered structure, etching a section of the layered structure, reducing the horizontal area of ​​the mask structure, and removing the mask structure. The steps of etching a section of the layered structure and reducing the horizontal area of ​​the mask structure can be repeated several times before the step of removing the mask structure is performed. As a result of the trimming process, each of the potting structures 120 can have a step structure in the edge region of each of the mat regions MTR.

[0084] The upper interlayer insulating layer 150 can be formed to fill a region between the potting structures 120. Forming the upper interlayer insulating layer 150 can involve applying a thick insulating layer to cover the potting structures 120 and performing a planarization process on the insulating layer. The upper interlayer insulating layer 150 can be formed from an insulating material that exhibits etch selectivity with respect to the sacrificial layers SL.

[0085] As in the Fig. As shown in Figures 21 to 23, several vertical structures VS can be formed such that they penetrate the potting structures 120. The formation of the vertical structure VS can include vertical holes VH that penetrate the potting structures 120 (for example, in the third direction D3). For example, the formation of the vertical holes VH can include forming a hard mask structure to cover the potting structures 120 and anisotropic etching of the potting structures 120 using the hard mask structure as an etching mask. In an exemplary embodiment, the anisotropic etching process on the potting structures 120 can be a plasma etching process, a reactive ion etching (RIE) process, an inductively-coupled plasma reactive ion etching (ICP-RIE) process, or an ion beam etching (IBE) process.

[0086] According to an exemplary embodiment of the inventive concepts discussed here, in an embodiment in which the anisotropic etching process is carried out using the high-performance plasma, positive charges induced by ions and / or radicals in the plasma can be applied to the surfaces of the horizontal structures 100a and 100b, which are exposed by the vertical holes VH. Furthermore, according to an exemplary embodiment of the inventive concepts discussed here, during the fabrication of the three-dimensional semiconductor device, the semiconductor substrate 1 can be placed on a support of a semiconductor fabrication device, and during the anisotropic etching to form the vertical holes VH, a grounding voltage can be applied from the support to the semiconductor substrate 1.

[0087] During the anisotropic etching process using plasma, the horizontal structures 100a and 100b can be interconnected by the preliminary conductive source structure PSC, which includes the aforementioned structures PP, and can be in direct contact with the top surface of the edge of the semiconductor substrate 1 at the edge of the wafer. Therefore, the positive charges that are applied to the surfaces of the horizontal structures 100a and 100b during the formation of the vertical holes VH can be dissipated to the outside through the semiconductor substrate 1.

[0088] Since, as described above, the grounding voltage can be applied to the preliminary conductive source structure PSC during the formation of the vertical holes VH, it may be possible to prevent the positive charges on the horizontal structures 100a and 100b from causing an arcing problem.

[0089] The vertical structures VS can then be formed in the vertical holes VH. The vertical structures VS can be formed from or comprise at least one of semiconductor materials and conductive materials, as described above. In an exemplary embodiment, data storage structures DSP, which are related to the vertical structures VS, can be formed before the vertical structures VS are formed. Fig. 9 are described, in which the vertical holes VH are formed.

[0090] The first intermediate insulating layer 160 can be formed to cover the vertical structures VS, and dividing trenches DH can be formed in the division region DV. The dividing trenches DH can be formed to penetrate the first intermediate insulating layer 160 and the upper intermediate insulating layer 150, dividing the preliminary conductive source structure PSC into the first conductive source structures SCP1, which are separated from each other in division region DV. Furthermore, the dividing trenches DH can be formed to expose the top of the etch stop structure ES. In an exemplary embodiment, the dividing trenches DH need not penetrate the etch stop structure ES, and the etch stop structure ES can prevent damage to an interconnect link that might occur if the peripheral circuit lines 33 are exposed by the dividing trenches DH.Therefore, the ES etch stop structure can prevent a metal contamination problem caused by a damaged interconnect connection line.

[0091] Subsequently, Gate Division Regions (GIR) can be formed such that they extend from the Mat Regions (MTR) in the first direction D1 and penetrate vertically into the potting structures 120 (for example, in the third direction D3). In one exemplary embodiment, the Gate Division Regions (GIR) can be formed by the same etching process as the etching process for the Division Trenches (DH). However, exemplary embodiments of the inventive concepts discussed here are not limited to this. The Gate Division Regions (GIR) can penetrate the first conductive Source structure (SCP1) and can expose the horizontal structures 100a and 100b. At least one segment of the Gate Division Regions (GIR) can expose the first through third sacrificial structures 51, 53, and 55.

[0092] As in the Fig. As shown in Figures 24 to 26, the first through third sacrificial structures 51, 53, and 55 can be replaced by the second conductive source structures SCP2. For example, the first through third sacrificial structures 51, 53, and 55 can be removed, and the second conductive source structures SCP2 can be formed in the regions where the first through third sacrificial structures 51, 53, and 55 were removed. The first through third sacrificial structures 51, 53, and 55 can be selectively removed. In one exemplary embodiment, for example, the second sacrificial structure 53, exposed by Division Region DV, can be selectively removed, and subsequently, the first and third sacrificial structures 51 and 55 together can be selectively removed. Sections of the first through third sacrificial structures 51, 53, and 55 located in a region relatively far from the Gate Division Regions GIR can be left in Division Region DV.In other words, a remaining potting structure RM, comprising the first to third remaining sacrificial structures 51, 53, and 55, can be formed in the division region DV. During the removal of the first to third sacrificial structures 51, 53, and 55, the sidewalls of the sacrificial layers SL and the insulating layers ILD can be coated with a protective layer.

[0093] We return to the Fig. 5 to 9, where a replacement process can be carried out to replace the sacrificial layers SL of the potting structures 120 with the electrodes EL. Accordingly, the electrode structures ST can be formed, comprising the electrodes EL stacked vertically on the horizontal structures 100a and 100b. For example, the sacrificial layers SL exposed by the parting trenches DH can be removed to form gate regions between the insulating layers ILD. In an embodiment where the sacrificial layers SL are silicon nitride layers and the insulating layers ILD are silicon oxide layers, the removal of the sacrificial layers SL can be carried out by an isotropic etching process using an etching solution comprising phosphoric acid.

[0094] The electrodes EL can then be formed in the gate regions. Each electrode EL can comprise a barrier metal layer and a metal layer, which are deposited sequentially. The electrode structure ST can exhibit the step structure at the edge of each mat region MTR.

[0095] The first insulating spacer SS1 and the common source electrode CSP can each be formed in the gate division regions GIR. The common source electrode CSP can be connected to the horizontal structures 100a and 100b. In an exemplary embodiment, the common source electrode CSP can be formed from (or comprise) at least one compound selected from doped polysilicon, metals, and conductive metal nitrides. The second interlayer insulating layer 165 can be formed to cover the common source electrode CSP.

[0096] The intrusion plugs TPLG can be formed such that they penetrate vertically (for example, in the third direction D3) into the first and second intermediate insulating layers 160 and 165, the upper intermediate insulating layer 150, the first and second insulating intrusion layers 105 and 107, the intermediate intermediate insulating layer 65, and the etch stop layer 60, and are connected to the peripheral circuit lines 33. In an exemplary embodiment, the second insulating spacer SS2 can be formed such that side surfaces are covered by intrusion holes, and subsequently, intrusion plugs TPLG can be formed.

[0097] The cell contact connectors PLG can be formed such that they penetrate vertically (for example, in the third direction D3) into the first and second intermediate insulating layers 160 and 165 as well as the upper intermediate insulating layer 150 and are each coupled to end sections of the electrodes EL. Additionally, the bit line contact connector BPLG can be formed such that it is electrically connected to the vertical structure VS.

[0098] The bit lines BL and the connecting lines CL, described above, can be formed on the second intermediate insulating layer 165. Afterwards, the semiconductor substrate 1 can be laid down along the scribed line region 20 (see Fig. 1) can be cut with a cutting or sawing machine, thereby enabling the separation of the three-dimensional semiconductor devices formed on the semiconductor substrate 1 from several semiconductor chips.

[0099] Fig. 27 is a cross-sectional view along line II-II' of Fig. 5, to illustrate a three-dimensional semiconductor storage device according to an exemplary embodiment of the inventive concepts discussed here.

[0100] As in the exemplary embodiment of Fig. As shown in Figure 27, the electrode structure can comprise a first electrode structure ST1 and a second electrode structure ST2 on top of the first electrode structure ST1 (for example, in the third direction D3). The distance between the uppermost electrode EL of the first electrode structure ST1 and the lowermost electrode EL of the second electrode structure ST2 (for example, a distance in the third direction D3) can be greater than the corresponding distance between the uppermost and lowermost electrodes EL of the first electrode structure ST1.

[0101] The data storage structures DSP and the vertical structures VS, arranged to penetrate the first and second electrode structures ST1 and ST2, can exhibit a stair-step structure TS3 near an interface between the first and second electrode structures ST1 and ST2. For example, the data storage structures DSP and the vertical structures VS can be arranged in channel holes that penetrate each of the first and second electrode structures ST1 and ST2. In an exemplary embodiment, separate structuring processes can be performed on the first and second electrode structures ST1 and ST2, respectively, to form the channel holes in each of the first and second electrode structures ST1 and ST2. The stair-step structure TS3 can be a result of the structuring processes performed separately on the first and second electrode structures ST1 and ST2.

[0102] According to an exemplary embodiment of the inventive concepts discussed here, horizontal structures comprising multiple mat regions can be grounded by source structures during a process using high-frequency power. Accordingly, when a process using high-frequency power is carried out to fabricate three-dimensional semiconductor storage devices, it may be possible to prevent arcing problems caused by positive charges being built up in the horizontal structures.

[0103] According to an exemplary embodiment of the inventive concepts discussed here, it may be possible to prevent damage to an interconnect connecting line that can occur when peripheral circuit lines are exposed during the separation of the horizontal structures, and to prevent a metal contamination problem caused by a damaged interconnect connecting line.

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