Phase control loop (PLL) circuit and clock generator with under-probing circuit

Abstract

Phase-locked loop circuit, PLL circuit, (PLL_CKT) including: a voltage-controlled oscillator (40) configured to generate an output clock; and a subsampling PLL circuit (30) configured to to receive the generated output clock signal as feedback from the voltage-controlled oscillator (40), and Perform a phase locking operation on the received output clock signal. wherein the subsampling PLL circuit (30) includes a buffer (31) configured to buffer the received output clock, and wherein the subsampling PLL circuit (30) is further configured to adaptively adjust an internal signal based on a change in a characteristic curve of the buffer (31) according to a process, voltage and temperature change (PST change) in order to maintain a loop bandwidth of the subsampling PLL circuit (30).

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] The present application is based on and claims priority pursuant to 35 USC § 119 of Korean patent application No. 10-2019-0087095, filed with the Korean Patent Office on July 18, 2019. STATE OF THE ART

[0002] The disclosure relates to a phase-locked loop (PLL) circuit and a clock generator which has a PLL circuit with undersampling for locking one phase of a clock signal.

[0003] A PLL circuit, or a clock generator with a PLL circuit, can generate a phase-locked clock signal. This clock signal can be used, for example, to send data via a transmitter or to retrieve data via a receiver. In this case, the PLL circuit can be a ring PLL, an inductive-capacitive PLL (LC-PLL), etc.

[0004] A method for locking the phase of a clock signal via undersampling to improve noise curves has recently been applied to PLL circuits. These PLL circuits include a buffer circuit to prevent instantaneous phase distortion of an oscillator (for example, a voltage-controlled oscillator) during a undersampling operation. Since buffer circuits typically use complementary metal-oxide-semiconductor (CMOS) transistors, they are susceptible to process, voltage, and temperature changes (PST changes). Therefore, the buffer circuit can be used to modify the loop bandwidth of the PLL circuit depending on these PST changes.

[0005] US 2013 / 0 156 076 A1 discloses the following: Circuits and methods for a combined phase detector are provided. In some examples, circuits for a combined phase detector are provided, wherein the circuits include: a tri-state phase frequency detector and a charge pump that receives a reference signal and a first input signal and generates a first output signal; and a subsampling phase detector that receives the reference signal and a second input signal and outputs a second output signal, wherein the first output signal and the second output signal are coupled together. SUMMARY OF THE INVENTION

[0006] The scope of protection is defined by the attached claims.

[0007] According to embodiments, a phase-locked loop (PLL) circuit comprises a voltage-controlled oscillator configured to generate an output clock and a subsampling PLL circuit configured to receive the generated output clock as feedback from the voltage-controlled oscillator and to perform a phase-locking operation on the received output clock. The subsampling PLL circuit includes a buffer configured to buffer the received output clock and is further configured to adaptively adjust an internal signal based on a change in a characteristic curve of the buffer corresponding to a process, voltage, and temperature change (PST change) in order to maintain a loop bandwidth of the subsampling PLL circuit.

[0008] According to embodiments, a phase-locked loop (PLL) circuit comprises a voltage-controlled oscillator configured to generate an output clock and a subsampling PLL circuit configured to perform a phase-locking operation on the generated output clock. The subsampling PLL circuit includes a buffer configured to buffer the generated output clock and a replication buffer used to detect a change in the buffer's characteristic curve corresponding to a process, voltage, and temperature (PST) change. The subsampling PLL circuit is further configured to generate a reference voltage signal that reflects a characteristic curve of the replication buffer and, based on the generated reference voltage signal, to adaptively adjust the pulse width of an internal signal to maintain a loop bandwidth of the subsampling PLL circuit.

[0009] According to embodiments, a PLL circuit comprises a voltage-controlled oscillator configured to generate an output clock, a phase-locked loop (PLL) auxiliary circuit configured to perform a primary phase-lock operation on the generated output clock, and a subsampling PLL circuit configured to perform a secondary phase-lock operation on the output clock after the primary phase-lock operation has been performed.The PLL circuit further comprises a buffer configured to buffer the generated output clock, a replication buffer configured to have a characteristic curve identical to a characteristic curve of the buffer and to buffer a reference clock, a characteristic curve detector configured to detect, based on the buffered reference clock, a change in the characteristic curve of the buffer corresponding to a process, voltage and temperature change (PST change), and a pulse generator configured to generate a pulse signal with a pulse width that is adjusted based on the detected change in the characteristic curve of the buffer. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram representing a clock generator according to embodiments. Fig. Figure 2 is a flowchart describing a phase interlock operation according to embodiments. Fig. 3 is a flowchart for a detailed description of process S20 of Fig. 2; Fig. Figure 4 shows diagrams describing changes in loop bandwidth according to PST changes; Fig. Figure 5A is a block diagram that represents another example of a clock generator according to embodiments. Fig. 5B is a circuit diagram representing a transconductance circuit of Fig. 5A represents. Fig. 6A and Fig. 6B are circuit diagrams for a detailed description of components contained in a subsampling PLL circuit according to embodiments. Fig. Figure 7 is a timing diagram describing a process of the subsampling PLL circuit of Fig. 6A and Fig. 6B. Fig. Figure 8 is a circuit diagram for a detailed description of another example of components contained in a subsampling PLL circuit according to embodiments. Fig. Figure 9 is a block diagram that represents another example of a clock generator according to embodiments. Fig. Figure 10 is a flowchart describing another example of a phase interlock operation according to embodiments. Fig. Figure 11 is a diagram describing the operation of a clock generator for tracking the optimal loop bandwidth according to embodiments. Fig. Figure 12 is a flowchart describing another example of a phase interlock operation according to embodiments. Fig. Figure 13 is a diagram describing another example of the operation of a clock generator for tracking the optimal loop bandwidth according to embodiments. Fig. Figure 14 is a block diagram illustrating a wireless communication device according to embodiments. Fig. Figure 15 is a figure illustrating communication devices with clock generators for performing a phase locking operation of a clock according to embodiments. DETAILED DESCRIPTION OF THE EXECUTION FORMS

[0010] Embodiments provide a phase-locked loop (PLL) circuit and a clock generator capable of constantly adjusting a loop bandwidth of the PLL circuit or clock generator, or of generating a reliable clock by tracking a loop bandwidth that changes according to changes in a noise characteristic.

[0011] Fig. Figure 1 is a block diagram representing a clock generator according to embodiments.

[0012] As in Fig. As shown in Figure 1, a clock generator 10 can have a phase-locked loop (PLL) circuit PLL_CKT, and the PLL circuit PLL_CKT can have an assistant PLL circuit 20, a subsampling PLL circuit 30, and a voltage-controlled oscillator (VCO) 40. The VCO 40 can be implemented in various configurations, such as a ring oscillator or an inductive-capacitive (LC) oscillator.

[0013] The assistant PLL circuit 20 can receive an output clock (or oscillation signal) from the VCO 40 as feedback and perform a primary phase-lock operation. The primary phase-lock operation can be defined as a phase-lock operation that positions a phase difference between the phase of an output clock of the subsampling PLL circuit 30 and the phase of a reference clock into a locking region for a secondary phase-lock operation of the output clock. In other words, the primary phase-lock operation occurs before the execution of the secondary phase-lock operation of the subsampling PLL circuit 30 and can also be referred to as an assistant phase-lock operation. Phase-locking (PLL) performed by the assistant PLL circuit 20 can also be defined as an assistant PLL.A detailed design and operation of the assistant PLL circuit 20 will be described later with reference to . Fig. 5 described.

[0014] The subsampling PLL circuit 30 can include a buffer circuit 31 and a circuit 32 for managing the loop bandwidth (BW). The subsampling PLL circuit 30 can receive the output clock (a primary phase-locked output clock from the assistant PLL circuit 20) as feedback from the VCO 40 and perform subsampling using the output clock. In this case, the buffer circuit 31 can be configured to receive an output clock and to prevent phase distortion of the VCO 40 that might occur during a subsampling operation. A PLL performed by the subsampling PLL circuit 30 can be defined as a subsampling PLL.

[0015] The loop bandwidth management circuit 32 adaptively adjusts an internal signal for a subsampling operation based on a variable characteristic curve of the buffer circuit 31 as a function of process, voltage, and temperature changes (PST changes), thus maintaining the loop bandwidth of the subsampling PLL circuit 30 (or a PLL circuit PLL_CKT). The loop bandwidth is determined according to a noise characteristic curve of the subsampling PLL circuit 30 (or the PLL circuit PLL_CKT). Detailed descriptions follow with reference to Fig. 4.

[0016] In embodiments, the characteristic curve of the buffer circuit 31 can include a slew rate of an output clock passing through the buffer circuit 31. In the following terminology, the slew rate of an output clock passing through the buffer circuit 31 can be referred to synonymously as the slew rate of the buffer circuit 31. In this case, the loop bandwidth management circuit 32 can detect the slew rate of the buffer circuit 31 and, based on the detection result, adaptively adjust an internal signal to maintain a loop bandwidth. In embodiments, this internal signal is a pulse-shaped signal for adjusting the loop gain and loop bandwidth of the subsampling PLL circuit 30 and can be applied to a transconductance circuit of the subsampling PLL circuit 30.In embodiments, the transconductance circuit can perform a process to convert sampled voltage information into current information in response to an internal signal. Specifically, the transconductance circuit can be configured to operate only at one level of an internal signal, and the configuration of the transconductance circuit of the subsampling PLL circuit 30 is described below with reference to [reference to be added]. Fig. 5B described in detail.

[0017] In embodiments, the charge pump can perform a charge pumping operation in response to an internal signal. Specifically, the charge pump can be configured to perform a charge pumping operation only at the level of an internal signal, and the configuration of the charge pump of the subsampling PLL circuit 30 is described below with reference to Fig. 5B described in detail.

[0018] According to the presentation in Fig. In Figure 1, the subsampling PLL circuit 30 includes the buffer circuit 31 as a PST-change-sensitive component, but this is an example, and the embodiments are not limited to it. The subsampling PLL circuit 30 can further include PST-change-sensitive components in which the loop bandwidth management circuit 32 can adaptively adjust an internal signal according to the PST changes, taking into account one or a combination of the characteristics of the other components. The loop bandwidth management circuit 32 can also adaptively adjust an internal signal according to the PST changes, taking into account changes in the characteristics of other components besides the buffer circuit 31.

[0019] The optimal loop bandwidth can vary depending on the noise characteristics of the PLL circuit PLL_CKT, which vary depending on different environmental conditions. The loop bandwidth management circuit 32 can therefore track the varying optimal bandwidth by adjusting an internal signal. Specifically, the loop bandwidth management circuit 32 can monitor (or detect) whether the optimal loop bandwidth changes according to a change in the noise characteristics of the PLL circuit PLL_CKT, and the loop bandwidth management circuit 32 can adaptively adjust an internal signal to track the changed optimal loop bandwidth. The loop bandwidth management circuit 32 can also adaptively adjust an internal signal so that a tracked loop bandwidth is maintained even if the PST changes.

[0020] A phase-locked output clock, phase-locked via a phase-locking operation, can be provided to a sampling block outside the clock generator 10. By maintaining the optimal loop bandwidth even during a PST change, the clock generator 10 can produce a highly reliable output clock. Furthermore, the clock generator 10 can perform various processing operations using this highly reliable output clock, thereby improving the overall performance of an electronic device incorporating the clock generator 10.

[0021] Fig. Figure 2 is a flowchart describing a phase interlock operation according to embodiments. Fig. 2 is referred to below. Fig. 1 described.

[0022] As in Fig. 1 and Fig. As shown in Figure 2, a primary phase-locking operation can be performed on an output clock of VCO 40 using the Auxiliary PLL Circuit 20 (Operation S10). The Auxiliary PLL Circuit 20 can implement a PLL to lock the output clock of VCO 40 and can perform a primary phase-locking operation such that the phase difference between the output clock and a reference clock is within a locking region. In other words, the Auxiliary PLL Circuit 20 can be deactivated when the phase difference between the output clock and the reference clock is in a dead zone.

[0023] Subsequently, a secondary phase-locking operation can be performed on the output clock of VCO 40 using the subsampling PLL circuit 30 (operation S20). Specifically, the subsampling PLL circuit 30 can perform a phase-locking PLL on the output clock by subsampling the output clock and executing a secondary phase so that the output clock matches the phase of the reference clock. The subsampling operation of the subsampling PLL circuit 30 can minimize the change in loop bandwidth corresponding to PST changes, and an exemplary operation is described below with reference to Fig. 3 described in detail.

[0024] Fig. 3 is a flowchart for a detailed description of process S20 of Fig. 2. The following descriptions of Fig. 3. This is done with reference to Fig. 1.

[0025] As in Fig. 1 and Fig. 3 can be seen, the subsampling PLL circuit 30, after process S10 of Fig. 2, detect a change in the characteristic curve of the subsampling PLL circuit 30 that affects the loop bandwidth of the subsampling PLL circuit 30 or the PLL circuit PLL_CKT, corresponding to a PST change (process 21). Specifically, the subsampling PLL circuit 30 can detect that the characteristic curve of the buffer circuit 31 in the subsampling PLL circuit 30 changes in accordance with a PST change. In embodiments, the subsampling PLL circuit 30 can also have a replication buffer circuit with a characteristic curve equal to or similar to the characteristic curve of the buffer circuit 31 and can indirectly detect a change in the characteristic curve of the buffer circuit 31 corresponding to the PST changes via the replication buffer circuit. In embodiments, the subsampling PLL circuit 30 can be configured to enable direct detection of a change in the characteristic curve of the buffer circuit 31.

[0026] Subsequently, the subsampling PLL circuit 30 can perform subsampling by adaptively adjusting an internal signal based on a changed characteristic curve of the buffer circuit 31 to maintain a constant loop bandwidth (operation S22). Specifically, the subsampling PLL circuit 30 can adjust an internal signal to suppress an increase in loop bandwidth when the characteristic curve of the buffer circuit 31 is changed by a PST change to increase the loop bandwidth. Conversely, if the characteristic curve of the buffer circuit 31 is changed to decrease the loop bandwidth, the internal signal can be adjusted to suppress the decrease in loop bandwidth. As described above, an internal signal can be applied to the charge pump of the subsampling PLL circuit 30 as a pulsed signal to adjust the loop gain of the subsampling PLL circuit 30.However, this is just one example, and the embodiments are not limited to it. Internal signals can be defined as different signals capable of adjusting the loop gain according to the configuration of the subsampling PLL circuit 30.

[0027] Fig. Figure 4 shows diagrams describing changes in loop bandwidth according to PST changes.

[0028] As shown in diagram (a) of Fig. As shown in Figure 4, the loop bandwidth of a subsampling PLL (or PLL circuit) can be determined based on the XTAL_noise of a crystal within the subsampling PLL (or PLL circuit) and the VCO_noise of a VCO. The crystal can be the source of a reference clock used to lock the phase of the VCO's output clock. The XTAL_noise of the crystal and the VCO_noise can exhibit different frequency-dependent characteristic curves. For example, an optimal loop bandwidth (Loop_BW) can be determined based on a frequency (fBW) at which the sum of the XTAL_noise of the crystal and the VCO_noise can be minimized.

[0029] As described above, the characteristic curve of the subsampling PLL circuit can be changed according to the PST changes, and the optimal loop bandwidth Loop_BW can thus be changed to a different loop bandwidth Loop_BW' or Loop_BW''. Since noise corresponding to a change in the loop bandwidth of a frequency f BW' or f BW'' corresponds to a value greater than noise of frequency f BW Accordingly, a PST change can degrade the performance of the subsampling PLL circuit or PLL circuit. In other words, when performing a phase-locking operation of the subsampling PLL circuit, as shown in diagram (b) of Fig. As shown in 4, the jitter is measured at a frequency f BW (or a loop bandwidth) minimizes. However, the loop bandwidth can vary depending on a PST change, and thus the jitter can increase.

[0030] The subsampling PLL circuit can adaptively adjust the loop gain, a parameter used to determine the loop bandwidth, to maintain the optimal Loop_BW for jitter minimization, even when the PST changes. Specifically, the subsampling PLL circuit maintains the optimal Loop_BW by adjusting the pulse width of an internal signal related to the loop gain, taking into account characteristic changes resulting from a PST change.

[0031] Fig. Figure 5A is a block diagram that represents another example of a clock generator according to embodiments, and Fig. 5B is a circuit diagram representing a transconductance circuit of Fig. 5A represents. For better explanation, signals are shown in Fig. 5A simplified representation. In embodiments, however, a voltage-controlled oscillator (VCO) 101 can output differential signals with opposite phases over two lines, and signal lines can be designed such that the clock generator 10 can perform a phase-locking operation using the different signals.

[0032] As in Fig. As shown in Figure 5A, the clock generator 10 can include the VCO 101, a divider 102, a phase frequency detector (PFD) 103, a dead zone circuit 104, a charge pump (CP) 105, a loop filter 106, a buffer circuit 107, a sampler 108, a transconductance (Gm) circuit 109, a replication buffer circuit 100, a characteristic curve detector 111 and a pulse generator 112.

[0033] In embodiments, the divider 102, the phase frequency detector 103, the dead zone circuit 104 and the charge pump 105 can be used to power the assistance PLL circuit 20 of Fig. 1 form, and the buffer circuit 107, the sampler 108, the transconductance circuit 109, the replication buffer circuit 110, the characteristic curve detector 111 and the pulse generator 112 can form the subsampling PLL circuit 30 of Fig. 1. The replication buffer circuit 110, the characteristic curve detector 111 and the pulse generator 112 can form the loop bandwidth management circuit 32 of Fig. Form 1.

[0034] The VCO 101 can first provide an output clock VCO_clk to the divider 102, and the divider 102 can generate a feedback clock fb_clk from the output clock VCO_clk and provide the feedback clock fb_clk to the phase frequency detector 103. According to embodiments, the divider 102 can be implemented as an integer divider. The phase frequency detector 103 can receive the reference clock ref_clk and the feedback clock fb_clk, detect a phase difference between the reference clock ref_clk and the feedback clock fb_clk, and provide a detection result to the dead zone circuit 104. The dead zone circuit 104 can determine whether the phase difference between the reference clock ref_clk and the feedback clock fb_clk lies within a preset dead zone. If the phase difference lies within the dead zone, the dead zone circuit 104 can perform a phase locking operation using an assistant PLL and deactivate the assistant PLL.If the phase difference lies outside the dead zone, the dead zone circuit 104 can provide a detection result received from the phase frequency detector 103 to the charge pump 105. Based on the detection result, the charge pump 105 can generate a current signal to produce a voltage control signal Vctrl and provide the current signal to the loop filter 106. The loop filter 106 can generate a voltage control signal Vctrl by filtering the current signal and provide the voltage control signal Vctrl to the VCO 101.

[0035] An assistant PLL, utilizing the divider 102, the phase frequency detector 103, the dead-zone circuit 104, and the charge pump 105, can be executed repeatedly until the phase frequency between the reference clock ref_clk and the feedback clock fb_clk lies within the dead zone. As described above, a phase-locking operation performed using the assistant PLL can be referred to as the primary phase-locking operation. Subsequently, the clock generator 10 can execute an exclusive subsampling PLL for fine-tuning the phase of the output clock VCO_clk based on the reference clock ref_clk.

[0036] According to embodiments, the replication buffer circuit 110 can be configured, taking into account the design and configuration of the buffer circuit 107, such that it exhibits a characteristic curve similar to that of the buffer circuit 107. The subsampling PLL can indirectly detect a change in the characteristic curve of the buffer circuit 107 corresponding to a PST change using the replication buffer circuit 110, maintain the loop bandwidth of the subsampling PLL constant based on a detection result, and lock the phase of the output clock VCO_clk.

[0037] Specifically, VCO 101 can provide the output clock VCO_clk, which is primary-phase locked by the assistant PLL, to the buffer circuit 107. Buffer circuit 107 can buffer the output clock VCO_clk and provide a buffered output clock VCO_clk' to the sampler 108. Sampler 108 can receive the buffered output clock VCO_clk' and the reference clock ref_clk and generate a sampling voltage signal V_sam by sampling the buffered output clock VCO_clk' based on the reference clock ref_clk. Sampler 108 can be described as an undersampling phase detector. Transconductance circuit 109 can receive the sampling voltage signal V_sam, convert the sampling voltage signal V_sam into a sampling current signal I_sam, and provide the sampling current signal I_sam to the loop filter 106. The loop filter 106 can generate a voltage control signal Vctrl using the sampling current signal I_sam.

[0038] The replication buffer circuit 110 can receive the reference clock ref_clk, buffer the reference clock ref_clk, and provide a buffered reference clock ref_clk' to the characteristic curve detector 111. The characteristic curve detector 111 can detect the characteristic curve of the replication buffer circuit 110 based on the buffered reference clock ref_clk'. In embodiments, the characteristic curve detector 111 can detect a change in the slew rate of the buffered reference clock ref_clk' corresponding to a PST change and detect the characteristic curve of the replication buffer circuit 110 based on a detected change in the slew rate of the buffered reference clock ref_clk'. The characteristic curve detector 111 can provide a detection result DT_R to the pulse generator 112.Based on the detection result DT_R and the sampling voltage signal V_sam, the pulse generator 112 can generate a pulse signal (or an internal signal) pul for the operation of the transconductance circuit 109 and provide the pulse signal pul to the transconductance circuit 109. The pulse signal pul can be a signal for adjusting the loop gain of the subsampling PLL, and the pulse generator 122 can adjust the pulse width of the pulse signal pul such that a change in the loop bandwidth is prevented, even if the characteristic curve of the replication buffer circuit 110 changes according to a PST change. For detailed descriptions of this, Equation 1 is given below with respect to the loop bandwidth. Loop bandwidth = C*SRVCO_clk*(TpulTref)*Gm*ZLF(s)*KVCO

[0039] The loop bandwidth of the subsampling PLL can be set to any constant C and a slew rate SR.VCO_clk the buffer circuit 107, a pulse width T pul of the pulse signal pul of the pulse generator 112, one pulse period T ref , a transconductance value Gm of the transconductance circuit 109, a transfer function Z LF (s) of the loop filter 106 and a gain K VCO a VCO can be defined. The rate of rise SR VCO_clk The buffer circuit 107 can be modified according to a PST change and thus lead to a change in the loop bandwidth. To prevent a change in the loop bandwidth, the characteristic curve detector 111 can use the replication buffer circuit 110 to detect a change in the slew rate SR. VCO_clk The buffer circuit 107 is recorded according to a PST change. The following are described with reference to Fig. Section 6A describes a characteristic curve detection method and an embodiment of the characteristic curve detector 111 according to embodiments. The pulse generator 112 can determine the pulse width T. pul of the pulse signal pul according to a change in the rate of rise SR VCO_clk The buffer circuit 107 is adaptively adjusted, thereby keeping the loop bandwidth constant. The pulse generator 112 can, for example, adjust the pulse width T. pul decrease when the rate of ascent (SR) changes. VCO_clk The buffer circuit 107 is increased according to a PST change, and the pulse width T pul increase if the rate of ascent (SR) changes VCO_clk The buffer circuit 107 is reduced according to a PST change. The pulse width T pul in relation to the impulse period T ref This refers to the loop gain. In other words, the pulse generator 112 can adjust the pulse width T. pulChange to keep the loop bandwidth constant even when PST changes.

[0040] As shown in the illustration of Fig. As shown in Figure 5B, to which reference is made again for the description of the configuration of the transconductance circuit 109, the transconductance circuit 109 can have a first and second current source IS1 and IS2 as well as a first and second switching circuit SW1 and SW2. A first current source IS1 can generate a positive sampling current signal I_samP by converting a positive sampling voltage signal V_samP received from the sampler 108. The second current source IS2 can generate a negative sampling current signal I_samN by converting a negative sampling voltage signal V_samN received from the sampler 108. The first and second switching circuits SW1 and SW2 can receive the pulse signal pul from the pulse generator 112 and perform a switching operation in response to the pulse signal pul.

[0041] Fig. Figure 5A shows the charge pump 105 and the transconductance circuit 109 as separate components, but this is just one example, and the embodiments are not limited to this. The clock generator 10 can also include a multiplexer, and the transconductance circuit 109 can be used in place of the charge pump 105 in an auxiliary PLL via the multiplexer.

[0042] The transconductance circuit 109 can receive the pulse signal pul and the sampling voltage signal V_sam and perform a charge pumping operation in response to the pulse signal pul. In embodiments, the transconductance circuit 109 can perform a charge pumping operation when the pulse signal pul has a high level.

[0043] A subsampling PLL, which uses the buffer circuit 107, the sampler 108, the transconductance circuit 109, the replication buffer circuit 110, the characteristic curve detector 111, and the pulse generator 112, can be repeated until the reference clock ref_clk is equal to or similar to the phase of the output clock VCO_clk. As described above, a phase-locking operation performed using the subsampling PLL can be referred to as a secondary phase-locking operation.

[0044] The VCO 101 can output the output clock VCO_clk, which is phase-locked via a subsampling PLL.

[0045] The description of Fig. Although Section 5A focuses on the design of the clock generator 10 using a method for indirect detection of the characteristic curve of the buffer circuit 107 via the replication buffer circuit 110, this is only one example, and the embodiments are not limited to it. The clock generator 10 can also be implemented using a method for direct detection of the characteristic curve of the buffer circuit 107.

[0046] Fig. 6A and Fig. 6B are circuit diagrams for a detailed description of components contained in a subsampling PLL circuit according to embodiments, and Fig. Figure 7 is a timing diagram describing an operational process of the subsampling PLL circuit of Fig. 6A and Fig. 6B.

[0047] As in Fig. As shown in Figure 6A, a subsampling PLL can comprise the buffer circuit 107, the sampler 108, the replication buffer circuit 110, the characteristic curve detector 111, and the pulse generator 112. The buffer circuit 107 can include multiple inverters INV1 to INV4. The sampler 108 can include multiple sampling capacitors Cap1 to Cap4 and multiple switching elements SWa1, SWa2, SWb1, and SWb2. The sampling capacitors Cap1 to Cap4 can each have a sampling capacitance Cs. The replication buffer circuit 110 can include multiple inverters INV1' to INV4'. As mentioned above, the replication buffer circuit 110 can have a circuit configuration that duplicates the buffer circuit 107 and can have a characteristic curve (for example, a slew rate) equal to or similar to the characteristic curve of the buffer circuit 107. The characteristic curve detector 111 can include several capacitors Cap5 and Cap6 and comparators Comp1 and Comp2.Capacitors Cap5 and Cap6 can each have a capacitance NCs equal to N times the sampling capacitance Cs of the sampling capacitors Cap1 to Cap4 (where N is a real number equal to or greater than 1). The capacitance NCs of capacitors Cap5 and Cap6 can be determined based on the loop bandwidth of the subsampling PLL. A detailed description follows. Pulse generator 112 can include multiple OR gates OR1 and OR2, multiple AND gates AND1 and AND2, and multiple buffers BUF1 and BUF2.

[0048] The replication buffer circuit 110 can buffer reference clocks ref_clk_P and ref_clk_N via inverters INV1' to INV4'. From the reference clocks ref_clk_P and ref_clk_N, comparison voltage signals V_saP and V_saN can be generated via capacitors Cap5 and Cap6 and provided to comparators Comp1 and Comp2. The buffer circuit 107 can buffer buffer output clocks VCO_clk_P and VCO_clk_N via inverters INV1 to INV4. The sampler 108 can, by performing a sampling operation based on a positive reference clock ref_clk_P, generate sampling voltage signals V_samP and V_samN using the sampling capacitors Cap1 to Cap4 and the switching elements SWa1, SWa2, SWb1 and SWb2, and provide the sampling voltage signals V_samP and V_samN to the comparators Comp1 and Comp2.A first comparator, Comp1, can receive a negative sampling voltage signal V_samN and a negative comparison voltage signal V_saN, compare them, and generate a first comparison result signal. A second comparator, Comp2, can receive a positive sampling voltage signal V_samP and a positive comparison voltage signal V_saP, compare them, and generate a second comparison result signal.

[0049] A first OR gate OR1 and a second OR gate OR2 of pulse generator 112 can each receive the first comparison result signal and the positive reference clock ref_clk_P, perform an OR operation, and provide a first operation result V_cN to a first buffer BUF1. The first buffer BUF1 can amplify the first operation result V_cN and generate a negative pulse signal pul_N. A first AND gate AND1 and a second AND gate AND2 of pulse generator 112 can each receive the second comparison result signal and the negative reference clock ref_clk_N, perform an AND operation, and provide a second operation result V_cP to a second buffer BUF2. The second buffer BUF2 can amplify the second operation result V_cP and generate a positive pulse signal pul_P.

[0050] To describe how the subsampling PLL works Fig. 6A shows Fig. 7. Changes in the levels of the output clocks ref_clk_P and ref_clk_N, sampling voltage signals V_samP and V_samN, comparison voltage signals V_saP and V_saN, comparison result voltage signals V_cN and V_cP, and pulse signals pul_P and pul_N according to the time interval during a phase-lock operation using the subsampling PLL. Descriptions based on positive signals from differential signals follow. Negative signals can be sufficiently derived from the descriptions based on positive signals and are therefore not described in detail here.

[0051] With renewed reference to Fig. 7 The positive sampling voltage signal V_samP, which passes through the buffer circuit 107 and is output by the sampler 108, can be expressed according to the following equation 2. V_samP(t)=Vdd(1−e−t(Ro*Cs))

[0052] The positive sampling voltage signal V_samP can be defined with a power voltage Vdd, an output impedance Ro of the buffer circuit 107, and the sampling capacitance Cs. A slew rate SR can be determined here. VCO_ The positive sampling voltage signal V_samP due to the buffer circuit 107 can be expressed according to the following equation 3. SRVCO(t)=dV_samP(t)dt=VddRo*Cs*e−t(Ro*Cs)

[0053] The rate of ascent SR VCO_ This refers to the output impedance Ro of the buffer circuit 107, and the output impedance Ro of the buffer circuit 107 is a factor that can vary depending on a PST change. A change in the output impedance Ro can therefore change the slew rate SR. VCO_ cause. To compensate for the change in the rate of ascent SR VCO_ can the change in the rate of ascent SR VCO_a PST change can be detected using the replication buffer circuit 110 and the characteristic curve detector 111, and the pulse width of the positive pulse signal pul_P generated by the pulse generator 112 can be adjusted.

[0054] To implement an operational process for compensating for a change in the rate of ascent SR VCO_ To describe the positive comparison voltage signal V_saP generated by the replication buffer circuit 110 and a capacitor Cap6, it can be expressed according to the following equation 4. V_saP(t)=Vdd(1−e−t(Ro'*NCs))

[0055] The positive sampling voltage signal V_samP can be defined by the power voltage Vdd, an output impedance Ro' of the replication buffer circuit 110, and the capacitance NCs of the capacitor Cap6. The second comparator ComP2 can detect a rising and falling slew rate of the positive comparison voltage signal V_saP based on the positive sampling voltage signal V_samP, generate a negative comparison result voltage signal V_cN, and provide the negative comparison result voltage signal V_cN to the pulse generator 112. The pulse generator 112 can generate the positive pulse signal pul_P, which has a pulse width T. pul , which is adjusted so that a constant loop bandwidth is maintained even when the PST changes, and a pulse period T ref exhibits.

[0056] According to embodiments, when a subsampling PLL (or a clock generator) enters a latching state (for example, a state during an interval from 't1' to 't4'), the positive sampling voltage signal V_samP can converge to a value based on the power voltage Vdd at which the buffer circuit 107 operates. For example, the positive sampling voltage signal V_samP can converge to half the value of the power voltage Vdd (0.5 Vdd). In the latching state, equations 2, 3, and 4 can be simplified to equations 5, 6, and 7 as follows. Hereinafter, 'ts' denotes a time parameter in the latching state. 0.5*Vdd=V_samP(ts)=Vdd(1−e−ts(Ro*Cs))∴0.5=e−ts(Ro*Cs) SRVCO(ts)=dV_samP(ts)dt=VddRo*Cs*e−ts(Ro*Cs)=Vdd2*Ro*Cs 0.5*Vdd=V_saP(ts)=Vdd(1−e−ts(Ro'*NCs))∴Tpul=Ro'*NCs*In2

[0057] As described above, the positive pulse signal pul_P generated by pulse generator 112 can have a pulse width T pul exhibit according to equation 7 (for example, a pulse width corresponding to the length between 't1' and 't2'). In other words, the positive pulse signal pul_P can have the pulse width T pul exhibit characteristics that can vary according to the output impedance Ro' of the replication buffer circuit 110, which varies during a PST change.

[0058] When performing a subsampling-based phase locking operation based on the pulse signal pul_P adaptively adjusted according to a PST change as described above, the loop bandwidth can be expressed according to Equation 8. Loop bandwidth=C*Vdd2*Ro*Cs*(Ro'*NCs*In2Tref)*Gm*ZLF(s)*KVCO=C*0.5*Vdd*N*In2*Fref*Gm*ZLF(s)*KVCO∵Ro≒Ro',Fref=1Tref

[0059] As shown in Equation 8, all parameters defining the loop bandwidth can be kept constant regardless of a PST change, and thus a constant loop bandwidth can be maintained even when a PST change occurs.

[0060] As with renewed reference to Fig. As shown in Figure 6B, a pulse generator 112' can also include a dithering circuit D_CKT. The dithering circuit D_CKT can include several switching elements SWc1 to SWc3 and SWd1 to SWd3, several capacitors Cap7 to Cap12, several resistors R1 and R2, and several buffers BUF3 and BUF4. The switching elements SWc1 to SWc3 and SWd1 to SWd3 of the dithering circuit D_CKT perform switching operations based on a dithering signal DTH, thereby delaying pulse signals pul_P and pul_N by a time interval (for example, by a time interval between 't3' and 't1'). As shown in Fig. As shown in Figure 7, by using the dithering circuit D_CKT, the pulse generator 112' does not immediately output the pulse signal pul_P at time 't1', when the pulse generator 112' has just entered the interlocking state, but outputs a pulse signal pul_PD at time 't3', when the interlocking state is stably maintained. This allows a phase interlocking operation to be performed more stably. The in Fig. The dithering circuit D_CKT shown in Figure 6B is an example, and its embodiments are not limited to it. The dithering circuit D_CKT can be implemented in various forms depending on the time delay.

[0061] The in Fig. 6A and Fig. The subsampling PLL configurations shown in Figure 6B are examples, and the embodiments are not limited to them. Various circuit configurations can be used that are capable of detecting the characteristic curve of the buffer circuit 107 as a function of a PST change and of keeping a loop bandwidth constant by adjusting the pulse widths of the pulse signals pul_P and pul_N based on a detection result.

[0062] Fig. Figure 8 is a circuit diagram for a detailed description of another example of components included in a subsampling PLL circuit according to embodiments. The descriptions below focus on the differences from the one in Fig. Subscanning PLL shown in 6A.

[0063] As in Fig. As shown in section 8, a subsampling PLL can be compared to Fig. 6A also includes a reference voltage generation circuit RVG_CKT connected to the power voltage Vdd, and the reference voltage generation circuit RVG_CKT can generate a reduced voltage signal Vdd / M (where M is a real number equal to or greater than 1) (M can be defined according to the values ​​in Fig. In the embodiments shown in 7, for example in example 2, the signal generated by lowering the level of the power voltage Vdd by one level is provided to each of the comparators Comp1 and Comp2. The comparators Comp1 and Comp2 can compare the lowered voltage signal Vdd / M with the comparison voltage signals V_saP and V_saN and output comparison result signals.

[0064] However, this is just one example, and the subsampling PLL can utilize various circuit designs capable of providing a reference voltage signal for the Comp1 and Comp2 comparators.

[0065] Fig. Figure 9 is a block diagram representing another example of a clock generator according to embodiments. The following descriptions focus on components that differ from the components of clock generator 10. Fig. 5a differ.

[0066] As in Fig. As shown in 9, a clock generator 10' can be compared to the clock generator 10 of Fig. 5A also features a loop bandwidth (BW) detector 113. Furthermore, a characteristic curve detector 111' can have several variable capacitors V_Caps. For better understanding, see again Fig. Reference is made to Section 6A, where the capacitors Cap5 and Cap6 of the characteristic curve detector 111 can be replaced with the variable capacitors V_Caps in the characteristic curve detector 111'. The variable capacitors V_Caps can have capacitances 'NCs', and 'N' can correspond to a variable value. The optimal striped bandwidth can vary depending on the noise characteristic of the clock generator 10' (or a subsampling PLL), and the striped bandwidth detector 113 can detect a varying optimal striped bandwidth, generate striped bandwidth information LBWI, and provide the striped bandwidth information LBWI to the characteristic curve detector 111'. The noise characteristic of the clock generator 10' can vary as a result of various factors, including the degradation of the VCO 101. The capacitances of the variable capacitors V_Caps of the characteristic curve detector 111' can be adjusted based on the striped bandwidth information LBWI.For better understanding, reference is made to equation 8, where the quantity 'N', which defines the loop bandwidth, can be adjusted according to a changed loop bandwidth.

[0067] The characteristic curve detector 111' can generate a detection result DT_R' using the variable capacitors V_Caps and provide the detection result DT_R' to the pulse generator 112. The pulse generator 112 can generate a pulse signal pul' and provide the pulse signal pul' to the transconductance circuit 109 to maintain a constant optimal loop bandwidth. The in Fig. However, the embodiment shown in Figure 9 is just one example, and the embodiments are not limited to it. Various embodiments can be applied to the clock generator 10', which can track a varying loop bandwidth.

[0068] Fig. Figure 10 is a flowchart describing another example of a phase interlock operation according to embodiments. Fig. 10 is referred to below. Fig. 9 described.

[0069] As in Fig. 9 and Fig. As shown in Figure 10, a change in the loop bandwidth corresponding to the noise characteristic of the clock generator 10' can be detected using the loop bandwidth detector 113 (process S30). The noise characteristic of the clock generator 10' can vary, for example, due to factors such as the degradation of a VCO contained within the clock generator 10'. The loop bandwidth detector 113 can monitor a change in the noise characteristic of the clock generator 10' and, based on a monitoring result from the stored data, determine the optimal loop bandwidth. The loop bandwidth detector 113 can generate the loop bandwidth information LBWI, which indicates a determined optimal loop bandwidth. However, this is just one example, and the embodiments are not limited to this. Various embodiments can be applied to the loop bandwidth detector 113.The loop bandwidth detector 113 can, for example, learn optimal loop bandwidths according to the noise characteristic of the clock generator 10' via machine learning and detect an optimal loop bandwidth using a trained model.

[0070] A subsampling operation can be performed to maintain the optimal loop bandwidth detected by the characteristic curve detector 111' and the pulse generator 112 (step S40). The capacitances of the variable capacitors V_Caps of the characteristic curve detector 111' can be changed based on the loop bandwidth information LBWI. For example, the capacitance of the variable capacitors V_Caps can be increased if the detected optimal loop bandwidth is higher than before, and decreased if the detected optimal loop bandwidth is lower than before. The characteristic curve detector 111' can generate a detection result DT_R' using the variable capacitors V_Caps with the changed capacitances and provide the detection result DT_R' to the pulse generator 112.The pulse generator 112 can generate a pulse signal pul', the pulse width of which is adjusted based on the detection result DT_R', and provide the pulse signal pul' to the transconductance circuit 109, thereby performing a phase locking operation while keeping the detected optimal loop bandwidth constant.

[0071] Fig. Figure 11 is a diagram describing the operation of a clock generator for tracking the optimal loop bandwidth according to embodiments.

[0072] As in Fig. As shown in Figure 11, a noise curve can vary according to the noise characteristic of a clock generator, and thus the optimal loop bandwidth can vary. The noise characteristic of a clock generator can vary, for example, according to different environmental conditions, such as the degradation of a VCO of the clock generator. The optimal loop bandwidth corresponding to a first noise characteristic 1. N_F can be Loop_BW1, while the optimal loop bandwidth corresponding to a second noise characteristic 2. N_F can be Loop_BW2. In other words, if the noise characteristic of a clock generator changes from a first noise characteristic 1. N_F to a second noise characteristic 2. N_F, a change can occur in the optimal loop bandwidth that corresponds to a difference between a first frequency f. BW1 and a second frequency f BW2 corresponds.

[0073] A clock generator can track the changed optimal loop bandwidth as described above and can also perform a phase-lock operation on an output clock, keeping the changed optimal loop bandwidth constant even when the PST changes.

[0074] Fig. Figure 12 is a flowchart describing another example of a phase-locking operation according to embodiments. Descriptions of the following are provided. Fig. 12 with reference to Fig. 9.

[0075] As in Fig. 9 and Fig. As shown in Figure 12, the optimal loop bandwidth can be detected using the loop bandwidth detector 113, based on the noise-related performance of the VCO 101 of the clock generator 10' (operation S50). The loop bandwidth detector 113 can generate the loop bandwidth information LBWI, which indicates an optimal loop bandwidth. The characteristic curve detector 111' can adjust the capacitances of variable capacitors based on a detected optimal loop bandwidth (operation S60). In other words, the characteristic curve detector 111' can adjust the capacitances of the variable capacitors V_Caps using the loop bandwidth information LBWI. For example, the larger the detected optimal loop bandwidth, the higher the capacitance of the variable capacitors V_Caps can be. Conversely, the smaller the detected optimal loop bandwidth, the smaller the capacitance of the variable capacitors V_Caps can be.The characteristic curve detector 111' can generate a detection result DT_R' using the variable capacitors V_Caps, which have set capacitances, and provide the detection result DT_R' to the pulse generator 112. The pulse generator 112 can generate a pulse signal pul', the pulse width of which is adjusted based on the detection result DT_R', and provide the pulse signal pul' to the transconductance circuit 109, thereby performing a phase-locking operation while simultaneously keeping the detected optimal loop bandwidth constant.

[0076] In summary, if the clock generator 10' has a configuration in which it generates a clock signal by selectively using (or having) one of several VCOs, the clock generator 10' can set (or adjust) the capacitances of the variable capacitors V_Caps to perform a phase-locking operation with an optimal loop bandwidth according to the noise-related power characteristics of each of the VCOs.

[0077] Fig. Figure 13 is a diagram describing another example of the operation of a clock generator for tracking the optimal loop bandwidth according to embodiments.

[0078] As in Fig. As shown in Figure 13, a noise curve can vary according to the noise-related power characteristics of the VCOs VCO1 and VCO2 (or ring oscillators) contained in a clock generator, and thus the optimal loop bandwidth can vary. For example, the clock generator may have the first noise characteristic 1. N_F if the clock generator has a first voltage-controlled oscillator VCO1 with a first noise-related power characteristic, and the optimal loop bandwidth may correspond to a first loop bandwidth Loop_BW1' corresponding to a first frequency f. BW1 ' corresponds. Furthermore, the clock generator can have the second noise characteristic 2. N_F if the clock generator has a second voltage-controlled oscillator VCO2 with a second noise-related power characteristic, and the optimal loop bandwidth can correspond to a second loop bandwidth Loop_BW2', which corresponds to a second frequency f BW2' corresponds. The optimal loop bandwidth when performing a phase locking operation in a clock generator can vary depending on the VCOs VCO1 and VCO2 of the clock generator.

[0079] A clock generator can track the optimal loop bandwidth corresponding to VCOs VCO1 and VCO2 by simply adjusting the capacitances of variable capacitors and performing a phase-locking operation corresponding to the optimal loop bandwidth. Furthermore, the phase-locking operation can be performed on an output clock while simultaneously maintaining a constant, modified optimal loop bandwidth even during PST changes.

[0080] Fig. Figure 14 is a block diagram representing a wireless communication device according to embodiments.

[0081] As in Fig. As shown in Figure 14, a wireless communication device 1000 can comprise multiple antennas 1100, a radio frequency (RF) circuit 1200, a processor 1300, and a clock generator 10. The RF circuit 1200 can include an analog-to-digital converter (ADC) 1210 for converting the data received via the antennas 1100 into digital data and a digital-to-analog converter (DAC) 1220 for converting the data received from the processor 1300 into analog data. The clock generator 10 utilizes the embodiments described above and can lock the phase of an output clock clk to a constant loop bandwidth even during a PST change. Furthermore, the clock generator 10 can track the optimal loop bandwidth according to the noise-related performance of a VCO of the clock generator 10.

[0082] The ADC 1210 and the DAC 1220 can perform conversion operations based on the highly reliable output clock clk from the clock generator 10. As a result, the performance of the wireless communication device 1000 can be improved.

[0083] Fig. Figure 15 is a figure illustrating communication devices according to embodiments which have clock generators for performing a phase-locking operation of a clock.

[0084] As in Fig. As shown in Figure 15, a home device 2100, a household appliance 2120, an entertainment device 2140, and an access point (AP) 2200 can each have a clock generator that performs a phase-locking operation of a clock. In embodiments, the home device 2100, the household appliance 2120, the entertainment device 2140, and the AP 2200 can form an Internet of Things (IoT) network system. The Fig. The 15 communication devices shown are examples, and it would be obvious that a wireless communication device could also be used in other, non-industrial applications. Fig. It may contain the 15 communication devices shown.

[0085] As is customary in the field of inventive concepts, the embodiments are described and illustrated in the drawings in the form of functional blocks, units, and / or modules. It will be apparent to those skilled in the art that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, connecting wires, and so on, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. If the blocks, units, and / or modules are implemented by microprocessors or the like, they may be programmed by means of software (for example, microcode) to perform various functions discussed herein and may optionally be controlled by firmware and / or software.Alternatively, each block, unit, and / or module can be implemented using dedicated hardware or as a combination of dedicated hardware for performing some functions and a processor (for example, one or more programmed microprocessors and related circuit arrangements) for performing other functions. Each block, unit, and / or module of the embodiments can also be physically separated into two or more interacting and discrete blocks, units, and / or modules without altering the scope of the inventive concepts. Furthermore, the blocks, units, and / or modules of the embodiments can be physically combined to form more complex blocks, units, and / or modules without altering the scope of the inventive concepts.

Claims

[1] Phase-locked loop circuit, PLL circuit, (PLL_CKT) comprising: a voltage-controlled oscillator (40) configured to generate an output clock; and a subsampling PLL circuit (30) configured to to receive the generated output clock signal as feedback from the voltage-controlled oscillator (40), and Perform a phase locking operation on the received output clock signal. wherein the subsampling PLL circuit (30) includes a buffer (31) configured to buffer the received output clock, and wherein the subsampling PLL circuit (30) is further configured to adaptively adjust an internal signal based on a change in a characteristic curve of the buffer (31) according to a process, voltage and temperature change (PST change) in order to maintain a loop bandwidth of the subsampling PLL circuit (30). [2] PLL circuit (PLL_CKT) according to claim 1, wherein the internal signal is a pulse signal for adjusting a loop gain of the subsampling PLL circuit (30). [3] PLL circuit (PLL_CKT) according to claim 1, wherein the subsampling PLL circuit (30) further comprises a replication buffer (110) corresponding to the buffer (31), and wherein the subsampling PLL circuit (30) is further configured to to detect the change in the characteristic curve of the buffer (31) using the replication buffer (110); and to adjust the internal signal based on the detected change in the characteristic curve of the buffer (31). [4] PLL circuit (PLL_CKT) according to claim 1, wherein the characteristic curve of the buffer (31) is a rise rate of the buffer (31). [5] PLL circuit (PLL_CKT) according to claim 4, wherein the subsampling PLL circuit (30) is further configured to based on the increasing slew rate of the buffer (31), the internal signal is adjusted to reduce the loop gain of the subsampling PLL circuit (30); and based on the decreasing slew rate of the buffer (31) to adjust the internal signal to increase the loop gain of the subsampling PLL circuit (30). [6] PLL circuit (PLL_CKT) according to claim 1, wherein the subsampling PLL circuit (30) further comprises: a replication buffer (110) configured to buffer a reference clock, wherein the replication buffer (110) corresponds to the buffer (31), a characteristic curve detector (111) configured to detect the change in the characteristic curve of the buffer (31) based on the buffered reference clock and a sampling voltage signal; and a pulse generator (112) which is configured to generate the internal signal based on the detected characteristic curve of the replication buffer (110). [7] PLL circuit (PLL_CKT) according to claim 6, wherein the subsampling PLL circuit (30) further comprises: a sampler (108) that is set up to to sample the output clock buffered by buffer (31) based on the reference clock; and to generate the sampling voltage signal based on the sampled output clock; a transconductance circuit (109) configured to generate a sampling current signal based on the generated sampling voltage signal; and a charge pump (105) which is configured to perform a charge pumping operation in order to generate a voltage control signal, based on the adapted internal signal and the generated sampling current signal, which is applied to the voltage-controlled oscillator (40). [8] PLL circuit (PLL_CKT) according to claim 7, wherein the charge pump circuit (105) is configured to perform the charge pumping process in a high-level pulse period of the adapted internal signal. [9] PLL circuit (PLL_CKT) according to claim 8, wherein the pulse generator (112) is further configured to based on an increasing slew rate of the replication buffer (110) to generate the internal signal with a reduced pulse width; and based on the decreasing rise rate of the replication buffer (110) to generate the internal signal with an increased pulse width. [10] PLL circuit (PLL_CKT) according to claim 6, wherein the subsampling PLL circuit (30) further comprises a sampler (108) configured to to sample the output clock buffered by buffer (31) based on the reference clock; and to generate the sampling voltage signal based on the sampled output clock. [11] PLL circuit (PLL_CKT) according to claim 6, wherein the subsampling PLL circuit (30) further comprises a reference voltage generation circuit (RVG-CKT) which is configured to generate a dropped voltage signal as a sampling voltage signal based on a power voltage. [12] PLL circuit (PLL_CKT) according to claim 6, wherein the characteristic curve detector (111) further comprises: a capacitor (Cap5, Cap6, V_Caps) configured to generate a comparison voltage signal reflecting a characteristic curve of the replication buffer (110) based on the buffered reference clock; and a comparison circuit designed to compare the generated comparison voltage signal with the sampling voltage signal in order to generate a detection result signal. [13] PLL circuit (PLL_CKT) according to claim 12, wherein a capacitance of the capacitor (Cap5, Cap6, V_Caps) is determined based on the loop bandwidth. [14] PLL circuit according to claim 6, wherein a pulse generator (112) further comprises a dithering circuit configured to delay the generated internal signal. [15] PLL circuit (PLL_CKT) according to claim 1, wherein the PLL circuit (PLL_CKT) further comprises an assistant PLL circuit (20) configured to perform a primary phase-locking operation on the received output clock, and wherein the subsampling PLL circuit (30) is further configured to perform a secondary phase locking operation at the output clock after the primary phase locking operation has been performed. [16] PLL circuit (PLL_CKT) according to claim 1, wherein the subsampling PLL circuit (30) is further configured to adaptively adjust the internal signal to track the loop bandwidth varying based on a noise characteristic of the PLL circuit (PLL_CKT). [17] Phase-locked loop circuit, PLL circuit, (PLL_CKT) comprising: a voltage-controlled oscillator (40) configured to generate an output clock; and a subsampling PLL circuit (30) configured to perform a phase-locking operation on the generated output clock, the subsampling PLL circuit (30) comprises: a buffer (31) configured to buffer the generated output clock, and a replication buffer (110) which is used to detect a change in a characteristic curve of the buffer (31) according to a process, voltage and temperature change (PST change), and wherein the subsampling PLL circuit (30) is further configured to to generate a comparison voltage signal that reflects a characteristic curve of the replication buffer (110); and based on the generated comparison voltage signal, a pulse width of an internal signal is adaptively adjusted to maintain a loop bandwidth of the subsampling PLL circuit (30). [18] PLL circuit (PLL_CKT) according to claim 17, wherein the subsampling PLL circuit (30) further comprises a capacitor comprising: a first end connected to an output of the replication buffer (110); and a grounded second end, and wherein the subsampling PLL circuit (30) is further configured to generate the comparison voltage signal based on a reference clock which is buffered by the replication buffer (110) and capacitor. [19] PLL circuit (PLL_CKT) according to claim 18, wherein the subsampling PLL circuit (30) further comprises a sampler (108) configured to to sample the output clock buffered by buffer (31) based on the reference clock; and to generate a sampling voltage signal based on the sampled output clock, and wherein the subsampling PLL circuit (30) is further configured to to compare the generated voltage signal with the generated reference voltage signal in order to generate a detection result signal; and to adaptively adjust the pulse width based on the generated detection result signal. [20] PLL circuit (PLL_CKT) according to claim 17, wherein the subsampling PLL circuit (30) further comprises a charge pump (105) configured to perform a charge pumping operation in a high-level period of the internal signal in order to generate a voltage control signal applied to the voltage-controlled oscillator (40). [21] PLL circuit (PLL_CKT) according to claim 20, wherein the characteristic curve of the buffer (31) is a rise rate of the buffer (31). [22] PLL circuit (PLL_CKT) according to claim 21, wherein the subsampling PLL circuit (30) is further configured to based on the increasing slew rate of the buffer (31) to reduce the pulse width of the internal signal in order to decrease the loop gain of the subsampling PLL circuit (30); and based on the decreasing rise rate of the buffer (31) to increase the pulse width of the internal signal in order to increase a loop gain of the subsampling PLL circuit (30). [23] PLL circuit (PLL_CKT) according to claim 17, wherein the subsampling PLL circuit (30) further comprises a loop bandwidth detector configured to detect the loop bandwidth varying based on a noise characteristic of the PLL circuit (PLL_CKT), and the PLL circuit (PLL_CKT) is further configured to adjust the pulse width of the internal signal based on the detected loop bandwidth. [24] Clock generator (10) comprising: a voltage-controlled oscillator (40) configured to generate an output clock; an assistant phase-locked loop (PLL) circuit (20) configured to perform a primary phase-lock operation on the received output clock; and a subsampling PLL circuit (30) configured to perform a secondary phase-locking operation at the output clock after performing the primary phase-locking operation, the subsampling PLL circuit (30) further comprises: a buffer (31) configured to buffer the generated output clock; a replication buffer (110) configured to have a characteristic curve identical to a characteristic curve of the buffer (31) and to buffer a reference clock; a characteristic curve detector (111) configured to detect, based on the buffered reference clock, a change in the characteristic curve of the buffer (31) corresponding to a process, voltage, and temperature change (PST change); and a pulse generator (112) which is configured to generate a pulse signal with a pulse width that is adapted based on the detected change in the characteristic curve of the buffer (31) [25] Clock generator (10) according to claim 24, wherein the characteristic curve of the buffer (31) is a rise rate of the buffer (31), and wherein the pulse generator (112) is further configured to based on the increasing slew rate of the buffer (31), the pulse width of the internal signal is adjusted to reduce the loop gain of the subsampling PLL circuit (30); and based on the decreasing rate of rise of the buffer (31) to adjust the pulse width in order to increase the loop gain.

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