Electronic component comprising a semiconductor chip having a low-resistance part with an active region and a high-resistance part on a dielectric layer

Abstract

An electronic component (100) configured to be encapsulated to form a housing (120), the electronic component (100) comprising: - a molding layer (102), wherein the molding layer (102) comprises or consists of a film-shaped molding film (106); - a semiconductor chip (104) having a low-resistance first section (142) and a high-resistance second section (144), wherein the first section (142) has an active region (140) and the second section (144) is arranged on the mold layer (102); and an electrically conductive back-end-of-line structure (110) on one main surface of the semiconductor chip (104) opposite another main surface of the semiconductor chip (104) on which the mold layer (102) is arranged.

Description

BackgroundTechnical area

[0001] Various embodiments generally relate to an electronic component, a package, and a method of manufacturing electronic components. Description of the state of the art

[0002] Housings can be described as encapsulated electronic components whose electrical connections protrude from the encapsulation and can be mounted on an electronic peripheral, for example on a printed circuit board.

[0003] Housing costs are an important factor for industry. This affects performance, dimensions, and reliability. The various housing solutions are diverse and must meet the requirements of the application.

[0004] US 2015 / 0 147 869 A1 discloses a wafer comprising, from top to bottom, a polymer film, a bonding film, and a device layer. The device layer contains semiconductor circuits. The polymer film serves as a temporary protective layer against etching agents and is removed from the wafer before it is further processed into individual chips. Furthermore, removing the polymer film is essential, as otherwise the two wafers cannot be joined together as intermediate products. After the polymer film has been removed and both wafers are bonded together, various packages or chips are manufactured from them.

[0005] US 2018 / 0 076 174 A1 discloses an electronic component that is already encapsulated with all components and forms a complete housing. The electronic component comprises: a mold layer; a semiconductor chip having a first portion and a high-resistance second portion, wherein the first portion has an active region and the second portion is arranged on the mold layer; and a back-end-of-line structure on one main surface of the semiconductor chip that is opposite another main surface of the semiconductor chip on which the mold layer is arranged. Summary

[0006] There may be a need to provide a means of manufacturing electronic components that focuses on reducing processing complexity while maintaining high device reliability. This need is met by an electronic component having the features of claim 1 and by a method having the features of claim 17.

[0007] According to an exemplary embodiment, the electronic component is provided which comprises a mold layer and a semiconductor chip having a low-resistance first section and a high-resistance second section, wherein the first section has an active region and the second section is arranged on the mold layer.

[0008] According to a further exemplary embodiment, a housing having the features of claim 14 is provided, which housing comprises the electronic component comprising a dielectric layer and a semiconductor chip having a low-resistance first section and a high-resistance second section, wherein the first section has an active region and the second section is arranged on the dielectric layer, and an encapsulant which encapsulates at least a part of the electronic component.

[0009] According to a further exemplary embodiment, a method with the features of claim 17 for producing electronic components is provided, the method comprising providing a semiconductor wafer having a plurality of semiconductor chips, each having a low-resistance first section and a high-resistance second section, each of the first sections having an active region, arranging the second sections on a mold layer, and then separating the semiconductor wafer on the mold layer into a plurality of separate electronic components, each having at least one of the semiconductor chips and a section of the mold layer.

[0010] According to an exemplary embodiment, an electronic component and a corresponding housing can be provided in which a semiconductor chip is equipped with a low-resistance (or lower-resistance) part and a high-resistance (or higher-resistance) part. Advantageously, the high-resistance section can be connected (preferably directly) to a (preferably substantially planar or flat) dielectric (preferably mold) layer, while the low-resistance section can be connected to an active chip region facing away from the dielectric layer. With this configuration, a very compact electronic component and a housing can be produced, since both the semiconductor chip and the dielectric layer can be made very thin. The ohmic losses during operation of the electronic component orof the package can also be low, since the integrated circuit element(s) can only be arranged in the low-resistance region. The high-resistance part can serve as a support during production, simplify handling, and can be partially removed by thinning before the electronic component or package is manufactured. At the same time, a simple electrical connection to the active region is possible, while the dielectric layer can serve as a carrier. By using a simple dielectric layer (especially a mold layer) as a carrier, the effort required to manufacture and separate electronic components can be significantly reduced. Furthermore, such a concept can achieve reliable component-to-component isolation and improved high-frequency performance. Description of further exemplary embodiments

[0011] Further exemplary embodiments of the electronic component, the housing and the method are explained below.

[0012] In the context of the present application, the term "electronic component" may in particular encompass a semiconductor chip (in particular a power semiconductor chip), an active electronic component (such as a transistor), a passive electronic component (such as a capacitor, an inductor, or an ohmic resistor), a sensor (e.g., a microphone, a light sensor, or a gas sensor), a light-emitting, semiconductor-based component (e.g., a light-emitting diode (LED) or a laser), an actuator (e.g., a loudspeaker), and a microelectromechanical system (MEMS). In particular, the electronic component may have a semiconductor chip with at least one integrated circuit element (e.g., a diode or a transistor) in a surface portion thereof.

[0013] In the context of the present application, the term "semiconductor chip" can in particular refer to a bare piece of semiconductor material, which may also have electrically insulating structures and electrically conductive structures in the semiconductor material and which may have at least one integrated circuit element monolithically integrated in the semiconductor material. A semiconductor chip can therefore be a small block of semiconducting material on which a specific functional circuit is manufactured. Such integrated circuits can be manufactured in large batches on a single semiconductor wafer, e.g., using processes such as photolithography. The processed semiconductor wafer can then be singulated into many pieces, each containing an example of the circuit. Each of these pieces can be referred to as a semiconductor chip.Semiconductor chips realized according to exemplary embodiments may be formed in silicon technology, gallium nitride technology, silicon carbide technology, etc.

[0014] In the context of the present application, the terms "low-resistance semiconductor section" and "high-resistance semiconductor section" may, in particular, refer to different integrally connected sections of a semiconductor chip having different electrical conductivity values. More specifically, the low-resistance semiconductor section may have a higher electrical conductivity value than the high-resistance semiconductor section. For example, the low-resistance semiconductor section may be a crystalline semiconductor section (in particular silicon), while the high-resistance semiconductor section may be a high-resistance semiconductor section (in particular silicon). In one embodiment, the low-resistance semiconductor section and the high-resistance semiconductor section may be separated by an intervening dielectric layer. In such embodiments, the semiconductor chip may be embodied as an SOI (silicon-on-insulator) chip.

[0015] In the context of the present application, the term “active region” may in particular refer to a section of the semiconductor chip in which at least one integrated circuit element (e.g. a transistor, a diode, etc.) is monolithically integrated.

[0016] In the context of the present application, the term "dielectric layer" can refer, in particular, to a flat or planar body made of an electrically insulating material. Such a dielectric material can be, for example, a molding compound or another dielectric, such as a polymer.

[0017] In the context of the present application, the "molding layer" may, for example, comprise or consist of a resin, such as an epoxy resin. It is also possible for the "molding layer" to contain such a resin and additional filler particles in the resin matrix.

[0018] In the context of the present application, the term "housing" may in particular refer to an electronic device that may have one or more electronic components, preferably mounted on a carrier (where the carrier may have or consist of a single part, multiple parts connected via an encapsulation or other housing components, or a subassembly of carriers). The component(s) of the housing may be at least partially encapsulated by an encapsulation. Optionally, one or more electrically conductive connecting bodies (such as bonding wires and / or clips) may be implemented in a housing, for example for electrically coupling the electronic component to the carrier.

[0019] In the context of the present application, the term "encapsulation" may, in particular, refer to a substantially electrically insulating material that surrounds at least part of an electronic component (and optionally at least part of a carrier) to provide mechanical protection, electrical insulation, and optionally contribute to heat dissipation during operation. In particular, the encapsulation may be a molding compound. A molding compound may consist of a matrix of flowable and curable material and filler particles embedded therein. The filler particles may be used, for example, to adjust the properties of the molded component, in particular to improve thermal conductivity.

[0020] In one embodiment of the housing, the dielectric layer is a molded foil.

[0021] In one invention, the molding layer comprises or consists of a molding film. Because it is designed as a film, the molding layer can be flexible and contribute only a very small amount to the thickness of the electronic component and the housing. For example, a molding film can have a thickness in the range of 2 µm to 200 µm.

[0022] In one embodiment, the mold layer is a dual mold layer (i.e., with exactly two layers of mold material that may be bonded together), which may, for example, have or consist of a mold foil. Appropriate material selection of the dual mold layer may enable fine-tuning of the properties of the electronic component in the package.

[0023] In one embodiment, the molding layer comprises a resin matrix, in particular epoxy resin, and filler particles, in particular metal oxide, in the resin matrix. The matrix material can be curable. The filler particles can be used to adjust the physical properties (e.g., thermal conductivity, electrical insulation, coefficient of thermal expansion, high-frequency properties, etc.) of the molding material.

[0024] In one embodiment, the active region comprises at least one integrated circuit element. The one or more circuit elements may be monolithically integrated into the (preferably low-resistance portions of) the semiconductor chips. At least one electrically conductive pad of a back-end-of-line (BEOL) structure may be an exposed electrically conductive region coupled to the at least one integrated circuit element of the active region to connect the electronic component to an external electronic periphery.

[0025] In one embodiment, the electronic component has an adhesive layer between the mold layer and the semiconductor chip. This adhesive layer can prevent unwanted delamination of the electronic component and the package.

[0026] In one embodiment, the active region has a thickness of less than 1 µm, in particular in a range from 50 nm to 500 nm, particularly preferably in a range from 100 nm to 200 nm. Thus, the partial volume processed by the semiconductor technology can be extremely small.

[0027] In one embodiment, the semiconductor chip is substantially free of unprocessed semiconductor material. This can make the electronic component and package very compact, since essentially all of the semiconductor material across the entire thickness of the semiconductor chip can contribute to the formation of functional integrated circuit elements.

[0028] In another embodiment, the semiconductor chip has unprocessed semiconductor material with a thickness of less than 150 µm, in particular less than 30 µm. With such a small thickness, the configuration of the electronic component and the package can still be very compact. However, retaining a portion of the unprocessed semiconductor material can avoid the risk of inadvertently damaging the active area of the semiconductor chip when thinning a wafer during manufacturing.

[0029] In one embodiment, the semiconductor chip has a thickness in a range from 1 µm to 200 µm, in particular in a range from 10 µm to 40 µm, very particularly in a range from 20 µm to 30 µm. In particular, very thin semiconductor chips can also be used, e.g., having a thickness of less than 50 µm, preferably in a range from 20 µm to 30 µm. If the thickness is significantly less than 20 µm, heat dissipation can be made more difficult. If the thickness is significantly greater than 30 µm, the electrical influence of the semiconductor material (in particular silicon material) can increase.

[0030] In one embodiment, the high-resistance second part of the semiconductor chip is made of a high-resistance semiconductor material, in particular of a semiconductor material with an electrical resistance of at least 500 Ωcm, in particular of at least 1000 Ωcm. It is advantageous that such a high-resistance semiconductor can be provided with little effort. Thus, a more expensive low-resistance semiconductor portion (e.g., made of crystalline silicon) can be essentially limited to the extent of the active region in order to keep manufacturing costs low. High-resistance semiconductor material, which fulfills a supporting function and simplifies the handling of a semiconductor wafer, can nevertheless be partially removed later by thinning, so that its higher resistance does not impair the overall performance and reliability of the electronic component of the package.For example, the low-resistance semiconductor portion may have an electrical resistance of less than 100 Ωcm, in particular less than 10 Ωcm. For example, the electrical resistance of the low-resistance semiconductor section may be in a range from 1 Ωcm to 100 Ωcm, in particular in a range from 1 Ωcm to 10 Ωcm.

[0031] In one embodiment, the semiconductor chip is a silicon-on-insulator (SOI) chip. Silicon-on-insulator (SOI) technology can be used to manufacture silicon semiconductor components in a layered silicon-insulator-silicon substrate to reduce parasitic capacitance within the component and thereby improve performance. SOI-based semiconductor components have the specific property that the silicon junction can be disposed over an electrical insulator, such as silicon dioxide. Alternatively, an electrical insulator of a base used for manufacturing electronic components and packages according to example embodiments can be made of another dielectric material, such as sapphire, so that the semiconductor chip according to such embodiments can be referred to as a silicon-on-sapphire die.The choice of a suitable insulator can be made according to the intended application. For example, sapphire may be a suitable choice for radio frequency (RF) applications.

[0032] In one embodiment, the electronic component has an electrically conductive back-end-of-line (BEOL) structure on one main surface of the semiconductor chip, which faces another main surface of the semiconductor chip on the mold layer. The BEOL may be a part of integrated circuit manufacturing in which the individual integrated circuit elements (such as transistors, capacitors, etc.) are connected to the wiring on the wafer, i.e., the metallization layer (e.g., copper, aluminum, etc.). The beginning of the BEOL may be considered when the first metal layer is deposited on the wafer. Thus, the BEOL structure may be directly connected to the active area of the semiconductor chip. The mentioned BEOL structure may include at least one from the group consisting of one or more pads, contacts, insulating layers, metal levels, and bonding sites for die-to-package connections.The semiconductor chip can be embedded between the dielectric layer or the mold layer on one side and the BEOL structure on the other side.

[0033] In one embodiment, the electronic component has at least one electrically conductive protrusion extending beyond the BEOL structure. Such a protrusion may comprise, for example, a pillar, pin, bump, ball, etc., extending beyond a flat base of the BEOL structure. Such a protrusion may be configured to promote a solder connection of the electronic component when it forms the base of a package (which may have a carrier for supporting the electronic component with a solder connection therebetween) or when it is mounted (and soldered) on a submount such as a printed circuit board. In one embodiment, the protrusion may have a low-resistance base structure with a solder cap thereon.

[0034] In one embodiment, the semiconductor chip is an active semiconductor chip, in particular a radio-frequency semiconductor chip. A semiconductor chip configured to provide power amplification may be an active semiconductor chip. Such an active semiconductor chip may supply power to an electrical circuit of which it is a part and may control the flow of electrical current within the circuit. Examples of active semiconductor chips are transistor chips, rectifier chips, or thyristor chips. In the field of radio-frequency technology, the semiconductor chip may, for example, be configured to operate in a frequency range from approximately 20 kHz to approximately 300 GHz.

[0035] In one embodiment, the mold layer in the electronic component or in the housing is already fully cured and consists of a material that has adhesive properties in the uncured state. Curing can be understood, for example, as the polymerization and / or crosslinking of the material of the mold layer, in particular a resin (e.g., an epoxy resin). Before curing, the mold layer can be tacky and thus bond well to the semiconductor chip or a semiconductor wafer. After curing, which can be triggered, for example, by supplying thermal energy to the mold layer, the polymerization or crosslinking can lead to the formation of an intrinsic bond between the mold layer and the semiconductor chip(s), whereby the tacky property on the outer surface of the mold layer can be lost during curing.

[0036] In one embodiment, the housing has a carrier that is partially enclosed by the encapsulation and electrically connected to the electronic component. In the context of the present application, the term "carrier" can in particular refer to a support structure (which can be at least partially electrically conductive) that serves as a mechanical support for one or more electronic components to be mounted thereon and that can also contribute to the electrical connection between the chip(s) and the periphery of the housing. In other words, the carrier can fulfill a mechanical support function and an electrical connection function. A carrier can have or consist of a single part, multiple parts connected via an encapsulation or other housing components, or a subassembly of carriers.

[0037] For example, the carrier may be a leadframe carrier, i.e., a textured metal plate. If the carrier forms part of a leadframe, it may have a die pad and one or more leads.

[0038] In another embodiment, the carrier has a stack consisting of a central electrically insulating and thermally conductive layer (e.g., a ceramic layer) covered on both opposite main surfaces by a respective electrically conductive layer (e.g., a copper layer or an aluminum layer, wherein the respective electrically conductive layer may be a continuous or structured layer). In particular, the carrier may also be designed as a direct copper bonding (DCB) substrate or as a direct aluminum bonding (DAB) substrate.

[0039] In particular, the above-described BEOL structure on a main surface of the semiconductor chip can be electrically connected to the at least partially electrically conductive carrier. Thus, the connection between the BEOL structure and the carrier can simultaneously establish both a mechanical connection between the electronic component and the carrier and an electrical coupling therebetween.

[0040] In one embodiment, the encapsulation is a molding compound, in particular with different material properties than the dielectric layer. By selecting different materials for the mold layer of the electronic component and the encapsulation of the housing, a specific adaptation of the required properties (support of the semiconductor chips during processing at the component level, reliable mechanical protection, and electrical decoupling at the housing level) can be individually adjusted for the two mold structures.

[0041] A molding compound can consist of a matrix of flowable and curable material and embedded filler particles. Filler particles can be used, for example, to adjust the properties of the molded component, particularly to improve thermal conductivity. Molding can be achieved, for example, by injection molding, transfer molding, or die casting.

[0042] In one embodiment, overmolding may involve overmolding the respective electronic component with an encapsulation after separation from a wafer. However, one or more electrical contacts for accessing the encapsulated semiconductor chip from an exterior of the package may remain exposed. Such contacts may relate to an electrically conductive carrier on which an electronic component may be mounted within an interior of the package.

[0043] In one embodiment, the method includes temporarily bonding a carrier wafer to the semiconductor wafer prior to arranging and removing the carrier wafer from the semiconductor wafer prior to separating. Such a temporary carrier wafer may, for example, be a glass plate that can be reused multiple times.

[0044] In one embodiment, the method includes thinning the semiconductor wafer prior to bonding the semiconductor wafer to the mold layer, in particular by removing material at least from or exclusively from the second sections. The thinning can be performed, for example, mechanically by grinding, by laser ablation, and / or chemically (e.g., by wet etching). It is also possible to combine at least two of the aforementioned and / or other thinning technologies.

[0045] In one embodiment, the method includes temporarily bonding a dicing film to the mold layer before or after arranging and removing the dicing film from the electronic components during or after dicing. A dicing film or dicing tape may be a film or tape used in wafer dicing, i.e., separating pieces of semiconductor material after wafer-level processing. The dicing film may hold the semiconductor chips together during the dicing or singulation process. The dicing film may be attached to a thin frame (e.g., made of a metal) for stability. The singulated semiconductor chips may then be removed from the dicing film, e.g., with a pick-and-place tool. The singulated semiconductor chips with a mold layer on one side thereof may then be further processed, e.g.,They can be assembled on a mounting base and / or they can be encapsulated in the sense of a housing.

[0046] In one embodiment, the method includes embedding electrically conductive protrusions on an electrically conductive back-end-of-line (BEOL) structure on a main surface of the semiconductor wafer into a temporary (i.e., later removed) adhesive structure, which in particular connects the semiconductor wafer to a carrier wafer. The temporary adhesive structure may temporarily connect the carrier wafer to the semiconductor wafer and may be sufficiently soft to temporarily accommodate the protrusions without risk of damage. Before singulation, the temporary adhesive structure may be removed from the electronic components, preferably without leaving residues on the electronic components.

[0047] In one embodiment, the method includes separating by at least one of the group consisting of mechanical sawing, laser sawing, and etching. These separation techniques can also be combined.

[0048] In one embodiment, the semiconductor chip is designed as a power semiconductor chip. Thus, the semiconductor chip can be used for power applications, e.g., in the automotive sector, and can, e.g., comprise at least one integrated insulated-gate bipolar transistor (IGBT) and / or at least one transistor of another type (such as a MOSFET, a JFET, etc.) and / or at least one integrated diode. Such integrated circuit elements can, e.g., be manufactured using silicon technology or based on wide-bandgap semiconductors (e.g., silicon carbide or gallium nitride). A semiconductor power die or chip can contain one or more field-effect transistors, diodes, inverter circuits, half-bridges, full-bridges, drivers, logic circuits, other components, etc.

[0049] A semiconductor substrate, preferably a silicon substrate, can be used as the substrate or wafer that forms the basis for the semiconductor chips. It is also possible to use a germanium substrate or a III-V semiconductor material. Exemplary embodiments can be realized, for example, using gallium nitride or silicon carbide technology.

[0050] Furthermore, exemplary embodiments may make use of standard semiconductor processing technologies, such as suitable etching technologies (including isotropic and anisotropic etching technologies, in particular plasma etching, dry etching, wet etching), patterning technologies (which may include lithographic masks), deposition technologies (such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.).

[0051] The above and other objects, features and advantages will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are designated by like reference numerals. Brief description of the drawings

[0052] The accompanying drawings, which are included to provide a further understanding of exemplary embodiments and constitute a part of the specification, illustrate exemplary embodiments.

[0053] In the drawings: Fig. 1 illustrates a cross-sectional view of an electronic component according to an exemplary embodiment. Fig. 2 to Fig. 9 show cross-sectional views of structures obtained when performing a method for manufacturing electronic components at the wafer level according to an exemplary embodiment. Fig. 10 illustrates a cross-sectional view of a housing according to an exemplary embodiment. Fig. 11 shows a cross-sectional view of a housing according to another exemplary embodiment. Detailed description

[0054] The representation in the drawing is schematic and not to scale.

[0055] Before exemplary embodiments are described in more detail with reference to the figures, some general considerations on the basis of which exemplary embodiments were developed should be summarized.

[0056] According to an exemplary embodiment, an electronic component, a package, and a method for manufacturing a semiconductor component are provided, which can preferably operate on the basis of thin-wafer technology. The monolithically integrated circuit element(s) in an active region of the semiconductor component can be arranged in a low-resistance section of a semiconductor wafer or chip. The low-resistance silicon section can be arranged on a high-resistance silicon section. High-resistance silicon (e.g., with a resistivity of approximately 1 kOhmcm) is most advantageous at very high frequencies, e.g., in the GHz range, since high-resistance silicon can be substantially transparent.

[0057] Linearity and low losses are important performance factors in high-power RF (radio frequency) circuits.

[0058] However, performance limitations can arise from active and passive integrated circuit elements and the capacitive and inductive interaction of these circuit elements and traces with the semiconductor substrate.

[0059] Therefore, for some components, the substrate must be removed or significantly thinned. For this purpose, carrier technologies can be used to stabilize the thin wafers and chips.

[0060] According to exemplary embodiments, an expensive carrier can be dispensed with, thereby reducing manufacturing effort. In particular, an electronic component or a package according to an exemplary embodiment can comprise a semiconductor chip (e.g., an active RF semiconductor chip) having little or thin unprocessed high-resistance silicon on the backside, or even substantially no such silicon. A corresponding bare semiconductor chip can, for example, be equipped with a back-end-of-line (BEOL) metallization structure with contact terminals facing the topside. In addition, bumps or pillars (e.g., made of copper) or balls can be provided on the BEOL structure.

[0061] An exemplary embodiment may also provide a dielectric (particularly molding) layer or backside protective film on the backside of the electronic component. Such a dielectric layer may stabilize the electronic components or a wafer as a preform. This dielectric layer or film may preferably be made of a mold-like material with adhesive properties.

[0062] Such a structure can be advantageously used for a simple and cost-effective singulation process, since only a thin component with a thin mold film needs to be singulated. Simple separation processes can thus be used for singulation.

[0063] Advantageously, exemplary embodiments may eliminate the need for thick permanent glass plates, since, for example, it may be sufficient to apply a mold layer or film directly or indirectly to a semiconductor chip.

[0064] In one exemplary embodiment, a composite of semiconductor chip and mold layer can be used, with the latter acting as an insulating carrier. By eliminating the need for a conventional bulky carrier wafer made of glass, silicon, or ceramic, the dimensions of the electronic components and the manufacturing effort can be reduced. In particular, the high sawing effort required to separate the semiconductor dies or chips can also be eliminated. This allows for improved component-to-component isolation and improved RF performance while simultaneously keeping the manufacturing process simple.

[0065] Exemplary embodiments may provide an electronic component without free charge carriers outside the active chip area, which can contribute to nonlinearities, losses, and / or isolation limits. Exemplary embodiments may therefore be well-suited for high-performance RF devices, RF switches, LNA (low-noise amplifier) devices, and millimeter-wave devices.

[0066] Replacing a conventional insulating substrate with a molded or mold-like film or layer can reduce the dimensions of electronic components and reduce manufacturing costs. In such an electronic component, the backside of the semiconductor die or chip can be covered with a film of molding compound or a plastic material or plastic composite. An electronic component obtained in this way can be used as a chip-scale package without further processing using packaging technologies. However, it is also possible to package an obtained electronic component, e.g., through encapsulation.

[0067] Fig. 1 shows a cross-sectional view of an electronic component 100 according to an exemplary embodiment.

[0068] The illustrated electronic component 100 has a film-shaped molding layer 102 as its base. Thus, the molding layer 102 is embodied here as a molding film 106. A bare semiconductor chip 104 is applied to the molding film 106.

[0069] The semiconductor chip 104 may, for example, be a silicon chip and may have a low- or lower-resistance first section 142 and a high- or higher-resistance second section 144. The low-(resistance) first section 142 may, for example, be made of crystalline silicon. In contrast, the high-resistance second section 144 may, for example, be made of high-resistance silicon. The high-resistance second part 144 may, for example, have an electrical resistance of 1 kΩcm. In contrast, the low-resistance first section 142 may have a significantly lower electrical resistance, e.g., 10 Ωcm.

[0070] As shown, the first section 142 has an active area 140 in which one or more integrated circuit elements may be monolithically integrated (in Fig. 1). Such integrated circuit elements may be, for example, field-effect transistors or diodes, e.g., when the semiconductor chip 104 is configured for power semiconductor applications. In particular, the semiconductor chip 104 may be an active semiconductor chip 104 and configured for high-frequency applications.

[0071] The second portion 144 can be directly connected to the mold layer 102. However, as shown in detail 137, it is also possible for an adhesive layer 154 to be arranged between the mold layer 102 and the second portion 144 of the semiconductor chip 104. As can be seen from detail 137, the adhesive layer 154 can be arranged between the mold layer 102 and the semiconductor chip 104 to further promote adhesion between the mold layer 102 and the bare semiconductor chip 104.

[0072] No monolithically integrated circuit elements are formed in the second section 144, and it can therefore be free of an active region.

[0073] The second section 144, in combination with a part of the first section 142 that is directly connected to the second section 144, thus forms unprocessed semiconductor material with a thickness B of, for example, slightly less than 25 µm. A total thickness D of the semiconductor chip 104 may be, for example, 25 µm. A thickness L of the active region 140 in the low-resistance first section 142 may be D - B. More specifically, the active region 140 may, for example, have a thickness L of less than 1 µm, for example, 150 nm. A vertical thickness d2 of the second section 144 may be greater than a vertical thickness d1 of the first section 142. For example, d2 may be at least 10 times d1. The illustration in Fig. 1 is therefore not to scale.

[0074] The electronic component 100 has a layered, electrically conductive back-end-of-line (BEOL) structure 110 on its front side. The BEOL structure 110 can function as a redistribution layer and has one or more electrically insulating layers 141 with electrically conductive traces 143 located thereon and / or therein. In particular, the BEOL structure 110 can have pads 146. The BEOL structure 110 can be formed directly on an upper main surface of the semiconductor chip 104. The upper main surface is arranged opposite a lower main surface of the semiconductor chip 104, which can be in direct physical contact with the mold layer 102 or can be separated from the mold layer 102 only by an adhesive layer 154. The BEOL structure 110 can be directly connected to an active side, i.e., the active region 140, of the semiconductor chip 104.

[0075] As shown, electrically conductive protrusions 111 protrude beyond the BEOL structure 110 for interconnection purposes. Each of these protrusions 111 may have a pin or pillar 131 (e.g., a copper pillar) and a solder cap 133 made of a solderable material (e.g., AgSn or another solderable alloy) on top of the pillar 131.

[0076] The mold layer 102 can, for example, be in the Fig. 1 may already be cured (i.e., fully crosslinked or polymerized). Preferably, the material of the mold layer 102 is designed to exhibit adhesive properties in the uncured state. This material property facilitates a bond between the mold layer 102 and the semiconductor chip 104 during the manufacturing process and before curing.

[0077] As in detail 135 of the Fig. As shown in Figure 1, the mold layer 102 may include a resin matrix 150 (e.g., epoxy resin) and filler particles 152 embedded in the resin matrix 150. The filler particles 152 may be made of metal oxide (e.g., aluminum oxide, calcium oxide, magnesium oxide, manganese oxide), silicon oxide, and / or a ceramic material (e.g., aluminum nitride). Other filler particles 152 may also be used to adjust the electrical conductivity, thermal conductivity, thermal expansion coefficient, etc. of the mold layer 102.

[0078] For example, the Fig. 1 can be used as such, e.g., surface-mounted on a printed circuit board (PCB) not shown. However, it is also possible for the electronic component 100 to be encapsulated in a housing 120, as shown, for example, in Fig. 10 and Fig. 11 shown.

[0079] Fig. 2 to Fig. 9 show cross-sectional views of structures obtained when performing a method for manufacturing electronic components 100 according to an exemplary embodiment.

[0080] In Fig. 2 shows a fully processed component wafer 130. The wafer 130 is a semiconductor wafer comprising a plurality of still integrally connected semiconductor chips 104 arranged along a horizontal direction of Fig. 2 are arranged side by side. The wafer 130 is configured as a silicon-on-insulator (SOI) wafer. This means that the wafer 130 has a layer of low-resistance first sections 142 of its integrally connected semiconductor chips 104. This layer of first sections 142 consists of crystalline silicon material with a relatively high electrical conductivity. In addition, the wafer 130 has a layer of high-resistance second sections 144 of the integrally connected semiconductor chips 104. The layer of second sections 144 may partially consist of non-crystalline silicon material with a relatively low electrical conductivity. Each of the plurality of semiconductor chips 104 thus has a low-resistance first section 142 and a high-resistance second section 144, wherein the first section 142 has an active region 140. For illustration, Fig. 2 does not represent the actual thickness properties of the sections 142, 144 to scale. In reality, the thickness of the first section 142 is much smaller than the thickness of the second section 144 (see description of Fig. 1).

[0081] Furthermore, the layer of first sections 142 may be separated from the layer of second sections 144 by an electrically insulating layer 153, e.g., a silicon oxide layer. Thus, the wafer 130 is a silicon-on-insulator wafer.

[0082] The wafer 130 has the plurality of semiconductor chips 104 still integrally connected, each with an active area 140, although in Fig. 2 only one semiconductor chip 104 is shown. The active area 140 of each semiconductor chip 104 has monolithically integrated circuit elements 148 (e.g., transistors, diodes, RF circuit elements, etc.) connected to electrically conductive pads 146 (in Fig. 2 not shown, see Fig. 1) of the back-end-of-line structure 110. Each active region 140 forms part of the associated low-resistance first section 142 and may have a thickness L, for example, in a range of 100 nm to 200 nm.

[0083] The BEOL structures 110 are provided on an upper main surface of the semiconductor wafer 130. Electrically conductive protrusions 111 protrude upward from the BEOL structures 110 for each of the still integrally connected semiconductor chips 104.

[0084] To Fig. To obtain the structure shown in Figure 3, the electrically conductive protrusions 111 are embedded in a temporary adhesive structure 138. The adhesive structure 138 can consist of a thermoplastic adhesive or a UV (ultraviolet radiation) curable adhesive that adheres under surface tension and can later be removed without residue. The adhesive structure 138 can therefore be a non-permanent adhesive.

[0085] Furthermore, a carrier wafer 132 (e.g. made of glass) is temporarily connected to the semiconductor wafer 130, with the adhesive structure 138 in between.

[0086] Therefore, in Fig. 3 shows the mounting of the component wafer 130 on the reversible carrier wafer 132 by the adhesive structure 138.

[0087] Referring to Fig. 4 is the Fig. 3 is shown inverted and is thinned on an exposed side of the component wafer 130. In order to Fig. To obtain the structure shown in Figure 4, the thinning of the semiconductor wafer 130 is performed by removing a portion of the material of the high-resistance second section 144. In the embodiments shown, neither material of the electrically insulating layer 153 nor of the low-resistance first section 142 is removed. This is illustrated in a detail 155.

[0088] In other words: Fig. 4 shows the result of thinning the device wafer 130 from the backside to a target silicon thickness D of, for example, 25 µm. This thinning can be achieved, for example, by a mechanical treatment and / or a chemical-mechanical treatment and / or a chemical wet etching treatment.

[0089] Referring to Fig. 5, a mold layer 102, which is formed here as a film 106, is applied to an exposed surface of the second section 144 after thinning. The mold layer 102 can be bonded to the wafer 130, for example, by lamination, pressure die casting, transfer casting, or bonding by means of a separate adhesive layer (in Fig. 5 not shown, see reference numeral 154 in Fig. 1) can be connected.

[0090] For example, a molding tape or a molding film 106 is applied or mounted as a backside protective film to the back of the wafer 130. Applying a molding compound instead of or in addition to providing the molding film 106 is also possible in other embodiments. Furthermore, further processes, such as curing and / or annealing, can be performed subsequently.

[0091] As in Fig. 6, it is possible to temporarily bond a dicing film 134 to the mold layer 102. In one embodiment, the dicing film 134 can be bonded to the mold layer 102 after performing the method according to Fig. 5 to the mold layer 102 on the wafer 130. Therefore, in Fig. 6 shows the assembly or attachment of the dicing tape or dicing film 134 to the backside die protective mold film 106, which has already been previously bonded to the component wafer 130.

[0092] In another embodiment, it may be advantageous to provide the foils 106, 134 as a preformed double foil, which is then bonded to the (thinned) wafer 130 in one operation (not shown).

[0093] To Fig. To obtain the structure shown in Figure 7, the (optional) carrier wafer 132 can then be removed from the semiconductor wafer 130, since it is no longer required as a carrier for handling. The non-permanent adhesive structure 138 can then also be removed, preferably without leaving residue.

[0094] Thus, the carrier wafer 130 and the adhesive structure 138 can be removed in preparation for the subsequent separation of the manufactured electronic components 100.

[0095] With reference to Fig. 8, the semiconductor wafer 130 on the mold layer 102 can then be separated into a plurality of separate electronic components 100, each having one (or more) of the semiconductor chips 104, a portion of the mold layer 102, a portion of the BEOL structure 110, and one or more protrusions 111. The dicing can be performed, for example, by laser ablation. More generally, the dicing can be performed by mechanical sawing, laser sawing, and / or etching. As shown, the dicing film 134 continues to hold the dicing electronic components 100 together.

[0096] This shows Fig. 8 the separation of the individual semiconductor chips or dies 104 by mechanical sawing, laser sawing or a combination of laser sawing / ablation and mechanical sawing.

[0097] As in Fig. 9, it is then possible to detach the electronic components 100 from the dicing film 134, for example by means of a pick-and-place tool (not shown).

[0098] In other words, the singulation process may be followed by a pick-and-place process to bring the individual electronic components 100 to a destination (e.g., to an encapsulation tool) to subsequently produce a housing 120, as in Fig. 10 or Fig. 11 shown.

[0099] Fig. 10 shows a cross-sectional view of a housing 120 according to an exemplary embodiment.

[0100] The housing 120 can be produced by encapsulating, in particular overmolding, an electronic component 100 (which can be produced in a similar manner as in Fig. 1 or Fig. 9) with a cast encapsulation 122 according to the Fig. 8 and Fig. 9. More specifically, the encapsulation 122 may be a molding compound. The encapsulation 122 may be produced, for example, by injection molding, compression molding, transfer molding, etc.

[0101] The illustrated package 120 thus has an electronic component 100 with a dielectric (e.g., mold) layer 102 and a semiconductor chip 104, as well as a BEOL structure 110 and protrusions 111. The dielectric layer 102 is made, for example, of a temperature-curable material. The semiconductor chip 104 has a low-resistance first section 142 made of crystalline silicon and a high-resistance second section 144, which can be made of a silicon material (e.g., at least partially of crystalline, polycrystalline, and / or amorphous silicon material) with a lower electrical conductivity than the material of the first section 142. As illustrated, the first section 142 has an active region 140 with monolithically integrated circuit elements 148. The second section 144 is arranged directly on (i.e., above or below) the dielectric layer 102. The encapsulation 122 encapsulates the electronic component 100 and a carrier 124.The molding materials of the encapsulation 122 on the one hand and the dielectric layer 102 on the other hand may be different.

[0102] As already mentioned, the housing 120 has an electrically conductive carrier 124, which can be embodied as a leadframe, for example, in the form of a structured copper sheet. Alternatively, the carrier 124 can be a printed circuit board (PCB), a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, etc.

[0103] The carrier 124 is partially enclosed by the encapsulation 122 and partially exposed with respect to the encapsulation 122. Electrically conductive connection structures 145 enable the electrical connection of the housing 120 to an electronic peripheral by soldering, e.g., to a mounting base (such as a printed circuit board (PCB), not shown), on which the housing 120 can be mounted. Furthermore, the carrier 124 is electrically connected to the electronic component 100 by soldering the solder caps 133 of the projections 111 of the electronic component 100 onto a top side of the plate-shaped carrier 124. As a result, the electrically conductive BEOL structure 110 on a main surface of the semiconductor chip 104 is connected to the carrier 124 via the projections 111.

[0104] The housing 120 according to Fig. 10 can thus be formed on the basis of an ultra-thin chip without a carrier plate in the housing only with a molding film 106 as a tiny carrier.

[0105] Fig. 11 shows a cross-sectional view of a housing 120 according to another exemplary embodiment.

[0106] The embodiment of Fig. 11 differs from the embodiment of Fig. 10 in particular by the fact that according to Fig. 11, the dielectric layer 102 is a dual mold layer consisting of a mold plate 108 and a mold foil 106. The mold foil 106 is arranged between the mold plate 108 and the semiconductor chip 104.

[0107] Therefore, the housing 120 can be Fig. 11 can be formed on the basis of an ultra-thin chip with a molding film 106 and an additional molding plate 108 as additional support.

[0108] It should be noted that the term "comprising" does not exclude other elements or features, and "a" or "an" does not exclude a plurality. Also, elements described in connection with different embodiments may be combined.

Claims

[1] An electronic component (100) configured to be encapsulated to form a housing (120), the electronic component (100) comprising: - a molding layer (102), wherein the molding layer (102) comprises or consists of a film-shaped molding film (106); - a semiconductor chip (104) having a low-resistance first section (142) and a high-resistance second section (144), wherein the first section (142) has an active region (140) and the second section (144) is arranged on the mold layer (102); and an electrically conductive back-end-of-line structure (110) on one main surface of the semiconductor chip (104) opposite another main surface of the semiconductor chip (104) on which the mold layer (102) is arranged. [2] The electronic component (100) of claim 1, wherein the mold layer (102) is a double mold layer. [3] Electronic component (100) according to one of claims 1 to 2, wherein the mold layer (102) comprises a resin matrix (150), in particular comprising epoxy resin, and filler particles (152), in particular comprising metal oxide, in the resin matrix (150). [4] Electronic component (100) according to one of claims 1 to 3, wherein the active region (140) comprises at least one integrated circuit element (148), in particular at least one transistor and / or at least one diode. [5] Electronic component (100) according to one of claims 1 to 4, comprising an adhesive layer (154) between the mold layer (102) and the semiconductor chip (104). [6] Electronic component (100) according to one of claims 1 to 5, wherein the active region (140) has a thickness (L) of less than 1 µm, in particular in a range from 50 nm to 500 nm, particularly preferably in a range from 100 nm to 200 nm. [7] Electronic component (100) according to one of claims 1 to 6, wherein the semiconductor chip (104) comprises unprocessed semiconductor material with a thickness (B) of less than 150 µm. [8] Electronic component (100) according to one of claims 1 to 7, wherein the semiconductor chip (104) has a thickness (D) in a range from 1 µm to 200 µm, in particular in a range from 10 µm to 40 µm, particularly preferably in a range from 20 µm to 30 µm. [9] Electronic component (100) according to one of claims 1 to 8, comprising at least one of the following features: the high-resistance second section (144) comprises a semiconductor material with a specific electrical resistance of at least 500 Ωcm, in particular at least 1000 Ωcm; the low-resistance first section (142) comprises a semiconductor material with a specific electrical resistance of less than 100 Ωcm, in particular less than 10 Ωcm; the semiconductor chip (100) is a silicon-on-insulator die; the semiconductor chip (100) contains at least one material from the group consisting of silicon, germanium, gallium nitride, gallium arsenide, indium phosphide, silicon carbide, sapphire, diamond and diamond-like coating. [10] Electronic component (100) according to one of claims 1 to 9, wherein the back-end-of-line structure (110) is directly connected to the active region (140) of the semiconductor chip (104). [11] Electronic component (100) according to one of claims 1 to 10, comprising at least one electrically conductive projection (111) projecting beyond the back-end-of-line structure (110). [12] Electronic component (100) according to one of claims 1 to 11, wherein the semiconductor chip (104) is an active semiconductor chip, in particular a high-frequency semiconductor chip. [13] Electronic component (100) according to one of claims 1 to 12, wherein the mold layer (102) is cured and has adhesive properties in the uncured state. [14] Housing (120), comprising: - an electronic component (100) according to any one of claims 1 to 13, comprising a dielectric layer (102) as the mold layer (102); and - an encapsulation (122) which encapsulates at least a part of the electronic component (100). [15] Housing (120) according to claim 14, wherein the dielectric layer (102) further consists of a curable layer, in particular a temperature-curable layer. [16] Housing (120) according to claim 14 or 15, comprising at least one of the following features: comprising a carrier (124) which is at least partially encapsulated by the encapsulation (122) and is electrically connected to the electronic component (100); wherein the electrically conductive back-end-of-line structure (110) is connected to an at least partially electrically conductive carrier (124); wherein the encapsulation (122) is a molding compound, in particular a molding compound with different material properties than the dielectric layer (102). [17] A method for manufacturing electronic components (100), the method comprising: - Providing a semiconductor wafer (130) having a plurality of semiconductor chips (104), each having a low-resistance first section (142) and a high-resistance second section (144), each of the first sections (142) having an active region (140); - arranging the second sections (144) on a molding layer (102), wherein the molding layer (102) comprises or consists of a film-shaped molding film (106); - arranging an electrically conductive back-end-of-line structure (110) on a main surface of the semiconductor chip (104) opposite another main surface of the semiconductor chip (104) on the mold layer (102); and - subsequently separating the semiconductor wafer (130) and the mold layer (102) into a plurality of separate electronic components (100), each comprising at least one of the semiconductor chips (104) and a portion of the mold layer (102), wherein the mold layer (102) comprises or consists of the film-shaped mold film (106). [18] Method according to claim 17, comprising at least one of the following features: wherein the method comprises temporarily bonding a carrier wafer (132) to the semiconductor wafer (130) prior to arranging and removing the carrier wafer (132) from the semiconductor wafer (130) prior to separating; wherein the method comprises thinning the semiconductor wafer (130), in particular by removing material of at least the second sections (144), before connecting the semiconductor wafer (130) to the mold layer (102); wherein the method comprises temporarily bonding a dicing film (134) to the molding layer (102) before or after the arranging and removing the dicing film (134) from the electronic components (100) during or after the separating; wherein the method comprises embedding electrically conductive protrusions (111) on the electrically conductive back-end-of-line structure (110) on a main surface of the semiconductor wafer (130) into a temporary adhesive structure (138) which in particular connects the semiconductor wafer (130) to a carrier wafer (132); wherein the method comprises separating by at least one of the group consisting of mechanical sawing, laser sawing and etching; wherein the method comprises encapsulating, in particular overmolding, each electronic component (100) with an encapsulation (122), in particular after separation.

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