IMAGE SENSOR DEVICE AND MANUFACTURING METHOD

Abstract

comprising image sensor device (200): a semiconductor layer with a first surface (202F) and a second surface (202B), wherein the second surface (202B) is opposite the first surface (202F); a conductive structure (412) arranged above the first surface (202F), wherein a dielectric layer (408) is arranged between the conductive structure (412) and the first surface (202F); and a pad area with a recess (600) extending through the semiconductor layer (202) from the first surface (202F) to the second surface (202B), wherein the pad area has: - a spacer layer (800) extending along the inner side walls (600S) of the recess (600); - an oxide layer (1100) lining the recess (600) and covering a surface of the dielectric layer (408) above the spacer layer (800); and - a pad structure (1300) extending through the oxide layer (1100) and the dielectric layer (408) to be in physical contact with the conductive structure (412).

Description

TECHNICAL BACKGROUND

[0001] The present disclosure relates generally to semiconductor devices and in particular to image sensor devices and their formation methods.

[0002] Semiconductor image sensors are used to detect incident visible or invisible radiation, such as visible light, infrared light, etc. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications, such as digital cameras, mobile phones, tablets, and eyeglasses. These image sensors use an array of pixels that absorb (e.g., detect) the incident radiation and convert it into electrical signals. Back-illuminated (BSI) image sensor devices are an example of an image sensor device. These BSI image sensor devices can detect light from their back side.

[0003] Semiconductor image sensors are known, for example, from US 2017 / 0 186 802 A1 and US 8426938 B2. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been enlarged or reduced arbitrarily for the sake of clarity. Fig. 1A and Fig. Figure 1B shows a flowchart of an exemplary method for manufacturing an image sensor device according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 and Fig. Figure 15 shows cross-sectional views of an exemplary image sensor device according to some embodiments at various manufacturing stages, produced according to the method of Fig. 1A to 1B is manufactured. Fig. Figure 16 shows a top view of the exemplary image sensor device, which is used in the Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. 15 is shown, according to some embodiments. DETAILED DESCRIPTION

[0005] The present invention provides image sensor devices with the features of claims 1 and 11, as well as a method for manufacturing an image sensor device with the feature of claim 19. Exemplary embodiments are given in the dependent claims. The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting.For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features need not be in direct contact. Additionally, this disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various described embodiments and / or configurations.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here can be interpreted accordingly.

[0007] The terms “approximately” and “essentially” can indicate a value of a given quantity that varies within 5% of the value (e.g. ± 1%, ± 2%, ± 3%, ± 4%, ± 5% of the value).

[0008] In general, a back-illuminated (BSI) image sensor device comprises a semiconductor substrate (e.g., a silicon substrate) with pixels or radiation detection areas formed therein. As disclosed herein, the terms "radiation detection areas" and "pixels" may be used interchangeably. A BSI image sensor device may include a pixel array arranged in the semiconductor substrate. The pixel array is arranged vertically with respect to a multi-layer metallization layer (e.g., one or more interconnect structures) formed on a first surface of the semiconductor substrate. The first surface of the semiconductor substrate is hereby referred to as the "front face" or "front surface" of the semiconductor substrate. The pixel array extends into the semiconductor substrate and is configured to receive radiation (e.g., light) from a second surface of the semiconductor substrate opposite the front face of the semiconductor substrate.through which it receives the radiation. This second surface of the semiconductor substrate, which receives the radiation (and is opposite the front of the semiconductor substrate), is referred to here as the "back side" or "back surface" of the semiconductor substrate.

[0009] The pixels in the semiconductor substrate are electrically insulated by insulating structures, such as deep trench insulation (DTI) structures. Aligned with these insulating structures (and formed on the back side of the semiconductor substrate) are corresponding grid structures that provide optical isolation between adjacent pixels. Adjacent grid structures together form cells. Furthermore, the cells together form a composite grid structure configured to hold color filter material. As described above, the composite grid structure is formed on the back side of the semiconductor substrate.

[0010] Color filter material can be arranged between adjacent grid structures to form color filters. The color filter material can be chosen so that light with a desired wavelength passes through the filter material, while light with other wavelengths is absorbed by the material. For example, a green-light filtering material receiving unfiltered natural light would allow the green light component (wavelengths between approximately 495 nm and approximately 570 nm) to pass through the filter, but would absorb all other wavelengths. The color filters are aligned with the respective pixels so that they deliver filtered light to the corresponding pixels.

[0011] The components of the BSI sensor device (e.g., pixels, transistors, capacitors, memory structures, other chips attached to the BSI sensor device, etc.) can be electrically connected to external devices (e.g., an external circuit) via wire connectors formed on the back of the semiconductor substrate and attached to pad structures. To achieve this, the pad structures of a BSI sensor device extend spatially from the back of the semiconductor substrate to the front of the semiconductor substrate and are electrically connected to the multi-layer metallization layer of the BSI sensor. Thus, the multi-layer metallization layer of the BSI sensor device, which provides an electrical signal connection to the BSI sensor device, can be electrically connected to an external device or circuit via the pad structures. The pad structures can be located at the edge of the BSI sensor device around the pixels or...Radiation detection zones are arranged around them.

[0012] Existing technologies for forming the pad structure in a BSI image sensor device generally create an opening (or recess) extending at least from the back to the front of its semiconductor substrate. This opening can be defined with a depth of up to several micrometers. Such a deep opening can often lead to the formation of one or more cavities in a dielectric layer above and / or below the pad structure. For example, the cavity may form at the corner of the opening, partly due to its considerable depth. Adversely, this cavity can facilitate the penetration of acids or etchants through the dielectric layer into the pad structure or one or more underlying interconnect structures, potentially causing various interconnect problems (e.g., increased contact resistance, increased RC delay, electromigration).Therefore, the existing technologies for manufacturing a BSI image sensor device are not entirely satisfactory.

[0013] The present disclosure provides various embodiments of a BSI image sensor device and their manufacturing methods. The BSI image sensor device disclosed herein includes a spacer layer formed at least around the corner of a recess in which a pad structure is formed. In various embodiments, the spacer layer may, for example, have a tapered profile defined by a lower section that is wider than an upper section. By forming such a spacer layer around the corners of a relatively deep recess, the profile of the recess can be effectively "rounded" or otherwise "improved." As such, by depositing a dielectric layer over the recess, the formation of cavities, which commonly occurs in image sensor devices manufactured by existing technologies, can be avoided.Accordingly, the disclosed BSI image sensor device can be defined as having more reliable pad structures and interconnect structures compared to existing BSI image sensor devices.

[0014] Fig. 1A and Fig. Figures 1B jointly disclose a flowchart of a method 100 for forming a BSI image sensor device according to one or more embodiments of the present disclosure. It is noted that method 100 is merely an example and is not intended to limit the present disclosure. Accordingly, it is understood that further processes before, during, and after method 100 of the Fig. 1A-B may be provided for and that some further processes can only be briefly described here. In some embodiments, processes of method 100 cross-sectional views of a BSI image sensor device at various manufacturing stages, as in the Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. They are shown in 14 and 15 respectively, which are described in more detail below.

[0015] In brief, Method 100 begins with Step 102, in which a number of pixels (or radiation detection areas) are formed on the front face of a semiconductor substrate. Method 100 continues with Step 104, in which one or more insulating areas are formed on the front face. Method 100 continues with Step 106 to form a fixture layer and one or more metallization layers on the front face. Method 100 continues with Step 108 to flip the semiconductor substrate. Method 100 continues with Step 110, in which an opening is formed from the back face of the semiconductor substrate. Method 100 continues with Step 112, in which a first oxide layer is formed. Method 100 continues with Step 114, in which a spacer layer is formed using the first oxide layer.Process 100 continues with step 116, in which a second oxide layer is formed. Process 100 continues with step 118, in which a section of one of the metallization layers is exposed. Process 100 continues with step 120, in which one or more pad structures are formed. Process 100 continues with step 122, in which a dielectric layer is deposited over the one or more pad structures. Process 100 continues with step 124, in which corresponding sections of the one or more pad structures are exposed.

[0016] As mentioned above, show Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. 15 each in a cross-sectional view a section of a BSI image sensor device 200 in different manufacturing stages of the process 100 of Fig. 1. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. Figures 15 have been simplified for better understanding of the concepts of this disclosure. Although the figures show the BSI image sensor device 200, it is understood that the BSI image sensor device 200 may include a number of other devices such as inductors, fuses, capacitors, coils, etc., which are described in the Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. 15 are not shown for the sake of clarity.

[0017] According to process 102 of Fig. 1A is Fig. Figure 2 shows a cross-sectional view of the BSI image sensor device 200 in one of the various fabrication stages, with a number of pixels 204A, 204B, and 204C formed over a front face 202F of a semiconductor substrate (or semiconductor layer) 202. Opposite the front face 202F (e.g., along the Z-axis), the semiconductor substrate 202 has a back face 202B, the BSI image sensor device 200 being configured to receive radiation through it.

[0018] The semiconductor substrate 202 can comprise a bulk semiconductor wafer or an upper layer of a semiconductor-on-insulator (SOI) wafer with a thickness greater than approximately 6 µm (e.g., approximately 6.15 µm, approximately 6.30 µm, approximately 6.50 µm, or approximately 6.70 µm). For example, the semiconductor substrate 202 can comprise a semiconductor material such as silicon, germanium, a compound semiconductor, an alloy semiconductor, any other suitable semiconductor material, and / or combinations thereof. Furthermore, the semiconductor substrate 202 can be an epitaxial material strained for performance enhancement and / or doped with n-type dopants, p-type dopants, or combinations thereof. In various embodiments, the semiconductor substrate 202 can have combinations of p- and n-doped regions.

[0019] The pixels 204A-C are formed in a section of the semiconductor substrate 202, which is referred to here as pixel area 203A. Although three pixels 204A-C in Fig. As shown in Figure 2 and the following cross-sectional figures, it is understood that the BSI image sensor device 200 can contain any desired number of pixels while remaining within the scope of this disclosure. In some embodiments, the pixel region 203A is a central region of the semiconductor substrate 202. For example, the pixel region 203A can correspond to a region in which a pixel array is formed in the BSI image sensor device 200, as shown in the top view of Figure 2. Fig. 16 shown.

[0020] The pixels 203A-C are each configured to detect electromagnetic radiation such as near-infrared light. By way of example, and not limited to, each of the pixels 203A-C incorporates a photodiode structure, such as a pinned photodiode, a photogate, a reset transistor, a source follower transistor, a transfer transistor, another suitable structure, and / or combinations thereof. Furthermore, the pixels 203A-C may sometimes be referred to as "radiation detection devices" or "light sensors." In some embodiments, the pixels 203A-C are formed by doping the semiconductor substrate 202 from the front face 202F. For example, the doping process may involve doping the semiconductor substrate 202 with a p-type dopant such as boron or an n-type dopant such as phosphorus or arsenic. In some embodiments, the pixels 203A-C are formed by a dopant diffusion process and / or an ion implantation process.

[0021] In some embodiments, the semiconductor substrate 202 includes a pad region 203B adjacent to the pixel region 203A. One or more pad structures can be formed in the pad region 203B. Such pad structures can be located at the edge of the semiconductor substrate 202 such that they surround the pixel region 203A. For example, the pad region 203B corresponds to a region in which one or more pad arrays are formed in the BSI image sensor device 200, as shown in the top view of Fig. 16 shown.

[0022] According to process 104 of Fig. 1A is Fig. Figure 3 shows a cross-sectional view of the BSI image sensor device 200 with one or more insulating areas 302 and 304 formed over the front surface 202F in one of the various manufacturing stages. In some embodiments, the insulating area 302 formed in the pad area 203B of the semiconductor substrate 202 can facilitate the formation of the one or more pad structures. In some embodiments, one or more insulating areas 304 can be formed in the pixel area 203A before, during, or after the formation of the insulating area 302 in the pad area 203B. Such insulating areas 304 can isolate the pixels 204A-C from one another. By way of example, and without limitation, the insulating areas 302 and 304 can be formed over respective sections of the front surface 202F.

[0023] In some embodiments, the insulating regions 302 and 304 can be formed by performing at least some of the following processes: forming a patternable layer (e.g., a photoresist (PR) layer) with a structure that defines respective locations of the insulating regions 302 and 304 in the semiconductor substrate 202; etching (e.g., dry etching) the semiconductor substrate 202 using the patternable layer as an etch mask to form recesses; removing (e.g., wet etching) the patternable layer; depositing one or more layers, such as, but not limited to, silicon dioxide, USG, PSG, BPSG, PEOX, FSG, a low-k dielectric (e.g., with a k-value of less than about 3.9), or combinations thereof, as a covering layer to fill the recesses; and planarizing (e.g. by a chemical-mechanical polishing (CMP) process) of the covering layer.

[0024] According to process 106 of Fig. 1A is Fig. Figure 4 shows a cross-sectional view of the semiconductor device 200 with a device layer 400 and one or more metallization layers 410 in one of the various fabrication stages. According to some embodiments, the device layer 400 and the metallization layers 410 can be formed sequentially on or over the front surface 202F of the semiconductor substrate 202. For example, the device layer 400 can contact a specific section of the front surface 202F.

[0025] The device layer 400 can contain one or more semiconductor devices 404 (e.g., field-effect transistors) formed according to a chip layout on the front face 202F of the semiconductor substrate 202. The device layer 400 can also contain additional elements or structures such as doped regions, dummy regions, epitaxial layers, capacitor structures, resistors, etc. These additional elements or structures of the device layer 400 are described in Fig. Figure 4 is not shown for simplicity. In some embodiments, the BSI image sensor device 200 includes vertical conductive structures 406 (e.g., vias) that electrically connect the semiconductor devices 404 and other elements of the device layer 400 to upper metallization layers. The conductive structures 406 can form a section of a middle-of-the-line (MOL) wiring network. In some embodiments, the device layer 400 further includes a nitride layer 402, which is used as an etch stop layer (ESL) in a subsequent etching process during the formation of the pad structures. In some embodiments, the ESL 402 is formed around the semiconductor devices 404, but not between the semiconductor devices 404 and the semiconductor substrate 202.The ESL 402, the semiconductor devices 404 and the conductive structures 406 can be embedded in or covered by a corresponding dielectric layer 408.

[0026] The metallization layers 410 can contain one or more metallization layers, such as metallization layers 410A, 410B, 410C and 41D, as shown in Fig. Figure 4 shows. It is understood that the image sensor device 200 can contain any number of metallization layers while remaining within the scope of this disclosure. In some embodiments, the metallization layer 410A along the Z-axis is a first or bottom metallization layer (sometimes referred to as the "M1 layer"), and the metallization layer 410D is a top metallization layer (sometimes referred to as the "top metal" (TM) layer). The metallization layers 410 can form a section of a BEOL (back-end-of-the-line) wiring network. Each of the metallization layers 410 (e.g., 410A-D) can contain one or more lateral conductive structures 412 (e.g., conductors) embedded in a corresponding dielectric layer 414.In some embodiments, one or more conductive structures and a dielectric layer in which the one or more conductive structures are embedded can sometimes be collectively referred to as a metallization layer.

[0027] Between different metallization layers 410, one or more vertical conductive structures 416 (e.g., vias) can extend through a corresponding dielectric layer 418 such that they electrically connect adjacent metallization layers along the Z-axis. The conductors 412 and vias 416, which are formed, for example, from copper, can sometimes be referred to as copper interconnect structures. Although not shown, in some embodiments each of the copper conductors 412 and copper vias 416 can be surrounded by a (diffusion) barrier layer. The barrier layer can contain a material selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW), and titanium (Ti).In some embodiments, such a barrier layer can sometimes be considered part of the corresponding metallization layer (or the corresponding conductive structure).

[0028] The dielectric layers 408, 414, and 418 can electrically insulate the elements and / or structures therein. In some embodiments, each of the dielectric layers 408, 414, and 418 is a portion of an interplane dielectric (ILD) layer or an intermetal dielectric (IMD) layer. For example, such an ILD or IMD layer contains silicon oxide, USG, BPSG, a low-k dielectric (e.g., with a dielectric constant of less than 3.9), or a stack of dielectrics—for example, a low-k dielectric and another dielectric: (i) a low-k dielectric (e.g., carbon-doped silicon oxide) and a nitrogen-doped silicon carbide; (ii) a low-k dielectric (e.g., carbon-doped silicon oxide) and an oxygen-doped silicon carbide; (iii) a low-k dielectric (e.g. carbon-doped silicon oxide) with silicon nitride; or (iv) a low-k dielectric (e.g.carbon-doped silicon oxide) with silicon oxide.

[0029] In some further embodiments, the device layer 400 and / or the metallization layers 410 can be formed on a separate semiconductor substrate (e.g. different from the semiconductor substrate 202) and then attached to the front face 202F of the semiconductor substrate 202.

[0030] In certain applications of the image sensor device 200, an application-specific integrated circuit (ASIC) and / or a system-on-a-chip (SoC) 420 can be attached to the upper metallization layer 410D. Such a structure may sometimes be referred to as a three-dimensional (3D) stack or integrated 3D circuit. In this respect, one or more bond structures 422 can be used to electrically and mechanically connect the ASIC / SoC 420 to the upper metallization layer 410D. The ASIC / SoC 420 can add functionality to the image sensor device 200 or control functions of the image sensor device 200. In some embodiments, the ASIC / SoC 420 includes metallization layers, semiconductor devices, or memory devices, or it may be a stack of chips such as memory chips, central processing units (CPU) chips, other functional chips (e.g., RF chips), or combinations thereof.

[0031] According to some embodiments, the fabrication of the BSI image sensor device 200 can proceed with the formation of additional structures in or on the semiconductor substrate 202 from the rear side 202B. In this respect, such a partially fabricated BSI image sensor 200 can be rotated (reversed) 180° about the X-axis (as shown in Fig. 5 shown), which also corresponds to process 108 of Fig. 1A corresponds to this.

[0032] After flipping the semiconductor substrate 202, one or more insulating regions 504 are formed, aligned with the insulating regions 304 to further isolate the pixels 204A-C in the pixel region 203A. The insulating regions 504 can contain one or more dielectrics and, for example, form deep trench insulation (DTI) structures. The insulating regions 504 can be formed by etching the semiconductor substrate 202 to create appropriate trenches between the pixels 204A-C. The trenches are then filled with one or more dielectrics. Although not in Fig. As shown in Figure 5, optionally, after the formation of the insulating regions 504, one or more high-k dielectric layers (with a dielectric constant greater than 3.9) can be formed over the insulating regions 504. For example, the high-k dielectric layers can each contain a material selected from: Ta₂O₅, HfO₂, Al₂O₃, and combinations thereof. Such a high-k dielectric layer can be configured to dissipate the charges accumulated in the BSI image sensor device 200.

[0033] In some embodiments, the dielectric layers (including, for example, the dielectric layers forming the insulating regions 504 and one or more optional high-k dielectric layers) can cover both the pixel region 203A and the pad region 204B of the semiconductor substrate 200. Before forming the insulating regions 504 on the back side 202B, the semiconductor substrate 202 can be thinned to a desired thickness T1. By way of example and without limitation, the thickness T1 can be between approximately 2 µm and approximately 6 µm, depending on the application of the BSI image sensor device 200. Thus, it is understood that the thickness T1 can be between any suitable values ​​while remaining within the scope of this disclosure. The thinning of the semiconductor substrate 202 can be achieved by a planarization process (e.g., a CMP process), a re-etching process (e.g., a dry etching process), another thinning process (e.g.,Loops) or a combination thereof can be achieved. Thinning the semiconductor substrate 202 can facilitate the formation of the insulating regions 504 and the subsequent formation of one or more pad structures.

[0034] After forming the insulating regions 504 (and the optional high-k dielectric layers) on the back side 202B, a passivation layer 506 can be deposited over the back side 202B, as shown in Fig. Figure 5 shows that the passivation layer 506 can be a dielectric layer, for example silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the passivation layer 506 is a protective layer or a hard mask (HM) layer that is grown or deposited on both the pixel area 203A and the pad area 203B.

[0035] According to process 110 of Fig. 1A is Fig. Figure 6 shows a cross-sectional view of the BSI image sensor device 200 with a recess (an opening or a trench) 600 in one of the various manufacturing stages. The recess 600 is formed in the pad region 203B such that a section of the dielectric layer 408 is exposed. As shown, the recess 600 can extend through at least the passivation layer 506, the one or more dielectric layers of the insulating regions 504, the semiconductor substrate 202, the insulating region 302, and the ESL 402. In the example where the thinned semiconductor substrate 202 has a thickness T1 of about 6 µm, the recess 600 can be defined with a depth T2 that is significantly greater than 6 µm. It is understood that the depth of the recess 600, according to the thickness of the diluted semiconductor substrate 202, can lie between any suitable values.Depending on the application for which the BSI image sensor device 200 is designed, the thickness of the thinned semiconductor substrate 202 (and the depth of the recess 600) can vary accordingly. For example, if the BSI image sensor device 200 is configured to absorb visible light, the thickness of the thinned semiconductor substrate 202 (and the depth of the recess 600) can be selected to be at least 2 µm.

[0036] The recess 600 can be formed by performing at least some of the following processes: forming a patternable layer (e.g., a photoresist (PR) layer) 602 over the passivation layer 506; patterning the patternable layer 602 in the pad area 203A such that a section of the passivation layer 506 is exposed which is aligned with the insulating area 302; etching (e.g., by one or more dry etching processes) the passivation layer 506, the one or more dielectric layers of the insulating areas 504, the semiconductor substrate 202, the insulating area 302, and the ESL 402 such that a section of the dielectric layer 408 is exposed; and removing the patternable layer 602.

[0037] In particular, the dry etching processes can use one or more different etching gases. For example, the semiconductor substrate 202 material (e.g., silicon) can be etched by a first dry etching process using a gas mixture of chlorine (Cl₂) and HBr, which stops at the insulating layer 302. In some embodiments, such a first dry etching process etches between approximately 20 nm and 30 nm of material from the insulating layer 302 before stopping. It is understood that the first dry etching process can etch the insulating layer 302 to any suitable depth while remaining within the scope of this disclosure. Subsequently, a second dry etching process, e.g., using tetrafluoromethane (CF₄) gas, removes the insulating layer 302 and stops at the ESL 402. A third dry over-etching process, e.g.,Using octafluorocyclobutane (C4F8) gas, the ESL 402 is removed such that the dielectric layer 408 of the device layer 400 is exposed, as shown in . Fig. 6 shown. In other words, one or more etching processes can be terminated when at least a section of the dielectric layer 408 of the device layer 400 in the pad area 203B is exposed through the recess 600.

[0038] According to process 112 of Fig. 1A, is Fig. Figure 7 shows a cross-sectional view of the BSI image sensor device 200 with a first oxide layer 700 in one of the various manufacturing stages. After removal of the structurable layer 602 ( Fig. 6) The first oxide layer 700 can be deposited conformally such that it lines the recess 600 (extends, for example, over a lower surface 600B and inner side walls 600S of the recess 600) and covers the exposed surface of the dielectric layer 408 and the passivation layer 506, as shown in Fig. Figure 7 shows that in some embodiments, the first oxide layer 700 is a silicon oxide dielectric such as PEOX with a thickness in the range of about 100 nm to about 700 nm. It is understood that the thickness of the buffer oxide layer 700 can lie between any suitable values ​​while remaining within the scope of this disclosure. In some further embodiments, the first oxide layer 700 comprises a material selected from USG, PSG, BPSG, FSG, a low-k dielectric, and combinations thereof.

[0039] According to process 114 of Fig. 1A is Fig. Figure 8 shows a cross-sectional view of the BSI image sensor device 200 with a spacer layer 800 in one of the various manufacturing stages. In some embodiments, the spacer layer 800 can be formed by performing at least one etching process 802 (shown by arrows in Figure 8). Fig. 8) are formed. The etching process 802 can be an anisotropic etching process (e.g., a reactive ion etching (RIE) process). As such, the etching process 802 can remove corresponding sections of the first oxide layer 700 that lie above the passivation layer 506 and a section of the lower surface 600B.

[0040] For example, the remaining first oxide layer 700 (i.e., the spacer layer 800) can be configured to extend along at least one section of the inner side wall 600S and cover a section of the bottom surface 600B. As shown, the sections of the inner side wall 600S and the bottom surface 600B are connected such that corners of the recess 600 are covered by the spacer layer 800, while a section of the bottom surface 600B is exposed. Such an exposed section of the bottom surface 600B (i.e., an exposed section of the dielectric layer 408) can facilitate the formation of one or more pad structures upon it, as described below.

[0041] Each of the inner sidewalls 600S can be defined (e.g., constituted) by at least one of: a sidewall of the ESL 402, a sidewall of the semiconductor substrate 202 in the pad region 203B, a sidewall of the one or more layers forming the insulating region 504, or a sidewall of the passivation layer 506. For example, the embodiments shown illustrate Fig. 8 (and the following cross-sectional representations), that the section of the inner sidewalls 600S along which the spacer layer 800 extends includes the sidewall of the ESL 402, the sidewall of the semiconductor substrate 202, and a section of the sidewall of the one or more layers forming the insulating region 504. It is understood, however, that the spacer layer 800 can extend over any combination of the sidewalls of the ESL 402, the semiconductor substrate 202, the one or more layers forming the insulating region 504, the passivation layer 506, and the one or more layers between the insulating regions 504 and the passivation layer 506, while remaining within the scope of this disclosure.

[0042] According to various embodiments, the spacer layer 800 can be defined with a tapered profile. For example, the tapered spacer layer 800 can be configured to have a lower section and an upper section, the lower section being significantly wider (along the X-axis) than the upper section. The width of the spacer layer 800 can gradually increase from the upper section to the lower section. In some embodiments, the spacer layer 800 can have a ratio of the lateral width of the lower section to the width of the upper section that is between approximately 2 and 5, although the ratio may lie in other ranges while remaining within the scope of this disclosure.By forming such a tapered spacer layer 800 in the recess 600, the respective corners of the recess 600 can be filled with at least the lower sections of the spacer layer, effectively rounding the corners. Although the recess 600 may have a profile with a relatively high aspect ratio, it can, as such, strongly prevent the formation of voids in the recess 600 if one or more layers (e.g., as filler) are formed above the recess 600. As a non-restrictive example, the sum of the lateral widths of all the lower sections of the spacer layer 800 can fill an optimal proportion of the lateral width of the recess 600, e.g., between approximately 0.1 and approximately 0.7. If the ratio is too low, voids may still form in one or more subsequently formed layers.On the other hand, if the ratio is too high, there may not be enough space to land one or more subsequently formed pad structures.

[0043] The Fig. Figures 9 and 10 show exemplary profiles of the spacer layer 800 according to different embodiments. With reference to Fig. In section 9, the spacer layer 800 is defined with an arc-shaped profile 900. For example, the profile 900 can have a circular upper surface extending from the lower section to the upper section of the spacer layer 800. Referring to Fig. In section 10, the spacer layer 800 is defined with a faceted profile 1000. For example, the profile 1000 from the lower section to the upper section of the spacer layer 800 can have one or more facets (edges or chamfers) 1000A and 1000B that are connected to each other.

[0044] According to process 116 of Fig. 1B is Fig. Figure 11 shows a cross-sectional view of the BSI image sensor device 200 with a second oxide layer 1100 in one of the various manufacturing stages. In some embodiments, the second oxide layer 1100 can be deposited conformally such that it lines the recess 600 (e.g., at least covering the spacer layer 800) and covers the exposed surface of the dielectric layer 408 and the passivation layer 506, as shown in Fig. Figure 11 shows that the spacer layer 800 is arranged (e.g., inserted) between the inner side wall 600S and the second oxide layer 1100. In some embodiments, the second oxide layer 1100 is a silicon oxide dielectric, such as PEOX, with a thickness in the range of about 100 nm to about 700 nm. It is understood that the thickness of the second oxide layer 1100 can be between any suitable values ​​while remaining within the scope of this disclosure. In some further embodiments, the second oxide layer 1100 comprises a material selected from USG, PSG, BPSG, FSG, a low-k dielectric, and combinations thereof. The second oxide layer 1100 can also comprise one or more other suitable dielectrics while remaining within the scope of this disclosure.

[0045] According to various embodiments, the first oxide layer 700 (the spacer layer 800) and the second oxide layer 1100 can contain the same oxide material, but the first oxide layer 700 can be defined with a higher resistance to various etchants than the second oxide layer 1100. For example, the oxide material of the first oxide layer 700 can have a higher density than the oxide material of the second oxide layer 1100. In another example, the oxide material of the first oxide layer 700 can have a higher dielectric constant than the oxide material of the second oxide layer 1100.

[0046] According to process 118 of Fig. 1B is Fig. Figure 12 is a cross-sectional view of the BSI image sensor device 200 in one of the various manufacturing stages, in which one or more sections of the conductor 412 are exposed in the metallization layer 410A. In some embodiments, one or more dry etching processes based on a structure formed in the recess 600 can be performed on the second oxide layer 1100 and the dielectric layer 408 to expose the one or more sections of the conductor 412. As such, one or more openings 1200 can be formed according to the structure. Once the openings 1200 are formed, the structure (which is formed, for example, in a photoresist layer) can be removed. For example, a dry etching process, e.g.,Using tetrafluoromethane (CF4) gas, a photoresist layer with a structure is exposed to one or more sections of the second oxide layer 1100 and one or more sections of the dielectric layer 408, stopping on the line 412 to form the openings 1200. Once the openings 1200 are formed, the photoresist layer can be removed by acids or etchants. During the etching of the second oxide layer 1100 and the dielectric layer 408, the spacer layer 800 can, according to various embodiments, remain covered (e.g., intact) by the second oxide layer 1100.

[0047] According to process 120 of Fig. 1B is Fig. Figure 13 shows a cross-sectional view of the BSI image sensor device 200 with one or more pad structures 1300 at one of the various manufacturing stages. The pad structure 1300 is configured to be in physical contact with the conductor 412 in the metallization layer 410A. In some embodiments, a metal layer can be deposited to fill the openings 1200 and can subsequently be patterned in the recess 600 to form the pad structure 1300. For example, the patterning of the metal layer can be carried out by one or more lithography processes followed by one or more etching processes. In some embodiments, the pad structure 1300 contains a metal alloy such as aluminum copper (AlCu). However, this is not limiting, and other suitable metals or metal alloys can be used to form the pad structure 1300.

[0048] According to process 122 of Fig. 1B is Fig. Figure 14 shows a cross-sectional view of the BSI image sensor device 200 with a dielectric layer 1400 in one of the various manufacturing stages. In some embodiments, the dielectric layer 1400 (e.g., a USG layer or another oxide) is deposited on the pad structure 1300. A top surface of the dielectric layer 1400 can be removed by a CMP process, which polishes and removes deposited portions of the dielectric layer 1400 on the second oxide layer 1100.

[0049] According to process 124 of Fig. 1B is Fig. Figure 15 shows a cross-sectional view of the BSI image sensor device 200 in one of the various manufacturing stages, showing an opening 1500 extending through the dielectric layer 1400. In some embodiments, the dielectric layer 1400 is structured such that the opening 1500 is formed to expose a section of the pad structure 1300. By way of example, and not limited to, a wire connector, a solder ball, and / or a connecting bump, which are in Fig. The components not shown in section 15 are formed in the opening 1500. According to some embodiments, such a connector structure electrically connects the conductor 412 of the metallization layers 410A to one or more external components via the pad structure 1300.

[0050] Referring to Fig. Figure 16 shows a top view of the BSI image sensor device 200 from the rear side 202B of the semiconductor substrate 202. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 to Fig. Figure 15 shows cross-sectional views of the BSI image sensor device 200 taken along line AA'. As shown, the BSI image sensor device 200 can include further pixels and pad structures substantially similar to pixels 204A-C and pad structure 1300, respectively. According to various embodiments, such pixels can form a pixel array 1602 laterally surrounded by one or more pad arrays 1604, each containing one or more of the pad structures 1300. In some embodiments, such pad arrays 1604 can be arranged around an edge of the semiconductor substrate 202.

[0051] In one aspect of the present disclosure, an image sensor device is disclosed. The image sensor device comprises a semiconductor layer with a first surface and a second surface, the second surface being opposite the first surface. The image sensor device includes a conductive structure arranged above the first surface, with a dielectric layer arranged between the conductive structure and the first surface. The image sensor device includes a pad region with a recess extending through the semiconductor layer from the first surface to the second surface.The pad area further includes: a spacer layer extending along inner sidewalls of the recess; an oxide layer lining the recess above the spacer layer; and a pad structure extending through the oxide layer and the dielectric layer in such a way as to be in physical contact with the conductive structure.

[0052] In another aspect of the present disclosure, an image sensor device is disclosed. The image sensor device has several pixels arranged above (relative to structures to be developed later: below) a first surface of a semiconductor layer. The image sensor device includes a device layer arranged above the first surface. The image sensor device has several metallization layers arranged above the device layer. One of the metallization layers, which is closer to the first surface than any of the other several metallization layers, has at least one conductive structure. The image sensor device includes an oxide layer arranged above a second surface of the semiconductor layer, the second surface being opposite the first surface, the oxide layer also lining a recess extending through the semiconductor layer.The image sensor device includes a spacer layer arranged between the inner sidewalls of the recess and the oxide layer. The image sensor device includes a pad structure extending through the oxide layer and the device layer such that the pad structure is in physical contact with the at least one conductive structure.

[0053] In another aspect of the present disclosure, a method comprises forming multiple pixels above (or below) a first surface of a semiconductor layer, configured to absorb radiation from a second surface of the semiconductor layer. The second surface of the semiconductor layer is opposite the first surface of the semiconductor layer. The method comprises forming a fixture layer above the first surface of the semiconductor layer. The method comprises forming a metallization layer above the fixture layer. The method comprises etching the second surface of the semiconductor layer to form a recess, the recess being laterally separated from the multiple pixels. The method comprises forming a spacer layer extending along the inner sidewalls of the recess.The method comprises forming an oxide layer over the second surface, wherein the spacer layer is arranged between the inner sidewalls and the oxide layer. The method comprises etching the oxide layer and a portion of the device layer such that a section of the metallization layer is exposed. The method comprises depositing a conductive material such that a pad structure is formed which is electrically connected to the exposed portion of the metallization layer.

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