SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising: an active pattern (102) protruding from a substrate (100); a silicon liner (110) having a crystalline structure conformal to the surfaces of the active pattern (102) and the substrate (100); an insulating layer (112) on the silicon liner (110); an insulating pattern (116) on the insulating layer (112) to fill a trench (104) adjacent to the active pattern (102); and a transistor containing a gate structure (130) on the silicon liner (110) and Impurity regions (132a, 132b) adjacent to the respective sides of the gate structure (130), wherein the active pattern (102) is isolated from other active patterns and extends in one direction, wherein a length in a direction of the long axis of the active pattern (102) is greater than a length in a direction of the short axis of the active pattern (102) perpendicular to the direction of the long axis, and wherein a first thickness of the silicon liner (110) on a sidewall of the active pattern (102) in the long axis direction differs from a second thickness of the silicon liner (110) on a sidewall of the active pattern (102) in the short axis direction.

Description

BACKGROUND1. AreaThe exemplary embodiments relate to semiconductor devices and methods of manufacturing the same. In particular, example embodiments relate to semiconductor devices including an active pattern and a method of manufacturing the same.2. Description of the Prior ArtSince semiconductor devices are highly integrated recently, it may be advantageous to reduce the area of an upper surface of each active pattern. Further, the distance between the active patterns can be reduced. Each of the active patterns should have few or no defects and have a sufficient area for forming transistors and contact terminals.U.S. Pat. No. 9,257,305 B2 discloses methods for producing a thin film, comprising supplying an organic silicon source to form a silicon seed layer directly on a surface of a silicon substrate; and supplying an inorganic silicon source to deposit a silicon film directly on the surface of the silicon substrate.SUMMARYExemplary embodiments provide methods for manufacturing a semiconductor device having excellent characteristics.Example embodiments provide a semiconductor device. Exemplary embodiments are set forth in the claims.In accordance with the exemplary embodiments, a semiconductor device is provided that may include an active pattern, a silicon liner, an insulating layer, an insulating pattern, and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be conformally on the surfaces of the active pattern and the substrate. The insulating layer may be formed on the silicon liner. The isolation pattern may be formed on the isolation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be located on the silicon liner, and the impurity regions may be located on the silicon liner adjacent to both sides of the gate structure and on the active structure adjacent to both sides of the gate structure.As described above, the active structure according to the exemplary embodiments may include the first active pattern formed by etching the substrate and the liner layer having a crystalline structure. Further, the insulating layer may be formed on the liner layer having a crystalline structure. The liner layer having a crystalline structure may have excellent surface roughness and may contain no defects. Therefore, the semiconductor device formed on the active structure can have high performance. Since the area of the top surface of the first active pattern is not reduced, transistors and contact terminals can be easily formed on the active structure.BRIEF DESCRIPTION OF THE DRAWINGSExemplary embodiments will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings. FIGS. 1-37 illustrate non-limiting example embodiments as described herein. FIGS. 1 to 10 and FIGS. 12 to 24 are cross-sectional views, plan views, and perspective views illustrating a vertical semiconductor device according to exemplary embodiments; FIG. 11 is an apparatus for manufacturing the semiconductor device; FIGS. 25 to 27 are plan views and perspective views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments; FIGS. 28 to 30 are a plan view and perspective views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments; FIGS. 31 to 35 are cross-sectional views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments; and FIGS. 36 and 37 are cross-sectional views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments.DESCRIPTION OF EMBODIMENTSExemplary embodiments will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings.Hereinafter, two directions substantially parallel to an upper surface of the substrate and crossing each other are defined as a first direction and a second direction, respectively. The first and second directions are substantially perpendicular to each other. An oblique direction with respect to the first direction is defined as a third direction, and a direction perpendicular to the third direction is defined as a fourth direction. The third and fourth directions are substantially parallel to the upper surface of the substrate.FIGS. 1 to 10 and FIGS. 12 to 24 are cross-sectional views, plan views, and perspective views illustrating a vertical semiconductor device according to exemplary embodiments. FIG. 11 is a device used for manufacturing the semiconductor device.Specifically, FIGS. 1, 7, 12 and 23 are plan views. FIGS. 2 to 5, 8 to 10, 13, 14, 16 to 19, 21, 22, and 24 are cross-sectional views, and FIGS. 6, 10, 15, and 20 are perspective views. FIGS. 2, 4, 8, 13, 16, and 18 are cross-sectional views taken along line I-I' of FIG. 1, FIG. 3, FIG. 5, FIG. 9, FIG. 14, FIG. 17, FIG. 19, FIG. 21, and FIG. 24 are cross-sectional views taken along line II-II' of FIG. 1, FIG. 22 is a cross-sectional view taken along line III-III' of FIG. 1.The semiconductor device may include a dynamic random access memory (DRAM=dynamic random access memory).Referring to FIGS. 1 to 3, a substrate 100 may include a single crystal semiconductor material. The substrate 100 may include a semiconductor material such as silicon, germanium, silicon germanium, and / or the like. In example embodiments, the substrate 100 may be made of single crystal silicon.A hard mask pattern (not shown) may be formed on the substrate 100. The substrate 100 may be etched using the hard mask pattern as an etch mask to form first active patterns 102 and a trench 104. The first active patterns 102 may protrude from the substrate 100, and the trench 104 may be formed between the first active patterns 102. In example embodiments, the first active pattern 102 may serve as an active region for forming a DRAM device. Thereafter, the hard mask pattern may be removed.Hereinafter, the substrate 100 and the first active patterns 102 will be described as different elements. However, the first active patterns 102 may be formed by etching the substrate 100, so that the first active patterns 102 and the substrate 100 may include the same semiconductor material. In addition, the first active patterns 102 and the substrate 100 may be the same single body.The first active patterns 102 may be insulated from each other, and the first active patterns 102 may be arranged regularly. The sidewalls of the trench 104 may correspond to the sidewalls of the first active patterns 102, and the bottom of the trench 104 may correspond to a surface of the substrate 100.In example embodiments, the first active pattern 102 may extend in the third direction. That is, a length in the third direction of the first active pattern 102 may be greater than a length in the fourth direction of the first active pattern 102. Therefore, in the first active pattern 102, the third direction may be a long axis direction and the fourth direction may be a short axis direction.When the process is performed, the surface of the substrate 100 and the surface of the first active pattern 102 may be exposed. In this case, at least a portion of the surface of the substrate 100 and the surface of the first active pattern 102 may be irregularly oxidized. That is, a native oxide layer 106 may be formed on the surfaces of the substrate 100 and the first active pattern 102. The native oxide layer 106 may be discontinuous and irregular, or alternatively appear as islands of oxide material.Referring to FIGS. 4 to 6, the native oxide layer 106 and the first active pattern 102 formed on the substrate 100 may be removed. The removal process of the native oxide layer 106 may include a dry or wet etch process.In example embodiments, a first process of introducing etch source gases onto the surfaces of the substrate 100 and the first active pattern 102 may be performed to remove the native oxide layer 106. Therefore, contact of at least one of the etching source gases with the surfaces of the substrate 100 and the first active pattern 102 can be made. In example embodiments, the etching source gases may include Ar, NH3, and / or NF3.Thereafter, a second process of applying heat and pressure to the substrate 100 and the first active pattern 102 may be performed. The native oxide layer 106 may be removed by the first and second processes.In example embodiments, the first process of introducing the etching source gases and the second process of applying heat and pressure may be performed in different etching chambers, respectively. That is, the first process may be performed in a first etching chamber and the second process may be performed in a second etching chamber. The first process and the second process may be performed in situ without a vacuum brake.The first operation may be carried out at room temperature. For example, the first operation may be performed at a temperature ranging from about 5° C. to about 30° C. The first process may also be performed at a pressure in the range of about 0.5 Torr to about 10 Torr.When the terms "about" or "substantially" are used in this specification in connection with a numerical value, the associated numerical value is intended to include a manufacturing or operating tolerance (e.g., ±10%) around the specified numerical value. Moreover, when the words "generally" and "substantially" are used in connection with geometric shapes, it is intended that the accuracy of the geometric shape is not required, but that the margin for the shape is within the scope of the disclosure. Further, whether numerical values or shapes are modified as "approximately" or "substantially", it is understood that these values and shapes are understood to include manufacturing or operating tolerance (e.g., ±10%) around the specified numerical values or shapes.The second process may be performed at a temperature in a range of about 100° C. to about 200° C., and the second process may be performed at a pressure in a range of about 1 Torr to about 20 Torr.Referring to FIGS. 7 to 10, a semiconductor liner having a crystalline structure may be formed on the substrate 100 and the first active pattern 102 having no native oxide layer.In example embodiments, the semiconductor liner may be a crystalline silicon liner. Hereinafter, the semiconductor liner is referred to as a first silicon liner 110.The first silicon liner 110 may be formed by crystal growth from the surfaces of the substrate 100 and the first active pattern 102. Therefore, the first silicon liner 110 may have a crystalline structure substantially the same as the crystalline structures of the substrate 100 and the first active pattern 102.The first silicon liner 110 may cover entire surfaces of the first active patterns 102 and the substrate 100. That is, a barrier layer may not be formed on the substrate 100 and the first active pattern 102, so that the first silicon liner 110 may be formed by crystal growth from the entire surfaces of the substrate 100 and the first active pattern 102. In other words, the first silicon liner may directly make contact with the substrate 100 and the first active pattern 102.The first silicon liner 110 may not be amorphous, but may already have a crystalline structure in the deposition process. Therefore, in a subsequent process, a crystallization process cannot be performed. Therefore, an amorphous silicon layer having a partially and / or non-uniformly crystallized surface in the crystallization process can be avoided, and thus poor surface roughness of the silicon liner can be reduced.Moreover, the surface of the first silicon liner 110 may be uniformly oxidized in a subsequent process.During the formation of the first silicon liner 110, when the native oxide layer 106 is on the surfaces of the substrate 100 and the first active patterns 102, the first silicon liner 110 may include crystal defects formed by the deposition process of the first silicon liner 110. Therefore, when the first silicon liner 110 is formed, the native oxide layer 106 may not be on the surfaces of the substrate 100 and the first active pattern 102. That is, the deposition process of the first silicon liner 110 and the removal of the native oxide layer 106 may be performed in situ, and the processes may be performed without a vacuum brake.To form the first silicon liner 110 having a crystalline structure, the deposition process may be performed at high temperature and high pressure, and the conditions of the deposition process may be adjusted to increase a partial pressure of the silicon source gas.In particular, the process of forming the first silicon liner 110 may be performed at a pressure in the range of about 50 Torr to about 500 Torr. The process temperature may be in the range of about 400° C. to about 800° C.The silicon source gas may be monosilane, disilane, dichlorosilane (DCS), and / or the like, for example. The silicon source gas may be introduced at a flow rate of about 30 standard cubic centimeters per minute (sccm) to about 150 sccm.The silicon source gas may not contain carbon. Further, in the deposition process, a process for forming a silicon seed layer containing carbon may be omitted. Therefore, the first silicon liner 110 may not contain carbon. As a result, defects caused by the carbon contained in the first silicon liner can be reduced.To meet the temperature and pressure conditions, the volume in the deposition chamber for forming the first silicon liner 110 may be about 20L or less. For example, the volume may be about 5L to about 20L. During the coating process, the nitrogen gas may be introduced into the deposition chamber to achieve a flow rate of about 100 sccm or more. For example, the nitrogen gas may be introduced at a flow rate of about 100 sccm to about 10000 sccm.As described above, the first silicon liner 110 having no crystal defects may be formed, and the first silicon liner 110 may have a crystal structure substantially the same as that of the substrate 100 and the first active pattern 102.In example embodiments, the first silicon liner 110 may be uniformly grown on the surfaces of the first active pattern 102 and the substrate 100. Therefore, the first silicon liner 110 may be conformally formed on the sidewall and the top surface of the first active pattern 102 and the surface of the substrate 100 to obtain a uniform thickness.The first silicon liner 110 may have a thickness such that the surface of the first active pattern 102 is not oxidized during the formation of the first insulating layer. The first silicon liner 110 may be formed so as not to completely fill the trench 104. Therefore, the first silicon liner 110 may be formed to have a thickness less than half of the minimum width of the trench 104. In example embodiments, the first silicon liner 110 may be formed to have a thickness in the range of about 30 Å to about 100 Å.FIG. 11 is an example of a device for etching the native oxide layer and depositing the first silicon liner.Referring to FIG. 11, the apparatus may include a first etching chamber 20 aand a second etching chamber 20 bfor the etching process and a deposition chamber 22 for the deposition process. Each of the first and second etching chambers 20 aand 20 band the deposition chamber 22 may be connected to a transfer chamber 16. The transfer chamber 16 may include transfer members 18 for transferring the substrate 100.The substrate 100 may be selectively transferred sequentially or alternatively into the first etching chamber 20 a, the second etching chamber 20 b, and the deposition chamber 22, while the vacuum may be maintained by the transfer chamber 16. The transfer chamber 16 may be connected to the loadlock chamber 14. The loadlock chamber 14 may be connected to a transfer port 12 and a loadlock port 10 including a cassette or a FOUP for receiving the substrate 100.Next, the etching of the native oxide film and the deposition process of the first silicon liner using the device will be briefly described.To perform the etching process illustrated with reference to FIGS. 4 to 6, the substrate may be loaded into the first etching chamber 20 aand the etching source gas may be introduced into the first etching chamber 20 a. Thereafter, the substrate is transferred to the second etching chamber 20b via the transfer chamber 16. The native oxide film formed on the substrate and the first active patterns can be removed by controlling the temperature and the pressure in the second etching chamber 20 b.Thereafter, to perform the coating operation illustrated with reference to Figs. 7 to 10, the substrate may be loaded via the transfer chamber 16 onto a holder in the deposition chamber 22. The first silicon liner may be formed in the deposition chamber 22.As described above, the vacuum may be maintained during the etching process and the deposition process so that the surfaces of the first active pattern 102 may not be oxidized during the movement of the substrate between the chambers. Therefore, defects such as crystal defects or particle adsorption caused by the native oxide layer on the surfaces of the first active patterns 102 can be reduced.Referring to FIGS. 12 to 15, a first insulating layer 112 may be formed on the first silicon liner 110 by a deposition process. The first insulating layer 112 may include silicon oxide. The deposition process may include a chemical vapor deposition process or an atomic layer deposition process.When the first insulating layer 112 is formed, the surface of the first silicon liner 110 may be oxidized by heat and oxygen sources. Through the oxidation, the first silicon liner 110 may be converted into a second silicon liner 110 ahaving a thickness less than that of the first silicon liner 110.That is, when the deposition process is performed, the first insulating layer 112 may be conformally formed on the second silicon liner 110 a. In this case, the first insulating layer 112 may include an oxide layer formed by oxidation of the surface of the first silicon liner 110, and an oxide layer formed by the deposition process.The first silicon liner 110 may have a crystalline structure, and a native oxide layer may not be on the surface of the first silicon liner 110. Therefore, the surface of the first silicon liner 110 can be uniformly oxidized, so that the surface of the second silicon liner 110 aafter oxidation can have excellent roughness. Also, crystal defects can hardly occur due to the irregular oxidation of the second silicon liner 110 a.The first silicon liner 110 may serve as a layer to prevent oxidation of the first active pattern 102 in subsequent operations. When the first insulating layer 112 is formed, the first active pattern 102 may not be oxidized. The first active pattern 102 may not be consumed by the oxidation, and therefore an area of the upper surface of the first active pattern 102 may not be reduced.In example embodiments, the thickness of the first insulating layer 112 may be greater than the thickness of the second silicon liner 110 a.The second silicon liner 110 amay cover entire surfaces of the first active pattern 102 and the substrate 100. In example embodiments, the second silicon liner 110 amay have a uniform thickness from the surfaces of the first active pattern 102 and the substrate.In some example embodiments, when forming the first insulating layer 112, the first silicon liner 110 may be fully oxidized. In this case, the entire first silicon liner 110 may be used up, so that the first insulating layer 112 may be formed on the first active pattern 102.Referring to FIGS. 16 and 17, a barrier layer 114 may be conformally formed on the first insulating layer 112. Thereafter, an insulating layer 116 may be formed on the barrier layer 114 to completely fill the trench 104.In example embodiments, the barrier layer 114 may include silicon nitride and / or silicon oxynitride. The barrier layer 116 may include silicon oxide.The process of forming the barrier layer 114 and the insulating layer 116 may include a chemical vapor deposition process or an atomic layer deposition process.In some example embodiments, the barrier layer 114 may not be formed. In this case, only the barrier layer 116 may be formed on the first insulating layer 112. Also, the first insulating layer 112 and the insulating layer 116 may be formed by the same deposition process.Referring to FIGS. 18 and 19, a top surface of the insulating layer 116 may be planarized until a top surface of the barrier layer 114 may be exposed to form an insulating pattern 116 a. The isolation pattern 116 amay fill the trench 104. The planarization process may be performed by a chemical mechanical polishing (CMP=chemical mechanical polishing) process and / or an etch-back process. Thereafter, an exposed portion of the barrier layer 114 may be etched to form a barrier layer pattern 114 a.Therefore, in the trench 104, the second silicon liner 110 a, the first insulating layer 112, the barrier pattern 114 a, and the insulating pattern 116 amay be formed. The second silicon liner 110 aand the first insulating layer 112 may also be formed on an upper surface of the first active pattern 102.The first active pattern 102 and the second silicon liner 110 amay serve as an active region. The first insulating layer 112, the barrier layer pattern 114 a, and the insulating pattern 116 aformed in the trench 104 may serve as a field region. During the field region forming process, an area of the upper surface of the first active pattern 102 and a volume of the first active pattern 102 may not be reduced, so that the active region may have a sufficient area.Referring to FIG. 20, the first active pattern 102, the second silicon liner 110 a, the first insulating layer 112, the barrier pattern 114 a, and the insulating pattern 116 amay be partially etched to form a gate trench 120 extending in the first direction.A bottom surface of the gate trench 120 may be higher than a bottom surface of the isolation pattern 116 a.In example embodiments, a bottom surface of the gate trench 120 disposed in the field region may be lower than a bottom surface of the gate trench 120 disposed in the active region. Therefore, portions of the first active pattern and the isolation pattern may be exposed on the bottom of the gate trench 120. The first active pattern 102 formed in the gate trench 120 may protrude from the isolation pattern 116 aformed in the gate trench 120. Portions of the first active pattern 102 and the second silicon liner 110 amay be exposed at the sidewalls of the gate trench 120 in the first direction.Referring to FIGS. 21 and 22, a gate structure 130 is formed in the gate trench 120.The gate structure 130 may include a gate insulating film pattern 130 a, a gate electrode 130 b, and a capping film pattern 130 c.The gate insulating film pattern 130 amay be conformally formed on surfaces of the first active pattern 102 and the second silicon liner 110 ain the gate trench 120. The gate electrode 130 bmay make contact with the gate insulating film pattern 130 a, and the gate electrode 130 bmay be formed in the gate trench 120. In example embodiments, the gate electrode 130 bmay include a metal. The gate electrode 130 bmay have a stacked structure including a barrier metal layer and a metal layer. For example, the gate electrode 130 bmay include tungsten nitride or tungsten. In some example embodiments, the gate electrode 130 bmay include polysilicon.The capping layer pattern 130 cmay be formed on the gate electrode 130 bto fill the gate trench 120. The capping layer pattern 130 cmay include a nitride, e.g., a silicon nitride.First and second impurity regions 132 aand 132 bserving as source / drain regions may be formed on the first active pattern 102 and the second silicon liner 110 aadjacent to both sides of the gate structure 130. For example, the first impurity region 132 amay include a side adjacent to the active pattern 102, a side adjacent to a side of the gate structure 130, and at least one side adjacent to the second silicon liner 110 a. Further, the second impurity region 132 bmay include a side adjacent to the active pattern 102, a side adjacent to another side of the gate structure 130, and at least one side adjacent to the second silicon liner 110 a.Referring to FIGS. 23 and 24, a first interlayer insulating layer 140 may be formed on the gate structure 130, the first active pattern 102, the second silicon liner 110 a, the first insulating layer 112, the barrier pattern 114 a, and the insulating pattern 116 a. The first interlayer insulating layer 140 may include an oxide such as silicon oxide.A first contact terminal 142 may be formed by the first interlayer insulating film 140, the first insulating film 112, and the second silicon liner 110 a. The first contact terminal 142 may make contact with the first impurity region 132 a. A bit line 144 may be formed on the first contact terminal 142 and the first interlayer insulating layer 140. The bit line 144 may extend in the second direction.The bit line 144 may be formed to make contact with a top surface of the first contact terminal 142. A hard mask pattern (not shown) may be formed on the bit line 144. Spacers (not shown) may be formed on the sidewalls of the bit lines 144 and the hard mask patterns.A second interlayer insulating layer 146 covering the bit line 144 may be formed on the first interlayer insulating layer 140.A second contact terminal 148 may be formed by the second interlayer insulating film 146, the first interlayer insulating film 140, the first insulating film 112, and the second silicon liner 110 a. The second contact terminal 148 may make contact with the second impurity region 132 b. The second contact terminal 148 may be formed so that a short-circuit fault cannot occur between the second contact terminal 148 and the bit line 144.As described above, the oxidation of the surface of the first active pattern 102 can hardly occur during the processes. Therefore, an area of the upper surface of the first active pattern 102 may not be reduced. The first and second contact terminals 142 and 148 may be formed on the first active pattern 102 to obtain a sufficient area margin. Since the area of the upper surface of the first active pattern 102 is sufficient, the resistances of the first and second contact terminals 142 and 148 can be reduced.A capacitor 150 may be formed to contact the second contact terminal 148. The capacitor 150 may include a lower electrode 150 a, a dielectric layer 150 b, and an upper electrode 150 c.The semiconductor device may have the following structural features. The structural features of the semiconductor device can be mostly described in the process of manufacturing the semiconductor device. Therefore, repetitive descriptions may be omitted below and only important parts will be described with reference to the drawings.Referring to FIGS. 20 to 24, the first active patterns 102 may be formed on the substrate 100. Between the first active patterns 102, the trench 104 may be formed.The second silicon liner 110 acovering the surface of the first active pattern 102 may be formed on the first active pattern 102. The second silicon liner 110 amay be conformally formed on the surface of the first active pattern 102. The second silicon liner 110 amay cover entire surfaces of the first active pattern 102 and the substrate 100.The second silicon liner 110 amay include crystalline silicon.The first insulating layer 112 may be formed on the second silicon liner 110 a. The first insulating layer 112 may include silicon oxide. At least portions of the first insulating layer 112 may be formed by oxidizing the surface of a silicon liner.In example embodiments, a thickness of the first insulating layer 112 may be greater than a thickness of the second silicon liner 110 a.The barrier pattern 114 aand the isolation pattern 116 amay be formed on the first insulating layer 112 to fill the trench 104.The gate trench 120 may be formed at portions of the first active pattern 102, the second silicon liner 110 a, the first insulating layer 112, the barrier pattern 114 a, and the insulating pattern 116 a, and the gate trench may extend in the first direction.The gate structure 130 may be formed in the gate trench 120. The gate structure 130 may include a gate insulating film pattern 130 a, a gate electrode 130 b, and a capping film pattern 130 c.In example embodiments, the bottom of the gate trench 120 in the field region may be lower than the bottom of the gate trench 120 in the active region.Therefore, the first active pattern 102 and the second silicon liner 110 amay be exposed on both sides in the first direction in the gate trench 120.That is, the gate insulating film pattern 130 acontacts the first active pattern 102 and the second silicon liner 110 a, which are exposed by the gate trench 120. Since the roughness of the surface of the second silicon liner 110 ais very good and the second silicon liner does not have crystal defects, crystal defects may not be included in the gate insulating film pattern 130 a. Therefore, the leakage currents of the transistor caused by the gate insulating film pattern 130 acan be reduced.First and second impurity regions 132 aand 132 bserving as source / drain may be formed on the first active pattern 102 and the second silicon liner 110 aadjacent to both sides of the gate structure 130.The first interlayer insulating layer 140 may be formed on the gate structure 130, the first active pattern 102, the second silicon liner 110 a, the first insulating layer 112, the barrier pattern 114 a, and the insulating pattern 116 a.The first contact terminal 142 may be formed by the first interlayer insulating film 140, the first insulating film 112, and the second silicon liner 110 a. The first contact terminal may make contact with the first impurity region 132 a. The bit line 144 may be formed by the first contact terminal 142 and the first interlayer insulating layer 140.The second interlayer insulating layer 146 covering the bit line 144 may be formed on the first interlayer insulating layer 140.The second contact terminal 148 may be formed by the second interlayer insulating film 146, the first interlayer insulating film 140, the first insulating film 112, and the second silicon liner 110 a. The second contact terminal 148 may make contact with the second impurity region 132 b.The capacitor 150 may make contact with the second contact terminal 148.Therefore, the first and second contact terminals 142 and 148 may be formed on the first active pattern 102. The first active pattern 102 may have a sufficient area to form the first and second contact terminals 142 and 148.In addition, crystal defects included in the gate insulating film pattern 130 amay decrease, so that the leakage currents of the transistor caused by the gate insulating film pattern 130 amay be reduced. Thereby, a failure in reliability of the transistor can be reduced.FIGS. 25 to 27 are plan views and perspective views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments. FIG. 25 is a plan view. Figs. 26 and 27 illustrate only the layers formed on the sidewalls of one of the active patterns.The method may be substantially the same as the method of manufacturing the semiconductor device illustrated with reference to FIGS. 1 to 24, except for the formation of the first silicon liner.First, the same operations as those illustrated with reference to FIGS. 1 to 6 may be performed. Therefore, the native oxide layer 106 (referring to FIG. 3 ) formed on the surfaces of the substrate 100 and the first active pattern 102 may be removed.Referring to FIGS. 25 and 26, a first silicon liner 210 having a crystalline structure may be formed on the substrate 100 and the first active pattern 102 having no native oxide layer.The first silicon liner 210 may be formed by crystal growth from the surfaces of the substrate 100 and the first active pattern 102. In this case, a growth rate of the crystal may be different depending on the surface of the first active pattern 102.In exemplary embodiments, when the first silicon liner 210 is crystal-grown, the growth rate at the sidewall surfaces of the first active pattern in the long axis direction (i.e., a third direction) and the growth rate at the sidewall surfaces of the first active pattern in the short axis direction (i.e., a fourth direction) may be different from each other. For example, the growth rate of the first silicon liner 210 on the sidewalls of the first active pattern 102 in the third direction may be higher than the growth rate of the first silicon liner 210 on the sidewalls of the first active pattern 102 in the fourth direction. Therefore, a first thickness d 1 of the first silicon liner 210 at the sidewall of the first active pattern 102 in the third direction may be greater than a second thickness d 2 of the first silicon liner 210 at the sidewall of the first active pattern 102 in the fourth direction.The growth rate of the first silicon liner 210 may be varied by controlling a temperature and a pressure during the deposition process of the first silicon liner 210. Moreover, the growth rate of the first silicon liner 210 may be varied by process conditions for removing the native oxide layer.In example embodiments, the process for removing the native oxide layer may be substantially the same as illustrated with respect to FIGS. 4-6. That is, the first process may be carried out at room temperature. For example, the first operation may be performed at a temperature ranging from about 5° C. to about 30° C. The first process may also be performed at a pressure in the range of about 0.5 Torr to about 10 Torr. The second process may be performed at a temperature in the range of about 100° C. to about 200° C. Also, the second process may be carried out at a pressure in the range of about 1 Torr to about 20 Torr. When the native oxide layer is removed by the process conditions, the deposition process may be performed at a temperature in the range of about 400° C. to about 490 ° C. and a pressure in the range of about 50 Torr to 150 Torr.Referring to FIG. 27, the first insulating layer 112 may be formed on the first silicon liner 210 by a deposition process. When the deposition process is performed, the first silicon liner 210 may be oxidized to reduce the thickness of the first silicon liner 210. Therefore, the first silicon liner 210 may be converted into the second silicon liner 210 a. The first insulating layer 112 may be formed on the second silicon liner 210 a.In this case, the first silicon liner 210 is oxidized to a uniform thickness. Therefore, a thickness of the second silicon liner 210 aformed on the sidewalls of the first active pattern 102 in the long axis direction and a thickness of the second silicon liner 210 aformed on the sidewalls of the first active pattern 102 in the short axis direction may be different from each other. That is, a third thickness d 3 of the second silicon liner 210 aon the sidewall of the first active pattern 102 in the third direction may be greater than a fourth thickness d 4 of the second silicon liner 210 bon the sidewall of the first active pattern 102 in the fourth direction.A thickness of the first insulating layer 112 may be greater than a thickness of the second silicon liner 210 a.Thereafter, the same operations as those illustrated with reference to FIGS. 16 to 24 may be performed. Therefore, an active region having a sufficient area in the third direction can be formed.The semiconductor device may have a structure substantially the same as a structure of a semiconductor device illustrated with reference to FIGS. 23 and 24. However, in the second silicon liner 210 a, the third thickness d 3 of the second silicon liner 210 aat the sidewall of the first active pattern 102 in the third direction may be greater than the fourth thickness d 4 of the second silicon liner 210 ain the fourth direction at the sidewalls of the first active pattern 102. Therefore, an area of the first active pattern 102 for forming the first and second contact terminals 142 and 148 can be sufficiently secured.FIGS. 28 to 30 are a plan view and perspective views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments. FIG. 28 is a plan view. Figs. 29 and 30 illustrate only the layers formed on the sidewalls of one of the active patterns.The method may be substantially the same as the method of manufacturing the semiconductor device illustrated with reference to FIGS. 1 to 24, except for the formation of the first silicon liner.First, the same operations as those illustrated with reference to FIGS. 1 to 6 may be performed. Therefore, the native oxide layer 106 (related to FIG. 3 ) formed on the surfaces of the substrate 100 and the first active pattern 102 may be removed.Referring to FIGS. 28 and 29, the first silicon liner 310 having a crystalline structure may be formed on the substrate 100 and the first active pattern 102 without a native oxide layer.In example embodiments, a growth rate of the first silicon liner 310 on the sidewalls of the first active pattern 102 in the third direction may be lower than a growth rate of the first silicon liner 310 on the sidewalls of the first active pattern 102 in the fourth direction. Therefore, a first thickness d 1 of the first silicon liner 310 on the sidewall of the first active pattern 102 in the third direction may be less than a second thickness d 2 of the first silicon liner 310 on the sidewall of the first active pattern 102 in the fourth direction.The growth rate of the first silicon liner 310 may be varied by controlling the temperature and pressure during the deposition process of the first silicon liner 310. In addition, the growth rate of the first silicon liner 310 may be changed by controlling the process conditions for the removal of the native oxide layer.In example embodiments, the process for removing the native oxide layer may be substantially the same as the processes illustrated with reference to FIGS. 4-6. When the native oxide layer is removed by the process conditions, the deposition process may be performed at a temperature in the range of about 490° C. to 700° C. and a pressure of about 50 Torr to about 150 Torr.Referring to FIG. 30, the first insulating layer 112 may be formed on the first silicon liner 310 by a deposition process. When the deposition process is performed, the first silicon liner 310 may be oxidized to reduce the thickness of the first silicon liner 310. Therefore, the first silicon liner 310 may be converted into the second silicon liner 310 a. Further, the first insulating layer 112 may be formed on the second silicon layer 310 a.In this case, the first silicon liner 310 is oxidized to a uniform thickness. Therefore, a thickness of the second silicon liner 310 aformed on the sidewalls of the first active pattern 102 in the long axis direction and a thickness of the second silicon liner 310 aformed on the sidewalls of the first active pattern 102 in the short axis direction may be different from each other. That is, a third thickness d 3 of the second silicon liner 310 aon the sidewall of the first active pattern 102 in the third direction may be less than a fourth thickness d 4 of the second silicon liner 310 aon the sidewall of the first active pattern 102 in the fourth direction.Further, a thickness of the first insulating layer 112 may be greater than a thickness of the second silicon liner 310 b.Thereafter, the same operations as those illustrated with reference to FIGS. 16 to 24 may be performed. Thereby, an active region having a sufficient area in the fourth direction can be formed.The semiconductor device may have a structure corresponding to the structure of a semiconductor device illustrated with reference to FIGS. 23 and 24. However, in the second silicon liner 310 a, the third thickness d 3 of the second silicon liner 310 aon the sidewall of the first active pattern 102 in the third direction may be less than a fourth thickness d 4 of the second silicon liner on the sidewall of the first active pattern 102 in the fourth direction. Therefore, the first active pattern 102 may have a sufficient surface area for forming the transistor and the first and second contact terminals 142 and 148.FIGS. 31 to 35 are cross-sectional views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments.The semiconductor device may be a fin field effect transistor.Referring to FIG. 31, a hard mask pattern (not shown) may be formed on the substrate 100, and the substrate 100 may be etched using the hard mask pattern as an etching mask to form first active patterns. The first active patterns 402 may be formed to protrude from the substrate 100.In example embodiments, the first active patterns 402 may extend in the second direction. The first active patterns 402 may be spaced apart from each other in the first direction. The trench 404 may be formed between the first active patterns 402.Referring to FIG. 32, the same operations illustrated with reference to FIGS. 4 to 10 may be performed on the first active pattern 402 and the substrate 100. Therefore, the first silicon liner 406 may be formed on the surfaces of the first active patterns 402 and the substrate 100.Referring to FIG. 33, the insulating layer may be formed on the first silicon liner 406 to sufficiently fill the trench 404 by a deposition process.When the deposition process for forming the insulating layer 410 is performed, the surface of the first silicon liner 406 may be oxidized to reduce the thickness of the first silicon liner 406. Therefore, the first silicon liner 406 may be converted into the second silicon liner 406 a. That is, the insulating layer 410 may be formed on the second silicon liner 406 a.The insulating layer 410 may include an oxide layer formed by oxidation of a surface of the first silicon liner 406 and an oxide layer formed by the deposition process. The oxide layers included in the insulating layer 410 may include substantially the same material, e.g., silicon oxide.Referring to FIG. 34, the insulating layer 410 may be planarized until a top surface of the second silicon liner 406 amay be exposed. The planarization process may include a chemical mechanical polishing (CMP=chemical mechanical polishing) process and / or an etch back process.Then, a portion of the insulating layer 410 may be etched to expose the second silicon liner 406 aformed on the upper sidewall of the first active pattern 402 to form the insulating pattern 410 a. The isolation pattern 410 amay fill a lower portion of the trench 404. That is, the second silicon liner 406 amay be exposed on the insulating pattern 410 a.Referring to FIG. 35, a gate structure 420 is formed on the exposed surfaces of the second silicon liner 406 aand the insulating pattern 410 a. The gate structure 420 may include a gate insulating film pattern 420 a, a gate electrode 420 b, and a capping film pattern 420 c.The first and second impurity regions serving as the source / drain may be formed on the first active pattern 402 and the second silicon liner 406 aadjacent to the both sides of the gate structure 420.Although not illustrated, contact terminals making contact with the first and second impurity regions and the gate electrode 420 bmay be formed.The second silicon liner 406 amay be formed such that the area of the first active pattern 402 may not be reduced. Therefore, an area for forming transistors and contact terminals can be sufficiently secured. In the semiconductor device, the gate insulating film pattern 420 amay be formed on the second silicon liner 406 a. Thereby, crystal defects included in the gate insulating film pattern 420 amay decrease, so that the leakage currents of the transistor caused by the gate insulating film pattern 420 amay be reduced. Further, the reliability failure of the transistor can be reduced.FIGS. 36 and 37 are cross-sectional views illustrating steps of a method of manufacturing a semiconductor device according to example embodiments.Referring to FIG. 36, a hard mask pattern (not shown) may be formed on the substrate 100, and the substrate 100 may be etched using the hard mask pattern as an etching mask to form first active patterns. The first active patterns 102 may protrude from the substrate 100. In example embodiments, the first active patterns 102 may be isolated from each other. A longitudinal direction of each of the first active patterns 102 may be the first direction.Thereafter, the same operations as those illustrated with reference to FIGS. 4 to 10 may be performed. Therefore, the first silicon liner may be formed on the surfaces of the first active patterns 102 and the substrate 100.Subsequently, an insulating layer 450 may be formed on the first silicon liner to sufficiently fill the trench 404 by a deposition process. When the insulating layer 450 is formed, a thickness of the first silicon liner may be reduced by oxidation of a surface of the first silicon liner. Therefore, the first silicon liner may be converted into the second silicon liner 110 a. The first insulating layer 450 may be formed on the second silicon liner 110 a.Referring to FIG. 37, the insulating layer 450 may be planarized until an upper surface of the second silicon liner 110 amay be exposed. The planarization process may include a chemical mechanical polishing (CMP=chemical mechanical polishing) process and / or an etch back process.The gate structure 460 may be formed on the second silicon liner 110 a. The gate structure 460 may include a gate insulating film pattern 460 a, a gate electrode 460 b, and a capping film pattern 460 c.In example embodiments, the gate structure 460 may be formed on the second silicon liner 110 aand the insulating layer 450 ato cross the first active pattern 102.The first and second impurity regions 462 aand 462 b, which serve as the source / drain, may be formed on the second silicon liner 110 aand the substrate 100 adjacent to both sides of the gate structure 460. Although not illustrated, contact terminals may be formed to make contact with the first and second impurity regions 462 aand 462 band the gate electrode 460 b, respectively.Therefore, a planar transistor may be formed on the second silicon liner 110 a.As described above, in exemplary embodiments, the area of the active region may be sufficiently secured. Therefore, the semiconductor device having excellent characteristics can be formed on the active region.

Claims

A semiconductor device comprising: an active pattern (102) protruding from a substrate (100); a silicon liner (110) having a crystalline structure conformal on the surfaces of the active pattern (102) and the substrate (100); an insulating layer (112) on the silicon liner (110); an insulating pattern (116) on the insulating layer (112) to fill a trench (104) adjacent to the active pattern (102); and a transistor including a gate structure (130) on the silicon liner (110) and impurity regions (132a, 132b) adjacent to the respective sides of the gate structure (130), wherein the active pattern (102) is insulated from other active patterns and extends in a direction, wherein a length in a long axis direction of the active pattern (102) is greater than a length in a short axis direction of the active pattern (102) perpendicular to the long axis direction, and wherein a first thickness of the silicon liner (110) on a sidewall of the active pattern (102) in the long axis direction is different from a second thickness of the silicon liner (110) on a sidewall of the active pattern (102) in the short axis direction.The semiconductor device of claim 1, wherein the silicon liner (110) has a crystalline structure that matches the crystalline structures of the active pattern (102) and the substrate (100).The semiconductor device according to claim 1, wherein the thickness of the insulating layer (112) is greater than the thickness of a silicon liner (110).The semiconductor device of claim 1, wherein the silicon liner (110) covers entire surfaces of the active pattern (102) and the substrate (100).The semiconductor device according to claim 1, wherein the gate structure (130) includes a gate insulating film pattern (130a), a gate electrode (130b), and a capping film pattern, and the gate insulating film pattern (130a) makes contact with a portion of the silicon liner (110).The semiconductor device of claim 1, wherein portions of the active pattern (102), the silicon liner (110), and the isolation pattern (116) include a gate trench (120) extending in a first direction, and the gate structure (130) is formed in the gate trench (120).The semiconductor device of claim 6, wherein the active pattern (102) and the silicon liner (110) are exposed by the gate trench (120), and a portion of the gate structure (130) makes contact with the silicon liner (110) in the gate trench (120).The semiconductor device according to claim 1, wherein a first thickness of the silicon liner (110) at a sidewall of the active pattern (102) in the long axis direction is greater than a second thickness of the silicon liner (110) at a sidewall of the active pattern (102) in the short axis direction.The semiconductor device of claim 1, wherein a first thickness of the silicon liner (110) at a sidewall of the active pattern (102) in the long axis direction is less than a second thickness of the silicon liner (110) at a sidewall of the active pattern (102) in the short axis direction.The semiconductor device of claim 9, further comprising: a barrier pattern (114a) between the insulating layer (112) and the insulating pattern (116).The semiconductor device according to claim 1, further comprising: a first interlayer insulating layer (140) covering the silicon liner (110), the insulating pattern (116), and the gate structure (130); a contact terminal passing through the first interlayer insulating layer (140) to make contact with the impurity regions (132a, 132b).The semiconductor device according to claim 1, further comprising: a first interlayer insulating film covering the silicon liner, the insulating pattern, and the gate structure; first and second contact terminals passing through the first interlayer insulating film to make contact with that of the corresponding impurity region; a bit line electrically connected to the first contact terminal; and a capacitor electrically connected to the second contact terminal.

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