Semiconductor device and method for manufacturing the semiconductor device

Abstract

Device (100; 300), comprising: an SOI structure (104) comprising a substrate (106), an insulating layer (108) over the substrate (106) and a semiconductor layer (110) over the insulating layer (108), wherein the semiconductor layer (110) has a first conductivity region (112) and a second conductivity region (114) which are at least partially located within the semiconductor layer (110); a gate structure (116) which is arranged above the semiconductor layer (110) and between the first conductivity region (112) and the second conductivity region (114); a first conductor element (118) that is arranged through the semiconductor layer (110) and the insulating layer (108) of the SOI structure (104) to electrically contact the substrate (106); a second conductor element (120) arranged to electrically contact the gate structure (116); a conductive element (126) that connects the first conductor element (118) and the second conductor element (120) in order to electrically couple the first conductor element (118) and the second conductor element (120); a third conductor element (122) arranged to electrically contact the second conductivity area (114), wherein the third conductor element (122) is electrically insulated from the first conductor element (118) and the second conductor element (120); and a fourth conductor element (124) arranged through the semiconductor layer (110) and the insulating layer (108) of the SOI structure (104) to electrically contact the substrate (106), wherein the fourth conductor element (124) is electrically insulated from the first conductor element (118), the second conductor element (120) and the third conductor element (122).

Description

Technical area

[0001] The present invention relates generally to semiconductor devices and methods of manufacturing the semiconductor devices. background

[0002] Semiconductor devices are widely used in many applications, such as communication or signal amplification. Switching devices, such as radio frequency (RF) switching devices, are one type of semiconductor device commonly used in modern communication systems. To date, the design and manufacture of switching devices with ultra-wide bandwidth and good linearity remains a challenge. In recent years, silicon-on-insulator (SOI) technology has been adopted for the design of switching devices. By manufacturing switching devices using SOI technology, the performance of switching devices can be improved due to the reduced parasitic capacitance and lower substrate loss in the SOI structures. However, switching devices with SOI structures often suffer from problems such as current leakage caused by plasma charging during the wafer manufacturing process.These problems can lead to nonlinearity in the switching devices and reduce the power handling capacity of the switching devices.

[0003] Document DE 11 2016 005 679 T5 discloses a device comprising a high-resistance semiconductor substrate, an insulating layer disposed on the substrate, an active layer disposed over the insulating layer and comprising active regions and insulating regions of the device, a transistor formed in an isolated portion of the active layer, the transistor comprising a drain region, a source region, and a gate channel region, and a first conductive structure. The first conductive structure resistively connects one of: a) a drain contact or a source contact; and b) a gate contact to the semiconductor substrate. The first conductive structure comprises a first conductive connection connecting a) and b) to a first conductive contact.The first conductive contact extends through the active layer in a region of the active layer outside the isolated region of the active layer and through the insulation layer to make contact with the semiconductor substrate.

[0004] An integrated circuit is known from US Pat. No. 9,472,512 B1. This circuit comprises a substrate comprising a handle layer, a buried oxide layer (BOX), and a semiconductor layer, wherein the buried oxide layer is positioned between the handle layer and the semiconductor layer, an electronic component lying above the buried oxide layer on a semiconductor layer side of the buried oxide layer, a gate line electrically connected to the electronic component, a body line electrically connected to the electronic component, a first via BOX contact electrically connecting the gate line to the handle layer, and a second via BOX contact electrically connecting the body line to the handle layer.

[0005] From the document US 2008 / 0 012 072 A1, a component formed on a solid substrate is known, comprising a bulk substrate, a buried insulating layer, and an active layer. The component comprises a transistor formed in an isolated portion of the active layer, the transistor comprising a gate electrode and a source region, a first conductive bulk substrate contact extending through the active layer and the buried insulating layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulating layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.

[0006] It is therefore desirable to provide an improved device that can overcome the above-mentioned problems. Summary

[0007] According to various non-limiting embodiments, a device having a semiconductor-on-insulator (SOI) structure is provided according to independent claim 1. More advantageous embodiments thereof are defined in dependent claims 2 to 6.

[0008] According to various non-limiting embodiments, a method according to independent claim 7 is provided. More advantageous embodiments thereof are defined in dependent claims 8 to 14.

[0009] According to various non-limiting embodiments, a structure having a plurality of devices is provided according to independent claim 15. A more advantageous embodiment thereof is defined in dependent claim 16. Short description of the drawings

[0010] In the drawings, reference characters generally refer to the same parts throughout the several views. Also, the drawings are not necessarily to scale, emphasis generally being placed upon illustrating the principles of the invention. Embodiments of the invention will now be illustrated, by way of example only, with reference to the following drawings, in which: Fig. 1 shows a cross-sectional view of a device according to various non-limiting embodiments. Fig. 2A to 2G show cross-sectional views illustrating a method of manufacturing the device of Fig. 1 according to various non-limiting embodiments; Fig. 3 shows a cross-sectional view of a device according to alternative, non-limiting embodiments; Fig. 4 is a schematic diagram of a double-pole double-throw switch (DPDT switch) having a plurality of devices similar to the device of Fig. 3 shows various non-limiting embodiments; Fig. 5 an enlarged view of a branch of the DPDT switch from Fig. 4 shows; Fig. 6 is a cross-sectional view of a device from the branch of Fig. 5 shows; Fig. 7 shows current-voltage graphs of a switch structure according to the prior art and a switch structure comprising a plurality of devices of Fig. 1 includes; Fig. 8 graphs showing the output power at a compression of 1 dB of a prior art switch structure and a switch structure with a majority of the devices of Fig. 1; and Fig. 9A shows graphs illustrating the second harmonics of a prior art switch structure and a switch structure having a plurality of the devices of Fig. 1, and Fig. 9B shows graphs illustrating the third harmonics of a prior art switch structure and a switch structure having a plurality of the devices of Fig. 1 represent. Detailed description

[0011] The embodiments generally relate to devices, such as semiconductor devices. In particular, some embodiments relate to semiconductor devices that may include transistors. In various non-limiting embodiments, the semiconductor devices may be used as switching devices, such as RF switching devices such as RF switching transistors. The switching devices may be used in various types of switch structures, such as dual-pole, dual-throw (DPDT) switch structures, which in turn may be used in communication systems. In various non-limiting embodiments, the semiconductor devices may be used in amplifiers. For example, the semiconductor devices may be used in low-noise amplifiers and / or power amplifiers, which in turn may be used in various applications, such asin communication systems and medical instruments.

[0012] According to various non-limiting embodiments, a device may comprise a semiconductor-on-insulator (SOI) structure comprising a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer. The semiconductor layer may comprise a first conductivity region and a second conductivity region disposed at least partially within the semiconductor layer.The device may further comprise a gate structure disposed over the semiconductor layer and between the first conductivity region and the second conductivity region; a first conducting element disposed through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate; a second conducting element disposed to electrically contact the gate structure; and a conducting element connecting the first conducting element and the second conducting element to electrically couple the first conducting element and the second conducting element.

[0013] According to various non-limiting embodiments, a method may include: providing a semiconductor-on-insulator (SOI) structure having a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer; forming a first conductivity region and a second conductivity region at least partially within the semiconductor layer; forming a gate structure over the semiconductor layer and between the first conductivity region and the second conductivity region; forming a first conductor element through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate; forming a second conductor element to electrically contact the gate structure; and forming a conductive element to connect the first conductor element and the second conductor element for electrically coupling the first conductor element and the second conductor element.

[0014] According to various non-limiting embodiments, a diameter of the first conductor element may be larger than a diameter of the second conductor element.

[0015] According to various non-limiting embodiments, the semiconductor layer of the SOI structure may further comprise an isolation region disposed at least partially therein. The first conductor element may be disposed through the isolation region.

[0016] According to various non-limiting embodiments, the method may further comprise forming an isolation region at least partially within the semiconductor layer of the SOI structure. Forming the first conductor element may comprise forming the first conductor element through the isolation region.

[0017] According to various non-limiting embodiments, the insulation region may extend at least partially into the insulator layer.

[0018] According to the invention, the device further comprises a third conductor element arranged to electrically contact the second conductivity region. The third conductor element is electrically insulated from the first conductor element and the second conductor element.

[0019] According to the invention, the device further comprises a fourth conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate. The fourth conductor element is electrically insulated from the first conductor element and the second conductor element.

[0020] According to various non-limiting embodiments, the device may further comprise a fifth conductor element arranged to electrically contact the first conductivity region. The fifth conductor element may be electrically insulated from the first conductor element and the second conductor element.

[0021] According to various non-limiting embodiments, the device may be an RF switching transistor, a single-pole multi-throw switch (e.g., a single-pole double-throw switch or a single-pole quadruple-throw switch), or a multi-pole multi-throw switch (e.g., a double-pole double-throw switch).

[0022] According to various non-limiting embodiments, forming the first conductor element may include a first mask, and forming the second conductor element may include a second mask. The first mask may be different from the second mask.

[0023] According to various non-limiting embodiments, forming the first conductor element and the second conductor element may comprise: forming a first opening for the first conductor element with the first mask; and forming a second opening for the second conductor element with the second mask; and simultaneously depositing a conductive material in the first opening and the second opening to form the first conductor element and the second conductor element, respectively.

[0024] According to various non-limiting embodiments, the method may further comprise: forming an insulating layer over the semiconductor layer such that the gate structure is at least partially disposed within the insulating layer; forming the first mask by depositing a first mask material over the insulating layer; and forming the second mask by depositing a second mask material over the insulating layer and in the first opening.

[0025] According to the invention, the method further comprises forming a third conductor element for electrically contacting the second conductivity region. The third conductor element is electrically insulated from the first conductor element and the second conductor element.

[0026] According to the invention, the method further comprises forming a fourth conductor element through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate. The fourth conductor element is electrically insulated from the first conductor element and the second conductor element.

[0027] According to various non-limiting embodiments, the method may further comprise forming a fifth conductor element to electrically contact the first conductivity region. The fifth conductor element may be electrically insulated from the first conductor element and the second conductor element.

[0028] According to various non-limiting embodiments, a structure may include a plurality of devices. One or more of the devices may include a semiconductor-on-insulator (SOI) structure comprising a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer. The semiconductor layer may include a first conductivity region and a second conductivity region disposed at least partially within the semiconductor layer.One or more of the devices may further comprise a gate structure disposed over the semiconductor layer and between the first conductivity region and the second conductivity region; a first conduction element disposed through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate; a second conduction element disposed to electrically contact the gate structure; and a conducting element connecting the first conduction element and the second conduction element to electrically couple the first conduction element and the second conduction element.

[0029] According to various non-limiting embodiments, the one or more devices of the structure may comprise an RF switching transistor, a single-pole multi-throw switch (e.g., a single-pole double-throw switch or a single-pole quadruple-throw switch), or a multi-pole multi-throw switch (e.g., a double-pole double-throw switch), or combinations thereof.

[0030] Aspects of the present invention, as well as certain features, advantages, and details thereof, are described in more detail below with reference to the non-limiting examples illustrated in the accompanying drawings. No description is given of known materials, manufacturing tools, processing techniques, etc. in order not to obscure the invention with unnecessary detail. It is to be understood, however, that the detailed description and specific examples, while indicating aspects of the invention, are intended to be illustrative and not limiting. Various substitutions, modifications, additions, and / or arrangements within the spirit and / or scope of the underlying inventive concepts will be apparent to those skilled in the art from this description.

[0031] Approximate language, as used throughout this specification and in the claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by one or more terms such as "approximately" is not limited to the precise value stated. In some cases, approximate language may correspond to the precision of an instrument used to measure the value.

[0032] The terminology used herein is for the purpose of describing particular examples only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It is further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “includes” and “containing”) are open-ended linking verbs.A method or apparatus that "comprises," "has," "includes," or "contains" one or more steps or elements has those one or more steps or elements, but is not limited to having only those one or more steps or elements. A step of a method or an element of an apparatus that "comprises," "has," "includes," or "contains" one or more features has those one or more features, but is not limited to having only those one or more features. Furthermore, a device or structure that is configured in a particular way is configured at least in that way, but may also be configured in other ways not listed.

[0033] As used herein, the term "connected," when referring to two physical elements, means a direct connection between the two physical elements. However, the term "coupled" can mean a direct connection or a connection through one or more intermediate elements.

[0034] As used herein, the terms "can" and "may" denote a possibility of occurrence within a set of circumstances; a possession of a particular property, characteristic, or function; and / or qualify another verb by expressing at least one ability, capacity, or possibility associated with the qualified verb. Accordingly, the use of "can" and "may" indicates that a modified term appears to be appropriate, capable, or suitable for a stated ability, function, or use, recognizing that the modified term may sometimes not be appropriate, capable, or suitable under certain circumstances.For example, an event or capability may be expected under certain circumstances, while under other circumstances the event or capability may not occur - this distinction is captured by the terms 'may' and 'can'.

[0035] Fig. 1 shows a cross-sectional view of a device 100 according to various non-limiting embodiments. In various non-limiting embodiments, the device 100 may be a semiconductor device having a transistor. For example, the device 100 may comprise an n-type metal oxide semiconductor (NMOS) or a p-type metal oxide semiconductor (PMOS). In various non-limiting embodiments, the device 100 may be a switching device for use in a switch structure. For example, the device 100 may comprise a switching transistor. The device 100 may, for example, be an RF switching device such as an RF switching transistor. The device 100 may, for example, be a single-pole multi-throw switch (e.g., a single-pole double-throw (SPDT) switch, a single-pole quadruple-throw (SPDT) switch) or a multi-pole multi-throw switch (e.g.,a double-pole double-throw (DPDT) switch). In various non-limiting embodiments, the apparatus 100 may be used to manufacture a low-noise amplifier. In various non-limiting embodiments, the apparatus 100 may be used to manufacture a power amplifier.

[0036] According to the presentation in Fig. 1, in various non-limiting embodiments, device 100 may include a semiconductor-on-insulator (SOI) structure 104. SOI structure 104 may include a substrate 106, an insulator layer 108 over substrate 106, and a semiconductor layer 110 over insulator layer 108. In various non-limiting embodiments, substrate 106 may be referred to as a handle substrate.

[0037] In various non-limiting embodiments, the semiconductor layer 110 may include a first conductivity region 112 and a second conductivity region 114 disposed at least partially within the semiconductor layer 110. The first conductivity region 112 may be a source region, and the second conductivity region 114 may be a drain region. However, in alternative non-limiting embodiments, the first conductivity region 112 may be a drain region, and the second conductivity region 114 may be a source region. A silicide layer 142 may be disposed over the first and second conductivity regions 112, 114.

[0038] In various non-limiting embodiments, the semiconductor layer 110 of the SOI structure 104 may further comprise a first isolation region 134, a second isolation region 136, a third isolation region 138, and a fourth isolation region 140 at least partially disposed therein. Each of the first isolation region 134, the second isolation region 136, the third isolation region 138, and the fourth isolation region 140 may extend at least partially into the insulator layer 108. For example, as shown in Fig. 1, each isolation region 134, 136, 138, 140 may extend through the entire semiconductor layer 110 and a portion of the insulator layer 108. Furthermore, each isolation region 134, 136, 138, 140 may taper toward the substrate 106. In various non-limiting embodiments, the second isolation region 136 may be disposed between the first isolation region 134 and the first conductivity region 112. For example, as shown in Fig. 1, the second isolation region 136 may be disposed adjacent to the first conductivity region 112 and in contact with the first conductivity region 112. However, in alternative, non-limiting embodiments, the second isolation region 136 may be spaced apart from the first conductivity region 112. In various non-limiting embodiments, the third isolation region 138 may be disposed between the fourth isolation region 140 and the second conductivity region 114. For example, as shown in Fig. 1, the third isolation region 138 may be disposed adjacent to the second conductivity region 114 and spaced apart from the second conductivity region 114. However, in alternative, non-limiting embodiments, the third isolation region 138 may be in contact with the second conductivity region 114.

[0039] With reference to Fig. 1, in various non-limiting embodiments, the device 100 may include a gate structure 116 disposed above the semiconductor layer 110 and between the first conductivity region 112 and the second conductivity region 114. As shown in Fig. 1, the gate structure 116 may include a gate oxide layer 116a and a gate element 116b disposed over the gate oxide layer 116a. The gate oxide layer 116a may be disposed over the semiconductor layer 110. The device 100 may further include a first spacer 144 and a second spacer 146 disposed adjacent to the gate element 116b. In various non-limiting embodiments, a further silicide layer 148 may be disposed over the gate element 116b.

[0040] In various non-limiting embodiments, the device 100 may further comprise a first conductor element 118 disposed through the semiconductor layer 110 and the insulator layer 108 of the SOI structure 104 to electrically contact the substrate 106. With reference to Fig. 1, for example, the first conductive element 118 may be arranged through the first isolation region 134, the insulator layer 108, and a portion of the substrate 106 to electrically contact the substrate 106. In various non-limiting embodiments, the device 100 may further comprise a second conductive element 120 arranged to electrically contact the gate structure 116. For example, the second conductive element 120 may contact the conductive silicide layer 148 to electrically contact the gate element 116b of the gate structure 116. In various non-limiting embodiments, the device 100 may further comprise a third conductive element 122 arranged to electrically contact the second conductive region 114. As shown in Fig. 1, the third conductor element 122 may contact the conductive silicide layer 142 to electrically contact the second conductivity region 114. In various non-limiting embodiments, the device 100 may further comprise a fourth conductor element 124 disposed through the semiconductor layer 110 and the insulator layer 108 of the SOI structure 104 to electrically contact the substrate 106. For example, with reference to Fig. 1 extend through the fourth insulation region 140, the insulator layer 108 and a part of the substrate 106 to electrically contact the substrate 106.

[0041] In various non-limiting embodiments, the second conductor element 120 and the third conductor element 122 may be normal contacts; whereas the first conductor element 118 and the fourth conductor element 124 may be through-body contacts (TBCs). In various non-limiting embodiments, the design rules for TBCs may not be as stringent as the design rules for normal contacts. For example, the pitch requirements for TBCs may not be as stringent as the pitch requirements for normal contacts. Therefore, in various non-limiting embodiments, TBCs may be larger than normal contacts. In various non-limiting embodiments, the diameters of the first conductor element 118 and the fourth conductor element 124 may be approximately the same, and the diameters of the second conductor element 120 and the third conductor element 122 may be approximately the same.In various non-limiting embodiments, a diameter of the first conductor element 118 may be greater than a diameter of the second conductor element 120. The diameter of the first conductor element 118 may also be greater than a diameter of the third conductor element 122. In various non-limiting embodiments, a diameter of the fourth conductor element 124 may be greater than a diameter of the second conductor element 120 and a diameter of the third conductor element 122. In various non-limiting embodiments, a diameter of the first conductor element 118 may be in the range of about 0.28 µm to about 0.4 µm, a diameter of the second conductor element 120 may be in the range of about 0.12 µm to about 0.20 µm, a diameter of the third conductor element 122 may be in the range of about 0.12 µm to about 0.20 µm, and a diameter of the fourth conductor element 124 may in the range of about 0.28 µm to about 0.4 µm.In various non-limiting embodiments, a diameter of the first conductor element 118 may have a ratio of about 1.5 to about 2.5 to a diameter of the second conductor element 120, a diameter of the first conductor element 118 may have a ratio of about 1.5 to about 2.5 to a diameter of the third conductor element 122, a diameter of the fourth conductor element 124 may have a ratio of about 1.5 to about 2.5 to a diameter of the second conductor element 120, and a diameter of the fourth conductor element 124 may have a ratio of about 1.5 to about 2.5 to a diameter of the third conductor element 122. However, the diameters of the conductor elements 118, 120, 122, 124 may be different in alternative non-limiting embodiments.

[0042] In various non-limiting embodiments, the device 100 may further include a first insulating layer 150 disposed over the SOI structure 104. For example, as shown in Fig. 1, the first insulating layer 150 may be disposed over the semiconductor layer 110 of the SOI structure 104. Each conductor element 118-124 may be spaced apart from one another at least partially within the first insulating layer 150. In various non-limiting embodiments, the device 100 may further include a second insulating layer 160 disposed over the first insulating layer 150.

[0043] The device 100 may also include a first conductive element 126, a second conductive element 128, and a third conductive element 130 disposed at least partially within the second insulating layer 160. In various non-limiting embodiments, the conductive elements 126, 128, 130 may be spaced apart from each other. As shown in Fig. 1, in various non-limiting embodiments, the first conductive element 126 may connect the first conductive element 118 and the second conductive element 120 to electrically couple the first conductive element 118 and the second conductive element 120. For example, the first conductive element 118 and the second conductive element 120 may each be connected to the first conductive element 126, and the first conductive element 126 may extend along a width of the second insulating layer 160. In various non-limiting embodiments, the third conductive element 122 may be electrically insulated from the first conductive element 118 and the second conductive element 120. For example, as in Fig. 1, the third conductor element 122 may be connected to the second conductive element 128, which may be spaced apart from the first conductive element 126. In other words, the third conductor element 122 may be electrically insulated from the first and second conductor elements 118, 120 by a portion of the first insulating layer 150 (between the conductor elements 118, 120, 122) and a portion of the second insulating layer 160 (between the conductive elements 126, 128). In various non-limiting embodiments, the fourth conductor element 124 may be electrically insulated from the first conductor element 118 and the second conductor element 120. For example, as shown in Fig. 1, the fourth conductor element 124 may be connected to the third conductive element 130, which may be spaced apart from the first conductive element 126. In other words, the fourth conductor element 124 may be electrically insulated from the first and second conductor elements 118, 120 by a portion of the first insulating layer 150 (between the conductor elements 118, 120, 124) and a portion of the second insulating layer 160 (between the conductive elements 126, 130). In various non-limiting embodiments, the fourth conductor element 124 may be electrically insulated from the third conductor element 122. For example, as shown in Fig. 1, the third conductive element 130 (to which the fourth conductive element 124 may be connected) may be spaced from the second conductive element 128. Thus, the fourth conductive element 124 may be electrically insulated from the third conductive element 122 by a portion of the first insulating layer 150 (between the conductive elements 122, 124) and a portion of the second insulating layer 160 (between the conductive elements 128, 130).

[0044] In various non-limiting embodiments, the device 100 may be fabricated using 130 nm radio frequency SOI (HFSOI) technology on a 300 nm substrate. However, the device 100 may also be fabricated using other technologies known to those skilled in the art in alternative, non-limiting embodiments. Fig. 2A to 2G show cross-sectional views illustrating a method of manufacturing the device 100 according to various non-limiting embodiments.

[0045] With reference to Fig. 2A, a method of manufacturing device 100 may begin, according to various non-limiting embodiments, by providing (SOI) structure 104 including substrate 106, insulator layer 108 over substrate 106, and semiconductor layer 110 over insulator layer 108. In various non-limiting embodiments, substrate 106 may comprise a silicon wafer. In various non-limiting embodiments, insulator layer 108 may be a buried oxide layer. In various non-limiting embodiments, insulator layer 108 may comprise silicon oxide, sapphire, or combinations thereof. In various non-limiting embodiments, semiconductor layer 110 may be formed of single-crystal silicon. However, other materials known to those skilled in the art may also be used.In various non-limiting embodiments, the insulator layer 108 may be thicker than the semiconductor layer 110 and thinner than the substrate 106. In various non-limiting embodiments, a thickness of the substrate 106 may be between about 750 μm and about 800 μm, a thickness of the insulator layer 108 may be between about 2000 Å and about 4000 Å, and a thickness of the semiconductor layer 110 may be between about 500 Å and about 1600 Å.

[0046] With reference to Fig. 2A, in various non-limiting embodiments, the method may further comprise forming the first conductivity region 112 and the second conductivity region 114 at least partially within the semiconductor layer 110 and forming the silicide layer 142 over each of the conductivity regions 112, 114. Each of the first and second conductivity regions 112, 114 and the semiconductor layer 110 may comprise one or more dopants. In various non-limiting embodiments, the first and second conductivity regions 112, 114 may have approximately equal dopant concentrations (i.e., approximately equal concentrations of dopants). The dopant concentrations of the first and second conductivity regions 112, 114 may be higher than the dopant concentration of the semiconductor layer 110.In various non-limiting embodiments, the dopant concentration of the first conductivity region 112 may be in the range of about 1e12 cm. -2 up to about 1e16 cm -2 the dopant concentration of the second conductivity region 114 can be in the range of about 1e12 cm -2 up to about 1e16 cm -2 and the dopant concentration of the semiconductor layer 110 can be in the range of about 4e10 cm -2 up to about 6e10 cm -2The first and second conductivity regions 112, 114 may have a first conductivity type. For example, the first and second conductivity regions 112, 114 may both have p-type conductivity, in other words, they may comprise dopants with p-type conductivity (e.g., p-type dopants). Alternatively, the first and second conductivity regions 112, 114 may each have n-type conductivity, in other words, they may comprise dopants with n-type conductivity (e.g., n-type dopants). In various non-limiting embodiments, the semiconductor layer 110 may have a second conductivity type that is different from the first conductivity type. For example, if the first and second conductivity regions 112, 114 have p-type conductivity, the semiconductor layer 110 may have n-type conductivity.If the first and second conductivity regions 112, 114 have n-type conductivity, the semiconductor layer 110 may alternatively have p-type conductivity. In one example, the implant material for the first and second conductivity regions 112, 114 and the semiconductor layer 110 may be the same implant material, e.g., in one non-limiting embodiment, it may be an epitaxial silicon material. The p-type material may be or comprise, without limitation, epitaxial silicon germanium and / or the n-type material may be or comprise, without limitation, doped silicon material, including n-type dopants. P-type dopants may include, for example, boron (B), aluminum (Al), indium (In), or a combination thereof, while n-type dopants may include, without limitation, carbon (C), phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof.Other types of implant materials and dopants known to those skilled in the art may also be used to form first and second conductivity regions 112, 114 and the semiconductor layer 110.

[0047] With reference to Fig. 2A, the method may further comprise forming the gate structure 116 over the semiconductor layer 110 and between the first conductivity region 112 and the second conductivity region 114. The first and second conductivity regions 112, 114 and the gate structure 116 may be formed using a technique known to those skilled in the art. In various non-limiting embodiments, the conductivity regions 112, 114 may be formed prior to formation of the gate structure 116. For example, the first and second conductivity regions 112, 114 may be arranged in the semiconductor layer 110 by ion implantation using an implantation mask (e.g., a photoresist mask) with gaps to expose portions of the semiconductor layer 110 intended for the conductivity regions 112, 114.The implantation mask may be formed over the semiconductor layer 110, and either p-type dopants (when the conductivity regions 112, 114 have p-type conductivity) or n-type dopants (when the conductivity regions 112, 114 have n-type conductivity) may be introduced into the exposed regions of the semiconductor layer 110. The implantation mask may then be removed, and the gate structure 116 may subsequently be formed over the semiconductor layer 110 between the conductivity regions 112, 114. In alternative, non-limiting embodiments, the gate structure 116 may be formed before the conductivity regions 112, 114 are formed. For example, the gate structure 116 may first be formed over the semiconductor layer 110, and the first and second conductivity regions 112, 114 may then be formed by ion implantation using the gate structure 116 as a mask.In various non-limiting embodiments, the gate structure 116 may be formed by depositing an oxide layer over the semiconductor layer 110 and an electrode layer over the oxide layer, and etching the oxide layer and the electrode layer to form the gate oxide layer 116a and the gate element 116b, respectively. The silicide layer 148 may then be formed over the gate element 116b using a technique known to those skilled in the art. In various non-limiting embodiments, the electrode layer for forming the gate element 116b may comprise polysilicon or other conductive materials such as metals or alloys, e.g., TiN, TaN, W, or combinations thereof, but other materials known to those skilled in the art may also be used. In various non-limiting embodiments, the oxide layer for forming the gate oxide layer 116a may comprise silicon dioxide or other materials known to those skilled in the art.In various non-limiting embodiments, the silicide layers 142, 148 may comprise one or more silicides, such as, without limitation, cobalt silicide (CoSi2), nickel silicide (NiSi), titanium silicide (TiSi2), tantalum silicide (TaSi2), platinum silicide (PtSi), palladium silicide (Pd2Si), rhodium silicide (RhSi), or combinations thereof. The silicide layers 142, 148 may comprise the same or different types of silicides.

[0048] With reference to Fig. 2A, the method may also include forming the first and second spacers 144, 146 adjacent to the gate element 116b. The first and second spacers 144, 146 may be formed by depositing a spacer layer over the gate structure 116 and etching the spacer layer. However, other techniques known to those skilled in the art may also be used. In various non-limiting embodiments, the first and second spacers 144, 146 may comprise an insulating material. In various non-limiting embodiments, the first and second spacers 144, 146 may comprise a dielectric material, such as, without limitation, silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or multiple layers of insulating materials. Other materials known to those skilled in the art may also be used.

[0049] With reference to Fig. 2A, in various non-limiting embodiments, the method may also comprise forming the first isolation region 134, the second isolation region 136, the third isolation region 138, and the fourth isolation region 140 at least partially within the semiconductor layer 110 of the SOI structure 104. The isolation regions 134, 136, 138, 140 may be formed to extend at least partially into the insulator layer 108. The isolation regions 134, 136, 138, 140 may be formed by etching the SOI structure 104 (e.g., the semiconductor layer 110 and the insulator layer 108) to form trenches and depositing insulation material in the trenches. In various non-limiting embodiments, the isolation regions 134, 136, 138, 140 may comprise shallow trench isolation regions (STIs).In various non-limiting embodiments, the insulation material for forming the insulation regions 134, 136, 138, 140 may comprise a gap-fill oxide or nitride, or a combination of both. However, the insulation regions 134, 136, 138, 140 may be formed using other techniques known to those skilled in the art and / or may comprise other materials known to those skilled in the art.

[0050] With reference to Fig. 2A, in various non-limiting embodiments, the method may further comprise forming the first insulating layer 150 over the semiconductor layer 110 such that the gate structure 116 may be at least partially disposed within the first insulating layer 150. The first insulating layer 150 may be formed by depositing a first insulating material over the semiconductor layer 110, the gate structure 116, and the spacers 144, 146 using a technique known to those skilled in the art. In various non-limiting embodiments, the first insulating layer 150 may comprise silicon oxide, silicon dioxide, silicon nitride, or combinations thereof, but other materials known to those skilled in the art may also be used.

[0051] With reference to Fig. 2A-2G, the method may further comprise forming the first conductor element 118 through the semiconductor layer 110 and the insulator layer 108 of the SOI structure 104 to electrically contact the substrate 106. The method may further comprise forming the second conductor element 120 to electrically contact the gate structure 116 and forming the third conductor element 122 to electrically contact the second conductivity region 114. The method may further comprise forming the fourth conductor element 124 through the semiconductor layer 110 and the insulator layer 108 of the SOI structure 104 to electrically contact the substrate 106. In various non-limiting embodiments, forming the conductor elements 118, 120, 122, 124 may comprise photolithography. However, other techniques known to those skilled in the art may also be used.

[0052] With reference to Fig. 2A, in various non-limiting embodiments forming the first conductor element 118 and the fourth conductor element 124, a first mask 202 may be used. For example, the method may include forming the first mask 202 over the first insulating layer 150. As shown in Fig. 2A, in various non-limiting embodiments, the first mask 202 may comprise a first gap 202a and a second gap 202b above the location where the first and fourth conductor elements 118, 124 are to be formed. Accordingly, the first and second gaps 202a, 202b of the first mask 202 may expose the portions of the first insulating layer 150 and the SOI structure 104 where the first and fourth conductor elements 118, 124 are to be formed. In various non-limiting embodiments, the first mask 202 may be formed by depositing a first mask material over the first insulating layer 150 using techniques known to those skilled in the art.In various non-limiting embodiments, the first mask 202 may be a photoresist mask and the first mask material may comprise a photosensitive material known to those skilled in the art, but other types of masks known to those skilled in the art may also be used.

[0053] With reference to Fig. 2B, in various non-limiting embodiments, forming the first and fourth conductor elements 118, 124 may further comprise forming the first openings 204, 206 with the first mask 202. For example, the first openings 204, 206 may be formed by etching the exposed portions of the first insulating layer 150, the semiconductor layer 110, the insulator layer 108, and the substrate 106 beneath the first and second gaps 202a, 202b of the first mask 202. In various non-limiting embodiments, forming the first conductor element 118 and the fourth conductor element 124 may comprise forming the first conductor element 118 and the fourth conductor element 124 through the first and fourth isolation regions 134 and 140, respectively.For example, the opening 204 for the first conductor element 118 may be formed by etching the first insulating layer 150, the first isolation region 134, the insulator layer 108, and the substrate 106; whereas the opening 206 for the fourth conductor element 124 may be formed by etching the first insulating layer 150, the fourth isolation region 140, the insulator layer 108, and the substrate 106. The first openings 204, 206 for the first and fourth conductor elements 118, 124 may be formed simultaneously in various non-limiting embodiments, but may alternatively be formed sequentially in alternative non-limiting embodiments. The method may further include removing the first mask 202 after forming the first openings 204, 206. The removal of the first mask 202 may be performed using a technique known to those skilled in the art, such as, without limitation, photoresist removal or stripping.

[0054] With reference to Fig. 2C, forming the second conductor element 120 and the third conductor element 122 may, in various non-limiting embodiments, include a second mask 208. In various non-limiting embodiments, the first mask 202 may be different from the second mask 208. For example, as in Fig. 2C, the method may further comprise forming the second mask 208 over the first insulating layer 150 such that at least a portion of the second mask 208 extends into the first openings 204, 206. In various non-limiting embodiments, the second mask 204 may include a first gap 208a and a second gap 208b, respectively, above the location where the second conductor element 120 and the third conductor element 122 are to be formed. Accordingly, the first and second gaps 208a, 208b of the second mask 208 may expose portions of the first insulating layer 150 and the silicide layers 142, 148 where the second and third conductor elements 120, 122 are to be formed.In various non-limiting embodiments, the second mask 208 may be formed by depositing a second mask material over the first insulating layer 150 and in the first openings 204, 206 using techniques known to those skilled in the art. In various non-limiting embodiments, the second mask 208 may be a photoresist mask, and the second mask material may comprise a photosensitive material known to those skilled in the art, but other types of masks may also be used, as known to those skilled in the art. The second mask material for forming the second mask 208 may be the same material as the first mask material for forming the first mask 202, or it may be a different material.

[0055] With reference to Fig. 2D, forming the second and third conductor elements 120, 122 may include forming second openings 212, 214 for the second and third conductor elements 120, 122 with the second mask 208. For example, the second openings 212, 214 may be formed by etching the exposed portions of the first insulating layer 150 and the silicide layers 142, 148 below the gaps 208a, 208b of the second mask 208. For example, the opening 212 for the second conductor element 120 may be formed by etching the first insulating layer 150 and the silicide layer 148 above the gate element 116b and below the first gap 208a of the second mask 208, and the opening 214 for the third conductor element 122 may be formed by etching the first insulating layer 150 and the silicide layer 142 below the second gap 208b of the second mask 208. The second openings 212, 214 may be formed simultaneously in various non-limiting embodiments.However, the second openings 212, 214 may alternatively be formed sequentially in alternative, non-limiting embodiments. Referring to FIG. Fig. 2D, in various non-limiting embodiments, the method may further comprise removing the second mask 208 after forming the second openings 212, 214. In various non-limiting embodiments, removing the second mask 208 may be performed by any technique known to those skilled in the art, such as, without limitation, removing photoresist. Removing the second mask 208 may expose the first openings 204, 206.

[0056] With reference to Fig. 2E, the method may further comprise depositing conductive material 218 in the first openings 204, 206 and the second openings 212, 214 to form the first conductor element 118, the fourth conductor element 124, the second conductor element 120, and the third conductor element 122, respectively. In other words, the conductor elements 118-124 may be formed simultaneously in one non-limiting embodiment. In various non-limiting embodiments, the deposition of the conductive material 218 may be performed as shown in Fig. 2E further form an upper conductive layer 220 over the conductor elements 118, 124, 120, 122.

[0057] In various alternative, non-limiting embodiments, the conductor elements 118, 124, 120, 122 are not necessarily formed simultaneously. In one non-limiting example, a conductive material may be deposited in the first openings 204, 206 after removal of the first mask 202 to form the first and fourth conductor elements 118, 124 before the second mask 208 is formed over the first insulating layer 150. In this non-limiting example, the second mask 208 does not necessarily extend into the first openings 204, 206. In this non-limiting example, a conductive material may be deposited in the second openings 212, 214 after formation of the second openings 212, 214 and removal of the second mask 208 to form the second and third conductor elements 120, 122.

[0058] In various non-limiting embodiments, the conductive material may be deposited using techniques such as, without limitation, linear deposition using tungsten chemical vapor deposition (WCVD). In various non-limiting embodiments, the conductive material for forming the conductor elements 118, 120, 122, 124 may comprise aluminum, copper, tungsten, alloys thereof, or combinations thereof. However, other materials known to those skilled in the art may also be used.

[0059] In various non-limiting embodiments, as in Fig. As shown in Figure 2E, each of the first and fourth conductive elements 118, 124 may be formed using a single deposition process. In other words, the conductive material in the first openings 204, 206 may be deposited only once. However, in alternative, non-limiting embodiments, each conductive element 118, 124 may be formed using more than one deposition process. For example, a lower portion of the openings 204, 206 may first be formed and filled with conductive material, after which an upper portion of the openings 204, 206 may then be formed and filled with conductive material.

[0060] With reference to Fig. 2F, the method may further include removing the upper conductive layer 220 by, for example, smoothing an upper surface of the first insulating layer 150. The upper conductive layer 220 may be removed, for example, by techniques such as, but not limited to, tungsten chemical mechanical polishing (WCMP).

[0061] With reference to Fig. 2G, the method may further include forming the first conductive element 126 for connecting the first conductive element 118 and the second conductive element 120 for electrically coupling the first conductive element 118 and the second conductive element 120. The method may further include forming the second conductive element 128 for connecting to the third conductive element 122 and forming the third conductive element 130 for connecting to the fourth conductive element 124. In various non-limiting embodiments, the first, second, and third conductive elements 126, 128, 130 may be formed simultaneously. For example, the method may include forming the second insulating layer 160 by depositing a second insulating material over the first insulating layer 150.The second insulating material may then be etched to form openings at the locations where the conductive elements 126, 128, 130 are to be formed, and a conductive material may then be deposited into these openings. The deposition of the second insulating material, the etching of the second insulating material, and the deposition of the conductive material may be performed using a technique known to those skilled in the art. In various non-limiting embodiments, the second insulating material may be identical to the first insulating material of the first insulating layer 150. However, in alternative non-limiting embodiments, the second insulating material may be different from the first insulating material.The second insulating material for forming the second insulating layer 160 may comprise silicon oxide, silicon dioxide, silicon nitride, or combinations thereof, but other materials known to those skilled in the art may also be used. The conductive material for forming the conductive elements 126, 128, 130 and the conductive material for forming the conductive elements 118, 120, 122, 124 may be the same in some non-limiting embodiments or different in other alternative non-limiting embodiments. In various non-limiting embodiments, the conductive material for forming the conductive elements 126, 128, 130 may comprise aluminum, copper, tungsten, compounds thereof, or combinations thereof.

[0062] Fig. Figure 3 shows a cross-sectional view of a device 300 according to alternative, non-limiting embodiments. The device 300 is similar to the device 100, and therefore, the common features are identified by the same reference numerals and need not be discussed. It should be noted that in the device 300, the first and second conductor elements 118, 120 may also be connected to a common conductive element 126 (similar to the device 100), but the portion of the conductive element 126 connecting these conductor elements 118, 120 is shown for simplicity. Fig. 3 is not shown. In various non-limiting embodiments, compared to device 100, device 300 may further comprise a fifth conductor element 302 arranged to electrically contact first conductivity region 112. Fifth conductor element 302 may be similar to third conductor element 122. For example, fifth conductor element 302 may similarly be arranged at least partially within first insulating layer 150 at a distance from the other conductor elements 118, 120, 122, 124. In various non-limiting embodiments, fifth conductor element 302 may contact conductive silicide layer 142 to electrically contact first conductivity region 112. Similar to third conductor element 122, fifth conductor element 302 may also be electrically insulated from first conductor element 118 and second conductor element 120.For example, the device 100 may further comprise a fourth conductive element 304 disposed at least partially within the second insulating layer 160, wherein the fourth conductive element 304 may be spaced apart from the first conductive element 126, second conductive element 128, and third conductive element 130. The fifth conductive element 302 may be connected to the fourth conductive element 304 such that the fifth conductive element 302 may be electrically insulated from the remaining conductive elements 118, 120, 122, 124 via a portion of the first insulating layer 150 (between the fifth conductive element 302 and each of the conductive elements 118, 120, 122, 124) and a portion of the second insulating layer 160 (between the fourth conductive element 304 and each of the conductive elements 126, 128, 130).Furthermore, similar to the third conductor element 122, the fifth conductor element 302 may be a normal contact having a diameter substantially equal to that of the second and third conductor elements 120, 122 and smaller than that of the first and fourth conductor elements 118, 124 in various non-limiting embodiments. In various non-limiting embodiments, the diameter of the fifth conductor element 302 may range from about 0.12 µm to about 0.20 µm. In various non-limiting embodiments, a diameter of the first conductor element 118 may have a ratio to a diameter of the fifth conductor element 302 of about 1.5 to about 2.5. In various non-limiting embodiments, a diameter of the fourth conductor element 124 may have a ratio to a diameter of the fifth conductor element 302 of about 1.5 to about 2.5.

[0063] In various non-limiting embodiments, the method of forming the device 100 may further comprise forming the fifth conductor element 302 to electrically contact the first conductivity region 112. The formation of the fifth conductor element 302 may comprise the second mask 208. For example, the second mask 208 may further comprise a third gap above the location where the fifth conductor element 302 is to be formed. The third gap may expose portions of the first insulating layer 150 and the silicide layer 142 where the fifth conductor element 302 is to be formed. An opening may be formed for the fifth conductor element 302 with the second mask 208, e.g., by etching the first insulating layer 150 and the silicide layer 142 below the third gap of the second mask 208.In various non-limiting embodiments, the opening for the fifth conductor element 302 may be formed simultaneously with the second openings 212, 214 for the second and third conductor elements 120, 122. However, in alternative non-limiting embodiments, the opening for the fifth conductor element 302 and the second openings 212, 214 may be formed sequentially. In various non-limiting embodiments, depositing the conductive material 218 may further comprise depositing the conductive material 218 in the opening for the fifth conductor element 302. In other words, the fifth conductor element 302 may be formed simultaneously with the second and third conductor elements 120, 122.In various non-limiting embodiments, the method may further include forming the fourth conductive element 304 for connection to the fifth conductive element 302 in a manner similar to the formation of the second and third conductive elements 128, 130 as described above.

[0064] In various non-limiting embodiments, a structure may include a plurality of devices 100 and / or devices 300. In various non-limiting embodiments, the structure may be a switch structure, such as, without limitation, an RF switch structure. In various non-limiting embodiments, the structure may have a series-shunt-series topology. For example, the structure may include a plurality of branches of the series-shunt series, where each branch may include a plurality of devices 100 and / or devices 300. For example, the structure may include a double-pole double-throw (DPDT) switch formed by four branches of the series-shunt series, where each branch may include a plurality of devices 100 and / or devices 300.However, in alternative, non-limiting embodiments, the structure may have a topology that differs from the topology of the serial shunt series. Furthermore, in alternative, non-limiting embodiments, the structure may have a different number of poles and throws and be formed by a different number and / or type of branches. For example, instead of a DPDT switch, the structure may comprise a single-pole double throw switch (SPDT switch) or a single-pole quad throw switch (SP4T switch). In various non-limiting embodiments, the structure may comprise a plurality of switches, which may include single-pole multi-throw switches (e.g., SPDT switches, SP4T switches), multi-pole multi-throw switches (e.g., DPDT switches), or combinations thereof. The structure may, for example, be an amplifier (e.g.,a low-noise amplifier or a power amplifier), a communications system, or a medical instrument.

[0065] Fig. 4 shows a schematic representation of a DPDT switch 400 according to various non-limiting embodiments. As shown in Fig. 4, the DPDT switch 400 may include two input ports P1, P3 and two output ports P2, P4 and may be electrically coupled to the voltages Vc1, Vc2 and to ground G. The DPDT switch 400 may further include four on-chip trim inductors L1-L4, wherein each of the trim inductors L1-L4 may be electrically coupled to one of the ports P1-P4. Furthermore, the DPDT switch 400 may include four series-connected shunt strings electrically coupled to the trim inductors L1-L4. Each branch may include a plurality of devices M1-M12. For example, branch 402 may include a first series segment including device M4, a second series segment including device M6, and a shunt segment including device M5. Each device M1-M12 may be similar to device 300.

[0066] Fig. Figure 5 shows an enlarged view of branch 402 of DPDT switch 400 according to various non-limiting embodiments. As previously mentioned, each device M4, M5, M6 of branch 402 may be similar to device 300, so the common features are identified by the same reference numerals and need not be discussed. Fig. Figure 6 shows a cross-sectional view of the shunt segment comprising device M5 along line AA'.

[0067] With reference to Fig. 5 and Fig. 6, the gate structure 116 of each device M4, M5, M6 may, in various non-limiting embodiments, include a base portion 510 and a plurality of gate fingers 508 extending from the base portion 510 and arranged parallel to each other above the SOI structure 104. As shown in Fig. 6, each gate finger 508 may include a gate oxide layer 508a and a gate element 508b similar to the gate oxide layer 116a and the gate element 116b of the gate structure 116 of the device 100 / 300. The gate fingers 508 of the series segments including devices M4, M6 may be substantially perpendicular to the gate fingers 508 of the shunt segment including device M5. In various non-limiting embodiments, for each segment including devices M4, M5, M6, a plurality of first conductivity regions 112 (not shown in Fig. 5) at least partially within the semiconductor layer 110 of the SOI structure 104 along one side of each gate finger 508 and a plurality of second conductivity regions 114 (not shown in Fig. 5) may be arranged at least partially within the semiconductor layer 110 of the SOI structure 104 along the other side of the gate finger 508. A plurality of fifth conductor elements 302 may be arranged along one side of each gate finger 508 to electrically contact the respective first conductivity regions 112, and a plurality of third conductor elements 122 may be arranged along the other side of the gate finger 508 to electrically contact the respective second conductivity regions 114. As shown in Fig. 4, the branch 402 may further include a plurality of first conductor elements 118 and fourth conductor elements 124 connected to the SOI structure 104.

[0068] With reference to Fig. 5 and Fig. 6, the branch 402 may also comprise a plurality of third conductivity regions 602 arranged at least partially within the semiconductor layer 110 of the SOI structure 104, and a plurality of sixth conductivity elements 512 arranged to electrically contact the respective third conductivity regions 602. In various non-limiting embodiments, the third conductivity regions 602 may serve as body contacts of the SOI structure 104 to connect the SOI structure 104 to an external voltage. A silicide layer 142 may be arranged over each third conductivity region 602. Each third conductivity region 602 may comprise one or more p-type dopants or one or more n-type dopants. The sixth conductivity element 512 may be connected to the first conductivity element 126.In other words, the sixth conductor elements 512 may be electrically coupled to the first and second conductor elements 118, 120 (in . Fig. 6, the portion of the conductive element 126 connecting the first and second conductive elements 118, 120 is again not shown for simplicity. A fifth isolation region 604 may be disposed between the gate oxide layer 508a and the third conduction region 602.

[0069] In various non-limiting embodiments, the first conductive element 126 and the third conductive element 130 of the device 100 may be connected to ground to discharge the charge carriers in the substrate 106. Furthermore, the first conductive element 118, the second conductive element 120, and the first conductive element 126 of the device 100 may form a conductive path between the substrate 106 and the gate structure 116 to discharge the charge carriers in the substrate 106. Thus, a structure comprising devices similar to the device 100, the device 300, or the devices 100, 300, such as those described with reference to Fig. 4 - 6, exhibit improved linearity and power handling capabilities over a wide frequency range.

[0070] The Fig. 7, 8, and 9A-9B show diagrams illustrating exemplary features of a prior art switch structure and a switch structure including devices 100. The prior art switch structure is similar to the switch structure including devices 100, except that the prior art switch structure does not include the first and fourth conductor elements 118, 124. In addition, the lengths of both the prior art switch structure and the switch structure including devices 100 may be approximately 0.2 µm. In particular, Fig. 7 shows the current-voltage graph (Id-Vg) 702, 704 of the switch structure according to the prior art and the switch structure with the devices 100. As in Fig. 6 with the first and fourth conductor elements 118, 124, the leakage current of the switch structure including the devices 100 may be lower than the leakage current of the switch structure according to the prior art. Fig. Figure 8 shows graphs 802 and 804, which represent the P1dB (output power at 1dB compression or, in other words, 1dB compression point) at different frequencies of the prior art switch structure and the switch structure with devices 100, respectively. As shown in Fig. As shown in Figure 8, the P1dB value of the switch structure including devices 100 can be about 2dB higher than the P1dB value of the prior art switch structure over a wide frequency range from 1 GHz to 15 GHz. Fig. 9A shows graphs 902 and 904, which illustrate the second harmonic of the prior art switch structure and the switch structure including devices 100, respectively, at various input power levels. Fig. Figure 9B shows graphs 906 and 908, which illustrate the third harmonic of the prior art switching structure and the switching structure including devices 100, respectively, at various input power levels. As can be seen from the Fig. 9A and Fig. As can be seen from Figure 9B, the harmonic distortion in the switch structure including the devices 100 is lower compared to the switch structure according to the prior art.

Claims

[1] Device (100; 300) comprising: an SOI structure (104) having a substrate (106), an insulator layer (108) over the substrate (106), and a semiconductor layer (110) over the insulator layer (108), the semiconductor layer (110) having a first conductivity region (112) and a second conductivity region (114) disposed at least partially within the semiconductor layer (110); a gate structure (116) disposed over the semiconductor layer (110) and between the first conductivity region (112) and the second conductivity region (114); a first conductor element (118) disposed through the semiconductor layer (110) and the insulator layer (108) of the SOI structure (104) to electrically contact the substrate (106); a second conductor element (120) arranged to electrically contact the gate structure (116); a conductive element (126) connecting the first conductive element (118) and the second conductive element (120) to electrically couple the first conductive element (118) and the second conductive element (120); a third conductor element (122) arranged to electrically contact the second conductivity region (114), wherein the third conductor element (122) is electrically insulated from the first conductor element (118) and the second conductor element (120); and a fourth conductor element (124) arranged through the semiconductor layer (110) and the insulator layer (108) of the SOI structure (104) to electrically contact the substrate (106), wherein the fourth conductor element (124) is electrically insulated from the first conductor element (118) and the second conductor element (120) and the third conductor element (122). [2] The device (100; 300) of claim 1, wherein a diameter of the first conductor element (118) is larger than a diameter of the second conductor element (120). [3] The device (100; 300) of claim 1, wherein the semiconductor layer (110) of the SOI structure (104) further comprises an isolation region (134) at least partially disposed therein, wherein the first conductor element (118) is disposed through the isolation region (134). [4] Device (100; 300) according to claim 3, wherein the insulation region (134) extends at least partially into the insulator layer (108). [5] The device (300) of claim 1, further comprising a fifth conductor element (302) arranged to electrically contact the first conductivity region (112), wherein the fifth conductor element (302) is electrically insulated from the first conductor element (118) and the second conductor element (120). [6] The device (100; 300) of claim 1, wherein the device (100; 300) is an RF switching transistor, a single-pole multi-throw switch, or a multi-pole multi-throw switch (400). [7] Method comprising: providing an SOI structure (104) having a substrate (106), an insulator layer (108) over the substrate (106), and a semiconductor layer (110) over the insulator layer (108); forming a first conductivity region (112) and a second conductivity region (114) at least partially within the semiconductor layer (110); forming a gate structure (116) over the semiconductor layer (110) and between the first conductivity region (112) and the second conductivity region (114); forming a first conductor element (118) through the semiconductor layer (110) and the insulator layer (108) of the SOI structure (104) to electrically contact the substrate (106); forming a second conductor element (120) to electrically contact the gate structure (116); forming a conductive element (126) to connect the first conductive element (118) and the second conductive element (120) for electrically coupling the first conductive element (118) and the second conductive element (120); forming a third conductor element (122) to electrically contact the second conductivity region (114), wherein the third conductor element (122) is electrically insulated from the first conductor element (118) and the second conductor element (120); and forming a fourth conductor element (124) through the semiconductor layer (110) and the insulator layer (108) of the SOI structure (104) to electrically contact the substrate (106), wherein the fourth conductor element (124) is electrically insulated from the first conductor element (118) and the second conductor element (120) and the third conductor element (122). [8] The method of claim 7, wherein a diameter of the first conductor element (118) is greater than a diameter of the second conductor element (120). [9] The method of claim 7, further comprising forming an isolation region (134) at least partially within the semiconductor layer (110) of the SOI structure (104), wherein forming the first conductor element (118) comprises forming the first conductor element (118) through the isolation region (134). [10] The method of claim 9, wherein the insulation region (134) extends at least partially into the insulator layer (108). [11] The method of claim 7, wherein forming the first conductor element (118) comprises a first mask (202) and forming the second conductor element (120) comprises a second mask (208), and wherein the first mask (202) is different from the second mask (208). [12] The method of claim 11, wherein forming the first conductor element (118) and forming the second conductor element (120) comprises: forming a first opening (204) for the first conductor element (118) with the first mask (202); and forming a second opening (212) for the second conductor element (120) with the second mask (208), and simultaneously depositing conductive material in the first opening (204) and in the second opening (212) to form the first conductor element (118) and the second conductor element (120), respectively. [13] The method of claim 12, wherein the method further comprises: forming an insulating layer (150) over the semiconductor layer (110) such that the gate structure (116) is at least partially disposed within the insulating layer (150); forming the first mask (202) by depositing a first mask material over the insulating layer (150); and forming the second mask (208) by applying a second mask material over the insulating layer (150) and in the first opening (202). [14] The method of claim 7, further comprising forming a fifth conductor element (302) to electrically contact the first conductivity region (112), the fifth conductor element (302) being electrically insulated from the first conductor element (118) and the second conductor element (120). [15] A structure comprising a plurality of devices (100; 300), wherein one or more of the devices (100; 300) comprise: an SOI structure (104) comprising a substrate (106), an insulator layer (108) over the substrate (106), and a semiconductor layer (110) over the insulator layer (108), the semiconductor layer (110) comprising a first conductivity region (112) and a second conductivity region (114) disposed at least partially within the semiconductor layer (110); a gate structure (116) disposed over the semiconductor layer (110) and between the first conductivity region (112) and the second conductivity region (114); a first conductor element (118) disposed through the semiconductor layer (110) and the insulator layer (108) of the SOI structure (104) to electrically contact the substrate (106); a second conductor element (120) arranged to electrically contact the gate structure (116); a conductive element (126) connecting the first conductive element (118) and the second conductive element (120) to electrically couple the first conductive element (118) and the second conductive element (120); a third conductor element (122) arranged to electrically contact the second conductivity region (114), wherein the third conductor element (122) is electrically insulated from the first conductor element (118) and the second conductor element (120); and a fourth conductor element (124) arranged through the semiconductor layer (110) and the insulator layer (108) of the SOI structure (104) to electrically contact the substrate (106), wherein the fourth conductor element (124) is electrically insulated from the first conductor element (118) and the second conductor element (120) and the third conductor element (122). [16] The structure of claim 15, wherein the one or more of the devices (100; 300) comprise an RF switching transistor, a single-pole multi-throw switch, a multi-pole multi-throw switch (400), or combinations thereof.

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