TRIMNING MEMORY READ AMPLIFIERS

Abstract

Storage device comprising: a memory array (12) having a plurality of bit cells (210a, 210b), wherein the memory array (12) is configured to store trim information (16) and user data (18), wherein the trim information (16) is stored in a two-cells-per-bit mode in the memory array (12), and wherein the user data (18) is stored in a one-cell-per-bit mode in the memory array (12); a read amplifier (100) designed to read the trim information (18) from the memory array (12); a trim register (110) configured to receive the trim information (18) from the read amplifier (100); and wherein the read amplifier (100) is configured to receive the trim information (18) from the trim register (110) in order to be operated in a trimmed mode for reading the user data (18) from the memory array (12).

Description

STATE OF THE ART

[0001] The improvement in the integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) in integrated circuits (ICs) is due to the miniaturization of the semiconductor process node, which leads to a reduction in the operating voltage and power consumption of the electronic circuits implemented within that node. Consequently, the access speed of memory ICs is expected to increase. For example, some memories have a very small read window, which necessitates a low-offset read amplifier for a successful read operation.

[0002] A non-volatile memory device is capable of retaining data even after the power supply is switched off. Examples of non-volatile memory devices include flash memory, ferroelectric random-access memory (FRAM), phase-change random-access memory (PRAM), and magnetic random-access memory (MRAM). MRAMs store data by using variations in the magnetization direction at tunnel junctions. The two states of an MRAM cell can be detected by their relatively higher and lower resistances (RH and RL), which represent different binary logic values ​​of a bit stored in the memory. For example, RL (or high cell current) can be defined as logic "0" ("data-0"); RH (or low cell current) can be defined as logic "1" ("data-1").A data bit, a logical "0" or "1" value, stored in an MRAM bit cell can be determined by a read amplifier that compares a current flowing through the bit cell with a reference current. Due to process variations, individual MRAM cells in an array can have different RH values ​​(when programmed to RH) and different RL values ​​(when programmed to RL). Such process variations can also lead to a mismatch or offset in a read amplifier circuit.

[0003] The prior art relevant to the present invention is given by US 2019 / 0 164 579 A1, US 2015 / 0 262 640 A1 and US 2010 / 0 223 532 A1. Known from the prior art is an integrated circuit device comprising a read amplifier with a first and a second input terminal, a compensation network with a first compensation circuit coupled to the first input terminal of the read amplifier and a second compensation circuit coupled to the second input terminal of the read amplifier, and a latching circuit that can be operated to selectively activate either the first or the second compensation circuit, but not both simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood with reference to the following detailed description in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been enlarged or reduced arbitrarily for the sake of clarity. Furthermore, the drawings are to be considered illustrative examples of embodiments of the invention and not as limiting. Fig. Figure 1 is a block diagram that illustrates an example of a storage device according to some embodiments. Fig. 2 is a circuit diagram that shows an example of an MRAM memory array as described in Fig. 1 represents the storage device shown according to some embodiments. Fig. Figure 3 is a block diagram that represents another example of a storage device according to some embodiments. Fig. Figure 3 is a block diagram that represents another example of a storage device according to some embodiments. Fig. Figure 4 is a block diagram that represents another example of a storage device according to some embodiments. Fig. Figure 5 is a block diagram that shows yet another example of a storage device according to some embodiments. Fig. Figure 6 is a flowchart that illustrates an example of a procedure according to some embodiments. Fig. Figure 7 is a flowchart that illustrates an example of another method according to some embodiments. DETAILED DESCRIPTION

[0005] The present invention is defined by the subject matter of the accompanying independent claims. Particular embodiments are given by the additional features of the accompanying dependent claims. The following disclosure provides many different embodiments or examples for implementing various features of the intended subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not to be considered limiting.For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, and also embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or symbols in the various examples. This repetition serves the purpose of simplicity and clarity and does not automatically imply a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used in this document to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device during use or operation, in addition to the orientation shown in the figures. The device may be oriented in a different way (rotated by 90 degrees or in other orientations), and the spatially relative terms used in this document may be interpreted accordingly.

[0007] Fig. Figure 1 shows an exemplary storage device 10 according to disclosed embodiments. The device 10 has a storage array 12, which comprises an array of bit cells. In some examples, the array may comprise magnetic random-access memory (MRAM) bit cells, although other memory types, such as resistive random-access memory (RRAM) bits (ReRAM bits) or the like, are within the scope of protection of this disclosure. MRAM stores data in bit cells with two superimposed layers of magnetic material separated by a thin insulating film. The layered structure forms a magnetic tunnel junction (MTJ or MTJ element) of an MRAM cell.The two layers comprise a magnetic layer that is permanently magnetized in a fixed magnetic field orientation (this layer is called the "pinned layer") and a variably magnetized magnetic layer (this layer is called the "free layer"). The free layer can be magnetized in one of two orientations relative to the permanently magnetized layer. The two orientations are characterized by significantly different series resistances through the superimposed layers of the MTJ. The magnetic field orientation of the variable layer can be the same as that of the permanent magnet layer (parallel) or opposite to that of the permanent magnet layer (antiparallel). The parallel orientation exhibits a comparatively lower resistance (RL), and the antiparallel orientation exhibits a higher resistance (RH).

[0008] The bit cells are configured to store a logical "0" or "1" bit value of data Q. In an example read operation, read voltages are applied to the memory device 10, causing a read current to flow between the memory array 12 and a read amplifier 100. Additionally, a reference current Iref flows between a reference circuit 14 with reference MRAM cells and the read amplifier 100. The read amplifier 100 compares the read current Iread with the reference current Iref to detect a logical "0" or "1" bit value of data Q stored in a bit cell of the memory array 12. If the read current Iread is found to be less than the reference current Iref, the read amplifier 100 detects a logical "1" data value Q. Conversely, if the read current Iread is found to be greater than the reference current Iref, the read amplifier 100 detects a logical "0" value Q.The read amplifier 100 amplifies the level of the detected bit of data Q and provides the amplified data bit as output DATA_OUT, such that the bit of data Q can be read from the bit cell. In some embodiments, the read amplifier 100 is a differential read amplifier. In other embodiments, the read amplifier 100 is a single-ended read amplifier.

[0009] Fig. Figure 2 is a circuit diagram illustrating an example of the memory array 12 according to some embodiments. In the example shown, the array 12 has a plurality of bit cells arranged in an array of rows and columns. For clarity, in Fig. Only two of the bit cells are labeled, i.e., one of the bit cells in the first row is labeled 210a and one of the bit cells in the second row is labeled 210b. The bit cells can be generally referred to as bit cells 210.

[0010] As in Fig. As shown in Figure 2, the memory array 12 further comprises a plurality of word lines (WL1, WL2, WLM, etc.), bit lines (BL1, BLN, etc.), and source lines (SL1, SLN, etc.). The word line WL1 connects the bit cells 210 in the first row, the word line WL2 connects the bit cells 210 in the second row, and the word line WLN connects the bit cells 210 in the nth row. The bit line BL1 and the source line SL1 connect the bit cells 210a, 210b, etc., in the first column, and the bit line BLN and the source line SLN connect the bit cells 210 in the second column. Therefore, in the example shown, the memory array 12 has M rows, N columns, and M x N bit cells 210. The bit lines BL1, BLN, etc. can be selectively connected to the read amplifier 100 via switches (not shown), depending on which specific bit cell in the array is to be read from or written to.

[0011] Since the bit cells 210 are identical in terms of construction and operation, only one, i.e., bit cell 210a, is described here. In this embodiment, bit cell 210a comprises a transistor 230 and a resistive element 240. The transistor 230 can be a field-effect transistor (FET), e.g., a metal-oxide-semiconductor FET (MOSFET), and has a first source / drain terminal 230a connected to the source line SL1, a second source / drain terminal 230b, and a gate terminal 230c connected to the word line WL1. In an alternative embodiment, the storage device 10 does not have the source line SL. In such an alternative embodiment, the first source / drain terminal 230a of the transistor 230 is connected to ground or another node of the storage device 10. Transistor 230 can be any type of transistor, for example a junction transistor such as a bipolar transistor (BJT).

[0012] The resistive element 240 is connected between the second source / drain terminal 230b of transistor 230 and the bit line BL1. In some embodiments, the resistive element 240 is an MTJ. The resistive element 240 can be any type of resistive element or resistive circuit, provided it fulfills the intended function described herein.

[0013] In an example write operation, write voltages are applied to bit line BL1, source line SL1, and word line WL1. A voltage applied to word line WL1 activates transistor 230, and a write current flows through bit cell 210a. This write current flows through MTJ 240, causing it to switch from a parallel state to an antiparallel state, or vice versa, writing and storing a data bit in bit cell 210a. To switch MTJ 240 from the antiparallel state to the parallel state to store a value "0", a switching current is passed from the free layer through MTJ 240 to the reference layer. Conversely, to switch MTJ 240 from the parallel state to the antiparallel state to store a value "1", a switching current is passed from the reference layer through MTJ 240 to the free layer.

[0014] When the free layer of the MTJ 240 is in the parallel state, the MTJ 240 exhibits a low resistance, representing a "logic 0" value, and is considered to be in a parallel or low-resistance state. Conversely, when the free layer of the MTJ 240 is in the antiparallel state, the MTJ 240 exhibits a high resistance, representing a "logic 1" value, and is considered to be in an antiparallel or high-resistance state. In some embodiments, the logic represented by the MTJ 240 in a high-resistance or low-resistance state is arbitrary; for example, logic "1" can be represented by the MTJ 240 in a low-resistance state, and logic "0" can be represented by the MTJ 240 in a high-resistance state. This is determined by the desired convention applied to the storage device.Regardless of the convention chosen, the MTJ 240 is capable of storing binary data across two writable and readable states, e.g., the high-impedance and low-impedance states. For consistency, the convention used in embodiments described in this document is that the MTJ 240 represents a "0" in the low-impedance state and a "1" in the high-impedance state, unless otherwise specified.

[0015] In an example read operation, read voltages are applied to the bit line BL and the source line SL, which are assigned to a column of a selected bit cell 210 to be read, as well as to the word line WL, which is assigned to a word of a selected bit to be read. For example, read voltages can be applied to the bit line BL1, the source line SL1, and the word line WL1 to read the bit stored in bit cell 210a. To select other cells, other combinations of bit lines, source lines, and word lines are activated to generate a read current that is indicative of the data stored at the respective cell.

[0016] In the example shown, when bit cell 210a is read, a read current Iread flows through the resistive element 240, e.g., MTJ 240. The magnitude of the read current Iread corresponds to a resistance state of MTJ 240. For example, if MTJ 240 is in a low-resistance state, i.e., a parallel state, the read current Iread is greater than the reference current Iref from the reference cell in the Fig. The reference circuit 14 shown in Figure 1 indicates that bit cell 210a stores a "logic 0" bit value of data. Conversely, when MTJ 240 is in a high-impedance state, i.e., an antiparallel state, the read current Iread is smaller than the reference current Iref, indicating that bit cell 210a stores a "logic 1" bit value of data. The read amplifier 100 can compare the read current Iread with the reference current Iref to detect a "logic 0" or "logic 1" bit value of data stored in bit cell 210a. The read amplifier 100 amplifies a level of the detected data bit and outputs the amplified data bit in such a way that the data bit stored in bit cell 210a can be read from it.

[0017] In order for the read amplifier 100 to accurately detect the data bit stored in the bit cells 210, the magnitude of the reference current Iref should be between the magnitude of a read current Iread when the MTJ 240 is in the parallel state and the magnitude of a read current Iread when the MTJ 240 is in the antiparallel state. It should be understood that an MTJ is subject to temperature and process fluctuations. Therefore, in order for the reference circuit 14 to generate such a reference current Iref, the reference circuit 14, in some embodiments, has a resistive element of the same type as the resistive element 240 of the bit cells 210. For example, at least some of the resistive elements of the reference circuit 14 are MTJs of the same type as the MTJs 240 of the bit cells 210. This allows the reference circuit 14 to track temperature and process fluctuations of the resistive elements 240 of the bit cells 210.A voltage or current source that generates constant reference voltages or currents is not capable of tracking temperature and process variations of an MTJ.

[0018] In some embodiments, before the reference circuit 14 is operated, for example, to generate the reference current Iref for comparison with the read current Iread in a read operation, the resistive MTJ elements of the reference circuit 14 are first switched to an antiparallel state. The antiparallel, e.g., high-impedance, state generates a reference current that is smaller than implementations that pass the reference current through resistive MTJ elements in the parallel state. By passing the reference current through a combination of one or more MTJs in an antiparallel state, a reference current Iref can be generated that has a magnitude between that of the read current Iread when the bit cell contains a data value "0" and that of the read current Iread when the bit cell contains a data value "1".

[0019] Due to process, voltage, and temperature fluctuations (PVT fluctuations), individual MRAM cells of the array and / or the reference circuit can exhibit different RH values ​​(when programmed to RH) and different RL values ​​(when programmed to RL). Furthermore, such PVT fluctuations often result in mismatches or offsets between components in a read amplifier circuit. In some cases, such fluctuations are addressed by trimming or adjusting a read amplifier based on empirically derived trim information input into the read amplifier 100.

[0020] Once again on Fig. 1. Referring to Figure 1, the illustrated device 10 thus includes one or more trim registers 110, which store trim information for input into the read amplifier 100 in order to adjust or trim the read amplifier 100. The trim information is retrieved and entered into the trim register 110 after the device 10 is switched on. However, the trim information is retrieved from the memory array before user read operations to read the user data. In some known implementations, the trim information is stored in a separate non-volatile memory, for example, an embedded eFUSE array, and is read from it using separate read amplifier(s). Such additional memory arrays and such associated read amplifier(s) can result in a significant area disadvantage for the device.As noted above, trim information for the read amplifier is retrieved after power-up but before user read operations, since such read operations require that the trim information be applied to the read amplifier. With conventional storage devices, reading the trim information from the memory array before the read amplifier has been properly trimmed can result in inaccurate trim information being retrieved for subsequent application to the read amplifier.

[0021] According to some examples, trim information 16 is stored in one section of the memory array 12, while other sections of the array 12 store, for example, user data 18. This eliminates the need for a separate non-volatile memory and associated read amplifier for storing trim information, thus reducing the space requirement. As discussed in more detail below, trim information 16 is stored in the memory array 12 and read from it using methods such as two-cells-per-bit, error correction code schemes (ECC schemes), majority voting, read bias integrity checking, etc., to make the retrieval of the read amplifier trim information 16 more robust under PVT fluctuations that may accompany the memory array 12.Thus, trim information 16 can be read from the memory array 12 using the read amplifier 100, resulting in a more compact device, since an additional non-volatile memory for storing trim information is not required.

[0022] In the illustrated example, the read amplifier 100 comprises a read amplifier standard operating control terminal 102 and a trim setting input terminal 104. For example, embodiments of the storage device 10 are configured to load trim settings into the read amplifier 100 after the device 10 is switched on. Thus, the read amplifier 100 is configured to read the trim information 16 from the memory array 12 after the storage device 10 is switched on. Since the trim information 16 is stored in the memory array 12, such trim information 16 is not yet available to the read amplifier when the storage device 10 is switched on. Thus, the read amplifier 100 can be set to a state in which trim register settings are bypassed in response to a signal SA_DEFAULT received on the standard operating control terminal 102.In other words, when the trim information 16 is read from the memory array 12, the trim information 16 is not applied to the read amplifier 100—the read amplifier 100 operates in an “untrimmed” mode. This contrasts with the standard or “trimmed” mode used to read user data 18 by the trimmed read amplifier 100 (i.e., trim settings are applied to the read amplifier 100). As discussed below, disclosed embodiments employ various methods to make the retrieval of the read amplifier trim information 16 from the memory array 12 by the untrimmed read amplifier 100 more robust under PVT fluctuations.

[0023] The trim information 16, read from the memory array 12, can be stored in trim registers 110. In particular, in some embodiments, a control signal LOAD is input to a load control terminal 112 to store the read trim information data 16 in the trim registers 120, and a trim register selection control terminal 114 receives a signal TRIM_SEL to indicate which trim register 110 should be written to. Once the trim information 16 has been retrieved from the memory array 12 and stored in the trim registers 110, the signal SA_DEFAULT goes low, such that the read amplifier 100 is operated in trimmed mode, applying the trim settings received by the trim registers 110 at the trim setting input terminal 104. The trimmed mode is used when the read amplifier 100 is operated to read user data 18 from the memory array 12.

[0024] The read amplifier 100 is designed to operate in a “two-cells-per-bit” mode while retrieving the trim information 16 from the memory array 12. Fig. Figure 3 represents one such embodiment of the storage device 10. Fig. 3. Referring to the above, the illustrated read amplifier 100 has a retrieval mode control terminal 120 that receives a retrieval mode signal RECALL. By applying the RECALL signal (e.g., RECALL=1), the read amplifier 100 is configured for two-cells-per-bit mode, whereby each bit of the trim information 16 is written to two bit cells. As described below, in two-cells-per-bit mode, each bit of the trim information 16 is stored as complementary data in the array 12 using two cells in opposite states. For example, {Q=1, QB=0} can represent a bit of trim data with the logical value "1", while {Q=0, QB=1} can represent a bit of trim data with the logical value "0".

[0025] In normal operation for reading user data 18 from the memory array 12, the read amplifier 100 is configured to operate in a "one-cell-per-bit" mode, for example by setting RECALL = 0. When operating in one-cell-per-bit mode, each bit of user data 18 is written to a corresponding bit cell, as described above in connection with Fig. 2 for subsequent one-cell-per-bit mode read operations. In particular, for a one-cell-per-bit mode read operation, the read amplifier 100 receives reference data from the reference circuit 14 and compares the read current Iread for a specific bit cell with the reference current Iref from a reference cell of the reference circuit 14 to determine a logical bit value “0” or “1” of data stored in a bit cell such as the one described in Fig. to detect the bit cells 210a shown.

[0026] In contrast, in the two-cells-per-bit mode for retrieving trim information 16 from array 12, the trim information is written to array 12 using the two-cells-per-bit method. For example, a "1" trim data bit can be written as a "1" data value to bit cell 210a and as its complementary "0" data value to bit cell 210b. When the trim information is read from array 12, the read amplifier 100 compares the read current Iread for bit cell 210a with the read current Iread for bit cell 210b. Thus, the two-cells-per-bit mode offers a larger read margin compared to the one-cell-per-bit mode, where the read current Iread is compared with the reference current Iref. This allows for a more robust trim information retrieval function before the trim information is applied to the read amplifier 100.

[0027] Once again on Fig. 3. Referring to this, when the trim information 16 is to be read from the array 12, the read amplifier 100 is set to the default mode by applying the signal SA_DEFAULT (i.e., SA_DEFAULT = 1), so that the trim information 16 is read by the read amplifier 100 without being applied to it. Furthermore, the signal RECALL is applied (i.e., RECALL = 1) to operate the read amplifier 100 in two-cells-per-bit mode to retrieve the trim information 16. Column multiplexers (MUX) 130 are operated in response to decoded memory addresses for the trim information 16 to read Q and complementary QB data from two corresponding bit cells for each bit of trim information data. The read trim information 16 is stored in the appropriate trim registers 110 in response to the signals LOAD and TRIM_SEL.When the trim information 16 has been read from array 12 and stored in trim registers 110, the SA_DEFAULT and RECALL signals go low to set the read amplifier 100 for normal operation in order to read user data 18 from memory array 12. In this mode, the read amplifier 100 operates in trimmed mode (i.e., applying the trim settings) and in one-cell-per-bit mode. The various logic (i.e., 1 / 0) signals described for the discussed signals LOAD, TRIM_SEL, SA_DEFAULT, RECALL, etc., are merely examples. Other logic level settings for such signals are within the scope of the disclosure.

[0028] Fig. Figure 4 shows another embodiment in which the reliability of retrieving the trim information 16 from the memory array 12 using the untrimmed read amplifier 100 is further improved by using error correction code schemes (ECC schemes). ECC can be used to detect and correct bit errors in the trim information 16 stored in the memory array 12. For example, in some implementations, an ECC encodes trim information 16 by generating ECC check bits, such as redundancy bits or parity bits, which are stored together with the trim information 16 in the memory array 12. The data (i.e., trim information 16) and parity bits together form a codeword.For example, an ECC that generates 8 parity bits for 64 bits of trim data can typically detect two bit errors and correct one bit error in the 64 data bits, known as SECDED-Hamming code, single-error correction (SEC), and double-error correction (DED). Other suitable ECC schemes include Bose-Chaudhuri-Hocquenghem codes (BCH codes), which are constructed using polynomials over a finite field.

[0029] Data such as check bits used in the ECC scheme can be stored in the memory array 12. In some embodiments, ECC data 142 is also stored in the array 12 using the two-cells-per-bit scheme. For example, ECC data 142 contained in a row of the memory array 12 can be called a word. A codeword is a sequence of data that includes the word plus parity bits added in an additional column(s) of the memory array. If a codeword has a word segment with K bits and M parity bits, the codeword length would be NN = K+M. Thus, each of the K bits storing trim information 16 and the M parity bits can be written as complementary data into two bit cells—that is, two cells per bit.The use of the two-cells-per-bit scheme to store the trim data 16 and the ECC information improves the read reserve for retrieving the trim data by the untrimmed read amplifier 100.

[0030] At the in Fig. In the example shown in Figure 4, the device 10 is configured to use ECC protection for the read amplifier trim information 16 stored in the array 12. When the trim information 16 is to be read from the array 12, the read amplifier 100 is set to its default mode by applying the signal SA_DEFAULT (i.e., SA_DEFAULT = 1), so that the trim information 16 is read by the read amplifier 100 without being applied to it (i.e., the read amplifier 100 is in untrimmed mode). Furthermore, the signal RECALL is applied (i.e., RECALL = 1) to operate the read amplifier 100 in two-cells-per-bit mode.

[0031] The column multiplexes 130 are operated in response to decoded memory addresses for the ECC data 142 stored in the array 12. The data is read by the read amplifier 100 and output to an ECC decoder 140. Additionally, trim data 16, read by other read amplifiers 100 of the device 12, is input to the ECC decoder 140. Thus, during trim retrieval, the trim information 16 read from several I / Os is first fed to the ECC decoder 140. After decoding the appropriate settings, the decoded data DIN is fed back to the read amplifier(s) 100 and stored in the trim registers 110. The SA_DEFAULT and RECALL signals then go low to set the read amplifier 100 to operate for reading user data 18 from array 12 in trimmed mode (i.e., applying the trim settings) and in one-cell-per-bit mode. The various logical (i.e.,1 / 0) Signals described for the discussed signals SA_DEFAULT, RECALL, etc., are merely examples. Other logic level settings for such signals are within the scope of the disclosure.

[0032] As noted above, the ECC schemes can be used to improve the reliability of reading the trim information by the untrimmed read amplifier 100. Therefore, some embodiments employ a one-cell-per-bit scheme to store the trim information 16 in the array 12. In such embodiments, the input terminals 102 and 120 and the corresponding RECALL and SA_DEFAULT signals can be omitted, as it would not be necessary to configure the read amplifier 100 in two-cell-per-bit mode. Fig. Figure 5 presents an example where "majority voting" is used to retrieve trim information 16 by the untrimmed read amplifier 100. In majority voting, each bit of the trim information 16 is stored in the memory array 12 with multiple copies of the same content. In other words, to store a trim data bit with the logical value "1", multiple "1" data values ​​are written to the array, and to store a trim data bit with the logical value "0", multiple "0" data values ​​are written to the array. For example, in a 3-copy majority vote scheme for a "1" trim data bit, a "1" would be written as three "ones" (1, 1, 1) to three corresponding bit cells of the array 12.During the retrieval of the trim information 16, the read amplifier 100 reads each copy of each bit of trim data and determines the data bit to be written to the trim register 110 based on whether there are more zeros or more ones for a given data bit. If more zeros are read, a logical 0 data bit is written to the trim register, and if more ones are read, a logical 1 data bit is written to the trim register.

[0033] For example, in a 3-copy majority vote scheme, if the data for one bit of trim information 16, read from array 12 by read amplifier 100, is 1,1,1, the final trim data written to trim register 110 is 1. If the read data is 1,1,0, the final trim data written to trim register 110 is 1, and if the read data is 1,0,0, the final data written to trim register 110 is 0. If the read data is 0,0,0, then the final data written to trim register 110 is also 0. Such majority voting schemes can provide better immunity to occasional read errors due to marginal read bits.In other words, even if some bits of trim data might be misread due to PVT fluctuations, it is less likely that the majority of trim data bits would be misread.

[0034] At the in Fig. In the example shown in Figure 5, the two-cells-per-bit scheme can be used when writing the trim data 16 to array 12 and when reading the trim data from array 12. Thus, a "1" trim data bit Q is written as 1,1,1, while QB is written as 0,0,0. Accordingly, six bit cells are used to store one bit of trim information.

[0035] When the trim information 16 is to be read from array 12, the read amplifier 100 is set to the default mode by applying the signal SA_DEFAULT (i.e., SA_DEFAULT = 1), so that the trim information 16 is read by the read amplifier 100 without being applied to it (i.e., the read amplifier 100 is in the untrimmed mode). Furthermore, the signal RECALL is applied (i.e., RECALL = 1) to operate the read amplifier 100 in two-cells-per-bit mode. The column MUXs 130 are operated in response to decoded memory addresses for the trim data 16 stored in the array 12, and the data is read by the read amplifier 100 and output to a majority voting decoder 150, which evaluates the multiple Q, QB values ​​read for each copy of each bit of trim information 16.As described above, the multiple copies of each trim information data bit are counted, and the majority value (i.e., the value with the most ones or zeros) is output to trim register 110 as decoded data DIN. The SA_DEFAULT and RECALL signals then go low to set the read amplifier 100 to operate for reading user data 18 from array 12 in trimmed mode (i.e., applying the trim settings) and in one-cell-per-bit mode. The various logic (i.e., 1 / 0) signals described for the discussed signals SA_DEFAULT, RECALL, etc., are merely examples. Other logic level settings for such signals are within the scope of this disclosure.

[0036] In other embodiments, the majority voting arrangement is used in conjunction with a one-cell-per-bit read / write scheme, since majority voting itself improves the reliability of the trim information retrieval process. In such embodiments, input terminals 102 and 120 and the corresponding signals SA_DEFAULT and RECALL can be omitted, as it would not be necessary to configure the read amplifier 100 in two-cell-per-bit mode.

[0037] Fig. Section 6 describes a method 300 for storing trim information 16 in the memory array 12 according to some embodiments. As noted above, in a read amplifier circuit, a mismatch or offset between components can occur due to PVT fluctuations. In some cases, this fluctuation can be addressed by trimming or adjusting the read amplifier 100 based on empirically derived trim information input into the read amplifier 100. Accordingly, in step 310, suitable trim settings for the read amplifier 100 are determined.

[0038] In some embodiments, for example in the one described above, Fig. In the example shown in Figure 4, ECC parity bits are determined in step 312. In step 314, the trim information 16 and ECC parity bits, if applicable, are written to the memory array 12. In the example shown, the two-cells-per-bit mode is used, so that Q and QB data are written to the array 12 in two corresponding bit cells for each bit of trim and ECC data. Furthermore, in embodiments such as the one shown in Figure 4, the following are also performed: Fig. In the majority voting example shown in Figure 5, for each bit of trim information, multiple copies of the Q and QB data are written to array 12.

[0039] Fig. Figure 7 describes another method 350 according to some embodiments, wherein trim information is read from the array 12. In step 352, a read amplifier 100 is configured for a specific operating mode, for example, by receiving a configuration signal. For instance, the read amplifier 100 can be configured to an untrimmed mode (trim information is not applied to the read amplifier). In embodiments where the two-cells-per-bit read / write scheme is used, the read amplifier is further configured to the two-cells-per-bit mode. In other embodiments where a one-cell-per-bit read / write operation is used, this step is not required.

[0040] In some implementations, the read reliability of the trim information 16 is further improved by checking the read bias integrity at step 354. This provides a way to improve the accuracy and reliability of the trim information 16 read from the memory array 12. Specifically, in some cases, a predetermined fixed data pattern (i.e., a predetermined pattern of ones and zeros) is written to a specific address of the memory array 12. Data from this address is then read and compared to the known data pattern. For example, a pattern of eight ones might be written to address A. The data from address A is then read and compared to the known pattern (i.e., eight ones). Criteria for a read operation being "satisfactory" are predetermined.For example, if seven of the eight bits read from address A are correct, the read data could be considered a satisfactory match with the predetermined pattern. Specifically, for a predetermined pattern of 11111111 (eight ones) as described above, read values ​​of 11111111, 10111111, and 11110111 would all be considered successful reads. Conversely, read values ​​of 00000000, 11001111, and 11111001 would be considered unsuccessful reads (i.e., fewer than seven correct bits). In some examples, the data pattern is read repeatedly until the read data shows a satisfactory match with the known data pattern or until the read bias integrity check timeout occurs. Such reading bias integrity tests can determine whether factors such as PVT fluctuations negatively affect the reading process.

[0041] Once the read data shows a satisfactory match with the known data pattern, the trim information 16 is then read from the array 12 in step 356. Specifically, as noted above, in embodiments using the two-cell-per-bit scheme, the read amplifier 100 compares a read current Iread of a first bit cell 210a with the read current Iread of a second bit cell 210b of the array 12 to determine the data value. This contrasts with a one-cell-per-bit read mode, where the read current Iread of a bit cell is compared with a reference current Iref from a reference cell of a reference circuit to determine a data value.

[0042] In examples that use ECC and / or majority voting schemes, the read trim information 16 is processed by suitable decoders such as the one in step 358. Fig. 4 ECC decoders 140 shown and / or the one in Fig. The majority voting decoder 150 shown in step 5 is decoded. In step 360, the trim information 16 is written to the trim registers 110 to be applied to the read amplifier 100.

[0043] Thus, various disclosed examples provide a memory system, for example an MRAM, with a read amplifier 100 that can be operated in a trimmed mode for increased read robustness and yield. The trim information 16 to be applied to the read amplifier 100 is stored in the memory array 12 of the memory device 10, rather than in a separate memory array such as an eFUSE, and is therefore retrieved after power-up and before user read operations. In other words, the read amplifier 100 reads the trim information 16 from the array 12 before the trim information 16 is applied to the read amplifier 100 (i.e., untrimmed mode).

[0044] Several methods are employed to make the retrieval of the trim information 16 more robust under PVT fluctuations. Since the trim information 16 is stored and read from the memory array 12 itself by the device's read amplifier(s) 100, a more compact device can be provided.

[0045] According to some disclosed embodiments, a storage device comprises a memory array with a plurality of bit cells, for example, MRAM bit cells. The memory array is configured to store trim information and also user data. A read amplifier is configured to read the trim information from the memory array, and a trim register is configured to receive the trim information from the read amplifier. The read amplifier is configured to receive the trim information from the trim register and thereby be operated in a trimmed mode for reading the user data from the memory array.

[0046] According to other embodiments, a method comprises providing a memory array, for example an MRAM array. Trim information for a read amplifier is determined, and a first bit of the trim information is written to a first bit cell of the memory array, and a complement of the first bit of the trim information is written to a second bit cell of the memory array.

[0047] According to another embodiment, a method comprises reading trim information from a memory array by a read amplifier and storing the trim information on a trim register. The trim information is applied to the read amplifier, and then user data is read from the memory array by the read amplifier.

Claims

[1] Storage device comprising: a memory array (12) having a plurality of bit cells (210a, 210b), wherein the memory array (12) is configured to store trim information (16) and user data (18), wherein the trim information (16) is stored in a two-cells-per-bit mode in the memory array (12), and wherein the user data (18) is stored in a one-cell-per-bit mode in the memory array (12); a read amplifier (100) designed to read the trim information (18) from the memory array (12); a trim register (110) configured to receive the trim information (18) from the read amplifier (100); and wherein the read amplifier (100) is configured to receive the trim information (18) from the trim register (110) in order to be operated in a trimmed mode for reading the user data (18) from the memory array (12). [2] Storage device according to claim 1, wherein the plurality of bit cells (120a, 120b) comprises MRAM bit cells. [3] Storage device according to claim 1, wherein the read amplifier (100) is configured to read the trim information (16) from the storage array (12) in an untrimmed mode in which the trim information (16) is not applied to the read amplifier (100). [4] Storage device according to claim 1, further comprising a reference circuit (14) comprising a reference bit cell, wherein the read amplifier (100) is configured to compare a read current of a bit cell (120a, 120b) of the storage array (12) with a reference current of the reference bit cell (14) in one-cell-per-bit mode. [5] Storage device according to claim 1, further comprising an ECC decoder (140) connected to an output of the read amplifier (100), and wherein: the memory array (12) is designed to store ECC data (142); the read amplifier (100) is configured to read the ECC data (142) from the memory array (12) in the untrimmed mode; and the ECC decoder (140) is designed to receive the trim information (18) and the ECC data (142) from the read amplifier (100) and to output the trim information (18) to the trim register (110). [6] Storage device according to claim 1, further comprising a majority voting decoder (150) connected to an output of the read amplifier (100), and wherein: the memory array (12) is configured to store multiple copies of each bit of the trim information (16); the read amplifier (100) is configured to read each of the multiple copies of each bit of the trim information (16) in the untrimmed mode; and the majority voting decoder (150) is configured to receive the multiple copies of each bit of the trim information (16) and to output the trim information (16) to the trim register (110) in response to the multiple copies of each bit of the trim information (16). [7] Storage device according to claim 1, wherein the read amplifier (100) is configured to repeatedly read a predetermined data pattern from the storage array (12) before reading the trim information (16) from the storage array (12). [8] Methods, exhibiting: Providing a storage array (12); Determining trim information (16) for a reading amplifier (100); Writing a first bit of the trim information (16) to a first bit cell (120a, 120b) of the memory array (12) and writing a complement of the first bit of the trim information (16) to a second bit cell (120a, 120b) of the memory array (12), such that the trim information (16) is stored in a two-cells-per-bit mode in the memory array (12); and Writing user data (18) to the memory array, wherein the user data (18) is stored in a one-cell-per-bit mode in the memory array (12). [9] Method according to claim 8, wherein the memory array (12) is an MRAM array. [10] Method according to claim 8, further comprising reading the trim information (18) from the memory array (12) by the read amplifier (100). [11] The method of claim 10, further comprising: Applying the trim information (16) to the read amplifier (100); and then reading the user data (18) from the memory array (12) by the read amplifier (100). [12] Method according to claim 11, wherein the trim information (16) is read from the memory array (12) by the read amplifier (100) before the trim information (16) is applied. [13] Method according to claim 10, wherein reading the trim information (16) comprises comparing a read stream of the first bit cell (120a, 120b) with a read stream of the second bit cell (120a, 120b). [14] Method according to claim 8, further comprising writing multiple copies of the first bit of the trim information (16) to the storage array (12). [15] Procedure, encompassing: Reading trim information (16) from a memory array (12) by a read amplifier (100), wherein the trim information (16) is stored in a two-cells-per-bit mode in the memory array (12); Storing the trim information (16) on a trim register (110); Applying the trim information (16) to the reading amplifier (100); and then Reading user data (18) from the memory array (12) by the read amplifier (100), wherein the user data (18) is stored in a one-cell-per-bit mode in the memory array (12). [16] Method according to claim 15, further comprising reading ECC data (142) from the memory array (12) by the read amplifier (100) before the trim information (16) is applied to the read amplifier (100). [17] Method according to claim 15, wherein the memory array (12) comprises a plurality of MRAM bit cells (120a, 120b) and wherein reading the trim information (16) comprises comparing a read stream of a first bit cell (120a, 120b) from the plurality of bit cells (120a, 120b) with a read stream of a second bit cell (120a, 120b) from the plurality of bit cells (120a, 120b).

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