Single-photon avalanche diode devices

Abstract

Single-photon avalanche diode device, SPAD device, (2) comprising the following: a silicon layer (4); an active region (6) in the silicon layer (4) for detecting incident light, and which is defined by a pn junction; and a blocking structure which completely overlaps the active region to block incident light having a wavelength of at least in the range of 200 nm to 400 nm, such that light having this wavelength can only be detected by the SPAD device (2) when it is incident on a region of the silicon layer (4) outside the active region (6); wherein the blocking structure comprises a continuous metal layer (16) which overlaps the active region (6) or wherein the blocking structure comprises a continuous polysilicon layer (22).

Description

Technical application area

[0001] The present invention relates to photodiode devices and in particular to single-photon avalanche diodes (SPADs). background

[0002] Single-photon avalanche diodes (SPADs) are photodiodes that operate by applying a reverse bias voltage greater than the diode's breakdown voltage. A single charge carrier in the depletion region can therefore trigger a self-sustaining avalanche through impact ionization, enabling the detection of a single photon.

[0003] After the SPAD is triggered, current continues to flow until the reverse voltage is reduced to or below the breakdown voltage. To reduce the reverse voltage and thus reinitialize the SPAD, the diode can be loaded with a resistor across which the voltage drops. This is known as a passive quench circuit (PQC). The voltage drop V across the quench resistor is measured, and the voltage pulse is used as information indicating that an avalanche event has occurred. If no event occurs, the source voltage drops almost completely across the diode (in reverse bias). Alternatively, an active quench circuit can be used, which actively reduces the reverse voltage after the SPAD has been triggered.

[0004] Fig. Figure 1 shows a cross-section of a SPAD device 2 on a silicon substrate 4. The device has an active region 6 (also referred to as the detection region), which is defined by a pn junction. Photons incident on and absorbed by the active region 6 can release charge carriers and thus be detected. Passages 8 connect the silicon substrate 4 and the active region 6 to the first metal layer 10 of the backend stack 12 of the device 2. Further passages 14 connect the first metal layer 10 to the second metal layer 16 of the backend stack 12. The metal layers 10 and 16 are insulated from each other and from the underlying silicon substrate 4 by silicon oxide layers 18.

[0005] After absorbing a photon, a SPAD cannot be reactivated for a certain period of time (known as the "dead time"). The count rate of a SPAD, at a low rate of absorbed photons, is essentially linear (i.e., proportional to the photon absorption rate). At high light intensities, where the photon absorption rate is close to the inverse of the dead time, the SPAD begins to saturate, and the response becomes nonlinear. Consequently, the efficiency of a SPAD can decrease considerably at high light intensities, and SPAD devices therefore have a limited dynamic range (over which they produce a linear response), typically around four orders of magnitude. Other photodiodes can have a dynamic range of approximately 12 orders of magnitude, and the human eye has 14 orders of magnitude (5–6 without adaptation). Natural light conditions have 15 orders of magnitude, and artificial light can reach even higher values.

[0006] Since SPADs can detect single photons, the lower limit is typically not a problem with respect to the operating range. However, higher light intensities lead to saturation due to the limited number of counting cycles (dead time). To address this issue, a less sensitive SPAD can be used to extend the usable dynamic range. Two (or more) SPAD devices with staggered operating ranges can be combined (for example, in a silicon photomultiplier tube (SiPM)) to enable operation with a higher dynamic range.

[0007] US 2016 / 064579A1 describes a SPAD device comprising a radiation-blocking ring surrounding the active area of ​​the SPAD and a radiation-blocking cover configured to shield a portion of the active area from incident radiation. The blocking cover can be a metal layer with apertures, detecting only photons passing through the apertures. The effect of this attenuation is to reduce the number of photons detected by the SPAD, thus reducing the frequency of reinitialization and maintaining linearity at higher incident light intensities.

[0008] US 2012 / 0261547A1 describes the use of a transmission element with variable photon absorption properties, which is arranged in the upstream region of the light path of a photon-sensitive element. This allows for a variation in the intensity of the light reaching the element, thereby extending the operating range of the device.

[0009] EP 3 442 032 A1 discloses a single-photon avalanche diode (SPAD) comprising an active region that generates a photon-triggered avalanche current. A cover is arranged on or above the active region. The cover shields the active region from incident photons. The cover consists of a stack of at least one first and one second metal layer. At least one of the metal layers, e.g., the first metal layer, has an aperture. The metal layers are arranged in the stack with respect to an optical axis (OA) such that an effective aperture opens along this axis. Through the effective aperture, a portion of the active region is exposed to the photons incident along the optical axis (OA). The effective aperture is smaller than the aperture arranged in the first metal layer.

[0010] US 2008 / 0237769A1 discloses a sensor comprising a substrate provided with a circuit element-forming region and a photodiode-forming region, wherein the substrate has a silicon substrate, an insulating layer on the silicon substrate, and a silicon layer on the insulating layer; a photodiode in the silicon layer; a circuit element in the silicon layer; a first intermediate insulating film formed over the silicon layer; a first light-shielding film on the first intermediate film and having an opening in the photodiode-forming region; and a first intermediate-region light-shielding connector arranged between the two regions to connect the silicon substrate and the first light-shielding film.

[0011] US 2008 / 0295002 A1 discloses an embodiment of the present invention that provides a system for facilitating the capture of data displayed in a web browser for an application. During operation, the system receives a user command to retrieve data from the web browser for the application. The system then overlays a semi-transparent layer over at least a portion of the web browser so that the data in the web browser remains visible to the user. The system also receives a drawing command from the user to draw a shape around a data element in the web browser. The system then draws a shape around the data element in the web browser, with the shape being drawn on the semi-transparent layer. Finally, the system captures the data element bounded by the shape for the application.

[0012] US 2009 / 0057733A1 discloses an image sensor and a method for its fabrication. A semiconductor substrate can comprise a light-blocking and a light-receiving region. A photodiode can be formed in both the light-blocking and the light-receiving regions. A gate can be arranged laterally to the photodiode in the light-receiving region, and a light-blocking gate can be arranged on the photodiode in the light-blocking region. A salicide layer can be formed on the light-blocking gate.

[0013] US 2016 / 373676 A1 discloses an imaging system with single-photon avalanche diodes (SPADs) and sensor shifting for capturing multiple first images to generate an image with increased resolution, comprising (a) an image sensor with SPAD pixels for capturing the multiple first images at multiple spatially offset positions of the image sensor and (b) an actuator for shifting the image sensor parallel to its light-receiving surface to position it at the multiple spatially offset positions. A method for capturing multiple first images to generate an image with increased resolution comprises (a) shifting an image sensor parallel to its light-receiving surface to position it at multiple spatially offset positions and (b) capturing the multiple first images at the multiple spatially offset positions using SPAD pixels implemented in the pixel array of the image sensor.

[0014] Using known techniques, reducing the sensitivity (i.e., the photon detection probability (PDP)) of a SPAD device by more than 1 to 2 orders of magnitude is difficult to achieve in practice. For example, to achieve a PDP reduction of 2 orders of magnitude, the aperture opening would have to be 1% of the optically active area of ​​the device, which can be difficult to fabricate. Summary of the invention

[0015] Aspects of the present invention provide SPAD devices and methods for manufacturing them as set out in the attached claims.

[0016] Preferred embodiments of the present invention are described below with reference to the accompanying drawings. Brief description of the drawings Fig. Figure 1 is a schematic diagram of a cross-section of a SPAD device; Fig. Figure 2 is a schematic diagram of a cross-section of a SPAD device according to an embodiment which has a blocking structure comprising a continuous metal layer; Fig. Figure 3 is a schematic diagram of a cross-section of a SPAD device according to an embodiment which has a blocking structure comprising a polysilicon layer; Fig. Figure 4 is a schematic diagram of a cross-section of a SPAD device according to an embodiment which has a blocking structure comprising a salicide layer; Fig. Figure 5 is a schematic diagram of a cross-section of a SPAD device according to one embodiment; Fig. Figure 6 is a schematic diagram of a cross-section of a SPAD device according to an embodiment which has a silicon-on-insulator (SOI) structure; Fig. Figure 7 is a schematic diagram of a cross-section of a SPAD device according to an embodiment which has a deep trench isolation structure; and Fig. Figure 8 is a schematic diagram of a cross-section of a SPAD device according to an embodiment which has a protective ring. Detailed description

[0017] It is well known in the prior art that an aperture above the active region must allow some incident light to enter the photodiode's active region in order to trigger the avalanche current. Surprisingly, however, the inventors discovered that a SPAD with a blocking structure that blocks (i.e., reflects and / or absorbs) all light that would directly strike the active region still produces an output and can be used to detect photons. Sufficient light absorbed by the silicon outside the active region causes electron-hole pairs to reach the active region due to the longer carrier lifetime of electron-hole pairs, thus generating counts.SPAD devices are typically small in diameter (for example, a few tens of micrometers), and consequently, the light-generated carriers from the surroundings / periphery can contribute sufficiently to the sensitivity. Therefore, SPAD devices according to the embodiments described herein can provide an extended dynamic range. The embodiments described herein can be particularly useful for providing devices with a sensitivity reduction (PDP) of 4 to 8 orders of magnitude. Such low sensitivity is difficult to achieve with a single aperture, as such small apertures are extremely difficult to manufacture and exhibit a significant dependence on the angle of incidence.

[0018] Fig. Figure 2 shows a schematic diagram of a cross-section of a SPAD device 2 according to one embodiment. Similar features in the figures have been assigned the same reference numerals for ease of understanding. The SPAD device 2 comprises a silicon substrate 4, an active region 6 defined by a pn junction (also referred to as the "detection region"), and a first metal layer 10 in a backend stack 12 of the device 2. The first metal layer is connected to the silicon substrate 4 and the active region 6 by through holes 8, and additional through holes 14 connect the first metal layer 10 to a second metal layer 16. The metal layers 10 and 16 are insulated from each other and from the underlying silicon substrate 4 by insulating layers 18 (typically SiO2).Importantly, the second metal layer 16 forms a blocking structure that prevents incident photons from reaching the active region 6. Any photon that would directly strike the active region 6 of the device 2 would be reflected (or absorbed) by the second metal layer 16, thus significantly reducing the sensitivity of the device 2. Sensitivity is typically quantified by the photon detection probability (PDP). The blocking structure creates a SPAD 2 with an intentionally low PDP. The second metal layer 16 extends over a portion of the peripheral region 20 (i.e., the region outside the detection region 6) of the device 2. Further away from the active region 6, the coverage of the second metal layer 16 is reduced (e.g., intermittently) (not shown), allowing photons to reach the silicon 4 outside the active region 6.While the active region 6 is capable of detecting incident light, the blocking structure (in this case, the second metal layer 16) prevents any light from directly reaching the active region 6. Instead, the device 2 detects light indirectly by detecting charge carriers generated by light in the silicon 4 outside the active region 6, which then enter the active region 6 through lateral movement.

[0019] Fig. Figure 3 shows a schematic diagram of a cross-section of a SPAD device 2 according to another embodiment. The SPAD device 2 comprises a silicon substrate 4, an active region 6, and a first metal layer 10 in a backend stack 12 of the device 2. The first metal layer is connected to the silicon substrate 4 and the active region 6 by through holes 8, and additional through holes 14 connect the first metal layer 10 to a second metal layer 16. The metal layers 10 and 16 are insulated from each other and from the underlying silicon substrate 4 by insulating layers 18 (typically SiO2). A polysilicon layer 22 covers the active region 6. The polysilicon layer 22 can absorb incident photons to prevent photons from entering the active region 6, thereby reducing the sensitivity of the device 2.The polysilicon layer 22 can have a thickness in the range of 70 nm to 350 nm. Preferably, the polysilicon layer 22 is formed in the normal "POLY" step of a CMOS process, thus avoiding the need for a new, specific process step. The edges of the active region 6 are not covered by the polysilicon layer 22, but are covered by the first metal layer 10 and the second metal layer 16, which reflect any photons that would otherwise have been incident on the edge of the active region 6. The first metal layer 10, the second metal layer 16, and the polysilicon layer 22 together form a blocking structure that overlaps the entire active region. The blocking structure contains no apertures that would allow light to travel vertically, i.e., perpendicular to the plane of the silicon 4, to directly reach the active region 6.The SPAD can further contribute to the count rate by detecting charge carriers from photons absorbed in the silicon 4 outside the active region 6. Likewise, a small amount of light can be reflected between the first and second metal layers 10 and 16, thereby reaching the silicon 4. Polysilicon transmits low-frequency light (λ > 400 nm) and may not be suitable in a blocking structure for certain low-frequency applications. The embodiment can be used to block at least light with a wavelength in the range of approximately 200 nm to approximately 400 nm. Other embodiments, for example, those in [reference missing], [further details missing]. Fig. Two illustrated SPAD devices, which have a continuous metal layer overlapping the active area, can be used over a wider wavelength range.

[0020] In other embodiments, a polysilicon layer 22 can be used alone as a blocking structure or together with a portion of either the first metal layer 10 or the second metal layer 16 to provide continuous coverage. The through-holes 8 and 14 can likewise form part of the blocking structure.

[0021] Fig. Figure 4 shows a schematic diagram of a cross-section of a SPAD device 2 according to one embodiment. The SPAD device 2 is similar to the one shown in Fig. Figure 3 shows a polysilicon layer 22 that overlaps the active region 6 of the device 2. Directly on the polysilicon layer 22 is a salicide layer 24 (i.e., a metal silicide formed in a salicide process). The salicide layer 24 can have the additional advantage of also blocking IR light. The salicide layer 24 is preferably formed according to the normal gate formation sequence of a CMOS process.

[0022] The PDP of the SPAD can then be modified / controlled by incorporating guard rings (transitions with reverse bias) surrounding the SPAD. These guard rings can reduce the number of charge carriers originating from photons absorbed in the peripheral region or beyond that enter the active region, thereby further reducing the sensitivity of the SPAD device.

[0023] Deep trench insulation or silicon-on-insulator (SOI) technology can also be used to prevent the passage of light-generated carriers from the peripheral area to the active area of ​​the SPAD, in order to further reduce sensitivity.

[0024] Fig. Figure 5 shows a schematic diagram of a SPAD device 2 according to one embodiment, while the device 2 is in operation. A continuous section of the second metal layer 16 overlaps the active region 6 and reflects light 26 that would otherwise fall directly onto the active region 6. In the peripheral region 20 of the SPAD device 2, light 28 reaches the silicon substrate 4 via gap 30 in the metal layers 10 and 16. The light 28 is absorbed in the silicon 4 and excites an electron 32 and a hole (not shown). The electron 32 diffuses through the silicon 4 and eventually reaches the active region 6, where it causes a count due to the strong reverse bias applied to the active region 6 (i.e., applied via the photodiode of the SPAD device 2).

[0025] Fig. Figure 6 shows a schematic diagram of another embodiment of a SPAD device 2 in operation, which has a silicon-on-insulator (SOI) structure to further reduce the sensitivity of the SPAD device 2. The silicon substrate 4 is located on an insulating layer 34 (for example, SiO2), which in turn rests on another silicon substrate 36. Light 28 absorbed in the lower silicon substrate 26 cannot cause a count because excited charge carriers cannot traverse the insulating layer 34. An electron 32 excited by the incident light 28 diffuses a distance into the silicon 36 before undergoing recombination. Light 40 absorbed in the upper silicon substrate 4 can still cause counts.

[0026] Fig. Figure 7 shows a schematic diagram of another embodiment of a SPAD device 2 in operation, which has a deep trench insulation structure. A deep trench 42, which is filled with an insulating material, prevents some charge carriers from diffusing to the active area 6, and thereby reduces the sensitivity of the SPAD device 2.

[0027] Fig. Figure 8 shows a schematic diagram of a SPAD device 2 according to another embodiment while the device 2 is in operation. A guard ring 44 surrounds the active region 6 and prevents charge carriers from reaching the active region 6, thereby reducing the sensitivity of the SPAD device 2. The guard ring 44 is an n-doped well connected to a positive bias voltage that attracts the free electrons 32. Some charge carriers can diffuse below the guard ring 44 and into the active region 6, thereby causing counts.

[0028] The Fig. 6, Fig. 7 and Fig. Figure 8 shows embodiments which have a blocking structure comprising a continuous metal layer (the second metal layer 16) combined with other features (SOI, trench insulation, and protective rings) to further reduce the sensitivity of the SPAD device 2. One or more of these other features can also be combined with the one shown in the Fig. 3 and Fig. The polysilicon layer blocking structure 22 shown in 4 can be used.

[0029] The overlap of the metal cover (which extends into the peripheral area) can be used to modify the response. By making the metal cover wider so that it extends further into the peripheral area, the sensitivity of the SPAD can be further reduced. The metal layer can extend beyond the active area in a range of 1 µm to 1000 µm.

Claims

[1] Single photon avalanche diode device, SPAD device, (2) comprising the following: a silicon layer (4); an active region (6) in the silicon layer (4) for detecting incident light, and which is defined by a pn junction; and a blocking structure which completely overlaps the active region to block incident light having a wavelength of at least in the range of 200 nm to 400 nm, such that light having this wavelength can only be detected by the SPAD device (2) when it is incident on a region of the silicon layer (4) outside the active region (6); wherein the blocking structure comprises a continuous metal layer (16) which overlaps the active region (6) or wherein the blocking structure comprises a continuous polysilicon layer (22). [2] SPAD device (2) according to claim 1, wherein the blocking structure comprises the continuous metal layer (16) and wherein the continuous metal layer (16) further overlaps a peripheral area (20) of the SPAD device (2) which extends over a distance outside the active area (6), wherein the distance is in the range of 1 µm to 1000 µm. [3] SPAD device (2) according to claim 1 or 2, wherein the blocking structure comprises the continuous metal layer (16) and wherein the continuous metal layer (16) is the second metal layer in a CMOS backend stack (12) of the SPAD device (2). [4] SPAD device (2) according to claim 1, wherein the blocking structure comprises the continuous polysilicon layer (22) and wherein the continuous polysilicon layer (22) has a thickness in the range of 70 nm to 350 nm. [5] SPAD device (2) according to claim 1 or 4, wherein the blocking structure comprises the continuous polysilicon layer (22) and wherein the blocking structure further comprises a part of a metal layer (16). [6] SPAD device (2) according to claim 1, 4 or 5, wherein the blocking structure comprises the continuous polysilicon layer (22) and wherein the SPAD device (2) is a CMOS device. [7] SPAD device (2) according to one of claims 5 to 8, wherein the blocking structure further comprises a salicide layer (24) formed on the polysilicon layer. [8] SPAD device (2) according to any one of the preceding claims, and further comprising a silicon-on-insulator (SOI) structure. [9] SPAD device (2) according to any of the preceding claims, and further comprising a trench insulation (42). [10] SPAD device (2) according to one of the preceding claims, and further comprising a protective ring (44). [11] Method for manufacturing a single-photon avalanche diode device, SPAD device, (2) comprising the following: Providing a silicon layer (4); Forming an active region (6) in the silicon layer (4) for detecting incident light; Forming a blocking structure that completely overlaps the active area (6) to block incident light having a wavelength of at least in the range of 200 nm to 400 nm, so that light, which has this wavelength, can only be detected by the SPAD device (2) when it is incident on a region of the silicon layer (4) outside the active region (6); wherein the step of forming a blocking structure comprises depositing a continuous metal layer (16), which overlaps the active area (6) or wherein the step of forming the blocking structure comprises depositing a polysilicon layer (22) and patterning the polysilicon layer (22) such that at least part of the active area (6) is covered. [12] Method according to claim 11, wherein the step of forming a blocking structure comprises depositing the continuous metal layer (16) and wherein the continuous metal layer (16) further overlaps a peripheral area (20) of the SPAD device (2) which extends over a distance outside the active area (6), wherein the distance is in the range of 1 µm to 1000 µm. [13] Method according to claim 11 or 12, wherein the step of forming a blocking structure comprises depositing the continuous metal layer (16) and wherein the step of depositing the continuous metal layer (16) is carried out in a CMOS back-end-of-line (BEOL) process, and wherein the continuous metal layer (16) is the second metal layer in a CMOS back-end stack (12) of the SPAD device (2). [14] Method according to claim 11, wherein the step of forming the blocking structure comprises depositing the polysilicon layer (22) and patterning the polysilicon layer (22) such that at least a part of the active area (6) is covered and wherein the polysilicon layer (22) has a thickness in the range of 70 nm to 350 nm. [15] Method according to claim 11 or 12, wherein the step of forming the blocking structure comprises depositing the polysilicon layer (22) and patterning the polysilicon layer (22) such that at least a part of the active area (6) is covered, and wherein the steps of patterning the polysilicon layer (22) are carried out using the POLY mask in a CMOS process. [16] Method according to claim 11, 14 or 15, wherein the step of forming the blocking structure comprises depositing the polysilicon layer (22) and patterning the polysilicon layer (22) such that at least a part of the active area (6) is covered, and wherein the step of forming the blocking structure further comprises forming a salicide layer (24) on the polysilicon layer (22).

Images