METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH A DIFFUSION BLOCK

Abstract

Method for forming a semiconductor device, the method comprising: Formation of a conduction feature (30) in a first dielectric layer (24); Formation of a second dielectric layer (34) over the conduction feature (30); Etching an opening (42, 44) through the second dielectric layer (34), whereby the etching exposes an area of ​​the conduction feature (30); Deposition of a sacrificial layer (48) in the opening (42), wherein the sacrificial layer forms selectively more on the exposed surface of the conducting feature (30) than on surfaces of the second dielectric layer (34), wherein the sacrificial layer (48) consists of 5-decine with the chemical formula C 10 H 18 includes; Deposition of a barrier layer (50) in the opening (42, 44), wherein the barrier layer forms selectively on surfaces of the second dielectric layer (34) above the sacrificial layer (48), wherein the formation of the barrier layer comprises: Deposition of a conductive barrier material from one or more first precursors; and After deposition of the conductive barrier material, deposition of a doping metal from one or more second precursors; Removal of the sacrificial layer (48); and Depositing a conductive material (56) to fill the opening (42, 44), wherein the conductive material makes contact with the conducting feature; wherein the deposition of the conductive barrier material comprises the deposition of a first layer (51A) of the conductive barrier material, wherein the deposition of the dopant metal comprises the deposition of a layer (51B) of the dopant metal and further comprising the deposition of a second layer (51C) of the conductive barrier material on the layer of the dopant metal.

Description

GENERAL STATE OF THE ART

[0001] Integrated circuits contain interconnect structures that feature metal conductors and vias to serve as three-dimensional wiring structures. The function of these interconnect structures is to properly connect densely packed devices.

[0002] The interconnect structure incorporates metal conductors and vias. These conductors and vias are typically created using damascene processes, in which trenches and via openings are formed in dielectric layers. A barrier layer is then deposited, followed by the filling of the trenches and via openings with copper. After a chemical-mechanical polishing (CMP) process, the top surfaces of the conductors are flush, leaving the conductors and vias behind.

[0003] DE 10 2018 131 694 A1 describes a method for forming metallization layers of integrated circuits, wherein an etch stop layer is etched over a conductive structure with an etchant comprising an inhibitor, so that an inhibitor layer is formed on the conductive structure, which serves to prevent the deposition of a barrier layer on the conductive structure in a subsequent step.

[0004] US 2015 / 0255340A1 describes a barrier layer comprising multiple layers of tantalum / tantalum nitride or ruthenium / tantalum nitride, wherein the barrier layer is formed by atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

[0005] DE 10 2005 023 122 A1 describes an integrated circuit with a copper structure adjacent to a stack of three or more layers, the layer stack serving as a diffusion barrier.

[0006] US 2013 / 0140698A1 describes tantalum nitride layers doped with ruthenium, cobalt, or other materials to improve their barrier properties against copper. It also describes multilayer structures comprising a tantalum nitride layer and a layer containing ruthenium and / or cobalt.

[0007] US 2004 / 0197958A1 addresses the protection of copper wires during wafer manufacturing and specifically the vapor deposition of benzotriazole (BTA) for the protection of copper wires.

[0008] US Patent 2015 / 0294863A1 describes a method for forming a fin structure that has different materials at different locations in the fin structure, using a selective deposition process.

[0009] KR 10 2020 0 043 531 A describes a selective deposition process on a substrate comprising a first material with a first surface and a second material with a second surface. The first material consists essentially of hydrogen-terminated silicon, and the second material comprises a dielectric. The substrate is exposed to a radical initiator to activate the first surface. Subsequently, the substrate is exposed to a blocking compound to selectively deposit a blocking layer on the activated first surface. The blocking compound comprises a blocking molecule, which includes a start and a end group, the start group comprising at least one alkene or alkyne unit. A dielectric layer is then selectively formed on the second surface, with the blocking layer preventing the deposition of the dielectric layer on the first surface.The blocking layer comprises a multitude of silicon-carbon bonds.

[0010] WO 2019 / 018 379 A1 describes a process for the selective deposition of a barrier layer, wherein a substrate with a metal surface and a dielectric surface is exposed to a silane to selectively form a barrier layer on the metal surface. The silane comprises at least one compound with the general formula SiH3R, where R is selected from C4-C20 alkyl, perfluoroalkyl, alkenyl, or alkynyl groups. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The embodiments described in this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1, Fig. 2, Fig. 3 and Fig. Figure 4 shows cross-sectional views of intermediate stages in the formation of a metal conductor track and a via according to some embodiments. Fig. Figure 5 shows a cross-sectional view of an intermediate stage in the formation of a sacrificial material according to some embodiments. The Fig. 6A and Fig. Figure 6B shows cross-sectional views of intermediate stages in the formation of a barrier layer according to some embodiments. The Fig. 7A and Fig. Figure 7B shows deposition cycles used during the formation of a barrier layer according to some embodiments. The Fig. 8, Fig. 9, and Fig. Figure 10 shows cross-sectional views of intermediate stages in the formation of a metal conductor track and a via according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples of the realization of various features of the invention. To simplify the present disclosure, specific examples of components and arrangements or the like are described below. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are in direct contact, and it may also include embodiments in which additional features may be formed between the first and second features such that the first and second features cannot directly touch each other. Furthermore, reference numerals and / or symbols may be repeated in the various examples in the present disclosure.This repetition serves to simplify and clarify matters, and does not in itself establish any relationship between the various embodiments and / or configurations presented.

[0013] Furthermore, spatial relational terms such as "underlying," "below," "lower," "above," "upper," and the like can be used here for the sake of simplicity to describe the relationship of one element or feature to another element or feature (other elements or features), as illustrated in the figures. These spatial relational terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device can be oriented differently (rotated 90 degrees or in other directions), and the spatial designations used here can be interpreted accordingly.

[0014] A method for selectively forming a barrier layer for a conductivity feature is provided according to various embodiments. The intermediate steps in forming the conductivity feature are illustrated according to some embodiments. Some variants of some embodiments are presented. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. According to some embodiments of the present disclosure, forming the conductivity feature includes selectively forming a barrier layer over a conductive region in an opening, filling the opening with a metallic material, and performing planarization. The selective formation of the conductive barrier layer is achieved by forming a sacrificial layer on an underlying metallic feature.The sacrificial layer resists the adhesion of the barrier material such that the barrier layer selectively grows on the sidewalls of the via orifice, with little or no barrier forming on the sacrificial layer itself. The barrier layer is formed with a dopant metal incorporated into it (e.g., as a dopant or as a partial barrier layer) to increase its density. After the barrier layer has formed, machining is performed to remove the sacrificial layer. The remaining orifice is then filled with a metallic material, such as copper, formed on the metal feature.

[0015] Fig. Figure 1 shows a cross-sectional view of a package component 100 according to some embodiments of the present disclosure. The package component 100 can be a device wafer (such as a logic device wafer) with active devices, such as transistors and / or diodes, and can include passive devices, such as capacitors, inductors, resistors, or the like. According to alternative embodiments of the present disclosure, the package component 100 is an interposer wafer that may, but need not, include active and / or passive devices. According to further alternative embodiments of the present disclosure, the package component 100 is a package substrate strip that can include package substrates with cores or coreless package substrates. In the following discussion, a device wafer is used as an example of the package component 100.The findings from this disclosure can also be applied to interposer wafers, package substrates, packages, etc.

[0016] According to some embodiments of the present disclosure, the package component 100 comprises a semiconductor substrate 20 and features arranged on a top surface of the semiconductor substrate 20. The semiconductor substrate 20 may comprise crystalline silicon, crystalline germanium, silicon-germanium, a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, the like, or combinations thereof. In some embodiments, the semiconductor substrate 20 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. To isolate the active regions in the semiconductor substrate 20, shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 20.Although not shown, vias may be formed that extend into the semiconductor substrate 20 to electrically connect the features on opposite sides of the package component 100.

[0017] According to some embodiments of the present disclosure, the package component 100 is used to form a device die. In these embodiments, IC devices 22 are formed on a top surface of the semiconductor substrate 20. Examples of IC devices 22 include complementary metal-oxide-semiconductor transistors (CMOS transistors), resistors, capacitors, diodes, or the like. The details of the IC devices 22 are not shown here. According to alternative embodiments, the package component 100 is used to form interposers. According to these embodiments, the substrate 20 can, for example, also be a dielectric substrate.

[0018] In Fig. Figure 1 further shows a dielectric layer 24. The dielectric layer 24 can, for example, be an interlayer dielectric (ILD) or an intermetal dielectric (IMD). According to some embodiments of the present disclosure, the dielectric layer 24 is an ILD in which contact plugs are formed. The associated dielectric layer 24 can be formed from phosphor silicate glass (PSG), borosilicate glass (BSG), boron-doped phosphor silicate glass (BPSG), fluorine-doped silicate glass (FSG), a silicon oxide layer (formed using tetraethyl orthosilicate (TEOS)), the like, or combinations thereof.The dielectric layer 24 can be formed using spin coating, atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD) or the like.

[0019] According to some embodiments of the present disclosure, the dielectric layer 24 is an IMD in which metal conductors and / or vias are formed. The associated dielectric layer 24 can be formed from a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), another low-k dielectric material, the like, or combinations thereof. According to some embodiments of the present disclosure, forming the dielectric layer 24 comprises depositing a dielectric material containing a pore-forming agent and subsequently performing a post-treatment process to expel the pore-forming agent in order to form a porous dielectric layer 24.

[0020] Still with reference to Fig. In embodiment 1, a conduction feature 30 is formed in the dielectric layer 24. The conduction feature 30 can be a metal conductor, a conductive via, a contact connector, or the like. According to some embodiments, the conduction feature 30 has a diffusion barrier layer 26 and a conductive filler material 28 above the diffusion barrier layer 26. The diffusion barrier layer 26 can be formed from a conductive material, such as titanium, titanium nitride, tantalum, tantalum nitride, the like, or combinations thereof. The conductive filler material 28 can be formed from copper, a copper alloy, aluminum, another metal or metal alloy, the like, or combinations thereof. The function of the diffusion barrier layer 26 is to prevent the diffusion of the conductive material (such as copper) of the conductive filler material 28 into the dielectric layer 24.According to some embodiments of the present disclosure, the techniques described below can also be adopted in the formation of the conduction feature 30 in such a way that the bottom part of the diffusion barrier layer 26 is no longer formed.

[0021] As in Fig. As also shown in Figure 1, an etch stop layer 32 is formed above the dielectric layer 24 and the conductivity feature 30 according to some embodiments. The etch stop layer 32 is formed from a dielectric material that may contain one or more materials, such as aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, the like, or combinations thereof. In some cases, when using an etch stop layer 32 containing a metal (e.g., aluminum nitride, aluminum oxide, or the like), bonds may form with the subsequently formed sacrificial layer 48 (see Figure 1). Fig. 5), and thus, when using a metal-containing material for the etch stop layer, the blocking capacity of the sacrificial layer 48 can be improved. The etch stop layer 32 can be formed from a material that exhibits high etch selectivity with respect to the overlying dielectric layer 34, such that etching of the dielectric layer 34 can terminate at the etch stop layer 32. In some embodiments, the etch stop layer 32 can have a thickness T0 that is between approximately 1 nm and approximately 10 nm.

[0022] Still with reference to Fig. 1. A dielectric layer 34 is formed over the etch stop layer 32. In some embodiments, the dielectric layer 34 is an IMD or an ILD. The dielectric layer 34 can contain a dielectric material, such as an oxide, a nitride, a carbon-containing dielectric material, the like, or combinations thereof. For example, the dielectric layer 34 can be formed from PSG, BSG, BPSG, FSG, TEOS oxide, HSQ, MSQ, the like, or combinations thereof. In some embodiments, the dielectric layer 34 is a low-k dielectric layer, having a dielectric constant (k) value less than approximately 3.5 or less than approximately 3.0.

[0023] The Fig. 2 to 6B and the Fig. Figures 8 to 10 show a process for forming a metal conductor track 60 and a via 58 (see Fig. 10) according to some embodiments. It should be understood that while the examples shown in these figures describe a dual-damascene process, other embodiments also consider a single-damascene process in which a metal conductor track, a via, a contact plug, or the like is formed.

[0024] In the Fig. 2 and Fig. 3. According to some embodiments, a via opening 42 and a trench 44 are formed in the dielectric layer 34. The via opening 42 and the trench 44 can be formed, for example, using photolithography and etching techniques. In one example of a process for forming the via opening 42 and the trench 44, a hard metal mask 37 is first formed over the dielectric layer 34 and then structured to form an opening 38, as shown in Fig. Figure 2 is shown. The metal hard mask 37 can be formed from a material such as titanium nitride, boron nitride, another metal oxide or metal nitride, the like, or a combination thereof. The opening 38 in the metal hard mask 37 forms the structure of a trench (e.g., the one in Fig. 3 shown trench 44) fixed, which is then filled to accommodate a metal conductor track (e.g. the metal conductor track 60, which is in Fig. 10 is shown) to train.

[0025] After forming the opening 38, a photoresist 40 is formed over the dielectric layer 34 and over the metal hard mask 37. The photoresist 40 can be a single-layer photoresist or a multi-layer photoresist structure (e.g., a three-layer photoresist structure). The photoresist 40 is textured to expose the dielectric layer 34, which can be done using suitable techniques. The exposed dielectric layer 34 is then etched to form an opening 42 that extends at least partially into the dielectric layer 34, as shown in Fig. Figure 2 illustrates this. The etching of the dielectric layer 34 can be carried out using a wet etching process and / or a dry etching process (e.g., a plasma etching process). For example, the etching of the dielectric layer 34 can be carried out by using a process gas containing fluorine and carbon, where fluorine is used for etching and carbon protects the sidewalls of the resulting opening. With a suitable fluorine-to-carbon ratio, the opening 42 can be formed to have a desired profile. For example, the process gases for etching can contain one or more fluorine- and carbon-containing gases, such as C4F8, CH2F2, CF4, or the like, and they can include one or more carrier gases, such as Ar, N2, or the like.In one example of an etching process, the flow rate of C4F8 is in the range of approximately 0 sccm to approximately 50 sccm, the flow rate of CF4 is in the range of approximately 0 sccm to approximately 300 sccm (where at least one of the C4F8 molecules has a non-zero flow rate), and the flow rate of N2 is in the range of approximately 0 sccm to approximately 200 sccm. As another example, the process gases for etching can contain CH2F2 and a carrier gas, such as N2. The flow rate of CH2F2 can be in the range of approximately 10 sccm to approximately 200 sccm, and the flow rate of N2 can be in the range of approximately 50 sccm to approximately 100 sccm. During the etching process, the package component 100 can be maintained at a temperature in the range of approximately 30 °C to approximately 60 °C. A plasma can be generated from the etching gases during the etching process.The radio frequency (RF) power of the energy source for etching can be less than approximately 700 watts, and the pressure of the process gases is in the range of approximately 2 Pa to approximately 4 Pa. These are examples, and other etching processes or etching parameters are possible. In some embodiments, the etching of the dielectric layer 34 can be carried out for a period of time such that the opening 42 extends to an intermediate plane between a top surface and a bottom surface of the dielectric layer 34, as shown in [reference]. Fig. Figure 2 is shown. The duration can be specified.

[0026] With reference to Fig. 3. The photoresist 40 is then removed, followed by further etching of the dielectric layer 34 using the metal hard mask 37 as an etching mask. The etching process used to etch the dielectric layer 34 can, for example, be an anisotropic etching process. The etching process extends the opening 42 into the dielectric layer 34 until the opening 42 exposes the etch stop layer 32. The etching process extends the opening 42 and also forms a trench 44 that extends partially into the dielectric layer 34, as shown in Fig. Figure 3 is shown. In the structure resulting from the etching process, the finished opening 42 is referred to as the via opening 42, which lies below and adjoins the groove 44. The via opening 42 is then filled to form a via (e.g., the via 58 shown in Fig. 10 is shown).

[0027] According to alternative embodiments, the via opening 42 and the trench 44 are formed in separate photolithography processes. For example, in a first photolithography process, the via opening 42 can be formed, extending through the dielectric layer 34 to the etch stop layer 32. In a second lithography process, the trench 44 can be formed. According to various embodiments, the via opening 42 can be formed either before or after the trench 44.

[0028] The following refers to Fig. 4. An etching process is carried out to etch through the etch-stop layer 32 and expose the conductive filler material 28. In some cases, the etching process may also be referred to as a wet cleaning process if the etching of the etch-stop layer 32 involves a wet etching process. According to some embodiments of the present disclosure, the etching process uses a solution containing glycol, dimethyl sulfide, amine, H₂O₂, the like, or combinations thereof. For example, glycol may be used as a surfactant, dimethyl sulfide may be used as a solvent, amine may be used to remove the unwanted organic residue on the surfaces of the package component 100, and / or a compound of H₂O₂ and amine may be used to etch the etch-stop layer 32.

[0029] With reference to Fig. 5. A sacrificial layer 48 is now formed on the exposed surface of the conductive fill material 28. The sacrificial layer 48 can be formed to block, avoid, or otherwise prevent the subsequent formation of the barrier layer 50 on the conductive fill material 28 (see Fig. 6) is formed. By blocking the formation of the barrier layer 50 over the conductive filler material 28, the resistance of the interface between the conductive filler material 28 and the subsequently deposited conductive material 56 can be reduced. In some embodiments, the sacrificial layer 48 can extend over the via opening 42 so that it completely covers the exposed area of ​​the conductive filler material 28. In some embodiments, the sacrificial layer 48 is formed with a thickness T1 that is between approximately 0.5 nm and approximately 5 nm, for example, between approximately 1 nm and approximately 2 nm. The thickness T1 of the sacrificial layer 48 can be greater than, approximately equal to, or less than the thickness T0 of the etch stop layer 32. In this way, the sacrificial layer 48 can be formed on sidewall surfaces of the etch stop layer 32 in the via opening 42, as in Fig. 5 is shown.

[0030] According to some embodiments, the sacrificial layer 48 contains a material that adheres to or bonds with the conductive filler material 28 but does not adhere to or bond with the dielectric layer 34. For example, the material can form chelate bonds with the metal (e.g., copper or aluminum) in the conductive filler material 28 but not form bonds with the dielectric layer 34. In some cases, the sacrificial layer 48 can form chelate bonds with an etch stop layer 32 containing a metal (e.g., aluminum). Since the sacrificial layer 48 can form bonds with both the conductive filler material 28 and a metal-containing etch stop layer 32, the use of a metal-containing etch stop layer 32 can therefore enable the conductive filler material 28 to be more completely covered by the sacrificial layer 48.For example, the thickness of the sacrificial layer 48 in a metal-containing etch stop layer 32 can be greater than the thickness of the sacrificial layer 48 in an etch stop layer 32 that does not contain any metal (such as an etch stop layer 32 formed from silicon oxycarbohydride or the like). In this way, the barrier layer 50 (see . Fig. 6), which is subsequently formed, on the dielectric layer 34, but their formation on the conductive filler material 28 can be blocked. Furthermore, the sacrificial layer 48 can be a material to which the subsequently formed barrier layer 50 is unlikely to adhere or bond, or which is incapable of doing so. For example, the chemical structure of the material may be hydrophobic and / or contain nonpolar groups, making it unlikely that the precursors of the barrier layer 50 will bond, or incapable of doing so, or the chemical structure of the material may prevent the adsorption of the precursors of the barrier layer 50 due to steric hindrance. The material of the sacrificial layer 48 can be selected such that the precursors of the subsequently formed barrier layer 50 exhibit high selectivity for adsorption on the dielectric layer 34 above the sacrificial layer 48.For example, the selectivity of adsorption on the dielectric layer 34 compared to the adsorption on the sacrificial layer 48 can be greater than approximately 5:1, e.g., approximately 7.5:1, approximately 30:1, or greater than 30:1. The selectivity can depend on the different materials and / or manufacturing processes used. In this way, the sacrificial layer 48 is not covered (or only partially covered) by the barrier layer 50, and thus the sacrificial layer 48 can be treated by the post-deposition treatment 52, which is described below. Fig. As described in section 8, it can be removed more easily. In some cases, these material properties of the sacrificial layer 48 can cause an amount of the sacrificial layer 48 material to adhere to or be bound to the metal hard mask 37 in addition to the conductive filler material 28, although in other cases no material forms on the metal hard mask 37. The sacrificial layer 48 can be deposited by a suitable technique, such as wet chemical impregnation or chemical gas treatment, which may depend on the specific material(s) contained in the sacrificial layer 48.

[0031] As a first non-claims example, the sacrificial layer 48 can contain benzotriazole (BTA), which has the chemical formula C6H4N3H. The BTA molecules have a first side with three nitrogen atoms that can bond with a metal, such as copper, and a second side with a hydrophobic benzene ring that is incapable of bonding with the precursors of the barrier layer 50. The first side of the BTA molecule can bond with the conductive filler material 28, while the second side protrudes and blocks the binding of the precursors to the conductive filler material 28. In this way, a sacrificial layer 48, comprising a BTA monolayer or multiple BTA monolayers, can prevent the formation of the barrier layer 50 on the conductive filler material 28 or on the sacrificial layer 48.In some embodiments, a sacrificial layer 48 made of BTA can be formed by impregnating the package component 100 in a wet chemical solution containing BTA. For example, BTA can be a component of a solution containing H₂O and / or H₂O₂, but solutions with other compositions can also be used. The solution can be heated to a temperature between approximately 25 °C and approximately 50 °C, and the package component 100 can be impregnated for a duration of between approximately 10 seconds and approximately 60 seconds. After impregnation in the solution, a wet cleaning process can be performed on the package component 100. A sacrificial layer 48 containing BTA can be formed using solutions, process conditions, or techniques other than those described above. The material and deposition technique described are a non-claimed example, and the sacrificial layer 48 can be made of other non-claimed materials, such as...Bis-triazolyl-indolamine, thiol, phosphate, the like or combinations thereof, are formed using a wet chemical impregnation process.

[0032] In embodiments according to the invention, the sacrificial layer 48 contains a 5-decine with the chemical formula C 10 H 185-Decine molecules can form bonds with metals, such as copper, and also adhere to each other via van der Waals forces; however, the 5-decine molecules do not bond with the dielectric layer 34. Furthermore, the precursors of the barrier layer 50 do not form bonds with the 5-decine molecules. In this way, a sacrificial layer 48, which comprises a layer of 5-decine molecules, can prevent the formation of the barrier layer 50 on the conductive filler material 28 or on the sacrificial layer 48. In some embodiments, a sacrificial layer 48 made of 5-decine can be formed by exposing the package component 100 to a gas mixture containing 5-decine molecules. For example, the 5-decine can be part of a gas mixture containing carrier gases, such as helium, argon, or the like, but other mixtures can also be used.The gas mixture can be introduced into a process chamber, which can be the same process chamber in which other processes are carried out, such as etching, deposition of the barrier layer 50, post-deposition treatment 52, or other processes. By depositing the sacrificial layer 48 in this way "in-situ," contamination, costs, or the overall processing time for the package component 100 can be reduced. The gas mixture can be introduced into the process chamber at a flow rate between approximately 600 sccm and approximately 3000 sccm for a duration between approximately 10 seconds and approximately 120 seconds. A process temperature between approximately 100 °C and approximately 350 °C and a process pressure between approximately 133 Pa and approximately 4 kPa can be used. A 5-decine-containing sacrificial layer 48 can be formed using gas mixtures, process conditions, or techniques other than those described above.

[0033] In other non-claims examples, the sacrificial layer 48 is formed from other materials, such as thiol in the gas phase, BTA in the gas phase, other alkynes, alkenes, the like or combinations thereof, using a gas separation process.

[0034] With reference to the Fig. 6A and Fig. 6B, a conductive barrier layer 50 is deposited on surfaces in the via opening 42 and in the trench 44 according to some embodiments. The barrier layer 50 has the function of preventing atoms from entering the subsequently deposited conductive material 56 ( Fig. 9) diffuse into the dielectric layer 34. The barrier layer 50 forms over the exposed surfaces of the dielectric layer 34 and the etch stop layer 32, but its formation on the conductive filler material 28 is blocked by the sacrificial layer 48. Furthermore, as previously described, the barrier layer 50 does not form significantly on the exposed surfaces of the sacrificial layer 48. The barrier layer 50 can comprise a barrier material such as titanium, titanium nitride, tantalum, tantalum nitride, the like, or a combination thereof. In some embodiments, the barrier layer 50 also contains a dopant metal, which can be a transition metal such as Ru, Co, Mn, Al, Nb, or the like, another type of metal, the like, or a combination thereof.The incorporation of the dopant metal into the barrier layer 50 enables a denser barrier layer 50, which offers better protection against diffusion, and the incorporation of the dopant metal can also improve the thermal stability as well as the adhesion of the barrier layer 50. Fig. Figure 6A shows an embodiment in which a doping metal (e.g. Ru) is deposited together with a barrier material (e.g. TaN) to form the barrier layer 50, and Fig. Figure 6B shows an embodiment in which the barrier layer 50 comprises a sublayer 51B of a dopant metal (e.g., Ru) between two sublayers 51A, 51C of a barrier material (e.g., TaN). In some cases, by forming a barrier layer 50 containing the dopant metal, a barrier layer 50 with a total density greater than approximately 13 g / cm³ can be produced. 3 is.

[0035] In some embodiments, the barrier layer 50 can be deposited using a suitable process, such as an ALD process and / or a CVD process. In some cases, forming the barrier layer 50 using an ALD process and / or a CVD process can provide better stage coverage and higher conformance compared to other processes, such as a PVD process. In some embodiments, the deposition of the barrier layer 50 can take place in the same process chamber as the formation of the sacrificial layer 48. In some embodiments, the barrier layer 50 can be formed with a thickness T2 that is between approximately 1 nm and approximately 6 nm, for example, approximately 1.5 nm.

[0036] With reference to Fig. 6A The barrier layer 50 can be deposited using a process in which both a barrier material and a dopant metal are deposited. The barrier layer 50 can be deposited such that it has a desired concentration of the dopant metal. In some embodiments, the barrier layer 50 can be formed with a concentration of the dopant metal that is between approximately 5 atomic percent and approximately 30 atomic percent; however, other concentrations are possible. In some cases, a higher concentration of the dopant metal reduces the resistivity of the barrier layer 50.For example, a TaN barrier layer 50 doped with 10 atomic percent Ru may exhibit a resistivity approximately 59% of that of an undoped TaN barrier layer 50, and a barrier layer 50 doped with 20 atomic percent Ru may exhibit a resistivity approximately 17% of that of an undoped TaN barrier layer 50. These are examples, and the decrease in resistivity may differ in other cases. In some embodiments, the resistivity of the barrier layer 50 can be further reduced by the subsequent deposition treatment 52 (see Figure 52). Fig. 8) further reduced. In addition, a higher concentration of the doping metal can result in a denser barrier layer 50, and it can result in a barrier layer 50 that has a lower nitrogen concentration after the subsequent deposition treatment 52.

[0037] The barrier layer 50 can be deposited using an ALD process comprising one or more ALD cycles, with a layer of material being deposited in each cycle. An ALD cycle may include introducing a precursor of the barrier material into the process chamber, followed by purging the chamber using a purge gas, and then introducing a precursor of the dopant metal into the process chamber, followed by purging. The barrier material and / or the dopant metal may have more than one precursor, each of which can be introduced into the process chamber and followed by a corresponding purge. An ALD cycle can be repeated several times to deposit the barrier layer 50 to a desired thickness T2.For example, an ALD cycle can be performed between approximately 10 and approximately 80 times, although the ALD cycle can also be performed more or less often than specified.

[0038] With reference to Fig. Figure 7A presents an example of an ALD cycle of an ALD process for depositing a barrier layer 50 according to some embodiments. The Fig. The ALD cycle shown in 7A can be described in a similar way to the one in Fig. Figure 6A shows how to use a barrier layer 50 to deposit a barrier layer; however, other ALD cycles can be used in other cases. The example of an ALD cycle shown in Figure 6A is shown in Figure 6A. Fig. The process shown in Figure 7A comprises three steps. In the first step of the ALD cycle, a first precursor P1 of the barrier material flows into the process chamber for a certain period, and then purge gas is introduced into the process chamber for a certain period. In the second step, a second precursor P2 of the barrier material flows into the process chamber, and then purge gas is introduced into the process chamber. In this example of the ALD cycle, steps 1 and 2 together form one or more monolayers of the barrier material. In the third step, a precursor D1 of the dopant metal flows into the process chamber, and then the purge gas is introduced into the process chamber. In some cases, the concentration of the dopant metal in the barrier layer 50 can be controlled by controlling the parameters of the third step, such as the flow rate of precursor D1 or the duration of its flow into the process chamber.For example, a higher flow rate of D1 or a longer duration of D1 flow can result in more dopant metal being formed on the barrier material surface after step 2, thus increasing the concentration of dopant metal in the barrier layer 50. In some cases, step 3 may be skipped in some of the individual ALD cycles in which the barrier layer 50 is formed, which can result in a lower concentration of dopant metal in the barrier layer 50.

[0039] According to some embodiments of the present disclosure, the barrier layer comprises TaN 50 as a barrier material and Ru or Co as a dopant metal, and it is formed by an ALD process. The TaN precursors can, for example, be pentakis dimethylamine tantalum (“PDMAT”) as a first precursor (e.g., P1 in Fig. 7A), which has the chemical formula C 10 H 30N5Ta, and ammonia as a corresponding second precursor (e.g., P2), which has the chemical formula NH3. In some embodiments, when depositing Ru as a dopant metal, ruthenium tricarbonyl(1-methyl-1,4-cyclohexadiene) (“CHORuS”) can be used as a precursor (e.g., D1), and when depositing Co as a dopant metal, cobalt carbonyl tert-butylacetylene (“CCTBA”) can be used as a precursor (e.g., D1). Other precursors or combinations of precursors can be used to form the barrier material or the dopant metal. In some embodiments, in an ALD cycle, PDMAT flows into the process chamber at a flow rate between approximately 500 sccm and approximately 1500 sccm, and ammonia flows into the process chamber at a flow rate between approximately 500 sccm and approximately 3000 sccm.In some embodiments, the PDMAT is introduced for a duration of approximately 1 second to approximately 5 seconds, and the ammonia is introduced for a duration of approximately 1 second to approximately 5 seconds. In some embodiments, CHORuS flows into the process chamber at a flow rate of approximately 50 sccm to approximately 300 sccm and is introduced for a duration of approximately 1 second to approximately 10 seconds. The purge gas can be, for example, Ar, which can flow into the process chamber at a purge flow rate of approximately 1000 sccm to approximately 3000 sccm and be introduced for a duration of approximately 1 second to approximately 5 seconds. In some embodiments, the ALD cycles can be carried out at a process temperature between approximately 200 °C and approximately 350 °C and at a process pressure between approximately 133 Pa and approximately 667 Pa. Other process parameters are possible.

[0040] With reference to Fig. 6B The barrier layer 50 can be formed by alternately depositing partial layers of barrier material and dopant metal, according to some embodiments. Fig. Figure 6B shows, for example, an embodiment in which a partial layer 51A of barrier material is deposited, then a partial layer 51B of doping metal is deposited over the partial layer 51A, and then a partial layer 51C of barrier material is deposited over the partial layer 51B. Fig. Figure 6B shows an embodiment of a barrier layer 50 with a single dopant metal sublayer between two barrier material sublayers, but in other embodiments the barrier layer 50 may have more dopant metal sublayers or more barrier material sublayers than shown. In some embodiments, a dopant metal sublayer (or sublayers) may have a thickness TB between approximately 0.1 nm and approximately 0.6 nm, such as approximately 0.3 nm. In some embodiments, the barrier material sublayers may have a thickness between approximately 1 nm and approximately 6 nm, such as approximately 2 nm. Different sublayers of a barrier layer 50, including different sublayers of the same material, may have different thicknesses.More sublayers and / or thicker sublayers of doping metal can increase the overall density of the barrier layer 50 and thus improve the ability of the barrier layer 50 to block diffusion.

[0041] In some embodiments, the barrier layer 50 is formed using a deposition process comprising an ALD cycle, which is performed once or several times to deposit a partial layer of barrier material (e.g., partial layer 51A), followed by a CVD process to deposit a partial layer of dopant metal (e.g., partial layer 51B). By repeating the deposition process, alternating layers of barrier material and dopant metal can be deposited to form the barrier layer 50. A final partial layer of barrier material (e.g., partial layer 51C) can be deposited. In some embodiments, the ALD cycle can be performed between once and approximately 10 times to deposit a partial layer of barrier material to a desired thickness; however, in other embodiments, the ALD cycle can be performed more frequently.The ALD cycle(s) and the CVD process can be performed using the same process chamber.

[0042] With reference to Fig. Figure 7B presents an example of a deposition process for depositing a barrier layer 50 according to some embodiments. The deposition process described in Fig. As shown in 7B, it can be done in a similar way to the one in Fig. The process shown in Figure 6B can be used to deposit a barrier layer 50; however, in other cases, other deposition processes can be used. The example of a deposition process shown in Figure 6B is as follows: Fig. Figure 7B shows three stages, comprising a first ALD cycle, referred to as "ALD Cycle A", a CVD process, referred to as "CVD Process B", and a second ALD cycle, referred to as "ALD Cycle C". In the first stage, ALD Cycle A is performed once or several times to form a sublayer of barrier material (e.g., sublayer 51A). ALD Cycle A may include steps similar to those shown in Figure 7B. Fig. The ALD cycle shown in 7A is shown. For example, ALD cycle A can have a first step similar to step 1 of Fig. 7A is, and a second step similar to step 2 of Fig. 7A is included. In the second stage, CVD process B is carried out to deposit a partial layer of dopant metal (e.g., partial layer 51B). CVD process B may, for example, involve a precursor D1 of the dopant metal flowing into the process chamber, followed by the introduction of a purge gas. Other gases G1 may also flow into the process chamber while precursor D1 is being introduced. In some cases, the thickness of a partial layer of dopant metal can be influenced by controlling the parameters of CVD process B, such as the flow rate of precursor D1 or the duration of its flow into the process chamber. For example, a higher flow rate of D1 or a longer duration of D1 flow can result in a thicker layer of dopant metal being formed on the barrier material surface.

[0043] According to some embodiments of the present disclosure, the barrier layer comprises 50 barrier material sublayers containing TaN and one or more dopant metal sublayers containing Ru. The TaN precursors (e.g., P1 and P2) may, for example, contain PDMAT and ammonia. The Ru precursor (e.g., D1) may, for example, contain CHORuS. Other precursors or combinations of precursors may be used to form the barrier material or the dopant metal. The gas G1 may, for example, be H2, another gas, or a gas mixture. In some embodiments, during an ALD cycle, PDMAT flows into the process chamber at a flow rate between approximately 500 sccm and approximately 1500 sccm, and ammonia flows into the process chamber at a flow rate between approximately 500 sccm and approximately 3000 sccm.In some embodiments, PDMAT is introduced for a duration of approximately 1 second to approximately 5 seconds, and ammonia is introduced for a duration of approximately 1 second to approximately 5 seconds. In some embodiments, the ALD cycles are performed at a process temperature between approximately 200 °C and approximately 350 °C and a process pressure between approximately 133 Pa and approximately 667 Pa. In some embodiments, CHORuS flows into the process chamber in a CVD process at a flow rate between approximately 50 sccm and approximately 300 sccm and is introduced for a duration of approximately 1 second to approximately 10 seconds. In some embodiments, H2 flows into the process chamber at a flow rate between approximately 500 sccm and approximately 5000 sccm and is introduced for a duration of approximately 1 second to approximately 10 seconds. CHORuS and H2 can flow into the process chamber simultaneously.In some embodiments, the CVD process is carried out at a process temperature between approximately 150 °C and 300 °C and a process pressure between approximately 133 Pa and 2 kPa. The purge gas can be, for example, argon, which flows into the process chamber at a purge flow rate between approximately 1000 sccm and 3000 sccm and can be introduced for a duration of between approximately 1 second and 5 seconds. Other process parameters are possible.

[0044] With reference to Fig. In some embodiments, a subsequent deposition treatment 52 is carried out to remove the sacrificial layer 48 and expose the conductive filler material 28. The subsequent deposition treatment 52 can improve the performance of the barrier layer 50 by reducing its nitrogen content and its resistivity. In some cases, the subsequent deposition treatment 52 can also improve the adhesion of the barrier layer 50. After performing the subsequent deposition treatment 52, the barrier layer 50 can be separated from the conductive filler material 28 by a distance T1' approximately equal to the thickness T1 of the sacrificial layer 48. For example, the distance T1' can be between approximately 0.5 nm and approximately 5 nm, but other distances are also possible. As shown in Fig. As shown in Figure 8, the subsequent deposition treatment 52 can expose the side walls of the etch stop layer 32, which were previously covered by the sacrificial layer 48.

[0045] In some embodiments, the subsequent deposition treatment 52 includes a heat treatment, such as an annealing process. For example, the annealing process may involve annealing the package component 100 in an annealing chamber at a temperature between approximately 250 °C and approximately 400 °C for a duration between approximately 30 seconds and approximately 300 seconds. During the annealing process, the package component 100 may be exposed to one or more gases, such as a noble gas (e.g., He, Ar, or the like), a reducing gas (e.g., H₂ or the like), or a combination thereof. The gas(es) may flow into the annealing chamber at a flow rate between approximately 600 sccm and approximately 3000 sccm. During the annealing process, the pressure in the annealing chamber may be between approximately 133 Pa and approximately 4 kPa. In a subsequent deposition treatment 52, which includes a tempering process, tempering parameters other than these may be present.In some embodiments, the tempering chamber is the same chamber as the process chamber used for depositing the barrier layer 50.

[0046] In some embodiments, the subsequent deposition treatment 52 includes a plasma treatment. The plasma treatment may, for example, involve exposing the package component 100 to a plasma of one or more process gases, such as H₂, NH₃, Ar, the like, or combinations thereof. The process gas(es) may flow at a flow rate between approximately 600 sccm and approximately 3000 sccm. The plasma treatment may be performed at a pressure between approximately 13.3 Pa and approximately 667 Pa. In some embodiments, the plasma is generated by supplying a power between approximately 100 watts and approximately 600 watts. The plasma treatment may be performed at a temperature between approximately 25 °C and approximately 400 °C and may last between approximately 10 seconds and approximately 30 seconds. A subsequent deposition treatment 52 that includes a plasma treatment may have parameters other than those specified.In some embodiments, the plasma treatment is carried out in the same chamber as the process chamber used for depositing the barrier layer 50. In some embodiments, either a tempering process or a plasma treatment is performed. In other embodiments, both a tempering process and a plasma treatment are performed, and these can be carried out in any order.

[0047] The subsequent deposition treatment 52 can reduce the nitrogen concentration in the barrier layer 50, which can increase its density. The effectiveness of the barrier layer 50 in blocking diffusion into the dielectric layer 34 can thus be enhanced by the increased density of the barrier layer 50. In some cases, the subsequent deposition treatment 52 can reduce the nitrogen-to-tantal (N:Ta) ratio in the barrier layer 50 by approximately half. In some cases, the barrier layer 50 may exhibit an N:Ta ratio of 0.65:1 after the subsequent deposition treatment 52. However, it should be noted that the nitrogen reduction may be greater or lesser than in these examples, depending on the process details of the subsequent deposition treatment 52 and / or the composition of the barrier layer 50.

[0048] The subsequent deposition treatment 52 can reduce the resistivity of the barrier layer 50, which can improve the performance of the device. For example, after performing the subsequent deposition treatment 52, the barrier layer 50 may have a resistivity that is approximately 7% of the resistivity of the barrier layer 50 before performing the subsequent deposition treatment 52. In some cases, the barrier layer 50 may have a resistivity that is less than 200 µΩcm after performing the subsequent deposition treatment. However, it should be noted that the decrease in resistivity may be greater or less than in these examples, depending on the process details of the subsequent deposition treatment 52 and / or the composition of the barrier layer 50.

[0049] With reference to Fig. 9. A conductive material 56 is deposited to fill the via opening 42 and the trench 44 according to some embodiments. The conductive material 56 can be deposited, for example, by applying a cover coating using physical vapor deposition (PVD) to form a metal seed layer (e.g., a copper layer) and then filling the remainder of the via opening 42 and the trench 44, using, for example, electroplating, electroless plating, deposition, or the like. The conductive material 56 can comprise copper, a copper alloy, cobalt, tungsten, the like, other metals, or combinations thereof.

[0050] This is because the formation of the barrier layer 50 on the conductive filler material 28 is blocked (see the Fig. 6A-B), the conductive material 56 is deposited onto the exposed conductive filler material 28, forming a "barrier-free" interface between the conductive material 56 and the conductive filler material 28. In some cases, the contact resistance (Rc) of this barrier-free interface is lower than when the barrier layer 50 extends between the conductive material 56 and the conductive filler material 28. Furthermore, forming the conductive material 56 onto the conductive filler material 28 can improve the thermal stability of the interface between the conductive material 56 and the conductive filler material 28. In this way, the techniques described here can facilitate the formation of a dense barrier layer 50 (by incorporating a dopant metal) and improve the contact resistance between a via 58 and a metal conductor track 60 (see Fig. 10) enable. As in Fig. As shown in Figure 9, due to the separation distance T1' between the barrier layer 50 and the conductive filler material 28, the conductive material 56 can contact the side walls of the etch stop layer 32 that are not covered by the barrier layer 50. In this way, parts of the conductive material 56 can extend below the barrier layer 50, and the interface between the conductive material 56 and the conductive filler material 28 can be formed with a greater lateral width.

[0051] With reference to Fig. 10. A planarization process, such as a chemical-mechanical planarization process (CMP process), a mechanical polishing process, and / or a grinding process, can be performed to remove excess portions of the conductive material 56, according to some embodiments, so that the via 58 and the metal conductor track 60 are formed. The via 58 and the metal conductor track 60 each have a portion of the barrier layer 50 and a portion of the conductive material 56. Fig. Figure 10 also shows the formation of the dielectric etch stop layer 62, which covers and contacts the dielectric layer 34 and the metal conductor track 60. According to some embodiments, the dielectric etch stop layer 62 is formed from one or more layers of metal oxide, metal nitride, metal carbonitride, silicon nitride, the like, or combinations thereof.

[0052] The embodiments of the present disclosure exhibit several advantageous features. By using a sacrificial layer to block the formation of the barrier layer on a conducting feature, a conductive material (e.g., from a via) can be formed that directly contacts the conducting feature. This reduces the contact resistance of the interface between the conducting feature and the conductive material, which can improve the performance of the device. It also improves the thermal stability of the interface, thereby limiting the time-dependent dielectric breakdown (TDDB) of the device and improving the yield. Furthermore, by forming a barrier layer containing a dopant metal, the density of the barrier layer can be increased, which can improve its diffusion-blocking properties.This allows for the formation of a truly dense barrier layer, utilizing a higher conformance process such as ALD or CVD instead of lower conformance deposition processes. The dopant metal can be present throughout the barrier layer, or one or more sublayers of the dopant metal can be formed within the barrier layer. A barrier layer formed in this way can also exhibit improved adhesion and improved resistivity.

[0053] The invention is defined by the independent claims. Embodiments of the invention are defined by the dependent claims.

Claims

[1] Method for forming a semiconductor device, the method comprising: Formation of a conduction feature (30) in a first dielectric layer (24); Formation of a second dielectric layer (34) over the conduction feature (30); Etching an opening (42, 44) through the second dielectric layer (34), whereby the etching exposes an area of ​​the conduction feature (30); Deposition of a sacrificial layer (48) in the opening (42), wherein the sacrificial layer forms selectively more on the exposed surface of the conducting feature (30) than on surfaces of the second dielectric layer (34), wherein the sacrificial layer (48) consists of 5-decine with the chemical formula C 10 H 18 includes; Deposition of a barrier layer (50) in the opening (42, 44), wherein the barrier layer forms selectively on surfaces of the second dielectric layer (34) above the sacrificial layer (48), wherein the formation of the barrier layer comprises: Deposition of a conductive barrier material from one or more first precursors; and After deposition of the conductive barrier material, deposition of a doping metal from one or more second precursors; Removal of the sacrificial layer (48); and Depositing a conductive material (56) to fill the opening (42, 44), wherein the conductive material makes contact with the conducting feature; wherein the deposition of the conductive barrier material comprises the deposition of a first layer (51A) of the conductive barrier material, wherein the deposition of the dopant metal comprises the deposition of a layer (51B) of the dopant metal and further comprising the deposition of a second layer (51C) of the conductive barrier material on the layer of the dopant metal. [2] Method according to claim 1, wherein the removal of the sacrificial layer (48) comprises performing a plasma treatment process. [3] Method according to claim 2, wherein the density of the barrier layer (50) is increased by the plasma treatment process. [4] Method according to any of the preceding claims, wherein the deposition of the barrier layer (50) comprises an atomic layer deposition process. [5] Method according to any of the preceding claims, wherein the deposition of the conductive barrier material comprises a chemical vapor deposition process. [6] Method according to any of the preceding claims, wherein the deposition of the sacrificial layer (48) is carried out in the same process chamber as the etching of the opening (42, 44) through the second dielectric layer (34). [7] Method according to any of the preceding claims, wherein the doping metal is ruthenium. [8] Method according to any of the preceding claims, wherein the conductive barrier material is tantalum nitride. [9] Method according to any of the preceding claims, wherein the layer (51B) of the doping metal has a thickness in the range between 0.1 nm and 0.6 nm. [10] Method for forming a semiconductor device, comprising: Forming an insulating layer (34) over a conducting feature (30), wherein the conducting feature (30) has a conductive filler material (28) and the conductive filler material is formed from a metal or a metal alloy; Etching of the insulating layer (34) to expose a first surface of the conductive filler material (28); Covering the first surface of the conductive filler material (28) with a sacrificial material (48), wherein the side walls of the insulating layer (34) are free of the sacrificial material; Covering the side walls of the insulating layer (34) with a barrier material (50), wherein the first surface of the conductive filler material (28) is free of the barrier material, the barrier material comprising tantalum nitride doped with a transition metal; Removal of the sacrificial material (48); and Covering the barrier material (50) and the first surface of the conductive filler material (28) with a conductive material (56); wherein the sacrificial material (48) is deposited on the first surface of the conductive filler material (28) by exposing the semiconductor device to a gas mixture, wherein the gas mixture contains 5-decyne molecules with the chemical formula C 10 H 18 contains. [11] Method according to claim 10, further comprising forming an etch stop layer (32) over the conduction feature (30). [12] Method according to claim 10 or 11, wherein the barrier material (50) has an atomic percentage of the transition metal in the range between 5% and 30%. [13] Method according to any one of claims 10 to 12, wherein the removal of the sacrificial material (48) comprises heat treatment, wherein hydrogen is used as a process gas. [14] Method according to any one of claims 10 to 13, wherein the covering of the first surface of the conductive filler material (28) with the sacrificial material is carried out in the same process chamber as the etching of the insulating layer (34). [15] Method according to any one of claims 10 to 14, wherein the covering of the first surface of the conductive filling material (28) with the sacrificial material is carried out in the same process chamber as the covering of the side walls of the insulation layer (34) with the barrier material (50).

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