3D FERROELECTRIC STORAGE

Abstract

Storage device comprising: a lower source / drain region (106l) and an upper source / drain region (106u) located above the lower source / drain region (106l); a semiconductor channel (104) located above the lower source / drain region (106l) and which lies beneath the upper source / drain region (106u); a control gate electrode (114) extending along a sidewall of the semiconductor channel (104) and along individual sidewalls of the lower (106l) and upper source / drain regions (106u); a gate dielectric layer (110) and a ferroelectric layer (112) separating the control gate electrode (114) from the semiconductor channel (104) and the lower (106l) and upper source / drain regions (106u); and a second semiconductor channel (104) and a source / drain dielectric layer (116), which lie above the lower source / drain region (106l) and below the upper source / drain region (106u), wherein the source / drain dielectric layer (116) is located between the semiconductor channel (104) and the second semiconductor channel (104).

Description

GENERAL STATE OF THE ART

[0001] Two-dimensional (2D) memory blocks are prevalent in electronic devices and can include, for example, NOR flash memory blocks, NAND flash memory blocks, dynamic random access memory (DRAM) blocks, etc. However, 2D memory blocks are reaching scaling limits and therefore also limits in storage density. Three-dimensional (3D) memory blocks are a promising candidate for increasing storage density and can include, for example, 3D NAND flash memory blocks, 3D NOR flash memory blocks, etc.

[0002] WO 2018 / 144 957 A1 discloses a 3D device, the device comprising: at least four active transistor layers, each layer containing a plurality of transistors; and at least one programmable contact per layer for each layer of the at least four active transistor layers. US 10 403 631 B1 discloses three-dimensional ferroelectric memory devices and methods for forming the ferroelectric memory devices. Furthermore, relevant prior art for the present invention is provided by US 2014 / 0 340 952 A1 and US 2019 / 0 273 086 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1A to 1C illustrate various views of some embodiments of an MFIS memory cell. The Fig. 2A to 2D illustrate various views of some embodiments of a three-dimensional (3D) memory block comprising MFIS memory cells arranged as shown in FIGS. Fig. 1A to 1C are configured. The Fig. 3A to 3G illustrate cross-sectional views of various alternative embodiments of the 3D memory block of Fig. 2A, in which components of the 3D memory block are varied. The Fig. 4A to 4D illustrate cross-sectional views of various alternative embodiments of the 3D memory block of Fig. 2A, in which traces comprising metal define source lines and bit lines. The Fig. 5A to 5C illustrate various views of some embodiments of an integrated circuit (IC) having a 3D memory block. Fig. Figure 6 illustrates a schematic view of some embodiments of a portion of the 3D memory block of Fig. 5A to 5C. The Fig. 7A and Fig. 7B illustrate cross-sectional views of some alternative embodiments of the IC of Fig. 5A to 5C, in which word lines are located at a bottom surface of the 3D memory block and at a top surface of the 3D memory block, respectively. The Fig. 8A and Fig. 8B illustrate cross-sectional views of some alternative embodiments of the IC of Fig. 7A and Fig. 7B. The Fig. 9A and Fig. 9B to the Fig. 18A and Fig. 18B illustrate a series of views of some embodiments of a method for forming an IC having a 3D memory block of MFIS memory cells. Fig. Figure 19 illustrates a block diagram of some embodiments of the method of Fig. 9A and Fig. 9B to the Fig. 18A and Fig. 18B. The Fig. 20A and Fig. 20B to the Fig. 27A and Fig. 27B illustrate a series of views of some embodiments of a method for forming an IC having a 3D memory block of MFIS memory cells in which word lines are located at a bottom of the 3D memory block and a top of the 3D memory block, respectively. Fig. Figure 28 illustrates a block diagram of some embodiments of the method of Fig. 20A and Fig. 20B to the Fig. 27A and Fig. 27B. DETAILED DESCRIPTION

[0004] The present disclosure provides many different embodiments or examples for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and also embodiments where additional functions may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.

[0005] Furthermore, for ease of discussion, spatially relative terms such as "beneath," "under," "lower," "over," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device during use or operation of the device, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] Some three-dimensional (3D) memory devices include multiple memory cells defining multiple memory blocks at different elevations above a substrate. In some embodiments, a lower source / drain region, a semiconductor channel, and an upper source / drain region are stacked vertically and define a common sidewall. A control gate electrode and a data storage layer extend vertically through the multiple memory blocks along the common sidewall. The data storage layer is located between and adjacent to the semiconductor channel and the control gate electrode. The data storage layer further includes a silicon nitride layer separated from the control gate electrode and the semiconductor channel by silicon oxide.

[0007] During programming and erasing operations, electrons tunnel through silicon oxide into or out of the silicon nitride layer, so a bit of data can be represented by the amount of charge in the silicon nitride layer. One challenge is that programming and erasing operations depend on high voltages for electron tunneling and, therefore, for programming and erasing operations. Such high voltages can include, for example, voltages greater than approximately 10 volts or another suitable voltage. Another challenge is that the tunneling current is low, and therefore programming and erasing speeds are slow. Such slow speeds can include, for example, speeds greater than approximately 10 microseconds or another suitable time period.Another challenge is that power consumption is high due to the high voltages and also the slow speeds during programming and erasing operations.

[0008] Various embodiments of the present disclosure are directed to a metal-ferroelectric-insulator-semiconductor (MFIS) memory device and a method for forming the same. It should be noted that, although MFIS stands for metal-ferroelectric-insulator-semiconductor, doped polysilicon and other suitable conductive materials may be used instead of metal. According to some embodiments of the MFIS memory device, a lower source / drain region and an upper source / drain region are vertically stacked. A semiconductor channel lies above the lower source / drain region and below the upper source / drain region. Furthermore, the semiconductor channel extends from the lower source / drain region to the upper source / drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source / drain regions.The control gate electrode is separated from the semiconductor channel and the lower and upper source / drain regions by a ferroelectric layer and a gate dielectric layer.

[0009] The ferroelectric layer has a polarity that represents a data bit. During a programming operation, a programming voltage is applied across the ferroelectric layer from the control gate electrode to the semiconductor channel to change the polarity to a programmed state. During an erase operation, an erase voltage is applied across the ferroelectric layer from the control gate electrode to the semiconductor channel to change the polarity to an erased state. By using the ferroelectric layer for data storage, as opposed to a silicon nitride layer, there is no dependence on carrier tunneling. This allows programming and erase voltages to be reduced and programming and erase speeds to be increased. For example, programming and erase voltages can be reduced to less than approximately 5 volts and / or programming and erase speeds to less than approximately 100 nanoseconds.However, other suitable values ​​are conceivable. Power consumption can be reduced by reducing the programming and erase voltages and increasing the programming and erase speeds.

[0010] With reference to the Fig. 1A to 1C, various views 100A-100C of some embodiments of an MFIS memory cell 102 are provided. Fig. 1A corresponds to a cross-sectional view 100A along the line A in Fig. 1C, while Fig. 1B of a cross-sectional view 100B along the line B in Fig. 1C. Furthermore, Fig. 1C of a top view 100C. The MFIS memory cell 102 may be or include, for example, an MFIS field-effect transistor (MFIS-FET) or another suitable type of semiconductor device having an MFIS stack.

[0011] A semiconductor channel 104 lies above a lower source / drain region 106l and below an upper source / drain region 106u. The semiconductor channel 104, the lower source / drain region 106l, and the upper source / drain region 106u define a common sidewall 108 facing a gate dielectric layer 110, a ferroelectric layer 112, and a control gate electrode 114. In some embodiments, the common sidewall 108 is flat and / or planar. The gate dielectric layer 110, the ferroelectric layer 112, and the control gate electrode 114 extend along the common sidewall 108 from the lower source / drain region 106l to the upper source / drain region 106u.

[0012] The gate dielectric layer 110 and the ferroelectric layer 112 separate the control gate electrode 114 from the common sidewall 108. The gate dielectric layer 110 is located between the ferroelectric layer 112 and the common sidewall 108, and the ferroelectric layer 112 is located between the control gate electrode 114 and the gate dielectric layer 110. Furthermore, the ferroelectric layer 112 has a polarity that represents a data bit and is therefore used for data storage.

[0013] During programming and erasing operations of the MFIS memory cell 102, the lower and upper source / drain regions 106l, 106u are electrically coupled in parallel and are used as a proxy for the semiconductor channel 104. A programming voltage is applied from the control gate electrode 114 to the semiconductor channel 104 (e.g., via the lower and upper source / drain regions 106l, 106u) to set the polarity to a programmed state. Furthermore, an erase voltage with a polarity opposite to the programming voltage is applied from the control gate electrode 114 to the semiconductor channel 104 (e.g., via the lower and upper source / drain regions 106l, 106u) to set the polarity to an erased state. The programmed state may, for example, represent a binary "1," while the erased state may, for example, represent a binary "0," or vice versa.

[0014] The ferroelectric layer 112 shields an electric field generated by the control gate electrode 114 differently depending on whether the polarity is in the programmed or erased state. As such, the MFIS memory cell 102 has a programmed threshold voltage and an erased threshold voltage, respectively, while the polarity is in the programmed and erased states. During a read operation of the MFIS memory cell 102, the control gate electrode 114 is biased with a read voltage between the programmed and erased threshold voltages, and the resistance of the semiconductor channel 104 is measured. Depending on whether the semiconductor channel 104 is conductive, the polarity is either in the programmed or erased state.

[0015] By using the ferroelectric layer 112 for data storage, as opposed to a silicon nitride layer, there is no dependence on carrier tunneling for the programming and erase operations. This allows programming and erase voltages to be reduced and programming and erase speeds to be increased. For example, the programming and erase voltages can be reduced to less than approximately 5 volts and / or the programming and erase speeds to less than approximately 100 nanoseconds. However, other suitable values ​​are conceivable. By reducing the programming and erase voltages and increasing the programming and erase speeds, power consumption can be reduced.

[0016] With further reference to the Fig. 1A to 1C, the semiconductor channel 104 extends from the lower source / drain region 106l to the upper source / drain region 106u. The semiconductor channel 104 may, for example, be doped or undoped and may, for example, be or include polysilicon and / or other suitable semiconductor material(s). The semiconductor channel 104 may, for example, have a thickness (e.g., in the X-direction) of approximately 10 to 30 nanometers, approximately 10 to 20 nanometers, approximately 20 to 30 nanometers, or another suitable value.

[0017] The lower and upper source / drain regions 106l, 106u are doped and may, for example, be or comprise polysilicon and / or other suitable semiconductor material(s). In some embodiments, the lower and upper source / drain regions 106l, 106u are or comprise doped polysilicon with a first doping type, and the semiconductor channel 104 is or comprise doped polysilicon with a second doping type opposite to the first doping type. In some other embodiments, the lower and upper source / drain regions 106l, 106u are or comprise doped polysilicon, and the semiconductor channel 104 is or comprise undoped polysilicon.

[0018] The gate dielectric layer 110, the ferroelectric layer 112, and the control gate electrode 114 are located on the sides of the lower and upper source / drain regions 106l, 106u. As such, the gate dielectric layer 110, the ferroelectric layer 112, and the control gate electrode 114 are uncovered by the upper source / drain region 106u. The control gate electrode 114 may be or include, for example, titanium nitride, doped polysilicon (e.g., N+ or P+), tantalum nitride, tungsten, other suitable conductive materials, or any combination of the foregoing.

[0019] The gate dielectric layer 110 may be or include, for example, silicon oxide (e.g., SiO2), aluminum oxide (e.g., Al2O3), silicon oxynitride (e.g., SiON), silicon nitride (e.g., Si3N4), lanthanum oxide (e.g., La2O3), strontium titanium oxide (e.g., SrTiO3), undoped hafnium oxide (e.g., HfO2), other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the gate dielectric layer 110 is or includes a high-k dielectric material having a dielectric constant greater than about 3.9, about 10, or another suitable value. In some embodiments, the gate dielectric layer 110 has a dielectric constant of about 3.9 to 15, about 3.9 to 10, about 10 to 15, or another suitable value. If the dielectric constant is too low (e.g.less than approximately 3.9 or another suitable value), an electric field across the gate dielectric layer 110 may be high. The high electric field may result in a high time-dependent dielectric breakdown (TDDB) and therefore reduce the reliability of the gate dielectric layer 110.

[0020] In some embodiments, a thickness T gdl of the gate dielectric layer 110 (e.g., in an X-direction) is less than approximately 2.5 nanometers or another suitable value. In some embodiments, the thickness T gdl approximately 1.5 to 2.5 nanometers, approximately 1.5 to 1.75 nanometers, approximately 1.75 to 2.5 nanometers, or another suitable value. If the thickness T gdl is too small (e.g., less than approximately 1 nanometer or another suitable value), the leakage current may be high and therefore data storage low. If the thickness T gdlIf the thickness is too large (e.g., greater than approximately 2.5 nanometers or another suitable value), the programming and erase voltages may be large, and the memory window (e.g., a difference between the programming and erase threshold voltages) may be small. The former leads to low efficiency, while the latter leads to low reliability.

[0021] The ferroelectric layer 112 is in the orthorhombic phase and may, for example, be or include hafnium oxide (e.g., HfO2) doped with: 1) aluminum to less than about 20 atomic percent; 2) silicon to less than about 5 atomic percent; 3) zirconium to less than about 50 atomic percent; 4) lanthanum to less than about 50 atomic percent; 5) strontium to less than about 50 atomic percent; or 5) another suitable element. However, other atomic percentages are conceivable. Additionally or alternatively, the ferroelectric layer 112 may, for example, be or include one or more other suitable ferroelectric materials. In some embodiments, the dielectric constant of the ferroelectric layer 112 is greater than that of the gate dielectric layer 110.

[0022] In some embodiments, a thickness T feof the ferroelectric layer 112 (e.g., in the X-direction) is less than approximately 15 nanometers or another suitable value. In some embodiments, the thickness T gdl approximately 5 to 15 nanometers, approximately 5 to 10 nanometers, approximately 10 to 15 nanometers, or another suitable value. If the thickness T fe is too small (e.g., less than approximately 5 nanometers or another suitable value), the polarity may alternate weekly between the programmed and erased states during the programming and erasing process. As a result, reliability may be low. If the thickness T fe is too large (e.g., larger than approximately 15 nanometers or another suitable value), the programming and erase voltages may be large and therefore the power efficiency may be low.

[0023] A dielectric structure 116 surrounds the MFIS memory cell 102. The dielectric structure 116 separates the lower and upper source / drain regions 106l, 106u from each other and, as will be seen below, separates the MFIS memory cell 102 from other MFIS memory cells when the MFIS memory cell 102 is integrated into a memory block. Note that a portion of the dielectric structure 116 that separates the lower and upper source / drain regions 106l, 106u from each other may also be known as a source / drain dielectric layer. The dielectric structure 116 may, for example, be or include silicon oxide and / or other suitable dielectric(s).

[0024] With reference to the Fig. 2A to 2D are various views 200A to 200D of some embodiments of a 3D memory block 202 having a plurality of MFIS memory cells 102 arranged as shown in FIGS. Fig. 1A to 1C are configured. Fig. 2A corresponds to a cross-sectional view 200A along the line C in Fig. 2D. Fig. 2B corresponds to a cross-sectional view 200B along the line D in Fig. 2D. Fig. 2C corresponds to a cross-sectional view 200C along the line E in Fig. 2D. Fig. 2D corresponds to a plan view 200D along the lines CE in the Fig. 2A to 2C. For example, the 3D memory block 202 can provide high storage density as well as high reliability (e.g., high endurance and high retention) for high-speed and low-power applications.

[0025] The MFIS memory cells 102 are grouped into a first memory block 204a and a second memory block 204b. The first and second memory blocks 204a, 204b are stacked vertically above a dielectric substrate 206, and the second memory block 204b lies above the first memory block 204a. The first and second memory blocks 204a, 204b have the same layout and each have 9 rows and 8 columns (best in Fig. 2D). In alternative embodiments, the first and second memory blocks 204a, 204b have more or fewer rows and / or more or fewer columns. For readability, the rows and columns are not labeled. However, it should be understood that the rows extend in the X direction (e.g., laterally in the cross-sectional views 200A, 200B of Fig. 2A and Fig. 2B), while the columns extend in a Y-direction (e.g., laterally in the cross-sectional view 200C of Fig. 2C).

[0026] A plurality of control gate electrodes 114, a ferroelectric layer 112, and a gate dielectric layer 110 extend through the first and second memory blocks 204a, 204b and partially define the MFIS memory cells 102. The control gate electrodes 114 are shared by the MFIS memory cells in the first memory block 204a and the MFIS memory cells in the second memory block 204b. For example, each MFIS memory cell in the first memory block 204a may share a control gate electrode with an overlying MFIS memory cell in the second memory block 204b. Similarly, the ferroelectric layer 112 and the gate dielectric layer 110 are shared by MFIS memory cells in the first memory block 204a and MFIS memory cells in the second memory block 204b. For example, the ferroelectric layer 112 may be split because the polarization of the ferroelectric layer 112 may be localized to an MFIS memory cell in which the polarization has occurred.

[0027] The MFIS memory cells 102 are further grouped into pairs 208 of adjacent MFIS memory cells (e.g., the MFIS pairs 208) along corresponding rows. The MFIS memory cells in each of the MFIS pairs 208 share a corresponding one of the control gate electrodes 114. An MFIS memory cell on a right side of a corresponding control gate electrode is as shown in the Fig. 1A to 1C. An MFIS memory cell on the left side of a corresponding control gate electrode is as shown in Fig. 1A to 1C, except that the Fig. 1A and Fig. 1C should be mirrored horizontally along the Z-axis and the Y-axis accordingly. Fig. 1B is the same regardless of whether an MFIS memory cell is located on the left or right side of a corresponding control gate electrode.

[0028] The MFIS pairs 208 are arranged such that an MFIS pair occurs every two columns along each row and every other row along each column. Furthermore, the MFIS pairs 208 are staggered along adjacent columns and adjacent rows, so that a pitch P y the MFIS pairs 208 extend in a Y-direction over a row and a pitch P x of the MFIS pairs 208 extends across two columns in an X-direction. In some embodiments, the control gate electrodes 114 have individual widths W in the Y-direction. cg which is less than approximately half of the division P y in the Y direction.

[0029] A plurality of semiconductor channels 104, a plurality of lower source / drain regions 106l, and a plurality of upper source / drain regions 106u also partially define the MFIS memory cells 102. Note that "lower" and "upper" are relative to the corresponding MFIS memory cells 102 of the lower and upper source / drain regions 106l, 106u. The semiconductor channels 104 extend along the columns, respectively, and are shared by the corresponding MFIS memory cells in the corresponding columns. For example, a semiconductor channel may be shared by a plurality of MFIS memory cells because an electric field generated by an MFIS memory cell is localized to the MFIS memory cell. In alternative embodiments, the semiconductor channels 104 are individual to the MFIS memory cells 102 and are therefore not shared.Similar to the semiconductor channels 104, the lower and upper source / drain regions 106l, 106u extend along the columns, respectively, and are shared by the MFIS memory cells in the corresponding columns. Furthermore, the upper source / drain regions 106u define bit lines BL, and the lower source / drain regions 106l define source lines SL. In alternative embodiments, the upper source / drain regions 106u define source lines SL, and the lower source / drain regions 106l define bit lines BL.

[0030] A plurality of block dielectric layers 210 and a dielectric structure 116 surround the first and second memory blocks 204a, 204b. The block dielectric layers 210 are individual for the first and second memory blocks 204a, 204b and are each located on top of the upper source / drain region 106u of the individual memory block. The block dielectric layers 210 are made of a different material than the dielectric substrate 206 and may, for example, be or include silicon nitride and / or other suitable dielectrics. The dielectric structure 116 is located along sidewalls of the MFIS memory cells 102 to laterally separate the MFIS memory cells 102 from each other.

[0031] While the Fig. 2A to 2D illustrate a 3D memory block with two memory block levels, more memory block levels are conceivable. For example, the second memory block 204b may be repeated together with the corresponding block dielectric layer 210 over the second memory block 204b. While the Fig. While FIGS. 2A to 2D illustrate a 3D memory block with two memory block levels, a two-dimensional (2D) memory block with a single memory block level is conceivable. For example, the second memory block 204b may be omitted along with its corresponding one of the block dielectric layers 210.

[0032] With reference to Fig. 3A is a cross-sectional view 300A of some alternative embodiments of the 3D memory block 202 of Fig. 2A, in which the 3D memory block 202 is not covered by the gate dielectric layer 110 and the ferroelectric layer 112. As a result, the gate dielectric layer 110 comprises a plurality of discrete gate dielectric segments, and the ferroelectric layer 112 comprises a plurality of discrete ferroelectric segments. The gate dielectric segments and the ferroelectric segments are shared by the first and second memory blocks 204a, 204b, and they have U-shaped profiles. In alternative embodiments, the gate dielectric segments and / or the ferroelectric segments have other suitable profiles. Furthermore, the gate dielectric segments and the ferroelectric segments alternate with the lower and upper source / drain regions 106l, 106u along the rows. As shown in FIGS. Fig. 2A to 2D, rows extend in an X direction.

[0033] With reference to the Fig. 3B and Fig. 3C are cross-sectional views 300B, 300C of some alternative embodiments of the 3D memory block 202 of Fig. 2A, in which the control gate electrodes 114 and the dielectric structure 116 bulge at the semiconductor channels 104. Furthermore, the gate dielectric layer 110 and the ferroelectric layer 112 wrap around sides of the bulges. In Fig. 3B, the semiconductor channels 104 have rectangular profiles and are recessed relative to the sidewalls of the lower and upper source / drain regions 106l, 106u. In Fig. 3C, the semiconductor channels 104 have C-shaped and reverse C-shaped profiles, respectively. In alternative embodiments, the semiconductor channels 104 have other suitable profiles.

[0034] With reference to the Fig. 3D to 3F are cross-sectional views 300D-300F of some alternative embodiments of the 3D memory block 202 of Fig. 2A, in which the gate dielectric layer 110 comprises a plurality of discrete gate dielectric segments that are respectively located beneath the upper source / drain regions 106u. Fig. 3D and Fig. 3E, the semiconductor channels 104 have corresponding C-shaped and inverted C-shaped profiles that wrap around sides of the gate dielectric segments, respectively. In Fig. 3E, the control gate electrodes 114 and the dielectric structure 116 further bulge at the gate dielectric segments, and the gate dielectric segments have C-shaped and inverted C-shaped profiles that wrap around the sides of the bulges, respectively. In Fig. 3F, the semiconductor channels 104 have rectangular profiles and therefore do not wrap around the sides of the gate dielectric segments. In alternative embodiments, the semiconductor channels 104 and / or the gate dielectric segments have other suitable profiles.

[0035] With reference to Fig. Figure 3G is a cross-sectional view 300G of some alternative embodiments of the 3D memory block 202 of Fig. 2A, in which cavities 302 separate the control gate electrodes 114 from each other instead of the dielectric structure 116. The cavities 302 comprise air and / or other suitable gas(es). Furthermore, the cavities 302 are sealed by a sealing dielectric layer 304. The sealing dielectric layer 304 covers the 3D memory block 202 and the cavities 302 and may comprise, for example, silicon oxide and / or other suitable dielectric(s).

[0036] While the Fig. 3A to 3G are cross-sectional views 300A-300G of some alternative embodiments of Fig. 2A in which components are modified, it is understood that the modifications also apply to each of the Fig. 2B to 2D can be applied. For example, if the modifications of Fig. 3A on the Fig. 2B to 2D, the gate dielectric layer 110 and the ferroelectric layer 112 can be deposited from above on the block dielectric layer 210 of the second memory block 204b into the Fig. 2B and Fig. 2C be removed. Fig. 2D can remain unchanged. While Fig. 2D in relation to the Fig. 2A to 2C, each of the Fig. 3A to 3G for embodiments of Fig. 2D, modified as required as described above, taken along line C. Fig. 3G can be used in alternative embodiments of Fig. 2D, in which the dielectric structure 116 has been replaced by the cavities 302, taken along the line C. As a further example, the Fig. 3A to 3C in the embodiments of Fig. 2D along line C without modification of Fig. 2D must be taken.

[0037] With reference to Fig. 4A is a cross-sectional view 400A of some alternative embodiments of the 3D memory block of Fig. 2A, in which a plurality of metal lines 402 define the source lines SL and the bit lines BL instead of the lower and upper source / drain regions 106l, 106u. The metal lines 402 extend along the columns accordingly. Furthermore, the metal lines 402 for the lower and upper source / drain regions 106l, 106u are individual and electrically couple directly to the individual source / drain regions. In the case of the upper source / drain regions 106u, the upper source / drain regions 106u lie beneath the corresponding metal lines and directly contact them. In the case of the lower source / drain regions 106l, the lower source / drain regions 106l lie above the corresponding metal lines and directly contact them.

[0038] The metal lines 402 have lower resistances than the lower and upper source / drain regions 106l, 106u and therefore reduce voltage drops along the source lines SL and the bit lines BL. The reduced voltage drops enable larger memory blocks and / or reduced power consumption. The metal lines 402 include corresponding metal layers 404 and corresponding barrier layers 406. The barrier layers 406 are configured to prevent the diffusion of material from the metal layers 404 outward to an overlying structure and / or underlying structure. The metal layers 404 may be or include, for example, tungsten and / or other suitable metal(s). The barrier layers 406 may be or include, for example, titanium nitride (e.g., TiN), tungsten nitride (e.g., WN), other suitable barrier material(s), or any combination of the foregoing.

[0039] With reference to Fig. 4B is a cross-sectional view 400B of some alternative embodiments of the 3D memory block of Fig. 4A, in which dummy semiconductor channels 408 are located on sidewalls of the metal lines 402 to protect the metal lines 402 from oxidation. Such oxidation may occur, for example, before and / or during the deposition of the gate dielectric layer 110 and the ferroelectric layer 112. The oxidation may increase the resistances of the metal lines 402 and thereby increase voltage drops along the metal lines 402. This, in turn, may increase the power consumption and / or limit the size of the 3D memory block 202. The dummy semiconductor channels 408 are described accordingly as the semiconductor channels 104. This may be due, for example, to formation by the same or a similar process.

[0040] In some embodiments, the dummy semiconductor channels 408 have individual widths W dsc which are equal or substantially equal to individual widths W sc of the semiconductor channels 104. In alternative embodiments, the dummy semiconductor channels 408 have individual widths W dsc which are different (e.g. larger or smaller) than the individual widths W sc of the semiconductor channels 104. The different widths may, for example, be due to different etching processes during the formation of recesses within which the dummy semiconductor channels 408 and the semiconductor channels 104 are formed, and / or may, for example, be due to different etching rates during the formation of the recesses. However, other suitable reasons are conceivable.

[0041] With reference to Fig. 4C is a cross-sectional view 400C of some alternative embodiments of the 3D memory block of Fig. 2A, in which a plurality of silicide lines 410 are used instead of the plurality of metal lines 402. Therefore, the source lines SL and the bit lines BL are defined by the silicide lines 410. The silicide lines 410 are a metal silicide and may be or include, for example, nickel silicide or another suitable metal silicide.

[0042] As mentioned with reference to Fig. 4B, oxidation of the metal lines 402 may occur without dummy semiconductor channels 408 protecting sidewalls of the metal lines 402. Such oxidation, in turn, may negatively impact the performance of the 3D memory block 202. The silicide lines 410 may have comparable resistance to the metal lines 402 and therefore comparable performance to the metal lines 402. Furthermore, the silicide lines 410 may have lower reactivity to oxygen than the metal lines 402. Therefore, by replacing the metal lines 402 with the silicide lines 410, the challenges associated with oxidation without the dummy semiconductor channels 408 may be mitigated. The dummy semiconductor channels 408 may add complexity to forming the 3D memory block 202, so omitting the dummy semiconductor channels 408 may reduce costs and / or increase yields.

[0043] With reference to Fig. 4D is a cross-sectional view 400D of some alternative embodiments of the 3D memory block of Fig. 4C, in which the lower and upper source / drain regions 106l, 106u are omitted. Instead, the silicide lines 410 are used as source / drain regions for the MFIS memory cells 102.

[0044] While the Fig. 4A to 4D are cross-sectional views 400A-400D of some alternative embodiments of the 3D memory block of Fig. 2A in an X-direction, it is understood that plan views of the alternative embodiments as in Fig. can be illustrated in 2D. Fig. 2D can be, for example, along the line C in one of the Fig. 4A to 4D. Similarly, it is understood that the cross-sectional views of the alternative embodiments are taken in a Y-direction as in Fig. 2C, except that the vertical layer stacks would be modified to accommodate the Fig. 4A to 4D.

[0045] With reference to the Fig. 5A to 5C, various views 500A-500C of some embodiments of an integrated circuit (IC) including a 3D memory block 202 are provided. The 3D memory block 202 is as shown in FIGS. Fig. 2A to 2D and has additional columns. In alternative embodiments, the 3D memory block 202 is as shown in one of the Fig. 3A to 3G and 4A to 4D and further includes the additional columns. Fig. 5A corresponds to a cross-sectional view 500A along the line F in Fig. 5C and Fig. 5B corresponds to a cross-sectional view 500B along the line G in Fig. 5C. Furthermore, Fig. 5C the lines F and G in the Fig. 5A and Fig. 5B.

[0046] The 3D memory block 202 lies above a semiconductor substrate 502 within an interconnect structure 504. The semiconductor substrate 502 may, for example, be or include a bulk substrate made of monocrystalline silicon and / or another suitable semiconductor substrate type. The interconnect structure 504 includes a dielectric interconnect layer 506, a plurality of wires 508, and a plurality of vias 510. The wires 508 and the vias 510 are alternately stacked within the interconnect dielectric layer 506 to define conductive traces above and below the 3D memory block 202. The interconnect dielectric layer 506 may, for example, be or include silicon oxide and / or other suitable dielectric(s). The wires 508 and the vias 510 may, for example, be or include metal and / or other suitable conductive material(s).

[0047] The plurality of wires 508 define upper word line wires TWL (in Fig. 5C) overlying the 3D memory block 202 and extending along the rows of the 3D memory block 202, respectively. Furthermore, the plurality of vias 510 define top electrode vias TEV that extend from the control gate electrodes 114 to the top word lines TWL, respectively. Therefore, the top word lines TWL and the top electrode vias TEV electrically couple to control gate electrodes in corresponding rows and interconnect them.

[0048] The semiconductor devices 512 are located on the semiconductor substrate 502, between the semiconductor substrate 502 and the interconnect structure 504. The semiconductor devices 512 include corresponding pairs of source / drain regions 514, corresponding gate electrodes 516, and corresponding gate dielectric layers 518. The gate electrodes 516 correspond to the pairs of source / drain regions 514 and are arranged laterally between the source / drain regions of the corresponding pairs. The gate dielectric layer 518 is correspondingly located beneath the gate electrodes 516 to separate the gate electrodes 516 from the semiconductor substrate 502. The semiconductor devices 512 may be, for example, metal-oxide-semiconductor FETs (MOS), fin-FETs, nanostructure FETs, gate-all-around FETs (GAA), or another suitable semiconductor device type. Furthermore, the semiconductor devices 512 may implement, for example, read and write circuits for the 3D memory block 202.

[0049] A trench isolation structure 520 extends into the semiconductor substrate 502 to provide electrical isolation between the semiconductor devices 512 and other semiconductor devices (not shown) on the semiconductor substrate 502. The trench isolation structure 520 may be or include, for example, silicon oxide and / or other suitable dielectric(s). Further, the trench isolation structure 520 may be or include, for example, a shallow trench isolation (STI) structure and / or another suitable type of trench isolation structure.

[0050] With reference to Fig. 6 is a schematic view 600 of some embodiments of a portion of the 3D memory block 202 of the Fig. 5A to 5C in the box BX in the Fig. 5A to 5C. Box BX extends over two rows and eight columns. The rows have corresponding upper word lines TWL with subscripts indicating specific row numbers starting at row m, where m is an integer value. The columns have corresponding bit lines BL and corresponding source lines SL with subscripts indicating specific column numbers starting at column n, where n is an integer value.

[0051] The upper word lines TWL extend along the rows, respectively, and electrically couple to the MFIS memory cells 102 in the corresponding rows via the control gate electrodes 114 in the corresponding rows. The bit lines BL and the source lines SL extend along the columns, respectively, and electrically couple to the MFIS memory cells 102 in the corresponding columns via the lower and upper source / drain regions 106l, 106u (see, e.g., the Fig. 5A to 5C) in the corresponding columns. Together, the upper word lines TWL, the bit lines BL, and the source lines SL facilitate read and write operations with respect to the MFIS memory cells 102.

[0052] With reference to the Fig. 7A and Fig. 7B are cross-sectional views 700A, 700B of some alternative embodiments of the IC of the Fig. 5A to 5C, in which word lines electrically couple to the control gate electrodes 114, respectively, at a bottom of the 3D memory block 202 and a top of the 3D memory block 202. The cross-sectional view 700A of Fig. 7A corresponds to the cross-sectional view 500A of Fig. 5A and the cross-sectional view 700B of Fig. 7B corresponds to the cross-sectional view 500B of Fig. 5B.

[0053] Control electrodes in even-numbered rows electrically couple to lower word lines BWL on a bottom surface of the 3D memory block 202, and control electrodes in odd-numbered rows electrically couple to upper word lines TWL on a top surface of the 3D memory block 202, or vice versa. Furthermore, the control gate electrodes 114 have different cross-sectional profiles depending on whether they are electrically coupled to upper or lower word lines. Control gate electrodes electrically coupled to the lower word lines BWL have protrusions that protrude correspondingly to the lower word lines BWL and define lower electrode vias BEV. Control gate electrodes electrically coupled to the upper word lines TWL have no upward and downward protrusions and are electrically coupled to the upper word lines TWL by separate upper electrode vias TEV.

[0054] By splitting the word lines between the bottom of the 3D memory block 202 and the top of the 3D memory block 202, a split of the word lines in a Y-direction (e.g., into and out of the page; see, for example, Fig. 5C). Design constraints regarding wordline spacing may otherwise limit the pitch. By reducing the wordline pitch, the downsizing of the 3D memory block 202 may be improved.

[0055] With reference to the Fig. 8A and Fig. 8B are cross-sectional views 800A, 800B of some alternative embodiments of the IC of the Fig. 7A and Fig. 7B, in which the lower electrode vias BEV are independent of the control gate electrodes 114. The control gate electrodes 114 have the same or substantially the same profile regardless of whether they are electrically coupled to upper or lower word lines. Furthermore, the control gate electrodes 114 extend through a cap dielectric layer 802 between the 3D memory block 202 and the lower electrode vias BEV. Control gate electrodes electrically coupled to the lower word lines BWL extend, respectively, through the cap dielectric layer 802 to the lower electrode vias BEV. Control gate electrodes electrically coupled to the upper word lines TWL extend through the cap dielectric layer 802 to the interconnect dielectric layer 506. The cap dielectric layer 802 may, for example, be silicon nitride and / or another material.other suitable dielectrics.

[0056] The 3D memory block 202 is as in Fig. 3A is not covered by the gate dielectric layer 110 and the ferroelectric layer 112. As such, the gate dielectric layer 110 includes a plurality of discrete gate dielectric segments, and the ferroelectric layer 112 includes a plurality of discrete ferroelectric segments. A plurality of spacers 804 separate the control gate electrodes 114 from the ferroelectric segments. Furthermore, the dielectric structure 116 extends through the cap dielectric layer 802, the gate dielectric segments, and the ferroelectric segments. The spacers 804 may be or include, for example, silicon nitride and / or other suitable dielectric(s).

[0057] As will be seen below, the spacers 804 may be formed by a self-alignment process and used with an upper one of the block dielectric layers 210 as a mask to form openings in which the control gate electrodes 114 are formed. This may result in a reduction in the number of photomasks used during formation of the 3D memory block 202. Since photolithography is expensive, the reduction may substantially result in cost savings. Furthermore, as will be seen below, the spacers 804 protect the ferroelectric layer 112 while forming openings in which the control gate electrodes 114 are formed. This, in turn, reduces the likelihood of damage to the ferroelectric layer 112 and may therefore improve the performance of the MFIS memory cells 102. Furthermore, by forming the bottom electrode vias BEV independently of the control gate electrodes 114, aspect ratios (e.g.,The height-to-width ratios of the openings in which the control gate electrodes 114 are formed can be reduced. This, in turn, can reduce the complexity of the etching used to form the openings and increase the process window (e.g., elasticity).

[0058] While the IC designs in the Fig. 7A, Fig. 7B, Fig. 8A and Fig. 8B are not accompanied by any plan views, it is understood that the plan view 500C of Fig. 5C is representative of these top views with a few modifications. The top electrode vias TEV and the top word lines TWL for even-numbered rows or odd-numbered rows, but not both, instead correspond to bottom electrode vias BEV and bottom word lines BWL and should therefore be shown in phantom. Furthermore, the sizes of electrode vias and / or shapes of electrode vias may vary. Accordingly, the cross-sectional views 700A, 800A of Fig. 7A and Fig. 8A for example along line F in Fig. 5C (as modified above) and the cross-sectional views 700B, 800B of Fig. 7B and Fig. 8B for example along line G in Fig. 5C (as modified above).

[0059] With reference to the Fig. 9A and Fig. 9B to the Fig. 18A and Fig. 18B, a series of views of some embodiments of a method for forming an IC having a 3D memory block of MFIS memory cells are provided. Figures labeled with a suffix B illustrate cross-sectional views along line H, I, or J (whichever is present) in like-numbered figures with a suffix A. Figures with a suffix A illustrate top views along line H, I, or J (whichever is present) in like-numbered figures with a suffix B. The method can be used, for example, to form the IC of the Fig. 5A to 5C or other suitable ICs.

[0060] As illustrated by the top and cross-sectional views 900A, 900B of the Fig. 9A and Fig. 9B, a semiconductor device 512 and a trench isolation structure 520 are formed on a semiconductor substrate 502. The device 512 includes a pair of source / drain regions 514, a gate electrode 516, and a gate dielectric layer 518. The gate electrode 516 and the gate dielectric layer 518 are stacked between the source / drain regions 514. The trench isolation structure 520 surrounds the semiconductor device 512 to electrically isolate the semiconductor device 512 from other semiconductor devices (not shown).

[0061] Also by the top view and cross-sectional views 900A, 900B of Fig. 9A and Fig. As illustrated in Figure 9B, an interconnect structure 504 is partially formed over the semiconductor device 512 and the semiconductor substrate 502. The interconnect structure 504 includes a bottom interconnect dielectric layer 506a, a plurality of bottom wires 508a, and a plurality of bottom vias 510a. The bottom wires 508a and the bottom vias 510a are alternately stacked within the bottom interconnect dielectric layer 506a and define conductive traces extending from the semiconductor device 512 and other semiconductor devices (not shown) on the semiconductor substrate 502.

[0062] As shown by the top and cross-sectional views 1000A, 1000B of the Fig. 10A and Fig. 10B, a first storage film 1002a and a second storage film 1002b are formed over the interconnect structure 504 of the Fig. 9A and Fig. 9B. For the sake of simplicity, only an upper portion of the interconnect structure 504 is shown, which corresponds to the lower interconnect dielectric layer 506a. A remainder of the interconnect structure 504 is formed as shown in FIGS. Fig. 9A and Fig. 9B. The first and second memory films 1002a, 1002b include respective source / drain layers 1004, respective source / drain dielectric layers 116a, and respective block dielectric layers 210 that are vertically stacked. The source / drain dielectric layers 116a are each located between two of the source / drain layers 1004. The block dielectric layers 210 are respectively located on a top surface of the first and second memory films 1002a, 1002b and are made of a different material than portions of the lower interconnect dielectric layer 506a that extend along a top surface of the lower interconnect dielectric layer 506a.

[0063] In some embodiments, the source / drain layers 1004 are or include doped polysilicon and / or other suitable semiconductor material(s). In some embodiments, the source / drain dielectric layers 116a are or include silicon oxide and / or other suitable dielectric(s). In some embodiments, the block dielectric layers 210 are or include silicon nitride and / or other suitable dielectric(s).

[0064] While two memory films are deposited stacked over the interconnect structure 504, in alternative embodiments, more or fewer memory films may be deposited. For example, the second memory film 1002b may be omitted, so that only a single memory film may be deposited. As another example, the second memory film 1002b may be deposited repeatedly, so that three or more memory films may be deposited. In alternative embodiments, to form a 3D memory block according to Fig. 4A, barrier layers 406 and metal layers 404 may be deposited stacked with the source / drain layers 1004, the source / drain dielectric layers 116a, and the block dielectric layers 210. In alternative embodiments, to form a 3D memory block according to Fig. 4C, silicide layers stacked with the source / drain layers 1004, the source / drain dielectric layers 116a, and the block dielectric layers 210 may be deposited. In alternative embodiments, to form a 3D memory block according to Fig. 4D silicide layers are deposited instead of the 1004 source / drain layers.

[0065] As shown by the top and cross-sectional views 1100A, 1100B of the Fig. 11A and Fig. 11B, the first and second storage films 1002a, 1002b are patterned to form a plurality of trenches 1102. The trenches 1102 are laterally parallel in a direction (e.g., a Y direction) transverse to the cross-sectional view 1100B of Fig. 11B. In some embodiments, the direction is the direction in which the columns of the 3D memory block being formed extend, and / or the trenches 1102 have the same or substantially the same dimensions. Further, the patterning divides the source / drain layers 1004 into lower source / drain regions 106l and upper source / drain regions 106u. The lower source / drain regions 106l are located at lower sides of the corresponding source / drain dielectric layers, and the upper source / drain regions 106u are located at upper sides of the corresponding source / drain dielectric layers. The patterning may be performed, for example, by a photolithography / etch process and / or another suitable patterning process. The photolithography / etch process may use, for example, dry etching and / or another suitable etching process.

[0066] As illustrated by the top and cross-sectional views 1200A, 1200B of the Fig. 12A and Fig. 12B, the source / drain dielectric layers 116a are laterally recessed by the trenches 1102. The recessing recesses sidewalls of the source / drain dielectric layers 116a relative to adjacent sidewalls of the lower and upper source / drain regions 106l, 106u to form recesses 1202 having a lateral depth D r It should be noted that the recesses 1202 are shown as a phantom in Fig. 12A. In some embodiments, the lateral depth D r approximately 10 to 30 nanometers, approximately 10 to 20 nanometers, approximately 20 to 30 nanometers, or another suitable depth. The lateral recess can be achieved, for example, by wet etching and / or another suitable type of etching.

[0067] As shown by the top and cross-sectional views 1300A, 1300B of the Fig. 13A and Fig. 13B, a semiconductor layer 1302 is formed which defines the trenches 1102 (see, for example, Fig. 12A and Fig. 12B) and the recesses 1202 (see e.g. the Fig. 12A and Fig. 12B). In some embodiments, semiconductor layer 1302 is doped. In alternative embodiments, semiconductor layer 1302 is undoped. In some embodiments, semiconductor layer 1302 is or comprises polysilicon and / or other suitable semiconductor material(s).

[0068] A process for forming the semiconductor layer 1302 may, for example, include: 1) depositing the semiconductor layer 1302; and 2) performing planarization into the semiconductor layer 1302 until the block dielectric layer 210 of the second memory film 1002b is reached. Alternatively, other suitable processes may form the semiconductor layer 1302. The planarization may, for example, be performed by chemical mechanical polishing (CMP) or another suitable planarization.

[0069] While the semiconductor layer 1302 is formed by completely filling the trenches 1102 and the recesses 1202, in alternative embodiments the semiconductor layer 1302 may be formed by lining and partially filling the trenches 1102 and the recesses 1202. Such alternative embodiments may be used, for example, when forming a 3D memory block according to the Fig. 3C to 3E. In some embodiments, where the semiconductor layer 1302 is formed by lining and partially filling the trenches 1102 and the recesses 1202, a gate dielectric layer is formed that lines and partially fills the trenches and the recesses 1202 over the semiconductor layer 1302. Such alternative embodiments may be used, for example, when forming a 3D memory block according to the Fig. 3D and Fig. 3E arise.

[0070] As shown by the top and cross-sectional views 1400A, 1400B of the Fig. 14A and Fig. 14B, the trenches 1102 are cleared. The recesses 1202 (see, for example, the Fig. 12A and Fig. 12B) are not cleared or are only minimally cleared. This forms a plurality of semiconductor channels 104 that are localized to the recesses 1202 of the semiconductor layer 1302. The clearing may be performed, for example, by dry etching and / or another suitable type of etching. Alternatively, other suitable processes for clearing the trenches 1102 may be performed, for example. In some embodiments, the block dielectric layer 210 of the second memory film 1002b is used as a mask during the etching.

[0071] As illustrated by the top and cross-sectional views 1500A, 1500B of the Fig. 15A and Fig. 15B, a gate dielectric layer 110, a ferroelectric layer 112, and a control electrode layer 1502 (collectively, the trench layers) are formed, filling the trenches 1102. The gate dielectric layer 110 is formed by lining and partially filling the trenches 1102, and the ferroelectric layer 112 is formed by lining and partially filling the trenches 1102 over the gate dielectric layer 110. The control electrode layer 1502 is formed by filling a remainder of the trenches 1102 over the ferroelectric layer 112. In some embodiments, the control electrode layer 1502 is or comprises titanium nitride, doped polysilicon, tantalum nitride, tungsten, other suitable conductive material(s), or a combination of the foregoing. In some embodiments, the ferroelectric layer 112 is doped hafnium oxide (e.g.,doped with aluminum, silicon, zirconium, lanthanum, strontium, or the like) and / or other suitable ferroelectric material(s). In some embodiments, the gate dielectric layer 110 is or comprises silicon oxide, aluminum oxide, silicon oxynitride, silicon nitride, lanthanum oxide, strontium titanium oxide, undoped hafnium oxide, or other suitable dielectric material(s), or a combination of the foregoing. In some embodiments, the gate dielectric layer 110 is or comprises a high-k dielectric layer.

[0072] A process for forming the trench layers may, for example, include: 1) depositing the gate dielectric layer 110; 2) depositing the ferroelectric layer 112 over the gate dielectric layer 110; 3) depositing the control electrode layer 1502 over the ferroelectric layer 112; and 4) performing planarization into the control electrode layer 1502 until the ferroelectric layer 112 is reached. Alternatively, other suitable processes may form the trench layers. The planarization may, for example, alternatively be performed until the second memory film 1002b is reached. The planarization may, for example, be performed by a CMP or other suitable planarization.

[0073] As shown by the top and cross-sectional views 1600A, 1600B of the Fig. 16A and Fig. 16B, the control electrode layer 1502 is patterned to form a plurality of gate insulation openings 1602, which divides the control electrode layer 1502 into a plurality of control gate electrodes 114. The control gate electrodes 114 are arranged in a plurality of rows and a plurality of columns, such that a control gate electrode appears in every other column along each row, and such that a control gate electrode appears in every other row along each column. Furthermore, the control gate electrodes 114 are stepped along adjacent columns and adjacent rows, such that a pitch P y the control gate electrodes 114 in the Y direction over one row and one pitch P x of the control gate electrodes 114 extends over two columns in the X-direction. In some embodiments, the control gate electrodes 114 have individual widths W cg which is less than approximately half of the division P y in the Y direction.

[0074] The patterning may be performed, for example, by a photolithography / etching process and / or another suitable patterning process. The photolithography / etching process may, for example, use the ferroelectric layer 112 as an etch stop and / or may, for example, use dry etching and / or another suitable type of etching.

[0075] Dividing the control electrode layer 1502 into the control gate electrodes 114 completes a first memory block 204a and a second memory block 204b. The first and second memory blocks 204a, 204b are vertically stacked and formed from a plurality of MFIS memory cells 102. In some embodiments, the MFIS memory cells 102 are as described with respect to Fig. 1A to 1C and / or the Fig. 2A to 2D. Each of the MFIS memory cells 102 includes a localized portion of the ferroelectric layer 112 that represents a polarity of a data bit.

[0076] During the programming and erasing operations for one of the MFIS memory cells 102, the lower and upper source / drain regions 106l, 106u of the MFIS memory cell are electrically coupled in parallel and are used as a proxy for the semiconductor channel 104 of the MFIS memory cell. A programming voltage is applied from the control gate electrode 114 of the MFIS memory cell to the semiconductor channel 104 (e.g., via the lower and upper source / drain regions 106l, 106u) to set the polarity to a programmed state. Furthermore, an erase voltage with a polarity opposite to the programming voltage is applied from the control gate electrode 114 to the semiconductor channel 104 (e.g., via the lower and upper source / drain regions 106l, 106u) to set the polarity to an erased state. For example, the programmed state can represent a binary “1”, while the erased state can represent a binary “0”, or vice versa.

[0077] The ferroelectric layer 112 shields an electric field generated by the control gate electrode 114 differently depending on whether the polarity is in the programmed or erased state. As such, the MFIS memory cell has a programmed threshold voltage and an erased threshold voltage, respectively, while the polarity is in the programmed and erased states. During a read operation of the MFIS memory cell, the control gate electrode 114 is biased with a read voltage between the programmed and erased threshold voltages, and the resistance of the semiconductor channel 104 is measured. Depending on whether the semiconductor channel 104 is conductive, the polarity is either in the programmed or erased state.

[0078] By using the ferroelectric layer 112 for data storage, as opposed to a silicon nitride layer, there is no dependence on carrier tunneling for the programming and erase operations. This allows programming and erase voltages to be reduced and programming and erase speeds to be increased. For example, the programming and erase voltages can be reduced to less than approximately 5 volts and / or the programming and erase speeds to less than approximately 100 nanoseconds. However, other suitable values ​​are conceivable. By reducing the programming and erase voltages and increasing the programming and erase speeds, power consumption can be reduced.

[0079] As illustrated by the top and cross-sectional views 1700A, 1700B of the Fig. 17A and Fig. 17B, ​​an intergate dielectric layer 116b is formed, which fills the gate insulation openings 1602 (see, for example, the Fig. 16A and Fig. 16B). The intergate dielectric layer 116b may be or include, for example, silicon oxide and / or other suitable dielectric(s). A process for forming the intergate dielectric layer 116b may include, for example: 1) depositing an intergate dielectric layer 116b filling the gate insulation openings 1602; and 2) performing planarization into the intergate dielectric layer 116b until the ferroelectric layer 112 is exposed. In alternative embodiments, the intergate dielectric layer 116b is formed by another suitable process. Furthermore, in alternative embodiments, the planarization is stopped before the ferroelectric layer 112 is exposed, and top electrode vias, which are subsequently formed, are formed in an upper portion of the intergate dielectric layer 116b.

[0080] As shown by the top and cross-sectional views 1800A, 1800B of the Fig. 18A and Fig. As illustrated in Figure 18B, the interconnect structure 504 is completed. An upper interconnect dielectric layer 506b is formed over the first and second memory blocks 204a, 204b, and a plurality of upper wires 508b and a plurality of upper vias 510b are formed stacked in the upper interconnect dielectric layer 506b. At least some of the upper wires 508b define upper wordlines TWL, and at least some of the upper vias 510b define upper electrode vias TEV. The upper wordlines TWL extend, respectively, along rows of the control gate electrodes 114, and the upper electrode vias TEV extend, respectively, from the upper wordlines TWL to the control gate electrodes 114.

[0081] While the Fig. 9A and 9B to 18A and 18B are described with reference to various embodiments of a method, it is understood that the Fig. 9A and 9B to 18A and 18B are not limited to the method, but rather can be independent and separate from the method. While the Fig. 9A and Fig. 9B to the Fig. 18A and Fig. 18B are described as a series of acts, it is understood that the order of the acts may be changed in other embodiments. While the Fig. 9A and Fig. 9B to the Fig. 18A and Fig. 18B illustrate and describe a specific series of acts, some acts illustrated and / or described may be omitted in other embodiments. Furthermore, acts not illustrated and / or described may be included in other embodiments.

[0082] With reference to Fig. 19 is a block diagram 1900 of some embodiments of the method of Fig. 9A and Fig. 9B to the Fig. 18A and Fig. 18B provided.

[0083] At 1902, an interconnect structure is partially formed over a semiconductor device and a semiconductor substrate. See, for example, the Fig. 9A and Fig. 9B.

[0084] At 1904, a memory film is deposited over the interconnect structure, the memory film having a pair of source / drain layers and a source / drain dielectric layer between the source / drain layers. See, for example, the Fig. 10A and Fig. 10B.

[0085] At 1906, the storage film is patterned to form a plurality of grooves extending laterally parallel in a first direction. See, for example, the Fig. 11A and Fig. 11B.

[0086] At 1908, sidewalls of the source / drain dielectric layer are recessed laterally in the trenches in a second direction transverse to the first direction to form recesses. See, for example, the Fig. 12A and Fig. 12B.

[0087] At 1910, a semiconductor layer is deposited to fill the trenches and recesses. See, for example, the Fig. 13A and Fig. 13B.

[0088] In 1912, the semiconductor layer is patterned to remove the semiconductor layer from the trenches while leaving the semiconductor layer in the recesses. See, for example, the Fig. 14A and Fig. 14B.

[0089] At 1914, a gate dielectric layer and a ferroelectric layer are deposited, which line and partially fill the trenches. See, for example, the Fig. 15A and Fig. 15B.

[0090] At 1916, a control electrode layer is deposited to fill the remainder of the trenches. See, for example, the Fig. 15A and Fig. 15B.

[0091] At 1918, the control electrode layer is patterned to divide the control electrode layer into multiple control gate electrodes in multiple rows and multiple columns. See, for example, the Fig. 16A and Fig. 16B.

[0092] At 1920, the interconnect structure is completed over the memory film and the control gate electrodes. See, for example, the Fig. 17A and Fig. 17B and the Fig. 18A and Fig. 18B.

[0093] While the block diagram was created in 1900 by Fig. 19 is illustrated and described herein as a series of acts or events, it is understood that the illustrated order of such acts or events is not intended to be limiting. For example, some acts other than those illustrated and / or described herein may occur in a different order and / or concurrently with other acts or events. Further, not all of the illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.

[0094] With reference to the Fig. 20A and Fig. 20B to the Fig. 27A and Fig. 27B, a series of views of some embodiments of a method for forming an IC having a 3D memory block of MFIS memory cells is provided, in which word lines are located at a bottom and a top of the 3D memory block, respectively. Figures labeled with a suffix B illustrate cross-sectional views along line K, L, or M (whichever is present) in like-numbered figures with a suffix A. Figures with a suffix A illustrate top views along line K, L, or M (whichever is present) in like-numbered figures with a suffix B. The method can be used, for example, to form the IC of the Fig. 8A and Fig. 8B or other suitable ICs.

[0095] As illustrated by the top and cross-sectional views 2000A, 2000B of the Fig. 20A and Fig. 20B, a semiconductor device 512 and a trench isolation structure 520 are formed on a semiconductor substrate 502, as described with respect to Fig. 9A and Fig. 9B is illustrated and described.

[0096] Also by the top view and the cross-sectional views 2000A, 2000B of Fig. 20A and Fig.20B illustrates an interconnect structure 504 partially formed over the semiconductor device 512 and the semiconductor substrate 502. The interconnect structure 504 includes a bottom interconnect dielectric layer 506a, a cap dielectric layer 502, a plurality of bottom wires 508a, and a plurality of bottom vias 510a. The bottom wires 508a and the bottom vias 510a are alternately stacked within the bottom interconnect dielectric layer 506a and define conductive traces extending from the semiconductor device 512 and other semiconductor devices (not shown) on the semiconductor substrate 502. Furthermore, the bottom wires 508a define bottom wordlines BWL at a top surface of the interconnect structure 504, and the bottom vias 510a define bottom electrode vias BEV, respectively overlying the bottom wordlines BWL.The cap dielectric layer 802 covers the lower interconnect dielectric layer 506a and the lower electrode vias BEV.

[0097] As shown by the top and cross-sectional views 2100A, 2100B of the Fig. 21A and Fig. As illustrated in Figure 21B, the actions in the Fig. 10A and Fig. 10B to the Fig. 14A and Fig. 14B on the interconnect structure 504 of the Fig. 20A and Fig. 20B. For the sake of simplicity, only an upper portion of the interconnect structure 504 is shown. A remainder of the interconnect structure 504 is as shown in the Fig. 20A and Fig. 20B shown.

[0098] According to the actions in the Fig. 10A and Fig. 10B to the Fig. 14A and Fig. 14B, a first storage film 1002a and a second storage film 1002b are deposited as described with respect to the Fig. 10A and Fig. 10B. The first and second storage films 1002a, 1002b are patterned to form a plurality of trenches 1102, as described with respect to Fig. 11A and Fig. 11B. The source / drain dielectric layers 116a are laterally recessed by the trenches 1102 to form recesses 1202 (see, e.g., the Fig. 12A and Fig. 12B), as it is with regard to the Fig. 12A and Fig. 12B. A semiconductor layer 1302 is formed, which fills the trenches 1102 and the recesses 1202, as described with respect to Fig. 13A and Fig. 13B. The trenches 1102 are formed as described with respect to Fig. 14A and Fig. 14B illustrated and described.

[0099] As illustrated by the top and cross-sectional views 2200A, 2200B of the Fig. 22A and Fig. 22B, a gate dielectric layer 110, a ferroelectric layer 112, and a spacer layer 2202 are formed, which line and partially fill the trenches 1102. The ferroelectric layer 112 is formed by lining and partially filling the trenches 1102 over the gate dielectric layer 110, and the spacer layer 2202 is formed by lining and partially filling the trenches 1102 over the ferroelectric layer 112. The spacer layer 2202 may be or include, for example, silicon nitride and / or other suitable dielectric(s).

[0100] As illustrated by the top and cross-sectional views 2300A, 2300B of the Fig. 23A and Fig. As illustrated in Figure 23B, an etching process is performed into the spacer layer 2202, the ferroelectric layer 112, the gate electrode 110, and the cap dielectric layer 802 to extend the trenches 1102 to the bottom electrode contacts BEV. Initially, the spacer layer 2202 is etched back, and spacers 804 are formed from the spacer layer 2202 along sidewalls of the trenches 1102. Thereafter, the spacers 804 and the block dielectric layer 210 of the second memory film 1002b serve as a mask while etching through the ferroelectric layer 112, the gate dielectric layer 110, and the cap dielectric layer 802. These two steps of the etching process may, for example, be performed by the same etching process or by different etching processes.

[0101] In alternative embodiments, instead of forming the spacer layer 2202 in the Fig. 22A and Fig. 22B and then performing the etching process in the Fig. 23A and Fig. 23B, a photolithography / etching process may be performed to form openings at the bottom of the trenches 1102 that extend correspondingly to the bottom electrode vias BEV. The method may then continue as described below. These alternative embodiments may be used, for example, to form the IC of the Fig. 7A and Fig. 7B or other suitable ICs.

[0102] As shown by the top and cross-sectional views 2400A, 2400B of Fig. 24A and Fig. As illustrated in Figure 24B, a control electrode layer 1502 is formed, filling the trenches 1102. A process for forming the control electrode layer 1502 may, for example, include: 1) depositing the control electrode layer 1502; and 2) performing planarization into the control electrode layer 1502 until the block dielectric layer 210 of the second memory film 1002b is reached. Alternatively, other suitable processes may form the control electrode layer 1502. The planarization may, for example, be performed by a CMP or other suitable planarization.

[0103] As shown by the views of the Fig. 25A and Fig. 25B and the Fig. 26A and Fig. As illustrated in Figure 26B, the actions in the Fig. 16A and Fig. 16B and Fig. 17A and Fig. 17B. In the top and cross-sectional views 2500A, 2500B of the Fig. 25A and Fig. 25B, the control electrode layer 1502 is patterned to form a plurality of gate insulation openings 1602, which divide the control electrode layer 1502 into a plurality of control gate electrodes 114, as described with respect to the Fig. 16A and Fig. 16B. In the top and cross-sectional views 2600A, 2600B of Fig. 26A and Fig. 26B, an intergate dielectric layer 116b is formed, which fills the gate insulation openings 1602 (see, for example, the Fig. 25A and Fig. 25B), as it is with regard to the Fig. 17A and Fig. 17B is illustrated and described.

[0104] As shown by the top and cross-sectional views 2700A, 2700B of the Fig. 27A and Fig. 27B, the interconnect structure 504 is configured as described with respect to Fig. 18A and Fig. 18B. In contrast to the Fig. 18A and Fig. 18B, however, the upper word lines TWL and the upper electrode vias TEV are formed at even-numbered rows or odd-numbered rows, but not both.

[0105] While the Fig. 20A and 20B to 27A and 27B are described with reference to various embodiments of a method, it is understood that the Fig. 20A and 20B to 27A and 27B are not limited to the method, but rather can be independent and separate from the method. While the Fig. 20A and Fig. 20B to the Fig. 27A and Fig. 27B are described as a series of acts, it is understood that the order of the acts may be changed in other embodiments. While the Fig. 20A and Fig. 20B to the Fig. 27A and Fig. 27B illustrate and describe a specific series of acts, some acts illustrated and / or described may be omitted in other embodiments. Furthermore, acts not illustrated and / or described may be included in other embodiments.

[0106] With reference to Fig. 28 is a block diagram 2800 of some embodiments of the method of Fig. 20A and Fig. 20B to the Fig. 27A and Fig. 27B provided.

[0107] In 2802, an interconnect structure is partially formed over a semiconductor device and a semiconductor substrate, the interconnect structure having bottom wordlines and bottom electrode vias respectively overlying the bottom wordlines at a top surface of the interconnect structure. See, for example, Fig. 20A and Fig. 20B.

[0108] In 2804, a memory film is deposited over the interconnect structure, the memory film having a pair of source / drain layers and a source / drain dielectric layer between the source / drain layers. See, for example, the Fig. 21A and Fig. 21B and the Fig. 10A and Fig. 10B.

[0109] In 2806, the memory film is patterned to form a plurality of trenches extending laterally parallel in a first direction. See, for example, the Fig. 21A and Fig. 21B and the Fig. 11A and Fig. 11B.

[0110] In 2808, sidewalls of the source / drain dielectric layer are recessed laterally in the trenches in a second direction transverse to the first direction to form recesses. See, for example, the Fig. 21A and Fig. 21B and the Fig. 12A and Fig. 12B.

[0111] In 2810, a semiconductor layer is deposited to fill the trenches and recesses. See, for example, the Fig. 21A and Fig. 21B and the Fig. 13A and Fig. 13B.

[0112] In 2812, the semiconductor layer is patterned to remove the semiconductor layer from the trenches while leaving the semiconductor layer in the recesses. See, for example, the Fig. 21A and Fig. 21B and the Fig. 14A and Fig. 14B.

[0113] In 2814, a gate dielectric layer, a ferroelectric layer, and a spacer layer are deposited, which line and partially fill the trenches. See, for example, the Fig. 22A and Fig. 22B.

[0114] At 2816, an etch is performed to etch back the spacer layer, the ferroelectric layer, and the gate dielectric layer and to extend the trenches to the bottom electrode vias. See, for example, the Fig. 23A and Fig. 23B.

[0115] In the 2818, a control electrode layer is deposited to fill the trenches. See, for example, the Fig. 24A and Fig. 24B.

[0116] In 2820, the control electrode layer is patterned to divide the control electrode layer into multiple control gate electrodes in multiple rows and multiple columns. See, for example, the Fig. 25A and Fig. 25B.

[0117] In the 2822, the interconnect structure is completed over the memory film and the control gate electrodes. See, for example, the Fig. 26A and Fig. 26B and the Fig. 27A and Fig. 27B.

[0118] While the block diagram 2800 of Fig. 28 is illustrated and described herein as a series of acts or events, it is understood that the illustrated order of such acts or events is not intended to be limiting. For example, some acts other than those illustrated and / or described herein may occur in a different order and / or concurrently with other acts or events. Further, not all of the illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.

[0119] In some embodiments, the present disclosure provides a memory device comprising: a lower source / drain region and an upper source / drain region overlying the lower source / drain region; a semiconductor channel overlying the lower source / drain region and underlyng the upper source / drain region; a control gate electrode extending along a sidewall of the semiconductor channel and along individual sidewalls of the lower and upper source / drain regions; and a gate dielectric electrode and a ferroelectric layer separating the control gate electrode from the semiconductor channel and the lower and upper source / drain regions. In some embodiments, the semiconductor channel is located entirely and laterally between opposing sidewalls of the upper source / drain region, with the opposing sidewalls facing toward and away from the control gate electrode, respectively.In some embodiments, the control gate electrode is completely uncovered by the upper source / drain region. In some embodiments, the sidewall of the semiconductor channel is offset from the individual sidewalls of the lower and upper source / drain regions. In some embodiments, the ferroelectric layer extends along the sidewall of the semiconductor channel from top to bottom and further along the individual sidewalls of the lower and upper source / drain regions from top to bottom. In some embodiments, the memory device further comprises a second semiconductor channel and a source / drain dielectric layer overlying the lower source / drain region and underlyating the upper source / drain region, the source / drain dielectric layer being between the semiconductor channel and the second semiconductor channel.In some embodiments, the memory device further comprises a second semiconductor channel adjacent to the control gate electrode on a side of the control gate electrode opposite the semiconductor channel, wherein the ferroelectric layer and the gate dielectric layer wrap around a bottom surface of the control gate electrode and separate the control gate electrode from the second semiconductor channel.

[0120] In some embodiments, the present disclosure provides another memory device comprising: a first semiconductor channel; a second semiconductor channel overlying the first semiconductor channel; and a control gate electrode and a ferroelectric layer adjacent to the first and second semiconductor channels, the ferroelectric layer separating the control gate electrode from the first and second semiconductor channels. The memory device further comprises a high-k gate dielectric layer separating the ferroelectric layer from the first and second semiconductor channels. In some embodiments, the control gate electrode, the ferroelectric layer, and the first semiconductor channel partially define an MFIS-FET.In some embodiments, the memory device further comprises a second control gate electrode laterally spaced from the control gate electrode and also adjacent to the first and second semiconductor channels, wherein the ferroelectric layer separates the second control gate electrode from the first and second semiconductor channels. In some embodiments, the memory device further comprises a lower source / drain region and an upper source / drain region vertically stacked with the second semiconductor channel. In some embodiments, the upper source / drain region completely covers the first and second semiconductor channels. The control gate electrode individually buckles at the first and second semiconductor channels.

[0121] In some embodiments, the present disclosure provides a method of forming a memory device, the method comprising: depositing a memory film over a substrate, the memory film having a pair of source / drain layers and a source / drain dielectric layer between the source / drain layers; performing a first etch into the memory film to form a trench through the memory film; recessing a sidewall of the source / drain dielectric layer relative to sidewalls of the source / drain layers through the trench to form a recess; depositing a semiconductor layer filling the recess and the trench; performing a second etch into the semiconductor layer to remove the semiconductor layer from the trench; depositing a ferroelectric layer lining the trench and further lining the semiconductor layer at the recess; and depositing an electrode layer,which fills the trench above the ferroelectric layer. In some embodiments, the method further comprises performing a third etch into the electrode layer to form a plurality of control gate electrodes adjacent to the semiconductor layer at the recess. In some embodiments, the method further comprises depositing a high-k gate dielectric layer lining the trench between depositing the semiconductor layer and depositing the ferroelectric layer. In some embodiments, the semiconductor layer is deposited on the sidewall of the source / drain dielectric layer and the sidewalls of the source / drain layers, wherein the semiconductor layer is removed by the second etch from the sidewalls of the source / drain layers, but not from the sidewall of the source / drain dielectric layer. In some embodiments, the method further comprises depositing a second memory film over the memory film,wherein the second memory film comprises a pair of second source / drain layers and a second source / drain dielectric layer between the second source / drain layers, wherein the first etching is also performed into the second memory film, and wherein the recessing recesses a sidewall of the second source / drain dielectric layer relative to sidewalls of the second source / drain layers through the trench to form a second recess simultaneously with the recess. In some embodiments, the recessing recesses a second sidewall of the source / drain dielectric layer relative to the second sidewalls of the source / drain layers through the trench to form a second recess, and wherein the second recess is located on a side of the trench opposite the recess.

Claims

[1] A storage device comprising: a lower source / drain region (106l) and an upper source / drain region (106u) located above the lower source / drain region (106l); a semiconductor channel (104) located above the lower source / drain region (106l) and which lies beneath the upper source / drain region (106u); a control gate electrode (114) extending along a sidewall of the semiconductor channel (104) and along individual sidewalls of the lower (106l) and upper source / drain regions (106u); a gate dielectric layer (110) and a ferroelectric layer (112) separating the control gate electrode (114) from the semiconductor channel (104) and the lower (106l) and upper source / drain regions (106u); and a second semiconductor channel (104) and a source / drain dielectric layer (116), which lie above the lower source / drain region (106l) and below the upper source / drain region (106u), wherein the source / drain dielectric layer (116) is located between the semiconductor channel (104) and the second semiconductor channel (104). [2] The memory device of claim 1, wherein the semiconductor channel (104) is located entirely and laterally between opposite sidewalls (108) of the upper source / drain region (106u), and wherein the opposite sidewalls (108) face toward and away from the control gate electrode (114), respectively. [3] The memory device of claim 1 or 2, wherein the control gate electrode (114) is completely uncovered by the upper source / drain region (106u). [4] A memory device according to any preceding claim, wherein the sidewall (108) of the semiconductor channel (104) is offset from the individual sidewalls of the lower (106l) and upper source / drain regions (106u). [5] A memory device according to any preceding claim, wherein the ferroelectric layer (112) extends from top to bottom along the sidewall (108) of the semiconductor channel (104) and further extends from top to bottom along the individual sidewalls (108) of the lower and upper source / drain regions. [6] The memory device of any preceding claim, wherein the source / drain dielectric layer (116) directly contacts the semiconductor channel (104) and the second semiconductor channel (104). [7] A storage device according to any one of the preceding claims, further comprising: a third semiconductor channel (104) adjacent to the control gate electrode (114) on a side of the control gate electrode (114) opposite the semiconductor channel (104), wherein the ferroelectric layer (112) and the gate dielectric layer (110) wrap around a bottom side of the control gate electrode (114) and separate the control gate electrode (114) from the third semiconductor channel (104). [8] Storage device comprising: a first semiconductor channel (104); a second semiconductor channel (104) located above the first semiconductor channel (104); and a control gate electrode (114) and a ferroelectric layer (112) adjacent to the first and second semiconductor channels (104), the ferroelectric layer (112) separating the control gate electrode (114) from the first and second semiconductor channels (104); a high-k gate dielectric layer (110) separating the ferroelectric layer (112) from the first and second semiconductor channels (104), wherein the control gate electrode (114) individually bulges at the first and second semiconductor channels (104). [9] The memory device of claim 8, wherein the gate dielectric layer (110) has a first side in contact with the first and second semiconductor channels (104) and a second side opposite the first side in contact with the ferroelectric layer (112). [10] The memory device of claim 8 or 9, wherein the control gate electrode (114), the ferroelectric layer (112) and the first semiconductor channel (104) partially define an MFIS field effect transistor, MFIS-FET. [11] A storage device according to any one of the preceding claims 8 to 10, further comprising: a second control gate electrode (114) laterally spaced from the control gate electrode (114) and also adjacent to the first and second semiconductor channels (104), wherein the ferroelectric layer (112) separates the second control gate electrode (114) from the first and second semiconductor channels (104). [12] A storage device according to any one of the preceding claims 8 to 11, further comprising: a lower source / drain region (106l) and an upper source / drain region (106u) vertically stacked with the second semiconductor channel (104). [13] The memory device of claim 12, wherein the upper source / drain region (106u) completely covers the first and second semiconductor channels (104). [14] A method of forming a memory device, the method comprising: Depositing a storage film (1002a, 1002b) over a substrate, the storage film (1002a, 1002b) comprising a pair of source / drain layers (1004) and a source / drain dielectric layer (116a) between the source / drain layers (1004); performing a first etching into the memory film (1002a, 1002b) to form a trench (1102) through the memory film (1002a, 1002b); Recessing a sidewall of the source / drain dielectric layer (116a) relative to the sidewalls of the source / drain layers (1004) through the trench (1102) to form a recess (1202); depositing a semiconductor layer (1302) filling the recess (1202) and the trench (1102); performing a second etch into the semiconductor layer (1302) to remove the semiconductor layer (1302) from the trench (1102); Depositing a ferroelectric layer (112) lining the trench (1102) and further lining the semiconductor layer (1302) at the recess (1202); and Depositing an electrode layer filling the trench (1102) above the ferroelectric layer (112). [15] The method of claim 14, further comprising: Performing a third etch into the electrode layer to form a plurality of control gate electrodes (114) adjacent to the semiconductor layer (1302) at the recess (1202). [16] The method of claim 14 or 15, further comprising: Depositing a high-k gate dielectric layer lining the trench (1102), between the deposition of the semiconductor layer (1302) and the deposition of the ferroelectric layer (112). [17] The method of any one of the preceding claims 14 to 16, wherein the semiconductor layer (1302) is deposited on the sidewall of the source / drain dielectric layer (116a) and the sidewalls of the source / drain layers (1004), and wherein the semiconductor layer (1302) is removed by the second etching from the sidewalls of the source / drain layers (1004) but not from the sidewall of the source / drain dielectric layer (116a). [18] A method according to any one of claims 14 to 17, further comprising: Depositing a second storage film (1002a, 1002b) over the storage film (1002a, 1002b), the second storage film (1002a, 1002b) comprising a pair of second source / drain layers and a second source / drain dielectric layer between the second source / drain layers, the first etching also being performed into the second storage film (1002a, 1002b), and the recessing recessing a sidewall of the second source / drain dielectric layer (116a) relative to sidewalls of the second source / drain layers through the trench (1102) to form a second recess simultaneously with the recess (1202). [19] The method of any one of the preceding claims 14 to 18, wherein the recessing recesses a second sidewall of the source / drain dielectric layer (116a) relative to second sidewalls of the source / drain layers (1004) through the trench (1102) to form a third recess, and wherein the third recess is located on a side of the trench (1102) opposite the recess (1202).

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