SEMICONDUCTOR DEVICE AND METHOD

Abstract

Method comprising: Forming a semiconductor substrate (50) comprising epitaxial silicon germanium in a first region (50P) of the semiconductor substrate and silicon in a second region (50N) of the semiconductor substrate, wherein forming the semiconductor substrate comprises: providing a silicon substrate, forming an opening in the silicon substrate, and forming the epitaxial silicon germanium in the opening, wherein a ratio of an atomic percentage of germanium at a top surface of the epitaxial silicon germanium to an atomic percentage of germanium at a bottom surface of the epitaxial silicon germanium is in the range of approximately 1:2 to approximately 1:8; Forming a first semiconductor fin (55) in the first region of the semiconductor substrate (50), and forming a second semiconductor fin (55) in the second region of the semiconductor substrate, wherein: a germanium concentration of a first portion of the first semiconductor fin (55) is greater than a germanium concentration of a second portion of the first semiconductor fin, a first distance between the first portion of the first semiconductor fin (55) and a main surface of the semiconductor substrate (50) is smaller than a second distance between the second portion of the first semiconductor fin (55) and the main surface of the semiconductor substrate; and the procedure further comprises: Trimming the first semiconductor fin (55), wherein: the first portion of the first semiconductor fin is trimmed at a greater rate than the second portion of the first semiconductor fin, and after trimming the first semiconductor fin (55), a first angle between a sidewall of the first semiconductor fin and a main surface of the semiconductor substrate (50) is closer to the normal than a second angle between a sidewall of the second semiconductor fin (55) and the main surface of the semiconductor substrate.

Description

BACKGROUNDSemiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.The semiconductor industry constantly improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a particular area.US 2020 / 0058773 A1 describes a method for producing a trimmed fin. First, a fin is formed, the fin including silicon and germanium protruding from a substrate, and having a first germanium concentration at a top surface and a second germanium concentration at a position below the top surface, the first germanium concentration being less than the second germanium concentration. An exposed surface of the fin is then oxidized so that the fin is covered by an oxide layer. Subsequently, the oxide layer is removed to obtain the trimmed fin.US 2018 / 0247938 A1 describes a method for simultaneously forming fins on a substrate. A mask segment is formed on a first region of the substrate while exposing the surface of a second region of the substrate. In the second region, a part of the sub-start is removed to form a recess. A fin layer is formed in the recess, the fin layer having a different material composition than the substrate. Fins are formed on the first and second regions of the sub-start, the fin being formed on the second region of the substrate from the fin layer and the substrate.US 2020 / 0135584 A1 describes FinFET devices and methods of making the same, wherein a fin comprises a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven.Furthermore, the following documents are relevant: US 2020 / 0176591 A1, US 2017 / 0005090 A1, US 2017 / 0133377 A1, US 2021 / 0375697 A1, US 2018 / 0122916 A1, US 2013 / 0161756 A1, US 2017 / 0025314 A1, and US 9484267 B1.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, according to the standard industry process, various elements are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various elements may be arbitrarily increased or decreased. FIG. 1 shows an example of a semiconductor device including fin field effect transistors (FinFETs) in a three-dimensional view, in accordance with some embodiments. FIGS. 2, 3A, 3B, 3C, 4A, 4B, 5, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 13A, 13B, 13C, 13D, 13E, 14A, 14B, FIGS. 14C, 15A, 15B, 16A, 16B, 16C, 16D, and 16E are cross-sectional views of intermediates in manufacturing semiconductor devices, in accordance with some embodiments. FIG. 17 shows an example of a semiconductor device including nanostructure field effect transistors (NSFETs) in a three-dimensional view, in accordance with some embodiments. FIGS. 18, 19A, 19B, 20A, 20B, 21, 22A, 22B, 23A, 23B, 24A, 24B, 25A, 25B, 26A, 26C, 27A, 27B, 27C, 28A, 28B, 28C, 28D, 29A, 29B, 29C, 30A, 30B, FIGS. 30C, 31A, 31B, 31C, 31D, 31E, 32A, 32B, 32C, 32D, 33C, 33D, 33E, 33F, 34A, 34B, 35A, 35A, 35A, 35B, and 35D are cross-sectional views of intermediates in manufacturing semiconductor devices according to some embodiments.The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are specified in the dependent claims.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples. For example, forming a first element over or on a second element in the description below may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for purposes of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or embodiments discussed.Moreover, terms relating to spatial relativeity, such as "below," "below," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature (to other elements or features) as depicted in the figures. The terms relating to spatial relativeness are intended to encompass different orientations of the device being used or operated in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or otherwise oriented) and the spatially relative terms used herein may likewise be construed accordingly.Various embodiments provided methods for forming channel regions in semiconductor devices having improved profiles, as well as semiconductor devices formed using the methods. The methods may include forming channel regions having gradient concentrations of semiconductor materials and thinning the channel regions. In some embodiments, the channel regions may be formed of silicon germanium having higher germanium concentrations at the bottom of the channel regions and lower germanium concentrations at the top of the channel regions. The channel regions may be thinned by exposing the channel regions to alkaline or acidic solutions that may be combined with or cyclized with oxidant solutions. Portions of the channel regions having higher germanium concentrations may be thinned at higher rates than portions of the channel regions having lower germanium concentrations, which may be used to provide channel regions having rectangular profiles. Providing channel regions having rectangular profiles reduces drain induced barrier (DIBL) degradation, thereby increasing performance and reducing device defects of the resulting semiconductor devices.FIG. 1 illustrates an example of FinFETs, in accordance with some embodiments. The FinFETs include fins 55 on a substrate 50 (e.g., a semiconductor substrate). STI (shallow trench isolation) regions 58 are disposed in substrate 50, and fins 55 protrude above and out of the space between adjacent STI regions 58. Although the STI regions 58 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may be used to refer exclusively to the semiconductor substrate or a semiconductor substrate including STI regions. Additionally, although the fins 55 are shown as single materials continuous with the substrate 50, the fins 55 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fins 55 refer to the portions extending between the adjacent STI regions 58.Gate dielectric layers 100 are along sidewalls and over a top surface of the fins 55, and gate electrodes 102 are over the gate dielectric layers 100. Epitaxial source / drain regions 92 are disposed on opposite sides of the fins 55, the gate dielectric layers 100, and the gate electrodes 102. FIG. 1 further shows reference cross-sections used in subsequent figures. The cross-section A-A' extends along a longitudinal axis of a gate electrode 102 and, for example, in a direction perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of the FinFETs. The cross-section B-B' is perpendicular to the cross-section A-A' and extends along a longitudinal axis of a fin 55, and in a direction of current flow between the epitaxial source / drain regions 92 of the FinFETs, for example. The cross-section C-C' is parallel to the cross-section A-A' and extends through the epitaxial source / drain regions 92 of the FinFETs. Subsequent figures refer to these reference cross-sections for clarity.Some embodiments discussed herein are discussed in the context of fin field effect transistors (FinFETs) and nanostructure field effect transistors (NSFETs) (e.g., nanofoil, nanowire, gate all around, or the like) formed using gate last processes. In some embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices or the like.FIGS. 2-16B are cross-sectional views of intermediate stages in fabricating FinFETs, in accordance with some embodiments. FIGS. 2, 3A, 3B, 3C, 4A, 4B, 5, 13C, 16C, 16D, and 16E show the reference cross section A-A' shown in FIG. 1, which has a region 50N and a region 50P. FIGS. 6A, 11A, 12A, 13A, 14A, 15A, and 16A are illustrated along the reference cross section A-A' shown in FIG. 1 in the region 50N or the region 50P. FIGS. 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 13D, 13E, 14B, 14C, 15B, and 16B are depicted along a similar cross-section B-B' shown in FIG. 1. FIGS. 7A, 8A, 9A, 10A and 10C are shown along the reference cross section C-C' shown in FIG. 1.In FIG. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, an SOI (semiconductor on insulator) substrate, or the like, which may be doped (e.g., with a p- or an n-type dopant) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an isolation layer. The isolation layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, or combinations thereof.The substrate 50 includes a region 50N and a region 50P. Region 50N may be provided for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. Region 50P may be provided for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. Region 50N may be physically separated from region 50P (as illustrated by separation 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between region 50N and region 50P.Additionally, in FIG. 2, a portion of the substrate 50 in the region 50P may be replaced with a first semiconductor epitaxial material 52. A patterned mask (not separately shown), such as a patterned photoresist, may be formed over the region 50N. The patterned resist may be formed by depositing a resist layer over the substrate 50 using spin-on coating or the like. The photoresist layer may then be patterned by exposing the photoresist layer to a patterned energy source (e.g., a patterned light source) and developing the photoresist layer to remove an exposed or unexposed portion of the photoresist layer, thereby forming the patterned photoresist layer. The substrate 50 in the region 50P is then etched using a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process) or the like, to form a first opening. The patterned photoresist may then be removed.The first semiconductor epitaxial material 52 is then formed to fill the first opening. The first semiconductor epitaxial material 52 may be deposited using an epitaxial growth process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first epitaxial semiconductor material 52 may include a semiconductor material such as silicon germanium or the like.The first epitaxial semiconductor material 52 may be formed with a gradient germanium concentration. For example, in some embodiments, a germanium concentration of the first epitaxial semiconductor material 52 may be gradually and continuously increased from an upper surface of the first epitaxial semiconductor material 52 to a lower surface of the first epitaxial semiconductor material 52. In some embodiments, an atomic percentage of germanium in the first epitaxial semiconductor material 52 may be in the range of about 0 percent at an upper surface of the first epitaxial semiconductor material 52 to about 90 percent at a lower surface of the first epitaxial semiconductor material 52. In some embodiments, the atomic percentage of germanium in the first epitaxial semiconductor material 52 may be in the range of about 8 percent at the top surface of the first epitaxial semiconductor material 52 to about 32 percent at the bottom surface of the first epitaxial semiconductor material 52. A ratio of the atomic percentage of germanium at the top surface of the first epitaxial semiconductor material 52 to the atomic percentage of germanium at the bottom surface of the first epitaxial semiconductor material 52 is in the range of about 1:2 to about 1:8, or from about 1:3 to about 1:5.In embodiments where the first semiconductor epitaxial materials 52 are deposited using CVD, the gradient germanium concentration in the first semiconductor epitaxial material 52 may be achieved by gradually decreasing a flow rate of a germanium-containing precursor (e.g., monogermane (GeH 4) or the like) relative to a flow rate of a silicon-containing precursor (e.g., dichlorosilane (H 2 Cl 2 Si), silane (SiH 4) or the like) during the deposition of the first semiconductor epitaxial material 52. For example, a ratio of a flow rate of a germanium precursor to a flow rate of a silicon precursor may be from about 1 to about 9, or from about 1 to about 3, at the beginning of the deposition process used to deposit the first epitaxial semiconductor materials 52, and a ratio of the flow rate of the germanium precursor to the flow rate of the silicon precursor may be from about 0 to about 1, or from about 0 to about 0.5, at the end of the deposition process used to deposit the first epitaxial semiconductor material 52. After the first semiconductor epitaxial material 52 is deposited, upper surfaces of the substrate 50 in the region 50N and the first semiconductor epitaxial material 52 in the region 50P may be planarized using a process such as chemical mechanical polishing (CMP). A thickness T of the first epitaxial semiconductor material 52 may be from about 10 nm to about 200 nm or from about 40 nm to about 60 nm.In FIG. 3A, fins 55 are formed in the substrate 50 and the first epitaxial semiconductor material 52. Fins 55 are semiconductor fins. In some embodiments, the fins 55 may be formed in the substrate 50 and the first epitaxial semiconductor material 52 by etching trenches in the substrate 50 and the first epitaxial semiconductor material 52. The etching may be any suitable etching process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic.The fins 55 may be patterned using any suitable method. For example, the fins 55 may be patterned using one or more photolithography processes including dual-patterning or multi-patterning processes. In some embodiments, dual-patterning or multi-patterning processes combine photolithography and self-aligning processes, thereby allowing patterns to be created that have, for example, smaller pitches than otherwise achievable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins 55. In some embodiments, the mask (or other layer) may remain on the fins 55. As shown in FIG. 3A, the fins 55 in both the region 50N and the region 50P may have tapered profiles in which widths at the bottom surfaces of the fins 55 are greater than widths at the top surface of the fins 55.In region 50N, fins 55 (comprising fin-shaped portions of substrate 50 extending from a flat top surface of substrate 50) may have a bottom width W 1 from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 to about 32 nm; a top width W 2 from about 2 nm to about 50 nm, from about 20 to 30 nm, or from about 23 nm to about 27 nm; a ratio of the top width W 2 to the bottom width W 1 from about 0.5 to about 2, or from about 0.7 to about 0.9; and a height H 1 from about 10 nm to about 200 nm, or from about 70 nm to about 90 nm. The fins 55 in the region 50N may be spaced at a pitch P 1 of from about 2 nm to about 100 nm or from about 25 nm to about 35 nm. An angle θ 1 between sidewalls of the fins 55 in the region 50N and a top surface of the substrate 50 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. In region 50P, fins 55 (which include fin-shaped portions of first semiconductor epitaxial material 52 and substrate 50 extending from a flat top surface of substrate 50) may have a bottom width W 3 from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 to about 32 nm; a mean width W 4 at an interface between substrate 50 and first semiconductor epitaxial material 52, from about 2.2 to about 80, from about 23 nm to about 33 nm, or from about 26 to about 30 nm; a top width W 5 from about 2 nm to about 50 nm, from about 20 to 30 nm, or from about 23 nm to about 27 nm; and have a height H 2 of from about 10 nm to about 200 nm or from about 70 nm to about 90 nm. A ratio of the upper width W 5 to the average width W 4 may be from about 2 to about 0.5, or from about 0.8 to about 1.0, and a ratio of the average width W 4 to the lower width W 3 may be from about 2 to about 0.5, or from about 0.8 to about 1.0. The fins 55 in the region 50P may be spaced at a pitch P 2 of from about 2 nm to about 100 nm, or from about 25 nm to about 35 nm. An angle θ 2 between sidewalls of the fins 55 in the region 50P and a top surface of the substrate 50 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°.FIG. 3B illustrates an embodiment in which a thinning process is performed to thin the fins 55 after forming the fins 55 and before the STI regions (such as the STI regions 58 discussed below with reference to FIG. 4A ). In the embodiment illustrated in FIG. 3B, the fins 55 in the region 50N may be exposed to etchants used to thin the fins 55 in the region 50P, and the fins 55 in the region 50P may be exposed to etchants used to thin the fins in the region 50N.In FIG. 3B, exposed portions of the fins 55 in the region 50N and exposed portions of the fins 55 in the region 50P formed in the substrate 50 may be etched using first etch chemistries in a first etch process. During the first etching process, the fins in both the region 50N and the region 50P may be exposed to the first etching chemicals. It may be desired that a first etch selectivity, which is the ratio of the etch rate (sometimes referred to as the trim rate) of the fins 55 in the region 50N and portions of the fins 55 in the region 50P formed in the substrate 50 (e.g., portions of the fins 55 formed of silicon) to the etch rate of portions of the fins 55 in the region 50P formed of the first epitaxial semiconductor material 52 (e.g., portions of the fins 55 formed of silicon germanium), be high to minimize the etching of the portions of the fins 55 in the region 50P formed of the first epitaxial semiconductor material 52. For example, the first etch selectivity may be higher than about 5 and may be in the range of about 5 to about 20, or higher. The first etching process may be performed at a temperature ranging from about 5° C. to about 100° C., such as about room temperature (e.g., about 23° C.). The fins 55 may be exposed to the first etch chemicals for a duration ranging from about 10 seconds to about 5 minutes, or from about 45 seconds to about 75 seconds.In some embodiments, the first etch chemicals may include a first etchant dissolved in a first solvent. The first etching chemicals may be free of oxidants. The first etchant may include a base or an acid. In embodiments where the first etchant comprises a base, the first etchant may comprise a metal hydroxide (M n+( OH-) n), amine derivatives, ammonium derivatives, combinations thereof, or the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, or the like. The amine derivatives may include ammonia (NH 3), ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH, (CH 3)4 N(OH)), tetraethylammonium hydroxide (TEAH, (C 2 H 5)4 N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH 3)3( C 14 H 29) N(OH)), tetrabutylammonium hydroxide (TBAH, (C 4 H 9)4 N(OH)), combinations thereof, or the like. In embodiments where the first etchant is a base, a pH of the first etching chemicals may be from about 7 to about 13, or from about 8 to about 10. The first etchant may be present in the first etching chemicals at a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.In embodiments where the first etchant comprises an acid, the first etchant may comprise hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H 2 SO 4), phosphoric acid (H 3 PO 4), nitric acid (HNO 3), carboxylic acid derivatives (C n H 2n+1 COOH), combinations thereof, or the like. In embodiments where the first etchant is an acid, a pH of the first etching chemicals may be from about 0 to about 7, or from about 1 to about 3. The first etchant may be present in the first etching chemicals at a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.The first solvent may be used to help mix and dispense the first etchant. The first solvent may not be involved in the etching reaction. In a particular embodiment, the first etching solvent may be a solvent such as deionized water or the like. However, any suitable solvent may be used.The first etch chemicals may also include ionic or non-ionic surfactants such as quaternary ammonium (NR 4+), sulfate (SO4 2-), sulfonate (R-SO 3-), phosphate (-PO4 3-), carboxylates (R-COO -), alcohol ethoxylates, alkylphenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerol esters, combinations thereof, or the like, which may be added to reduce the surface tension of the first etch chemicals. The surfactants may be present in the first etch chemicals at a concentration ranging from about 0.0001 M to about 1 M or from about 0.005 M to about 0.02 M.Prior to etching the fins 55 with the first etching process, the fins 55 have tapered profiles in which widths at the bottom of the fins 55 are greater than widths at the top of the fins 55 (as discussed above in the discussion with reference to FIG. 3A ). The first etching process may have the same etch rates at the top of the fins 55 and the bottom of the fins 55, such that the fins 55 in the region 50N and portions of the fins 55 in the region 50P formed in the substrate 50 continue to have a tapered profile after the fins 55 are etched with the first etching process.After the fins 55 in the region 50N and the region 50P are etched with the first etching process, the fins 55 in the region 50N may have a height H 5 from about 10 nm to about 200 nm, or from about 60 nm to about 80 nm; a bottom width W 10 from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm; a top width W 11 from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and a ratio of the top width W 11 to the bottom width W 10 from about 0.5 to about 2, or from about 0.65 to about 0.85. An angle θ 5 between sidewalls of the fins 55 in the region 50N and a top surface of the substrate 50 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. Portions of the fins 55 in the region 50P formed in the substrate 50 may have a bottom width W 12 of from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm; a top width W 13 of from about 2 nm to about 80 nm, from about 13 to 23 nm, or from about 16 nm to about 20 nm; and a ratio of the top width W 13 to the bottom width W 12 of from about 0.5 to about 2, or from about 0.8 to about 1.0. An angle θ 6 between sidewalls of the portions of the fins 55 formed in the substrate 50 in the region 50P and a top surface of the substrate 50 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°.Additionally, in FIG. 3B, exposed portions of the fins 55 in the region 50P formed of the first epitaxial semiconductor material 52 may be etched in a second etching process separate from the first etching process using second etching chemicals. During the second etching process, the fins in both the region 50P and the region 50N may be exposed to the second etching chemicals. It is desirable that a second etch selectivity, which is the ratio of the etch rate of the portions of the fins 55 in the region 50P formed from the first semiconductor epitaxial material 52 to the etch rate of the fins 55 in the region 50N and the portions of the fins 55 in the region 50P formed in the substrate 50, be high to minimize the etching of the fins 55 in the region 50N and the portions of the fins in the region 50P formed in the substrate 50. For example, the second etch selectivity may be higher than about 5 and may be in the range of about 5 to about 20, or higher. The second etching process may be performed at a temperature ranging from about 5° C. to about 100° C., such as about room temperature (e.g., about 23° C.).In some embodiments, the second etch chemicals may include an oxidizing agent and a second etchant dissolved in a second solvent. The fins 55 may be exposed to the oxidant and the second etchant simultaneously. In embodiments where the fins 55 are exposed to the oxidant and the second etchant simultaneously, the fins 55 may be exposed to the second etch chemicals for a duration of from about 30 seconds to about 2 minutes, or from about 45 seconds to about 75 seconds. In some embodiments, the second etchant may be the same as the first etchant. For example, in some embodiments, the second etchant may be a base or an acid.In embodiments where the second etchant comprises a base, the second etchant may comprise a metal hydroxide (M n+( OH-) n), amine derivatives, ammonium derivatives, combinations thereof, or the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, or the like. The amine derivatives may include ammonia (NH 3), ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH, (CH 3)4 N(OH)), tetraethylammonium hydroxide (TEAH, (C 2 H 5)4 N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH 3)3( C 14 H 29) N(OH)), tetrabutylammonium hydroxide (TBAH, (C 4 H 9)4 N(OH)), combinations thereof, or the like. In embodiments where the second etchant is a base, a pH of the first etching chemicals may be from about 7 to about 13, or from about 8 to about 10. The second etchant may be present in the second etching chemicals at a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.In embodiments where the second etchant comprises an acid, the second etchant may comprise hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H 2 SO 4), phosphoric acid (H 3 PO 4), nitric acid (HNO 3), carboxylic acid derivatives (C n H 2n+1 COOH), combinations thereof, or the like. In embodiments where the first etchant is an acid, a pH of the first etching chemicals may be from about 0 to about 7, or from about 1 to about 3. The second etchant may be present in the second etching chemicals at a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.The oxidizing agent may include ozonized deionized water (DIO 3), hydrogen peroxide (H 2 O 2), other nonmetallic oxidizing agents, combinations thereof, or the like. An oxidizing agent may be present in the second etching chemicals at a concentration ranging from about 0.0001 M to about 1 M, or from about 0.0005 M to about 0.002 M. Including the oxidizing agent in addition to the second etchant allows the first semiconductor epitaxial material 52 to be selectively etched with respect to the fins 55 in the region 50N and portions of the fins 55 in the region 50P formed in the substrate 50. The oxidizing agent may be used to oxidize the fins 55 in the region 50P, thereby forming silicon germanium oxide in the fins 55, and the second etchant may then be used to etch the silicon germanium oxide material, thereby thinning the fins 55 in the region 50P. On the other hand, in region 50N, the oxidizing agent may be used to oxidize fins 55, thereby forming silicon oxide in fins 55, which is etched at a slower rate by the second etchant. Silicon may also be oxidized at a slower rate than silicon germanium, such that a silicon oxide layer formed in fins 55 in region 50N and portions of fins 55 in region 50P formed in substrate 50 is thinner than an oxide layer formed in fins 55 in region 50P. Accordingly, the fins 55 in region 50N and portions of the fins 55 in region 50P formed in substrate 50 are substantially unthinked while the fins 55 in region 50P are thinned.The second solvent may be used to help mix and dispense the oxidant and the second etchant. The second solvent itself may not be involved in the etching reaction. In a particular embodiment, the second etching solvent may be a solvent such as deionized water, acetic acid (CH 3 COOH), or the like. In embodiments where the oxidant comprises ozonized deionized water, the deionized water may also act as a solvent. Any suitable solvents may be used.The second etch chemicals may also include ionic or non-ionic surfactants such as quaternary ammonium (NR 4+), sulfate (SO 42-), sulfonate (R-SO 3-), phosphate (-PO4 3-), carboxylates (R-COO -), alcohol ethoxylates, alkylphenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerol esters, combinations thereof, or the like, which may be added to reduce the surface tension of the first etch chemicals. The surfactants may be present in the second etch chemicals at a concentration ranging from about 0.0001 M to about 1 M or from about 0.005 M to about 0.02 M.In a specific embodiment, the second etch chemicals may include hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2) and acetic acid (CH 3 COOH). The acetic acid may be a solvent in which the hydrofluoric acid and the hydrogen peroxide dissolve. The hydrogen peroxide may be an oxidizing agent used to oxidize the fins 55 in the region 50P. The hydrofluoric acid may be a second etchant used to thin the fins 55 in the region 50P. A volume ratio of hydrofluoric acid:hydrogen peroxide:acetic acid may be about 1:2:3.In further embodiments, the fins 55 may be exposed to an oxidant, then the oxidant may be removed, and the fins 55 may be exposed to a second etchant in a cyclical process to thin the fins 55. Exposing the fins 55 to the oxidizing agent may oxidize the fins 55 in the region 50N and the region 50P. Exposing the fins 55 to the etchants may selectively etch the oxide formed in the first semiconductor epitaxial material 52 with respect to the oxide formed in the fins 55 in the region 50N and portions of the fins 55 in the region 50P formed in the substrate 50.The oxidant used in the cyclic process may be the same as those described above as being used in the process in which the fins 55 are simultaneously exposed to the oxidant and the second etchant. The oxidizing agent may include, for example, ozonized deionized water (DIO 3), hydrogen peroxide (H 2 O 2), other nonmetallic oxidizing agents, combinations thereof, or the like. An oxidizing agent may be present in the oxidant at a concentration ranging from about 0.0001 M to about 1 M, or from about 0.0005 M to about 0.002 M. As discussed above, exposing fins 55 may oxidize fins 55 in region 50P. The fins 55 in region 50N may also be oxidized, but may be oxidized at a slower rate than the fins 55 in region 50P.The second etchant used in the cyclical process may be the same as or similar to the first etchant. The second etchant may be present at a concentration ranging from about 0.01 M to about 20 M, or from about 0.5 M to about 1.5 M. Exposing the fins 55 to the second etchant thins the fins 55. As discussed above, the fins 55 in region 50N may be thinned at a slower rate than the fins 55 in region 50P.For each cycle, the fins 55 may be exposed to the oxidant for a duration ranging from about 10 seconds to about 2 minutes, or from about 45 seconds to about 75 seconds, and the fins 55 may be exposed to the second etchant for a duration ranging from about 10 seconds to about 5 minutes, or from about 45 seconds to about 75 seconds. The cyclic etching process may be repeated up to 20 cycles, up to 10 cycles, 4 to 6 cycles, or the like. Exposing the fins 55 to the oxidant, then the second etchant in a cyclical process may provide better control of the etching of the first epitaxial semiconductor material 52. This results in improved gate control of resulting FinFETs, reduces fin width variation, and results in reduced DIBL.The second etching process may include etch rates that are dependent on the germanium concentration in the first epitaxial semiconductor material 52. For example, the second etching process may have higher etch rates as the germanium concentration in the first epitaxial semiconductor material 52 increases. As discussed above in the discussion relating to FIG. 2, the first epitaxial semiconductor material 52 may have a gradient germanium concentration in which the germanium concentration is higher at the bottom surface of the first epitaxial semiconductor material 52 and gradually and continuously decreases toward the top surface of the first epitaxial semiconductor material 52. Thus, lower portions of the first epitaxial semiconductor material 52 may be etched at higher etch rates than upper portions of the first epitaxial semiconductor material 52 by the second etch process. a ratio of the etch rate at the lower surface of the first epitaxial semiconductor material 52 (e.g., a maximum etch rate) to the etch rate at the upper surface of the first epitaxial semiconductor material 52 (e.g., a minimum etch rate) may be from about 1 to about 3 or from about 1.25 to about 1.75.Prior to etching the fins 55 in the region 5P with the second etching process, the fins 55 have a tapered profile in which widths at the bottom of the fins 55 are greater than widths at the top of the fins 55 (as discussed above in the discussion with reference to FIG. 3A ). Etching the first epitaxial semiconductor material 52 with the second etching process, which has a higher etching rate at the bottom of the first epitaxial semiconductor material 52 than the top of the first epitaxial semiconductor material 52, results in the first epitaxial semiconductor material 52 having a rectangular profile after etching the first epitaxial semiconductor material 52 with the second etching process.After the first semiconductor epitaxial material 52 has been etched with the second etching process, portions of the fins 55 in the region 50P formed from the first semiconductor epitaxial material 52 may have a height H 6 of from about 5 nm to about 100 nm, or from about 60 nm to about 80 nm; a bottom width W 14 of from about 2.2 nm to about 100 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; a top width W 15 of from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and have a ratio of the upper width W 15 to the lower width W 14 of from about 0.8 to about 1.2 or from about 0.9 to about 1.1. An angle θ 7 between sidewalls of the portions of the fins 55 formed of the first semiconductor epitaxial material 52 in the region 50P and a top surface of the substrate 50 may be from about 80° to about 100°, from about 85° to about 95°, or from about 88° to about 92°. The fins 55 in the region 50P may have a height H, from about 10 nm to about 200 nm, or from about 70 nm to about 90 nm.Forming the fins 55 in the region 50P having a gradient germanium concentration and thinning the fins 55 in the region 50P using an etching process having a higher etch rate with increasing germanium concentration results in the fins 55 in the region 50P having rectangular profiles and improves control of the process used to etch the fins 55 in the region 50P. Incorporating the fins 55 into FinFETs results in better gate control, reduced fin width variation, and reduced DIBL.FIG. 3C illustrates another embodiment in which a thinning process is performed to thin the fins 55 after forming the fins 55 and before the STI regions (such as the STI regions 58 discussed below with reference to FIG. 4A ). In the embodiment illustrated in FIG. 3C, fins 55 in region 50N may be masked while fins 55 in region 50P are thinned, and fins 55 in region 50P may be masked while fins 55 in region 50N are thinned.In FIG. 3C, the fins 55 in the region 50N are exposed to the first etch chemicals while the fins 55 in the region 50P are protected. The fins 55 in the region 50P may be protected by forming a patterned mask (not separately shown), such as a patterned photoresist, over the region 50P. The patterned resist may be formed by depositing a resist layer over the substrate 50 using spin-on coating or the like. The photoresist layer may then be patterned by exposing the photoresist layer to a patterned energy source (e.g., a patterned light source) and developing the photoresist layer to remove an exposed or unexposed portion of the photoresist layer, thereby forming the patterned photoresist layer. The fins 55 in the region 50N are then thinned by exposing the fins 55 to the first etch chemicals. The patterned photoresist may then be removed. In some embodiments, fins 55 in region 50N may also be protected while fins 55 in region 50P are exposed to the second etch chemicals using a process the same or similar to the process used to protect fins 55 in region 50P. The first etch chemistries and processes used to etch the fins 55 in the region 50N and the second etch chemistries and processes used to etch the fins 55 in the region 50P may be the same or similar to those described above with reference to FIG. 3B.After the fins 55 in region 50N and region 50P have been etched, the fins 55 in region 50N may have the same dimensions as the fins 55 in region 50N discussed above with reference to FIG. 3B. Portions of the fins 55 in the region 50P formed in the substrate 50 may have the same or similar dimensions as the portions of the fins 55 in the region 50P formed in the substrate 50, as discussed above with reference to FIG. 3A. For example, widths of the fins 55 in the region 50P formed in the substrate 50P may be within about 10 nm of the widths discussed above with reference to FIG. 3A. Portions of the fins 55 in the region 50P formed of the first semiconductor epitaxial material 52 may have a height H 8 of from about 5 nm to about 100 nm, or from about 60 nm to about 80 nm; a bottom width W 16 of from about 2.2 nm to about 100 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; a top width W 17 of from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and a ratio of the top width W 17 to the bottom width W 16 of from about 0.8 to about 1.2, or from about 0.9 to about 1.1. An angle θ 8 between sidewalls of the portions of the fins 55 formed of the first semiconductor epitaxial material 52 in the region 50P and a top surface of the substrate 50 may be from about 80° to about 100°, from about 85° to about 95°, or from about 88° to about 92°. The fins 55 in the region 50P may have a height H 9 from about 10 nm to about 200 nm, or from about 70 nm to about 90 nm.Forming the fins 55 in the region 50P having a gradient germanium concentration and thinning the fins 55 in the region 50P using an etching process having a higher etch rate with increasing germanium concentration results in the fins 55 in the region 50P having rectangular profiles and improves control of the process used to etch the fins 55 in the region 50P. Incorporating the fins 55 into FinFETs results in better gate control, reduced fin width variation, and reduced DIBL. Using various masks to protect the fins 55 in region 50N while the fins 55 in region 50P are being etched, and to protect the fins in region 50P during the etching of the fins 55 in region 50N allows additional control of fin profiles in region 50N and region 50P.FIG. 4A illustrates an embodiment in which the fins 55 are not thinned until STI (shallow trench isolation) regions 58 have been formed. For example, the thinning process may be performed after forming the STI regions 58, as will be discussed below with reference to FIG. 4B, or after removing dummy gate stacks (such as dummy gate stacks including dummy gates 72 and dummy dielectric layers 60, discussed below with reference to FIGS. 6A and 6B ), as will be discussed below with reference to FIGS. 13C through 13E. However, it should be appreciated that the steps performed in FIG. 4A and subsequent figures may be performed on fins 55 that have been thinned as described above with reference to FIGS. 3B and 3C.In FIG. 4A, STI (shallow trench isolation) regions 58 are formed adjacent to the fins 55. The STI regions 58 may be formed by forming an isolation material (not separately shown) over the substrate 50 and between adjacent fins 55. The isolation material may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed via chemical vapor deposition using high density plasma (HDP-CVD), FCVD (flowable CVD) (e.g., CVD-based material deposition in a remote plasma system, followed by curing to convert the deposited material to another material such as an oxide), the like, or a combination thereof. Other insulation materials formed using any suitable process may be used. In the illustrated embodiment, the isolation material is silicon oxide formed using an FCVD process. A anneal process may be performed after the isolation material is formed. In some embodiments, the isolation material is formed such that excess isolation material covers the fins 55. The insulation material may have a single layer or may use multiple layers. For example, in some embodiments, a liner (not separately shown) may be first formed along surfaces of the substrate 50 and the fins 55. Thereafter, a fill material, such as those discussed above, may be formed over the liner.A removal process is then applied to the isolation material to remove excess isolation material over the fins 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch back process, combinations thereof, or the like may be used. The planarization process may collimate the isolation material and fins 55. The planarization process exposes the fins 55 so that top surfaces of the fins 55 and the isolation material are level after the planarization process is completed.The isolation material is then recessed to form the STI regions 58, as shown in FIG. 4A. The isolation material is recessed such that upper portions of the fins 55 and the substrate 50 protrude from the space between adjacent STI regions 58. Additionally, the top surfaces of the STI regions 58 may include flat surfaces as shown, convex surfaces, concave surfaces (such as a bump), or a combination thereof. The top surfaces of the STI regions 58 may be formed flat, convex, and / or concave using suitable etching. The STI regions 58 may be recessed using a suitable etching process, such as one that is selective to the material of the isolation material (e.g., that etches the material of the isolation material at a faster rate than the material of the fins 55 and the substrate 50). For example, oxide removal using, for example, dilute hydrofluoric acid (d) may be used. A height H 11 of the STI regions 58 may be from about 30 nm to about 100 nm or from about 55 nm to about 75 nm.Additionally, in FIG. 4A, suitable wells (not separately shown) may be formed in the fins 55 and / or the substrate 50. In some embodiments, a P-well may be formed in region 50N and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.In the embodiments with different well types, the different implantation steps for region 50N and region 50P may be achieved using a photoresist or other masks (not separately shown). For example, a photoresist may be formed over fins 55 and STI regions 58 in region 50N. The photoresist is patterned to expose the region 50P of the substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique and may be patterned using suitable photolithography techniques. After the photoresist is patterned, an n-type impurity implant is performed in region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as an NMOS region. The n-type impurities may be phosphorus, arsenic, antimony, or the like, implanted into the region to a concentration less than or equal to 1×10 18 atoms / cm 3 such as between about 1×10 18 atoms / cm 3 and about 1×10 18 atoms / cm 3, for example. After the implantation, the photoresist is removed, e.g., using a suitable ashing process.After implantation in region 50P, a photoresist is formed over fins 55 and STI regions 58 in region 50P. The photoresist is patterned to expose the region 50N of the substrate 50, such as the NMOS region. The photoresist may be formed using a spin coating technique and may be patterned using suitable photolithography techniques. After the photoresist is patterned, a p-type impurity implant may be performed in region 50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into region 50P, such as the PMOS region. The n-type impurities may be boron, boron fluoride, indium, or the like, implanted into the region to a concentration less than or equal to 1×10 18 atoms / cm 3 such as between about 1×10 16 atoms / cm 3 and about 1×10 18 atoms / cm 3, for example. After the implantation, the photoresist may be removed, e.g., using a suitable ashing process.After the implantations of the region 50N and the region 50P, an anneal may be performed to remedy implantation damage and activate the p- and / or n-type impurities that have been implanted. In some embodiments, epitaxial fin growth materials may be in situ doped during growth, which may avoid the implants, although in situ and implant doping may be used together.FIG. 4B illustrates an embodiment in which the thinning process is performed to thin the fins 55 after the STI regions 58 are formed and not after the formation of the fins 55 and before the formation of the STI regions 58, as discussed above with reference to FIGS. 3B and 3C. In the embodiment illustrated in FIG. 4B, the fins 55 in the region 50N may be exposed to etchants used to thin the fins 55 in the region 50P, and the fins 55 in the region 50P may be exposed to etchants used to thin the fins 55 in the region 50N.In the embodiment illustrated in FIG. 4B, the fins 55 in both the region 50N and the region 50P are exposed to the first etch chemicals and the second etch chemicals in processes similar to those described above with reference to FIG. 3B. After the first etching process, the fins 55 (comprising fin-shaped portions of the substrate 50 extending from a flat top surface of the substrate 50) in the region 50N may have a height H 3 of from about 5 nm to about 100 nm, or from about 60 nm to about 80 nm; a bottom width W 6 of from about 2.2 nm to about 80 nm, from about 17 nm to about 27 nm, or from about 20 nm to about 24 nm; a top width W 7 of from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and have a ratio of the upper width W 7 to the lower width W 6 of from about 0.5 to about 2 or from about 0.6 to about 0.8. An angle θ 3 between sidewalls of the fins 55 in the region 50N and a top surface of the substrate 50 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. After the second etching process, the fins 55 (comprising fin-shaped portions of the first epitaxial semiconductor material 52 and the substrate extending from a flat top surface of the substrate 50) in the region 50N may have a height H 4 from about 5 nm to about 100 nm, or from about 60 nm to about 80 nm; a bottom width W 8 from about 2.2 nm to about 80 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; a top width W 9 from about 2 nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm; and have a ratio of the upper width W 9 to the lower width W 8 of from about 0.8 to about 1.2 or from about 0.9 to about 1.1. In some embodiments, the bottom width W 8 of the fins 55 in the region 50P may be within 10 nm, within 5 nm, or within 1 nm of the top width W 9 of the fins 55 in the region 50P. An angle θ 4 between sidewalls of the fins 55 in the region 50P and a top surface of the substrate 50 may be from about 80° to about 100°, from about 85° to about 95°, or from about 88° to about 92°.Portions of the fins 55 in the region 50N and the region 50P surrounded by the STI regions 58 may remain unchanged after the thinning process is performed. For example, portions of the fins 55 disposed below upper surfaces of the STI regions 58 may have widths similar or equal to those discussed above with reference to FIG. 3A. As shown in FIG. 4B, due to the thinning process, there may be a step change in the widths of the fins 55 that are level with the top surfaces of the STI regions 58.Forming the fins 55 in the region 50P having a gradient germanium concentration and thinning the fins 55 in the region 50P using an etching process having a higher etch rate with increasing germanium concentration results in the fins 55 in the region 50P having rectangular profiles and improves control of the process used to etch the fins 55 in the region 50P. Incorporating the fins 55 into FinFETs results in better gate control, reduced fin width variation, and reduced DIBL.FIG. 5 illustrates an embodiment in which the fins 55 are not thinned until after dummy gate stacks (such as dummy gate stacks including the dummy gates 72 and the dummy gate dielectric layers 60, discussed below with reference to FIGS. 6A and 6B ) are formed. For example, the thinning process may be performed after the removal of the dummy gate stacks, as will be discussed below with reference to FIGS. 13C to 13E. However, it should be appreciated that the steps performed in FIG. 5 and subsequent figures may be performed on fins 55 that have been thinned as described above with reference to FIGS. 3B, 3C, and 4B.In FIG. 5, dummy dielectric layers 60 are formed on the fins 55 and the substrate 50. The dummy dielectric layers 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to suitable techniques. A dummy gate layer 62 is formed over the dummy dielectric layers 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layers 60 and then planarized using a process such as CMP. The mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be conductive or non-conductive materials and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer 62 may be deposited using physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 62 may be formed of other materials having a high etch selectivity to the material of the STI regions 58. The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed over the region 50N and the region 50P. It should be noted that the dummy dielectric layers 60 are shown to cover only the fins 55 and the substrate 50 for illustrative purposes only. In some embodiments, dummy dielectric layers 60 may be deposited such that dummy dielectric layers 60 cover STI regions 58 by extending between dummy gate layer 62 and STI regions 58.FIGS. 6A through 16E show various additional steps in manufacturing devices of the embodiments. FIGS. 6A-13B and FIGS. 14A-16B show features in either region 50N or region 50P. For example, the structures illustrated in FIGS. 6A-13B and 14A-16B may be applicable to both the region 50N and the region 50P. Differences (if any) in the structures of region 50N and region 50P are described in the text accompanying each figure. For example, the structures illustrated in FIGS. 13C to 13E and FIGS. 16C to 16E may describe differences between the region 50N and the region 50P.In FIGS. 6A and 6B, the mask layer 64 (see FIG. 5 ) may be patterned using suitable photolithography and etching techniques to form masks 74. A suitable etching technique may be used to transfer the pattern of the masks 74 to the dummy gate layer 62 to form dummy gates 72. In some embodiments, the pattern of the masks 74 may also be transferred to the dummy dielectric layers 60. Dummy gates 72 cover respective channel regions 68 of fins 55. The pattern of the masks 74 may be used to physically separate each of the dummy gates 72 from adjacent dummy gates. Dummy gates 72 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of respective fins 55. The dummy dielectric layers 60, dummy gates 72, and masks 74 may collectively be referred to as "dummy gate stacks.".In FIGS. 7A and 7B, a first spacer layer 80 and a second spacer layer 82 are formed over the structures illustrated in FIGS. 6A and 6B. In FIGS. 7A and 7B, the first spacer layer 80 is formed on top surfaces of the STI regions 58, top surfaces and sidewalls of the fins 55 and the masks 74, and sidewalls of the dummy gates 72 and the dummy dielectric layers 60. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed by thermal oxidation or deposited using a CVD, an ALD, or the like. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. The second spacer layer 82 may be deposited using a CVD, an ALD, or the like. The second spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.In FIGS. 8A and 8B, the first spacer layer 80 and a second spacer layer 82 are etched to form first spacers 81 and second spacers 83. The first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process) or the like. The first spacers 81 and the second spacers 83 may be disposed on sidewalls of the fins 55, the dummy dielectric layers 60, the dummy gates 72, and the masks 74. The first spacers 81 and the second spacers 83 may have different heights adjacent to the fins 55 and the dummy gate stacks due to the etching processes used to etch the first spacer layer 80 and the second spacer layer 82, as well as different heights between the fins 55 and the dummy gate stacks. In particular, in some embodiments, as shown in FIGS. 8A and 8B, the first spacers 81 and the second spacers 83 may partially extend upward along sidewalls of the fins 55 and the dummy gate stacks. In some embodiments, the first spacers 81 and the second spacers 83 may extend to top surfaces of the dummy gate stacks.After the first spacers 81 and the second spacers 83 have been formed, implantations for lightly doped source / drain (LDD) regions (not separately shown) may be performed. In embodiments with various device types, similar to the implants discussed above in FIG. 4, a mask, such as a photoresist, may be formed over the region 50N while the region 50P is exposed, and suitable type (e.g., p-type) contaminants may be implanted into the exposed fins 55 and the substrate 50 in the region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the region 50P while the region 50N is exposed, and impurities of suitable type (e.g., n-type) may be implanted into the exposed fins 55 and the substrate 50 in the region 50N. The mask may then be removed. The n-type impurities may be any of the n-type impurities discussed above, and the p-type impurities may be any of the p-type impurities discussed above. The lightly doped source / drain regions may have a concentration of impurities of about 1×10 15 atoms / cm 3 to about 1×10 19 atoms / cm 3. Annealing may be used to repair implantation damage and to activate the implanted contaminants.Note that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacers 81 may be formed prior to forming the second spacers 83, additional spacers may be formed and removed, and / or the like). In addition, n- and p-type devices may be formed using various structures and steps.In FIGS. 9A and 9B, first recesses 86 are formed in the fins 55 and the substrate 50. As shown in FIG. 9A, top surfaces of the STI regions 58 may be level with top surfaces of the substrate 50. The substrate 50 may be etched so that bottom surfaces of the first recesses 86 are disposed above and below the top surfaces of the STI regions 58. The first recesses 86 may be formed by etching the fins 55 and the substrate 60 using anisotropic etching processes, such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the masks 74 mask portions of the fins 55 and the substrate 50 during the etching processes used to form the first recesses 86. A single etching process or multiple etching processes may be used to form the first recesses 86. Timed etching processes may be used to stop etching the first recesses 86 after the first recesses 86 have reached a desired depth.In FIGS. 10A to 10C, epitaxial source / drain regions 92 are formed in the first recesses 86 to apply stress to the channel regions 68 of the fins 55, thereby improving performance. As illustrated in FIG. 10B, the epitaxial source / drain regions 92 are formed in the first recesses 86 such that each dummy gate 72 is disposed between respective adjacent pairs of the epitaxial source / drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 92 do not short subsequently formed gates of the resulting FinFETs.The epitaxial source / drain regions 92 in the region 50N, e.g., the NMOS region, may be formed by masking the region 50P, e.g., the PMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86. The epitaxial source / drain regions 92 may include any suitable material suitable for n-type FinFETs, for example. For example, when the fins 55 are silicon, the epitaxial source / drain regions 92 may include materials that apply tensile stress to the fins 55, such as silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphide, or the like. The epitaxial source / drain regions 92 may have surfaces raised from respective surfaces of the fins 55, and may have diamond surfaces.The epitaxial source / drain regions 92 in the region 50P, e.g., the PMOS region, may be formed by masking the region 50N, e.g., the NMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86. The epitaxial source / drain regions 92 may include any suitable material suitable for, e.g., p-NSFETs. For example, if the fins 55 are silicon, the epitaxial source / drain regions 92 may include materials that apply compressive stress to the fins 55, such as silicon germanium, boron doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 92 may also have surfaces raised from respective surfaces of the fins 55, and may have diamond surfaces.Dopants may be implanted into the epitaxial source / drain regions 92, the fins 55, and / or the substrate 50 to form source / drain regions, similar to the process discussed above for forming lightly doped source / drain regions followed by an anneal. The source / drain regions may have a concentration of impurities between about 1×10 19 atoms / cm 3 and about 1×10 21 atoms / cm 3. The n- and p-type impurities for source / drain regions may be any of the above-discussed impurities. In some embodiments, the epitaxial source / drain regions 92 may be in situ doped during growth.As a result of the epitaxial processes used to form the epitaxial source / drain regions 92 in the region 50N and the region 50P, top surfaces of the epitaxial source / drain regions 92 have diamond surfaces that extend laterally outward beyond sidewalls of the fins 55. In some embodiments, these diamond surfaces cause adjacent epitaxial source / drain regions 92 of a same FinFET to coalesce, as illustrated by FIG. 10A. In some embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, as illustrated by FIG. 10C. In the embodiments illustrated in FIGS. 10A and 10C, the first spacers 81 dmay be formed to cover portions of the sidewalls of the fins 55 that extend over the STI regions 58, thereby inhibiting epitaxial growth. In some embodiments, the spacers used to form the first spacers 81 may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region 58.In FIGS. 11A and 11B, a first interlayer dielectric (ILD) 96 is deposited over the structure shown in FIGS. 6A and 10B, respectively (the processes of FIGS. 7A through 10C do not change the cross-section shown in FIG. 6A, which illustrates dummy gates 72 and multilayer stack 56 protected by dummy gates 72). The first ILD 96 may be formed of a dielectric material and may be deposited using any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed using any suitable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the masks 74, and the first spacers 81. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a different etch rate than the material of the overlying first ILD 96.In FIGS. 12A and 12B, a planarization process, such as a CMP, may be performed to level the top surface of the first ILD 96 with the top surfaces of the dummy gates 72 or the masks 74. The planarization process may also remove the masks 74 on the dummy gates 72 and portions of the first spacers 81 along sidewalls of the masks 74. After the planarization process, upper surfaces of the dummy gates 72, the first spacers 81, and the first ILD 96 are at the same level. Accordingly, the top surfaces of the dummy gates 72 are exposed by the first ILD 96. In some embodiments, the masks 74 may remain, in which case the planarization process leveles the top surface of the first ILD 96 with a top surface of the masks 74 and the first spacers 81.In FIGS. 13A and 13B, the dummy gates 72 and the masks 74, if present, are removed in an etching step(s) so that second recesses 98 are formed. Portions of the dummy dielectric layers 60 in the second recesses 98 may also be removed. In some embodiments, only the dummy gates 72 are removed and the dummy dielectric layers 60 remain and are exposed by the second recesses 98. In some embodiments, the dummy dielectric layers 60 are removed from the second recesses 98 in a first region of a die (e.g., a core logic region) and remain in the second recesses 98 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gates 72 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process that uses a reaction gas(s) that selectively etch (etch) the dummy gates 72 at a faster rate than the first ILD 96 or the first spacers 81. Each second recess 98 exposes and / or overlies a channel region 68 of a respective fin 55. Each channel region 68 is disposed between adjacent pairs of the epitaxial source / drain regions 92. During the removal, the dummy dielectric layer 60 may be used as an etch stop layer when the dummy gates 72 are etched. The dummy dielectric layer 60 may then optionally be removed after the removal of the dummy gates 72.FIGS. 13C-13E show an embodiment in which the thinning process is performed to thin the fins 55 after the dummy gate stacks are removed, and not after the formation of the fins 55 and before the formation of the STI regions 58 as discussed above with reference to FIGS. 3B and 3C or after the formation of the STI regions 58 as discussed above with reference to FIG. 4B. In the embodiment illustrated in FIGS. 13C-13E, the fins 55 in region 50N may be exposed to etchants used to thin the fins 55 in region 50P, and the fins 55 in region 50P may be exposed to etchants used to thin the fins 55 in region 50N.In the embodiment illustrated in FIGS. 13C-13E, the fins 55 in both the region 50N and the region 50P are exposed to the first etch chemicals and the second etch chemicals in processes similar to those described above with reference to FIG. 3B. After the first etching process, the fins 55 in the region 50N may have the same dimensions as the fins 55 in the region 50N discussed above with reference to FIG. 4B. After the second etching process, portions of the fins 55 in the region 50P formed from the first epitaxial semiconductor material 52 may have the same dimensions as the portions of the fins 55 in the region 50P formed from the first epitaxial semiconductor material 52, as discussed above with reference to FIG. 4B.As shown in FIGS. 13D and 13E, thinning the fins 55 may recess exposed portions of upper surfaces of the fins 55 between the second spacers 83. In FIG. 13D, a recess is formed in an upper portion of the fins 55 formed from the substrate 50 in the region 50N. In FIG. 13E, a recess is formed in an upper portion of the fin 55 formed of the first semiconductor epitaxial material in the region 50P. Depths of the recesses may be greatest at points between the second spacers 83. The depths of the recesses may become shallower near the second spacer 83. The fins 55 in region 50N may be recessed to a depth D 2 from about 2 nm to about 50 nm, from about 5 nm to about 15 nm, or from about 8 nm to about 12 nm below top surfaces of the fins 55 in region 50N. The fins 55 in region 50P may be recessed to a depth D 3 from about 2 nm to about 50 nm, from about 5 nm to about 15 nm, or from about 8 nm to about 12 nm below top surfaces of the fins 55 in region 50P.Forming the fins 55 in the region 50P having a gradient germanium concentration and thinning the fins 55 in the region 50P using an etching process having a higher etch rate with increasing germanium concentration results in the fins 55 in the region 50P having rectangular profiles and improves control of the process used to etch the fins 55 in the region 50P. Incorporating the fins 55 into FinFETs results in better gate control, reduced fin width variation, and reduced DIBL.FIGS. 14A through 14C show an embodiment in which the fins 55 are not thinned after the dummy gate stacks are removed. In FIGS. 14A and 14B, gate dielectric layers 100 and gate electrodes 102 for replacement gates are formed. FIG. 14C shows a detailed view of the region 101 of FIG. 14B. The gate dielectric layers 100 are conformally deposited in the second recesses 98, such as on top surfaces and sidewalls of the fins 55 and the first spacers 81, and on top surfaces of the STI regions 58, the first ILD 96, the second spacers 83, and the CESL 94. In some embodiments, the gate dielectric layers 100 include silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectric layers 100 comprise a high-k dielectric material, and in these embodiments, the gate dielectric layers 100 may have a k value greater than about 7.0, and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The methods of forming the gate dielectric layers 100 may include molecular beam deposition (MBD), ALD, PECVD, or the like. In embodiments in which portions of the dummy dielectric layers 60 remain in the second recesses 98, the gate dielectric layers 100 comprise a material of the dummy dielectric layers 60 (e.g., SiO 2).The gate electrodes 102 are each deposited over the gate dielectric layers 100 and fill the remaining portions of the second recesses 98. the gate electrodes 102 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode 102 is illustrated in FIG. 14B, the gate electrode 102 may include any number of liner layers 102A, any number of work function adjustment layers 102B, and a fill material 102C, as illustrated by FIG. 14C. After filling the second recesses 98, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers 100 and the material of the gate electrodes 102, the excess portions being over the top surface of the first ILD 96. The remaining portions of material of the gate electrodes 102 and the gate dielectric layers 100 therefore form replacement gates of the resulting FinFETs. The gate electrodes 102 and the gate dielectric layers 100 may collectively be referred to as "gate stacks". The gate and gate stacks may extend along sidewalls of the channel regions 68 of the fins 55.The formation of the gate dielectric layers 100 in the region 50N and the region 50P may occur simultaneously such that the gate dielectric layers 100 in each region are formed of the same materials, and the formation of the gate electrodes 102 may occur simultaneously such that the gate electrodes 102 in each region are formed of the same materials. In some embodiments, the gate dielectric layers 100 in each region may be formed using different processes such that the gate dielectric layers 100 may be different materials, and / or the gate electrodes 102 in each region may be formed using different processes such that the gate electrodes 102 may be different materials. Different masking steps may be used to mask and expose appropriate regions when different processes are used.In FIGS. 15A and 15N, a second ILD 106 is deposited over the first ILD 96. In some embodiments, the second ILD 106 is a flowable film formed using an FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and may be deposited using any suitable method, such as CVD, PECVD, or the like. In some embodiments, prior to forming the second ILD 106, the gate stack (including the gate dielectric layers 100 and the corresponding overlying gate electrodes 102) is recessed such that a recess is formed directly over the gate stack and between opposing portions of the first spacers 81. A gate mask 104 comprising one or more layers of a dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled into the recess, followed by a planarization process to remove excess portions of the dielectric material that extend over the first ILD 96. Subsequently formed gate contacts 110 (such as gate contacts 112 discussed below with reference to FIGS. 16A and 16B ) penetrate through gate mask 104 to contact the top surface of recessed gate electrodes 102.In FIGS. 16A and 16B, gate contacts 112 and source / drain contacts 114 are formed by the second ILD 106 and the first ILD 96. Openings for the source / drain contacts 114 are formed through the first ILD 96 and the second ILD 106, and openings for the gate contacts 112 are formed through the second ILD 106 and the gate mask 104. The openings may be formed using suitable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesive layer, or the like and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the first ILD 106. The remaining liner and conductive material form the source / drain contacts 114 and the gate contacts 112 in the openings. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain regions 92 and the source / drain contacts 114. The source / drain contacts 114 are physically and electrically coupled to the epitaxial source / drain regions 92, and the gate contacts 112 are physically and electrically coupled to the gate electrodes 102. The source / drain contacts 114 and the gate contacts 112 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source / drain contacts 114 and the gate contacts 112 may be formed in different cross-sections, which may avoid shorting the contacts.FIGS. 16C through 16E show the structures of FIGS. 16A and 16B in embodiments where the fins 55 are thinned at different stages. FIG. 16C illustrates the embodiment of FIG. 3B where the fins 55 are simultaneously thinned prior to forming the STI regions 58. Portions of the fins 55 in the region 50N formed above and below upper surfaces of the STI regions 58 may have continuous sidewalls inclined at the same angles with respect to a main surface of the substrate 50. Portions of the fins 55 in the region 50P formed above and below upper surfaces of the STI regions 58 may include sidewalls inclined at different angles with respect to a main surface of the substrate 50. For example, as shown in FIG. 16C, sidewalls of the portion of the fins 55 in the region 50P above the top surfaces of the STI regions 58 formed from the first semiconductor epitaxial material 52 may be more vertical than sidewalls of the portion of the fins 55 in the region 50P below the top surfaces of the STI regions 58 formed in the substrate 50.FIG. 16D illustrates the embodiment of FIG. 3C, wherein the fins 55 in region 50P are masked during thinning of the fins 55 in region 50N, and the fins 55 in region 50N are masked during thinning of the fins 55 in region 50P. Portions of the fins 55 in the region 50N formed above and below upper surfaces of the STI regions 58 may have continuous sidewalls inclined at an equal angle with respect to a main surface of the substrate 50. Portions of the fins 55 in the region 50P formed of the first semiconductor epitaxial material 52 and formed in the substrate 50 may have sidewalls inclined at different angles with respect to a main surface of the substrate 50 and having a step difference of widths. For example, as illustrated in FIG. 16D, sidewalls of the portions of the fins 55 in the region 50P formed in the first semiconductor epitaxial material 52 may be more vertical than sidewalls of the portions of the fins 55 in the region 50P formed in the substrate 50. Further, there may be a step difference between widths of the portions of the fins 55 formed in the first semiconductor epitaxial material 52 and the portions of the fins 55 formed in the substrate 50, wherein the portions of the fins 55 formed in the first semiconductor epitaxial material 52 have widths smaller than widths of the portions of the fins 55 formed in the substrate 50.FIG. 16E illustrates the embodiment of FIGS. 4B or 13C- 13E, where the fins 55 are thinned after the formation of the STI regions 58 or after the removal of the dummy gate stacks. Portions of the fins 55 in the region 50N formed above and below upper surfaces of the STI regions 58 may include sidewalls inclined at different angles with respect to a main surface of the substrate 50, and having a step difference of widths. For example, as shown in FIG. 16E, sidewalls of the portions of the fins 55 in the region 50N formed below the top surfaces of the STI regions 58 may be more vertical than sidewalls of the portions of the fins 55 in the region 50N formed above the top surface of the STI regions 58. Further, there may be a step difference between widths of the portions of the fins 55 formed below the top surfaces of the STI regions 58 and the portions of the fins 55 formed above the top surfaces of the STI regions 58, where the portions of the fins 55 formed below the top surfaces of the STI regions 58 have greater widths than widths of the portions of the fins 55 formed above the top surfaces of the STI regions 58.Portions of the fins 55 in the region 50P formed above and below the top surfaces of the STI regions 58 may include sidewalls inclined at different angles with respect to a main surface of the substrate 50 and having a step difference of widths. For example, as shown in FIG. 16E, sidewalls of the portions of the fins 55 in the region 50P formed above the top surfaces of the STI regions 58 (e.g., portions of the fins 55 formed in the first semiconductor epitaxial material 52) may be more vertical than sidewalls of the portions of the fins 55 in the region 50P formed below the top surfaces of the STI regions 58 (e.g., portions of the fins 55 formed in the substrate 50). Further, there may be a step difference between widths of the portions of the fins 55 formed below the top surfaces of the STI regions 58 and the portions of the fins 55 formed above the top surfaces of the STI regions 58, where the portions of the fins 55 formed below the top surfaces of the STI regions 58 have greater widths than widths of the portions of the fins 55 formed above the top surfaces of the STI regions 58.As discussed above, forming the fins 55 in the region 50P having a gradient germanium concentration and thinning the fins 55 in the region 50P using an etching process having a higher etch rate with increasing germanium concentration results in the fins 55 in the region 50P having rectangular profiles and improves control of the process used to etch the fins 55 in the region 50P. Incorporating the fins 55 into FinFETs results in better gate control, reduced fin width variation, and reduced DIBL.FIG. 17 illustrates an example nanostructure field effect transistors (e.g., nanofoil, nanowire, gate-all-around field effect transistors, or the like) (NSFETs), in accordance with some embodiments. The NSFETs include nanostructures 255 over a substrate 250 (e.g., a semiconductor substrate). The nanostructures 255 include second semiconductor layers 254A- 254C that act as channel regions of the nanostructures 255. STI (shallow trench isolation) regions 258 are disposed in the substrate 250, and the nanostructures 255 are disposed over and between adjacent STI regions 258. Although the STI regions 258 are described / illustrated as being separate from the substrate 250, as used herein, the term "substrate" may refer exclusively to the semiconductor substrate or to a combination of the semiconductor substrate and the STI regions.Gate dielectric layers 300 are along top surfaces, sidewalls, and bottom surfaces of nanostructures 255, such as on top surfaces, sidewalls, and bottom surfaces of each of second semiconductor layers 254A- 254C, and along top surfaces and sidewalls of portions of substrate 250. Gate electrodes 302 are overlying the gate dielectric layers 300. Epitaxial source / drain regions 292 are disposed on opposite sides of the nanostructures 255, the gate dielectric layers 300, and the gate electrodes 302. FIG. 17 further shows reference cross sections used in later figures. The cross-section A-A' extends along a longitudinal axis of a gate electrode 302 and, for example, in a direction that is perpendicular to the direction of current flow between the epitaxial source / drain regions 292 of the NSFETs. The cross-section B-B' is perpendicular to the cross-section A-A' and extends along a longitudinal axis of a nanostructure 255 and, for example, in a direction of current flow between the epitaxial source / drain regions 292 of the NSFETs. The cross-section C-C' is parallel to the cross-section A-A' and extends through the epitaxial source / drain regions 292 of the NSFETs. Subsequent figures refer to these reference cross-sections for clarity.FIGS. 18 through 35D are cross-sectional views of intermediate stages in fabricating NSFETs, in accordance with some embodiments. FIGS. 18, 19A, 19B, 20A, 20B, 21, 31D, 35C, and 35D show the reference cross section A-A' shown in FIG. 17, which has a region 250N and a region 250P. FIGS. 22A, 29A, 30A, 31A, 32A, 32C, 33A, 33C, 33E, 34A, and 35A are depicted along the reference cross section A-A' shown in FIG. 17 in the region 250N or the region 250P. FIGS. 22B, 23B, 24B, 25B, 26B, 26C, 27B, 27C, 28B, 28C, 29B, 29C, 30B, 30C, 31B, 31C, 31E, 32B, 32D, 33B, 33D, 33F, 34B, and 35B are illustrated along a similar cross section B-B' shown in FIG. 17. Figs. 23A, 24A, 25A, 26A, 27A, 28A and 28D are shown along the reference cross section C-C' shown in Fig. 17.In FIG. 18, a substrate 250 for forming NSFETs is provided. The substrate 250 may be a semiconductor substrate, such as a bulk semiconductor, an SOI (semiconductor on insulator) substrate, or the like, which may be doped (e.g., with a p- or an n-type dopant) or undoped. The substrate 250 may be a wafer such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an isolation layer. The isolation layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 250 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, or combinations thereof.The substrate 250 includes a region 250N and a region 250P. Region 250N may be provided for forming n-type devices, such as NMOS transistors, e.g., n-NSFETs. Region 250P may be provided for forming p-type devices, such as PMOS transistors, e.g., p-NSFETs. Region 250N may be physically separated from region 250P (as illustrated by separation 251), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between region 250N and region 250P.The substrate 250 may be lightly doped with a p- or an n-type impurity. An anti-punch-through (APT) implant may be performed on an upper portion of the substrate 250 to form an APT region 253. During the APT implantation, dopants may be implanted into the region 250N and the region 250P. The dopants may have a conductivity type opposite to a conductivity type of the source / drain regions (such as epitaxial source / drain regions 292 discussed below with reference to FIGS. 28A-28D ) to be formed in each of region 250N and region 250P. The APT region 253 may extend under the subsequently formed source / drain regions in the resulting NSFETs formed in subsequent processes. The APT region 243 may be used to reduce the leakage current from the source / drain regions to the substrate 250. In some embodiments, the doping concentration in the APT region 253 may be from about 1×10 18 atoms / cm 3 to about 1×10 19 atoms / cm 3. For simplicity and readability, the APT region 253 is not illustrated in the subsequent drawings.In addition, in FIG. 18, a multilayer stack 256 is formed over the substrate 250. The multilayer stack 256 includes alternating first semiconductor layers 252 and second semiconductor layers 254 of different semiconductor materials. The first semiconductor layers 252 may be formed of first semiconductor materials, which may include, for example, silicon germanium (SiGe) or the like. The second semiconductor layers 254 may be formed of second semiconductor materials, which may include, for example, silicon (Si), silicon carbon (SiC), or the like. In some embodiments, the first semiconductor layers 252 may be formed of the second semiconductor materials and the second semiconductor layers 254 may be formed of the first semiconductor materials. For illustrative purposes, the multilayer stack 256 includes three of the first semiconductor layers 252 (e.g., first semiconductor layers 252A- 252C) and three of the second semiconductor layers 254 (e.g., second semiconductor layers 254A- 254C). In some embodiments, the multilayer stack 256 may include any number of the first semiconductor layers 252 and the second semiconductor layers 254. Each of the layers of the multilayer stack 256 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. Each of the first semiconductor layers 252A- 252C may have a thickness of from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm. Each of the second semiconductor layers 254A- 254C may have a thickness of from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm.The first semiconductor layers 252A- 252C may be formed with gradient germanium concentrations. For example, in some embodiments, a germanium concentration of each of the first semiconductor layers 252A- 252C may be gradually and continuously decreased from a bottom surface of the layer to a top surface of the layer. An atomic percentage of germanium in the first semiconductor layer 252A may range from about 90 percent at a bottom surface of the first semiconductor layer 252A to about 40 percent at a top surface of the first semiconductor layer 252A, from about 32 percent at the bottom surface of the first semiconductor layer 252A to about 15 percent at the top surface of the first semiconductor layer 252A, or the like. An atomic percentage of germanium in the first semiconductor layer 252B may range from about 60 percent at a bottom surface of the first semiconductor layer 252B to about 20 percent at a top surface of the first semiconductor layer 252B, from about 25 percent at the bottom surface of the first semiconductor layer 252B to about 8 percent at the top surface of the first semiconductor layer 252B, or the like. An atomic percentage of germanium in the first semiconductor layer 252C may range from about 50 percent at a bottom surface of the first semiconductor layer 252C to about o percent at a top surface of the first semiconductor layer 252C, from about 20 percent at the bottom surface of the first semiconductor layer 252C to about 8 percent at the top surface of the first semiconductor layer 252C, or the like.The ratio of the atomic percentage of germanium at the top surface of each of the first semiconductor layers 252A- 252C to the atomic percentage of germanium at the bottom surface of each of the first semiconductor layers 252A- 252C is in the range of about 1:2 to about 1:3. As will be discussed in more detail below, incorporating the first semiconductor layers 252A- 252C with the prescribed ratios of atomic percentages of germanium results in nanostructures (such as nanostructures 255 discussed below with reference to FIGS. 19A-20B ) having improved rectangular profiles, resulting in better gate control, reduced nanostructure width variation, and reduced drain-induced barrier stress.In embodiments where the first semiconductor layers 252A- 252C are deposited using CVD, the gradient germanium concentrations in the first semiconductor layers 252A- 252C may be achieved by gradually decreasing a flow rate of a germanium-containing precursor (e.g., monogermane (GeH 4) or the like) relative to a flow rate of a silicon-containing precursor (e.g., dichlorosilane (H 2 Cl 2 Si), silane (SiH 4) or the like) during the deposition of each of the first semiconductor layers 252A- 252C. For example, a ratio of a flow rate of a germanium precursor to a flow rate of a silicon precursor may be from about 1 to about 9, or from about 1 to about 3 at the beginning of the deposition process used to deposit the first semiconductor layer 252A, and a ratio of the flow rate of the germanium precursor to the flow rate of the silicon precursor may be from about o to about 1, or from about o to about 0.5 at the end of the deposition process used to deposit the first semiconductor layer 252C.For illustrative purposes, the second semiconductor layers 254 are described as forming channel regions in the region 250N, and the first semiconductor layers 252 are described as forming channel regions in the region 250P in completed NSFET devices. The first semiconductor layers 252 may be sacrificial layers in region 250N and the second semiconductor layers 254 may be sacrificial layers in region 250P that may be subsequently removed. In some embodiments, the first semiconductor layers 252 may form channel regions in the region 250N and the region 250P, and the second semiconductor layers 254 may be sacrificial layers. In some embodiments, the second semiconductor layers 254 may form channel regions in the region 250N and the region 250P, and the first semiconductor layers 252 may be sacrificial layers.In FIG. 19A, nanostructures 255 are formed in the multilayer stack 256, and the substrate 250 is etched. In some embodiments, nanostructures 255 may be formed by etching trenches in multilayer stack 256 and substrate 250. The etching may be any suitable etching process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic.Nanostructures 255 and substrate 250 may be patterned using any suitable method. For example, nanostructures 255 and substrate 250 may be patterned using one or more photolithography processes including double-patterning or multi-patterning processes. In general, double-patterning or multi-patterning processes combine photolithographic and self-aligning processes, thereby allowing patterns to be created that have, for example, smaller pitches than otherwise achievable using a single direct photolithographic process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the nanostructures 255 and the substrate 250. In some embodiments, after patterning nanostructures 255 and substrate 250, a mask (or other layer) may remain on nanostructures 255. As shown in FIG. 19A, nanostructures 255 in both region 250N and region 250P may have tapered profiles in which widths at the bottom surfaces of nanostructures 255 are greater than widths of the top surface of nanostructures 255.In region 250N, nanostructures 255 may have a bottom width W 18 from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 nm to about 32 nm; a top width W 19 from about 2 nm to about 50 nm, from about 20 to about 30 nm, or from about 23 nm to about 27 nm; and a ratio of the top width W 19 to the bottom width W 18 from about 0.5 to about 2, or from about 0.7 to about 0.9. The nanostructures 255 in the region 250N may be spaced at a pitch P 3 of from about 2 nm to about 50 nm or from about 15 nm to about 25 nm. An angle θ 9 between sidewalls of the nanostructures 255 in the region 250N and a top surface of the substrate 250 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. In region 250P, nanostructures 255 may have a bottom width W 20 from about 2.2 nm to about 100 nm, from about 25 nm to about 35 nm, or from about 28 nm to about 32 nm; a top width W 21 from about 2 nm to about 50 nm, from about 20 to about 30 nm, or from about 23 nm to about 27 nm; and a ratio of the top width W 21 to the bottom width W 20 from about 0.5 to about 2, or from about 0.7 to about 0.9. The nanostructures 255 in the region 250P may be spaced at a pitch P 4 of from about 2 nm to about 50 nm, or from about 15 nm to about 25 nm. An angle θ 10 between sidewalls of the nanostructures 255 in the region 250P and a top surface of the substrate 250 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. The nanostructures 255 in the region 250N and the region 250P may have heights H 10 from about 10 nm to about 200 nm, or from about 70 nm to about 90 nm. The substrate 250 may be etched to a depth D 1 from about 30 nm to about 100 nm, or from about 60 nm to about 70 nm below a top surface of the substrate 250.FIG. 19B illustrates an embodiment in which a thinning process is performed to thin nanostructures 255 after forming nanostructures 255 and before the STI regions (such as STI regions 258 discussed below with reference to FIG. 20A ). In the embodiment illustrated in FIG. 19B, nanostructures 255 in region 250N may be exposed to etchants used to thin nanostructures 255 in region 250P, and nanostructures 255 in region 250P may be exposed to etchants used to thin the fins in region 250N.In FIG. 19B, exposed portions of the second semiconductor layers 254A- 254C in the region 250N and the region 250P may be etched using first etching chemicals in a first etching process. During the first etching process, the first semiconductor layers 252A- 252C and the second semiconductor layers 254A- 254C may be exposed to the first etching chemicals in both the region 250N and the region 250P. It is desired that a first etch selectivity representing the ratio of the etch rate (sometimes referred to as the trim rate) of the second semiconductor layers 254A- 254C (e.g., formed of silicon) to the etch rate of the first semiconductor layers 252A- 252C (e.g., formed of silicon germanium) is high to minimize the etching of the first semiconductor layers 252A- 252C. For example, the first etch selectivity may be higher than about 5 and may be in the range of about 5 to about 20, or higher. The first etching process may be performed at a temperature ranging from about 5° C. to about 100° C., such as about room temperature (e.g., about 23° C.). The nanostructures 255 may be exposed to the first etch chemicals for a duration ranging from about 10 seconds to about 5 minutes, or from about 45 seconds to about 75 seconds.In some embodiments, the first etch chemicals may include a first etchant dissolved in a first solvent. The first etching chemicals may be free of oxidants. The first etchant may include a base or an acid. In embodiments where the first etchant comprises a base, the first etchant may comprise a metal hydroxide (M n+( OH-) n), amine derivatives, ammonium derivatives, combinations thereof, or the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, or the like. The amine derivatives may include ammonia (NH 3), ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH, (CH 3)4 N(OH)), tetraethylammonium hydroxide (TEAH, (C 2 H 5)4 N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH 3)3( C 14 H 29) N(OH)), tetrabutylammonium hydroxide (TBAH, (C 4 H 9)4 N(OH)), combinations thereof, or the like. In embodiments where the first etchant is a base, a pH of the first etching chemicals may be from about 7 to about 13, or from about 8 to about 10. The first etchant may be present in the first etching chemicals at a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.In embodiments where the first etchant comprises an acid, the first etchant may comprise hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H 2 SO 4), phosphoric acid (H 3 PO 4), nitric acid (HNO 3), carboxylic acid derivatives (C n H 2n+1 COOH), combinations thereof, or the like. In embodiments where the first etchant is an acid, a pH of the first etching chemicals may be from about o to about 7, or from about 1 to about 3. The first etchant may be present in the first etching chemicals at a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.The first solvent may be used to help mix and dispense the first etchant. The first solvent may not be involved in the etching reaction. In a particular embodiment, the first etching solvent may be a solvent such as deionized water or the like. However, any suitable solvent may be used.The first etch chemicals may also include ionic or non-ionic surfactants such as quaternary ammonium (NR 4+), sulfate (SO 42-), sulfonate (R-SO 3-), phosphate (-PO4 3-), carboxylates (R-COO -), alcohol ethoxylates, alkylphenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerol esters, combinations thereof, or the like, which may be added to reduce the surface tension of the first etch chemicals. The surfactants may be present in the first etch chemicals at a concentration ranging from about 0.0001 M to about 1 M or from about 0.0005 M to about 0.002 M.Prior to etching the second semiconductor layers 254A- 254C with the first etching process, all of the second semiconductor layers 254A- 254C have tapered profiles in which widths at the bottom of the second semiconductor layers 254A- 254C are greater than widths at the top of the second semiconductor layers 254A- 254C (as discussed above with respect to FIG. 19A ). The first etching process may have the same etch rates at the top of the second semiconductor layers 254A- 254C and the bottom of the second semiconductor layers 254A- 254C, such that the second semiconductor layers 254A- 254C continue to have tapered profiles after etching the nanostructures 255 with the first etching process. The first etching process may etch top surfaces and sidewalls of the second semiconductor layers 254C such that the second semiconductor layers 254C have heights less than the second semiconductor layers 254A- 254B.After the nanostructures 255 in the region 250N and the region 250P are etched with the first etching process, the second semiconductor layers 254A- 254B may have a height H 13 from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm, and the second semiconductor layers 254C may have a height H 14 from about 2 nm to about 30 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm. In some embodiments, the widths of nanostructures 255 may be different in region 250N and region 250P. For example, in region 250N, an average width W 22 of second semiconductor layers 254A may be from about 2.2 nm to about 80 nm, from about 12 nm to about 22 nm, or from about 15 nm to about 19 nm; an average width W 23 of second semiconductor layers 254B may be from about 2.2 nm to about 80 nm, from about 11 nm to about 21 nm, or from about 14 nm to about 18 nm; and an average width W24 of second semiconductor layers 254C may be from about 2.2, nm to about 50 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm. A ratio of the width W 24 to the width W 23 may be from about 0.5 to about 2, or from about 0.8 to about 1.0, a ratio of the width W 23 to the width W 22 may be from about 0.5 to about 2, or from about 0.8 to about 1.0, and a ratio of the width W 24 to the width W 22 may be from about 0.25 to about 4, or from about 0.64 to about 1.0. In region 250P, an average width W 25 of second semiconductor layers 254A may be from about 2.2 nm to about 80 nm, from about 12 nm to about 22 nm, or from about 15 nm to about 19 nm; an average width W 26 of second semiconductor layers 254B may be from about 2.2 nm to about 80 nm, from about 11 nm to about 21 nm, or from about 14 nm to about 18 nm; and an average width W 27 of second semiconductor layers 254C may be from about 2.2, nm to about 80 nm, from about 10 nm to about 20 nm, or from about 13 nm to about 17 nm. A ratio of the width W 27 to the width W 26 may be from about 0.5 to about 2, or from about 0.8 to about 1.0, and a ratio of the width W 26 to the width W 25 may be from about 0.5 to about 2, or from about 0.8 to about 1.0.Portions of the nanostructures 255 formed in the substrate 250 in the region 250N may have a bottom width W 30 of from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm, and a top width W 31 of from about 2.2 nm to about 80 nm, from about 13 to about 23 nm, or from about 16 nm to about 20 nm. A ratio of the upper width W 31 to the lower width W 30 may be from about 0.5 to about 2, or from about 0.8 to about 1.0. An angle θ 11 between sidewalls of the portions of the nanostructures 255 formed in the substrate 250 in the region 250N and a top surface of the substrate 250 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. Portions of the nanostructures 255 formed in the substrate 250 in the region 250P may have a bottom width W 32 of from about 2.2 nm to about 100 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm, and a top width W 33 of from about 2.2 nm to about 80 nm, from about 13 to about 23 nm, or from about 15 nm to about 20 nm. An angle θ 12 between sidewalls of the portions of the nanostructures 255 formed in the substrate 250 in the region 250P and a top surface of the substrate 250 may be from about 70° to about 85°, from about 78° to about 82°, from about 95° to about 120°, or from about 98° to about 102°. A ratio of the upper width W 33 to the lower width W 32 may be from about 0.5 to about 2, or from about 0.8 to about 1.0.In addition, in FIG. 19B, exposed portions of the first semiconductor layers 252A- 252C in the region 250N and the region 250P may be etched using second etching chemicals in a second etching process separate from the first etching process. During the second etching process, the first semiconductor layers 252A- 252C and the second semiconductor layers 254A- 254C may be exposed to the second etching chemicals in both the region 250N and the region 250P. It is desired that a second etch selectivity representing the ratio of the etch rate (sometimes referred to as the trim rate) of the first semiconductor layers 252A- 252C (e.g., formed of silicon germanium) to the etch rate of the second semiconductor layers 254A- 254C (e.g., formed of silicon) is high to minimize the etching of the second semiconductor layers 254A- 254C. For example, the second etch selectivity may be higher than about 5 and may be in the range of about 5 to about 20, or higher. The second etching process may be performed at a temperature ranging from about 5° C. to about 100° C., such as about room temperature (e.g., about 23° C.).In some embodiments, the second etch chemicals may include an oxidizing agent and a second etchant dissolved in a second solvent. The fins 55 may be exposed to the oxidant and the second etchant simultaneously. In embodiments where nanostructures 255 are exposed to the oxidants and the second etchants simultaneously, nanostructures 255 may be exposed to the second etching chemicals for a duration of from about 30 seconds to about 2 minutes, or from about 45 seconds to about 75 seconds. In some embodiments, the second etchant may be the same as the first etchant. The second etchant may be a base or an acid.In embodiments where the second etchant comprises a base, the second etchant may comprise a metal hydroxide (M n+( OH-) n), amine derivatives, ammonium derivatives, combinations thereof, or the like. The metal hydroxide may include sodium hydroxide (NaOH), potassium hydroxide (KOH), lithium hydroxide (LiOH), rubidium hydroxide (RbOH), cesium hydroxide (CsOH), combinations thereof, or the like. The amine derivatives may include ammonia (NH 3), ammonium hydroxide (NH 4 OH), tetramethylammonium hydroxide (TMAH, (CH 3)4 N(OH)), tetraethylammonium hydroxide (TEAH, (C 2 H 5)4 N(OH)), trimethyltetradecylammonium hydroxide (TTAH, (CH 3)3( C 14 H 29) N(OH)), tetrabutylammonium hydroxide (TBAH, (C 4 H 9)4 N(OH)), combinations thereof, or the like. In embodiments where the second etchant is a base, a pH of the first etching chemicals may be from about 7 to about 13, or from about 8 to about 10. The second etchant may be present in the second etching chemicals at a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.In embodiments where the second etchant comprises an acid, the second etchant may include hydrochloric acid (HCl), hydrofluoric acid (HF), sulfuric acid (H 2 SO 4), phosphoric acid (H 3 PO 4), nitric acid (HNO 3), carboxylic acid derivatives (C n H 2n+1 COOH), combinations thereof, or the like. In embodiments where the first etchant is an acid, a pH of the first etching chemicals may be from about o to about 7, or from about 1 to about 3. The second etchant may be present in the second etching chemicals at a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.The oxidizing agent may include ozonized deionized water (DIO 3), hydrogen peroxide (H 2 O 2), other nonmetallic oxidizing agents, combinations thereof, or the like. An oxidizing agent may be present in the second etching chemicals at a concentration ranging from about 0.0001 M to about 1 M, or from about 0.0005 M to about 0.002 M. Incorporating the oxidizing agent in addition to the second etchant allows the first semiconductor layers 252A- 252C to be selectively etched with respect to the second semiconductor layers 254A- 254C. The oxidizing agent may be used to oxidize the first semiconductor layers 252A- 252C, thereby forming silicon germanium oxide in the first semiconductor layers 252A- 252C, and the second etchant may then be used to etch the silicon germanium oxide material, thereby thinning the first semiconductor layers 252A- 252C. On the other hand, in region 250N, the oxidizing agent may be used to oxidize second semiconductor layers 254A- 254C, thereby forming silicon oxide in second semiconductor layers 254A- 254C that is etched at a slower rate by the second etchant. Silicon may also be oxidized at a slower rate than silicon germanium, such that a silicon oxide layer formed in the second semiconductor layers 254A- 254C is thinner than an oxide formed in the first semiconductor layers 252A- 25C. Accordingly, the second semiconductor layers 254A- 254C are substantially unstrained while the first semiconductor layers 252A- 252C are strained.The second solvent may be used to help mix and dispense the oxidant and the second etchant. The second solvent may not be involved in the etching reaction. In a particular embodiment, the second etching solvent may be a solvent such as deionized water, acetic acid (CH 3 COOH), or the like. In embodiments where the oxidant comprises ozonized deionized water, the deionized water may also act as a solvent. Any suitable solvents may be used.The second etch chemicals may also include ionic or non-ionic surfactants such as quaternary ammonium (NR 4+), sulfate (SO 42-), sulfonate (R-SO 3-), phosphate (-PO4 3-), carboxylates (R-COO-), alcohol ethoxylates, alkylphenol ethoxylates, fatty acid ethoxylates, fatty amine ethoxylates, glycol esters, glycerol esters, combinations thereof, or the like, which may be added to reduce the surface tension of the first etch chemicals. The surfactants may be present in the second etch chemicals at a concentration ranging from about 0.01 M to about 20 M or from about 0.5 M to about 1.5 M.In a specific embodiment, the second etch chemicals may include hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2) and acetic acid (CH 3 COOH). The acetic acid may be a solvent in which the hydrofluoric acid and the hydrogen peroxide are dissolved. The hydrogen peroxide may be an oxidizing agent used for oxidizing the first semiconductor layers 252A to 252C. The hydrofluoric acid may be a second etchant used to thin the first semiconductor layers 252A- 252C. A volume ratio of hydrofluoric acid: hydrogen peroxide: acetic acid may be about 1:2:3.In further embodiments, the nanostructures 255 may be exposed to the oxidant, then the oxidant may be removed, and the nanostructures 255 may be exposed to the second etchant in a cyclical process to thin the second semiconductor layers 254A- 254C of the nanostructures 255. Exposing nanostructures 255 to the oxidizing agent may oxidize nanostructures 255 in region 25 oN and region 250P. Exposing the nanostructures 255 to the second etchant may selectively etch the oxide formed in the first semiconductor layers 252A- 252 with respect to the oxide formed in the second semiconductor layers 254A- 254C.The oxidant used in the cyclic process may be the same as those described above as being used in the process in which the nanostructures 255 are simultaneously exposed to the oxidant and the second etchant. The oxidizing agent may include, for example, ozonized deionized water (DIO 3), hydrogen peroxide (H 2 O 2), other nonmetallic oxidizing agents, combinations thereof, or the like. An oxidant may be present in the oxidant at a concentration ranging from about 0.0001 M to about 1 M, or from about 0.0005 M to about 0.002 M. As discussed above, exposing the nanostructures 255 may oxidize the first semiconductor layers 252A- 252C. The second semiconductor layers 254A- 254C may also be oxidized, but may be oxidized at a slower rate than the first semiconductor layers 252A- 252C.The second etchant used in the cyclical process may be the same as or similar to the first etchant. The second etchant may be present at a concentration ranging from about 0.01 M to about 20 M, or from about 0.5 M to about 1.5 M. Exposing the nanostructures 255 to the second etchant thins the second semiconductor layers 254A- 254C. As discussed above, the first semiconductor layers 252A- 252C may be thinned at a slower rate than the second semiconductor layers 254A- 254C.For each cycle, the nanostructures 255 may be exposed to the oxidant for a duration ranging from about 10 seconds to about 5 minutes, or from about 45 seconds to about 75 seconds, and the nanostructures 255 may be exposed to the second etchant for a duration ranging from about 10 seconds to about 5 minutes, or from about 45 seconds to about 75 seconds. The cyclic etching process may be repeated up to 20 cycles, up to 10 cycles, 4 to 6 cycles, or the like. Exposing the nanostructures 255 to the oxidant, then the second etchant in a cyclical process may provide better control of the etching of the first semiconductor layers 252A- 252C. This results in improved gate control of resulting NSFETs, reduces nanostructure width variation, and results in reduced DIBL.The second etching process may include etch rates that are dependent on the germanium concentration in the first semiconductor layers 252A- 252C. For example, the second etching process may have higher etch rates as germanium concentration in the first semiconductor layers 252A- 252C increases. As discussed above in the discussion with respect to FIG. 18, each of the first semiconductor layers 252A- 252C may have a gradient germanium concentration in which the germanium concentration at the lower surface of the respective first semiconductor layer 252A- 252C is higher and gradually and continuously decreases toward the upper surface of the respective semiconductor layer 252A- 252C. Therefore, lower portions of the first semiconductor layers 252A- 252C may be etched by the second etching process at higher etch rates than upper portions of the first semiconductor layers 252A- 252C. A ratio of the etch rate at the bottom surface of the first semiconductor layer 252A (e.g., a maximum etch rate) to the etch rate at the top surface of the first semiconductor layer 252C (e.g., a minimum etch rate) may be from about 0.5 to about 2, or from about 0.75 to about 1.25.Prior to etching the first semiconductor layers 252A- 252C with the second etching process, all of the first semiconductor layers 252A- 252C have tapered profiles in which widths at the bottom of each of the first semiconductor layers 252A- 252C are greater than widths at the top of each of the first semiconductor layers 252A- 252C (as discussed above in the discussion with reference to FIG. 19A ). Etching the first semiconductor layers 252A- 252C with the second etching process having a higher etching rate at the bottom of each of the first semiconductor layers 252A- 252C than the top of each of the first semiconductor layers 252A- 252C results in the first semiconductor layers 252A- 252C having rectangular profiles after etching the first semiconductor layers 252A- 252C with the second etching process.After the first semiconductor layers 252A- 252C are etched with the second etching process, each of the first semiconductor layers 252A- 252C may have an average width W 28 in the region 250N of from about 2.2 nm to about 80 nm, from about 23 nm to about 33 nm, or from about 26 nm to about 30 nm. A ratio of the width W 28 of the upper first semiconductor layers 252C to the lower semiconductor layers 252A may be from about 0.8 to about 1.2, or from about 0.9 to about 1. Each of the first semiconductor layers 252A- 252C in the region 250P may have an average width W 29 of from about 2.2 nm to about 80 nm, from about 23 nm to about 33 nm, or from about 26 nm to about 30 nm. A ratio of the width W 29 of the first semiconductor layers 252C to the lower semiconductor layers 252A may be from about 0.8 to about 1.2, or from about 0.9 to about 1. Each of the first semiconductor layers 252A- 252C in the region 250N and the region 250P may have a height H 15 of from about 2 nm to about 50 nm, from about 15 nm to about 25 nm, or from about 18 nm to about 22 nm.Forming the first semiconductor layers 252A- 252C having a gradient germanium concentration and thinning the first semiconductor layers 252A- 252C using an etching process having a higher etching rate with increasing germanium concentration results in the first semiconductor layers 252A- 252C having rectangular profiles and improves control of the process used to etch the first semiconductor layers 252A- 252C. Incorporating the first semiconductor layers 252A- 252C into NSFETs results in better gate control, reduced nanostructure width variation, and reduced DIBL.FIG. 20A shows an embodiment in which nanostructures 255 are not thinned until after STI (shallow trench isolation) regions 258 are formed. For example, the thinning process may be performed after forming the STI regions 258, as will be discussed below with reference to FIG. 20B, or after removing dummy gate stacks (such as dummy gate stacks including dummy gates 272 and dummy dielectric layers 260, as will be discussed below with reference to FIGS. 22A and 22B ), as will be discussed below with reference to FIGS. 31D and 31E. However, it should be appreciated that the steps performed in FIG. 20A and subsequent figures may be performed on nanostructures 255 that have been thinned as described above with reference to FIG. 19B.In FIG. 20A, STI (shallow trench isolation) regions 258 are formed adjacent to the nanostructures 255 and the patterned portions of the substrate 250. The STI regions 258 may be formed by forming an isolation material (not separately shown) over the substrate 250 and between adjacent nanostructures 255 / patterned portions of the substrate 250. The isolation material may be an oxide such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed via chemical vapor deposition using high density plasma (HDP-CVD), FCVD (flowable CVD) (e.g., CVD-based material deposition in a remote plasma system, followed by curing to convert the deposited material to another material such as an oxide), the like, or a combination thereof. Other insulation materials formed using any suitable process may be used. In some embodiments, the isolation material is silicon oxide formed using an FCVD process. A anneal process may be performed after the isolation material is formed. In some embodiments, the isolation material is formed such that excess isolation material covers nanostructures 255. The insulation material may have a single layer or may use multiple layers. For example, in some embodiments, a liner (not separately shown) may be first formed along surfaces of the substrate 250 and nanostructures 255. Thereafter, a fill material, such as those discussed above, may be formed over the liner.A removal process is then applied to the isolation material to remove excess isolation material over the nanostructures 255. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch back process, combinations thereof, or the like may be used. The planarization process may collimate the isolation material and nanostructures 255. The planarization process exposes nanostructures 255 such that top surfaces of nanostructures 255 and the isolation material are level after the planarization process is completed.The isolation material is then recessed to form the STI regions 258, as shown in FIG. 20A. The isolation material is recessed such that upper portions of nanostructures 255 and substrate 250 protrude from the space between adjacent STI regions 258. Additionally, the top surfaces of the STI regions 258 may include flat surfaces as shown, convex surfaces, concave surfaces (such as a bump), or a combination thereof. The top surfaces of the STI regions 258 may be formed flat, convex, and / or concave using suitable etching. The STI regions 258 may be recessed using a suitable etching process, such as one that is selective to the material of the isolation material (e.g., that etches the material of the isolation material at a faster rate than the material of the nanostructures 255 and the substrate 250). For example, oxide removal using, for example, dilute hydrofluoric acid (d) may be used. A height H 12 of the STI regions 258 may be from about 30 nm to about 100 nm or from about 55 nm to about 75 nm.FIG. 20B illustrates an embodiment in which the thinning process is performed to thin the nanostructures 255 after the STI regions 258 are formed, rather than after the formation of the nanostructures 255 and before the formation of the STI regions 258, as discussed above with reference to FIG. 19B. In the embodiment illustrated in FIG. 20B, nanostructures 255 in region 250N may be exposed to etchants used to thin nanostructures 255 in region 250P, and nanostructures 255 in region 250P may be exposed to etchants used to thin nanostructures 255 in region 250N.In the embodiment illustrated in FIG. 20B, nanostructures 255 in both region 25 oN and region 250P are exposed to the first etch chemicals and the second etch chemicals in processes similar to those described above with reference to FIG. 19B. After the first etching process, the second semiconductor layers 254A- 254C in the region 25 oN and the region 250P may have the same or similar dimensions as the second semiconductor layers 254A- 254C discussed above with reference to FIG. 19B. After the second etching process, the first semiconductor layers 252A- 252C in the region 25 oN and the region 250P may have the same or similar dimensions as the first semiconductor layers 252A- 252C, as discussed above with reference to FIG. 19B. For example, the dimensions of the first semiconductor layers 252A- 252C and the dimensions of the second semiconductor layers 254A- 254C may be within 10 nm of the dimensions discussed above with reference to FIG. 19B.Forming the first semiconductor layers 252A- 252C having a gradient germanium concentration and thinning the first semiconductor layers 252A- 252C using an etching process having a higher etching rate with increasing germanium concentration results in the first semiconductor layers 252A- 252C having rectangular profiles and improves control of the process used to etch the first semiconductor layers 252A- 252C. Incorporating the first semiconductor layers 252A- 252C into NSFETs results in better gate control, reduced nanostructure width variation, and reduced DIBL.Portions of the nanostructures 255 in the region 50N and the region 50P surrounded by the STI regions 258 may remain unchanged after the thinning process is performed. For example, portions of nanostructures 255 disposed below top surfaces of STI regions 258 may have widths similar or the same as those discussed above with reference to FIG. 19A. As shown in FIG. 20B, due to the thinning process, there may be a step change in the widths of the nanostructures 255 level with the top surfaces of the STI regions 258.FIG. 21 shows an embodiment in which nanostructures 255 are not thinned until after dummy gate stacks (such as dummy gate stacks including dummy gates 272 and dummy gate dielectric layers 260, discussed below with reference to FIGS. 22A and 22B ) are formed. For example, the thinning process may be performed after removing the dummy gate stacks, as will be discussed below with reference to FIGS. 31D and 31E. However, it should be appreciated that the steps performed in FIG. 21 and subsequent figures may be performed on nanostructures 255 that have been thinned as described above with reference to FIG. 19B or FIG. 20B.In FIG. 21, dummy dielectric layers 260 are formed on nanostructures 255 and substrate 250. The dummy dielectric layers 260 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to suitable techniques. A dummy gate layer 262 is formed over the dummy dielectric layers 260, and a mask layer 264 is formed over the dummy gate layer 262. The dummy gate layer 262 may be deposited over the dummy dielectric layers 260 and then planarized using a process such as CMP. The mask layer 264 may be deposited over the dummy gate layer 262. The dummy gate layer 262 may be conductive or non-conductive materials and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. Dummy gate layer 262 may be deposited using physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit the selected material. The dummy gate layer 262 may be formed of other materials having a high etch selectivity to the material of the STI regions 258. The mask layer 264 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 262 and a single mask layer 264 are formed over the region 250N and the region 250P. It should be noted that the dummy dielectric layers 260 are shown to cover only the nanostructures 255 and the substrate 250 for illustrative purposes only. In some embodiments, the dummy dielectric layers 260 may be deposited such that the dummy dielectric layers 260 cover the STI regions 258 by extending between the dummy gate layer 262 and the STI regions 258.FIGS. 22A through 35D show various additional steps in manufacturing devices of the embodiments. Figures 22A-25B, 26A, 27A, 28A, 28D, 29A, 30A, 31A, 31E, 34A and 35A show features in either region 25oN or region 250P. For example, the structures illustrated in FIGS. 22A to 25B, 26A, 27A, 28A, 28D, 29A, 30A, 31A, 31E, 34A, and 35A may be applicable to both the region 250N and the region 250P. Differences (if any) in the structures of region 250N and region 250P are described in the text accompanying each figure. For example, FIGS. 26B, 27B, 28B, 29B, 30B, 31B, 32A, 32B, 33A, 33B, 33E, 33F, 34B, and 35B show structures in the region 250N, 26C, 27C, 28C, 29C, 31C, 32C, 32D, 33C, and 33D show structures in the region 250P, and FIG. 31D, FIGS. 35C and 35D show structures in the region 25 oN and the region 250P.In FIGS. 22A and 22B, the mask layer 264 (see FIG. 21 ) may be patterned using suitable photolithography and etching techniques to form masks 274. A suitable etching technique may be used to transfer the pattern of the masks 274 to the dummy gate layer 262 to form dummy gates 272. In some embodiments, the pattern of the masks 274 may also be transferred to the dummy dielectric layers 260. Dummy gates 272 cover respective channel regions of nanostructures 255. In some embodiments, the channel regions may be formed in the second semiconductor layers 254A- 254C including the second semiconductor materials in the region 250N, and the channel regions may be formed in the first semiconductor layers 252A- 252C including the first semiconductor materials in the region 250P. The pattern of the masks 274 may be used to physically separate each of the dummy gates 272 from adjacent dummy gates 272. Dummy gates 272 may have a longitudinal direction that is substantially perpendicular to longitudinal directions of respective nanostructures 255. The dummy dielectric layers 260, the dummy gates 272, and the masks 274 may collectively be referred to as "dummy gate stacks.".In FIGS. 23A and 23B, a first spacer layer 280 and a second spacer layer 282 are formed over the structures illustrated in FIGS. 25A and 25B. In FIGS. 26A and 26B, the first spacer layer 280 is formed on top surfaces of the STI regions 258, top surfaces and sidewalls of the nanostructures 255 and the masks 274, and sidewalls of the substrate 250, the dummy gates 272, and the dummy dielectric layers 260. The second spacer layer 282 is deposited over the first spacer layer 280. The first spacer layer 280 may be formed by thermal oxidation or deposited using a CVD, an ALD, or the like. The first spacer layer 280 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. The second spacer layer 282 may be deposited using a CVD, an ALD, or the like. The second spacer layer 282 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.In FIGS. 24A and 24B, the first spacer layer 280 and a second spacer layer 282 are etched to form first spacers 281 and second spacers 283. The first spacer layer 280 and the second spacer layer 282 may be etched using a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process) or the like. The first spacers 281 and the second spacers 283 may be disposed on sidewalls of the nanostructures 255, the dummy dielectric layers 260, the dummy gates 272, and the masks 274. The first spacers 281 and the second spacers 283 may have different heights adjacent to the nanostructures 255 and the dummy gate stacks due to the etching processes used to etch the first spacer layer 280 and the second spacer layer 282, as well as different heights between the nanostructures 255 and the dummy gate stacks. In particular, in some embodiments, as shown in FIGS. 24A and 24B, the first spacers 281 and the second spacers 283 may partially extend upward along sidewalls of the nanostructures 255, and may extend to top surfaces of the dummy gate stacks. In some embodiments, the first spacers 281 and the second spacers 283 may partially extend upward along sidewalls of the dummy gate stacks. For example, upper surfaces of the first spacers 281 and the second spacers 283 may be disposed above upper surfaces of the dummy gates 272 and below upper surfaces of the masks 274.In FIGS. 25A and 25B, first recesses 286 are formed in the nanostructures 255 and the substrate 250. The first recesses 285 may extend through the first semiconductor layers 252A- 252C and the second semiconductor layers 254A- 254C. In some embodiments, the first recesses 286 may also extend into the substrate 250. As shown in FIG. 28A, top surfaces of the STI regions 258 may be level with top surfaces of the substrate 250. In some embodiments, the substrate 250 may be etched such that bottom surfaces of the first recesses 286 are disposed below the top surfaces of the STI regions 258 or the like. The first recesses 286 may be formed by etching the nanostructures 255 and / or the substrate 250 using one or more anisotropic etching processes, such as RIE, NBE, or the like. The first spacers 281, the second spacers 283, and the masks 274 mask portions of the nanostructures 255 and the substrate 250 during the etching processes used to form the first recesses 286. A single etching process may be used to etch each layer of the multilayer stack 256. In some embodiments, multiple etching processes may be used to etch the layers of the multilayer stack. Timed etching processes may be used to stop etching the first recesses 286 after the first recesses 286 have reached a desired depth.In FIGS. 26A to 26C, portions of sidewalls of the first semiconductor layers 252A to 252C and the second semiconductor layers 254A to 254C of the multilayer stack 256 are etched to form sidewall recesses 288. For example, as shown in FIGS. 26B and 26C, respectively, sidewalls of the first semiconductor layers 252A to 252C in the region 250N formed of the first semiconductor materials and sidewalls of the second semiconductor layers 254A to 254C in the region 250P formed of the second semiconductor materials are etched to form the sidewall recesses 288. A mask, such as a photoresist, may be formed over the region 250P while sidewall recesses 288 are formed in the first semiconductor layers 252A- 252C in the region 250N. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the region 25 oN while sidewall recesses 288 are formed in the second semiconductor layers 254A- 254C in the region 250P. The mask may then be removed.Although sidewalls of the first semiconductor layers 252A to 252C and the second semiconductor layers 254A to 254C adjacent to the sidewall recesses 288 are illustrated in FIGS. 26B and 26C as being straight, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching, dry etching, or the like. The etchants used to etch the first semiconductor layers 252A- 252C may be selective to the first semiconductor materials such that the second semiconductor layers 254A- 254C and the substrate 250 remain relatively unetched compared to the first semiconductor layers 252A- 252C. Likewise, the etchants used to etch the second semiconductor layers 254A- 254C may be selective to the second semiconductor materials such that the first semiconductor layers 252A- 252C and the substrate 250 remain relatively unetched compared to the second semiconductor layers 254A- 254C.In FIGS. 27A to 27C, first internal spacers 290 are formed in the side wall recesses 288. The first interior spacers 290 may be formed by depositing an interior spacer layer (not separately shown) over the structures shown in FIGS. 26A-26C. The inner spacer layer may be deposited using a conformal deposition process, such as a CVD, an ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material such as low dielectric constant (low-k) materials having a k value less than about 3.5 may be used. The inner spacer layer may then be etched to form the first inner spacers 290. Although outer sides of the first inner spacers 290 are illustrated in FIGS. 27B and 27C, respectively, as being flush with sidewalls of the second semiconductor layers 254A- 254C and the first semiconductor layers 252A- 252C, respectively, the outer walls of the first inner spacers 290 may extend beyond or be recessed from sidewalls of the second semiconductor layers 254A- 254C and the first semiconductor layers 252A- 252C. Although the outer side walls of the first inner spacers 290 are illustrated as being straight in FIGS. 27B and 27C, the outer width walls of the first inner spacers 290 may be concave or convex. The inner spacer layer may be etched using an anisotropic etching process, such as RIE, NBE, or the like.The first internal spacers 290 may be used to prevent damage to subsequently formed source / drain regions (such as the epitaxial source / drain regions 292 discussed below with reference to FIGS. 28A-28D by subsequent etching processes. The first internal spacers 290 may also isolate subsequently formed gate electrodes (such as the gate electrodes 302) discussed below with reference to FIGS. 33A-33F ) from the subsequently formed epitaxial source / drain regions 292, which may prevent short circuits in the resulting NSFETs.In FIGS. 28A to 28D, epitaxial source / drain regions 292 are formed in the first recesses 286 to form stress on the second semiconductor layers 254A to 254C and the first semiconductor layers 252A to 252C of the nanostructures 255, thereby improving performance. As shown in FIGS. 28B and 28C, the epitaxial source / drain regions 292 are formed in the first recesses 286 such that each dummy gate 272 is disposed between respective adjacent pairs of the epitaxial source / drain regions 292. In some embodiments, the first spacers 281 are used to separate the epitaxial source / drain regions 292 from the dummy gates 272 by an appropriate lateral distance such that the epitaxial source / drain regions 292 do not short subsequently formed gates of the resulting NSFETs.The epitaxial source / drain regions 292 in the region 250N, e.g., the NMOS region, may be formed by masking the region 250P, e.g., the PMOS region. Then, the epitaxial source / drain regions 292 are epitaxially grown in the first recesses 286. The epitaxial source / drain regions 292 may include any suitable material suitable for n-type NSFETs, for example. For example, when the second semiconductor layers 254A- 254C are silicon, the epitaxial source / drain regions 292 may include materials that apply tensile stress to the second semiconductor layers 254A- 254C, such as silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphide, or the like. The epitaxial source / drain regions 292 may have surfaces raised from respective surfaces of the multilayer stack 256 and may have diamond surfaces.The epitaxial source / drain regions 292 in the region 250P, e.g., the PMOS region, may be formed by masking the region 250N, e.g., the NMOS region. Then, the epitaxial source / drain regions 292 are epitaxially grown in the first recesses 286. The epitaxial source / drain regions 292 may include any suitable material suitable for, e.g., p-NSFETs. For example, if the second semiconductor layers 254A- 254C are silicon germanium, the epitaxial source / drain regions 292 may include materials that exert compressive stress on the second half-later layers 254A- 254C, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 292 may also have surfaces raised from respective surfaces of the multilayer stack 256, and may have diamond surfaces.Dopants may be implanted into the epitaxial source / drain regions 292 to form source / drain regions, similar to the process discussed above for forming lightly doped source / drain regions followed by an anneal. The source / drain regions may have a concentration of impurities between about 1×10 19 atoms / cm 3 and about 1×10 21 atoms / cm 3. The n- and p-type impurities for source / drain regions may be any of the above-discussed impurities. In some embodiments, the epitaxial source / drain regions 292 may be in situ doped during growth.As a result of the epitaxial processes used to form the epitaxial source / drain regions 292 in the region 250N and the region 250P, top surfaces of the epitaxial source / drain regions 292 have diamond surfaces that extend laterally outward beyond sidewalls of the nanostructures 255. In some embodiments, these diamond surfaces cause adjacent epitaxial source / drain regions 292 of a same NSFET to coalesce, as illustrated by FIG. 28A. In some embodiments, adjacent epitaxial source / drain regions 292 remain separated after the epitaxial process is completed, as illustrated by FIG. 28D. In the embodiments illustrated in FIGS. 28A and 28D, the first spacers 281 may be formed to cover portions of the sidewalls of the nanostructures 255 and the substrate 250 that extend over the STI regions 258, thereby inhibiting epitaxial growth. In some embodiments, the spacers used to form the first spacers 281 may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region 258.In FIGS. 29A through 29C, a first interlayer dielectric (ILD) 296 is deposited over the structure shown in FIGS. 22A, 28B, and 28C, respectively (the processes of FIGS. 23A through 28D do not change the cross-section shown in FIG. 22A, which illustrates dummy gates 272 and multilayer stack 256 protected by dummy gates 272). The first ILD 296 may be formed of a dielectric material and may be deposited using any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed using any suitable process may be used. In some embodiments, a contact etch stop layer (CESL) 294 is disposed between the first ILD 296 and the epitaxial source / drain regions 292, the masks 274, and the first spacers 281. The CESL 294 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD 296.In FIGS. 30A to 30C, a planarization process such as CMP may be performed to level the top surface of the first ILD 296 with the top surfaces of the dummy gates 272 or the masks 274. The planarization process may also remove the masks 274 on the dummy gates 272 and portions of the first spacers 281 along sidewalls of the masks 274. After the planarization process, top surfaces of dummy gates 272, first spacers 281, and first ILD 296 are level. Accordingly, the top surfaces of the dummy gates 272 are exposed by the first ILD 296. In some embodiments, the masks 274 may remain, in which case the planarization process leveles the top surface of the first ILD 296 with a top surface of the masks 274 and the first spacers 281.In FIGS. 31A to 31C, the dummy gates 272 and the masks 274, if any, are removed in an etching step(s) so that second recesses 298 are formed. Portions of the dummy dielectric layers 260 in the second recesses 298 may also be removed. In some embodiments, the dummy gates 272 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process that uses a reaction gas(s) that selectively etch (etch) the dummy gates 272 at a faster rate than the first ILD 296 or the first spacers 281. Each second recess 298 exposes and / or overlies portions of the multilayer stack 256 that act as channel regions in subsequently completed NSFETs. Portions of the multilayer stack 256 that act as the channel regions are disposed between adjacent pairs of the epitaxial source / drain regions 292. During the removal, the dummy dielectric layers 260 may be used as etch stop layers when the dummy gates 272 are etched. The dummy dielectric layers 260 may then be removed after the removal of the dummy gates 272.FIGS. 31D and 31E show an embodiment in which the thinning process is performed to thin the nanostructures 255 after the dummy gate stacks are removed and not after the formation of the nanostructures 255 and before the formation of the STI regions 258 as discussed above with reference to FIG. 19B or after the formation of the STI regions 258 as discussed above with reference to FIG. 20B. In the embodiment illustrated in FIGS. 31D and 31E, nanostructures 255 in region 250N may be exposed to etchants used to thin nanostructures 255 in region 250P, and nanostructures 255 in region 250P may be exposed to etchants used to thin nanostructures 255 in region 250N.In the embodiment illustrated in FIGS. 31D and 31E, the nanostructures 255 in both the region 250N and the region 250P are exposed to the first etch chemicals and the second etch chemicals in processes similar to those described above with reference to FIG. 19B. After the first etching process, the second semiconductor layers 254A- 254C in the region 250N and the region 250P may have the same dimensions as the second semiconductor layers 254A- 254C discussed above with reference to FIG. 19B. After the second etching process, the first semiconductor layers 252A- 252C in the region 250N and the region 250P may have the same dimensions as the first semiconductor layers 252A- 252C discussed above with reference to FIG. 19B.As shown in FIG. 31E, thinning the nanostructures 255 may recess exposed portions of upper surfaces of the second semiconductor layers 254C between the second spacers 283. In FIG. 31E, recesses are formed in upper portions of the second semiconductor layer 254C. Depths of the recesses may be greatest at points between the second spacers 283. The depths of the recesses may become shallower near the second spacer 283. The second semiconductor layers 254C may be recessed to a depth D 4 of from about 5 nm to about 40 nm, from about 5 nm to about 15 nm, or from about 8 nm to about 12 nm below top surfaces of the second semiconductor layers 254C in both the region 250N and the region 250P.Forming the first semiconductor layers 252A- 252C having a gradient germanium concentration and thinning the first semiconductor layers 252A- 252C using an etching process having a higher etching rate with increasing germanium concentration results in the first semiconductor layers 252A- 252C having rectangular profiles and improves control of the process used to etch the first semiconductor layers 252A- 252C. Incorporating the first semiconductor layers 252A- 252C into NSFETs results in better gate control, reduced nanostructure width variation, and reduced DIBL.FIGS. 32A through 32D show an embodiment in which the fins 55 are not thinned after the dummy gate stacks are removed. In FIGS. 32A to 32D, the first semiconductor layers 252A to 252C are removed from the region 250N, and the second semiconductor layers 254A to 254C are removed from the region 250P, thereby extending the second recesses 98. A mask, such as a photoresist, may be formed over the region 250P while the first semiconductor layers 252A- 252C are removed from the region 250N. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the region 250N while the second semiconductor layers 254A- 254C are removed from the region 250P. The mask may then be removed.The layers of the multilayer stack 256 may be removed using isotropic etching processes, such as wet etching or the like. Etchants used to remove the first semiconductor layers 252A- 252C may be selective to materials of the second semiconductor layers 254A- 254C, while etchants used to etch the second semiconductor layers 254A- 524C may be selective to materials of the second semiconductor layers 252A- 252C. In an embodiment where the first semiconductor layers 252A- 252C include the first semiconductor material (e.g., SiGe or the like) and the second semiconductor layers 254A- 254C include the second semiconductor material (e.g., Si, SiC or the like), tetramethylammonium hydroxide (TMAH), ammonia water (NH 4 OH), or the like may be used to remove layers of the multilayer stack 256 in the regions 250N, and a diluted ammonia water hydrogen peroxide mixture (APM), sulfuric acid hydrogen peroxide mixture (SPM), or the like may be used to remove layers of the multilayer stack 256 in the region 250P. A plasma such as a plasma formed of hydrogen gas (H 2) or the like may be used to remove the first semiconductor layers 252A to 252C. A solution including hydrofluoric acid (HF) and hydrogen peroxide (H 2 O 2) a solution including hydrofluoric acid, nitric acid (HNO 3) and water (H 2 O), or the like may be used to remove the second semiconductor layers 254A to 254C.In FIGS. 33A to 33D, gate dielectric layers 300 and gate electrodes 302 for replacement gates are formed. FIG. 33E shows a detailed view of the region 303 of FIG. 33A and FIG. 33F shows a detailed view of the region 303 of FIG. 33B. In region 250N illustrated in FIGS. 33A and 33B, gate dielectric layers 300 are conformally deposited in second recesses 298, such as on top surfaces of STI regions 258, on top surfaces of substrate 250, and on top surfaces, sidewalls, and bottom surfaces of second semiconductor layers 254A- 254C. In region 250P illustrated in FIGS. 33C and 33D, gate dielectric layers 300 are conformally deposited in second recesses 298, such as on top surfaces of STI regions 258 and on top surfaces, sidewalls, and bottom surfaces of first semiconductor layers 252A- 252C.In accordance with some embodiments, the gate dielectric layers 300 include silicon oxide, silicon nitride, or multi-layers thereof. In some embodiments, the gate dielectric layers 300 comprise a high-k dielectric material, and in these embodiments, the gate dielectric layers 300 may have a k value greater than about 7.0, and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The methods of forming the gate dielectric layers 300 may include molecular beam deposition (MBD), ALD, PECVD, or the like. In embodiments in which portions of the dummy dielectric layers 260 remain in the second recesses 298, the gate dielectric layers 300 comprise a material of the dummy dielectric layers 260 (e.g., SiO 2).The gate electrodes 302 are respectively deposited over the gate dielectric layers 300 and fill the remaining portions of the second recesses 298. The gate electrodes 302 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although a single layer gate electrode 302 is illustrated in FIGS. 33A to 33D, the gate electrode 302 may include any number of liner layers 302A, any number of work function adjustment layers 302B, and a fill material 302C, as illustrated by FIGS. 33E and 33F. After filling the second recesses 298, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers 300 and the material of the gate electrodes 302, the excess portions being over the top surface of the first ILD 296. The remaining portions of material of the gate electrodes 302 and the gate dielectric layers 300 thus form replacement gates of the resulting NSFETs. The gate electrodes 302 and the gate dielectric layers 300 may collectively be referred to as "gate stacks". The gate and gate stacks may extend along sidewalls of the channel regions 268 of the nanostructures 255.The formation of the gate dielectric layers 300 in the region 25 oN and the region 250P may occur simultaneously such that the gate dielectric layers 300 in each region are formed of the same materials, and the formation of the gate electrodes 302 may occur simultaneously such that the gate electrodes 302 in each region are formed of the same materials. In some embodiments, the gate dielectric layers 300 may be formed in each region using different processes such that the gate dielectric layers 300 may be different materials, and / or the gate electrodes 302 may be formed in each region using different processes such that the gate electrodes 302 may be different materials. Different masking steps may be used to mask and expose appropriate regions when different processes are used.In FIGS. 34A and 34B, a second ILD 306 is deposited over the first ILD 296. In some embodiments, the second ILD 306 is a flowable film formed using an FCVD. In some embodiments, the second ILD 306 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and may be deposited using any suitable method, such as CVD, PECVD, or the like. In some embodiments, prior to forming the second ILD 306, the gate stack (including the gate dielectric layers 300 and the corresponding overlying gate electrodes 302) is recessed such that a recess is formed directly over the gate stack and between opposing portions of the first spacers 281. A gate mask 304 comprising one or more layers of a dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled into the recess, followed by a planarization process to remove excess portions of the dielectric material that extend over the first ILD 296. Subsequently formed gate contacts 110 (such as the gate contacts 312 discussed below with reference to FIGS. 35A and 35B ) penetrate through the gate mask 304 to contact the top surface of the recessed gate electrodes 302.In FIGS. 35A and 35B, gate contacts 312 and source / drain contacts 314 are formed by the second ILD 306 and the first ILD 296. Openings for the source / drain contacts 314 are formed through the first ILD 296 and the second ILD 306, and openings for the gate contacts 312 are formed through the second ILD 306 and the gate mask 304. The openings may be formed using suitable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesive layer, or the like and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the first ILD 306. The remaining liner and conductive material form the source / drain contacts 314 and the gate contacts 312 in the openings. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain regions 292 and the source / drain contacts 314. The source / drain contacts 314 are physically and electrically coupled to the epitaxial source / drain regions 292, and the gate contacts 312 are physically and electrically coupled to the gate electrodes 302. The source / drain contacts 314 and the gate contacts 312 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source / drain contacts 314 and the gate contacts 312 may be formed in different cross-sections, which may avoid shorting the contacts.FIGS. 35C and 35D show the structures of FIGS. 35A and 35B in embodiments where the nanostructures 255 are thinned at different stages. FIG. 35C illustrates the embodiment of FIG. 19B where nanostructures 255 are thinned prior to forming the STI regions 258. Portions of the nanostructures 255 in the region 250N formed over top surfaces of the STI regions 258 (e.g., portions of the nanostructures 255 formed in the second semiconductor layers 254A- 254C) and portions of the nanostructures 255 formed under the top surfaces of the STI regions 258 (e.g., portions of the nanostructures 255 formed in the substrate 250) may have sidewalls inclined at the same angles with respect to a main surface of the substrate 250. Portions of nanostructures 255 in region 250P formed above and below upper surfaces of STI regions 258 may include sidewalls inclined at different angles with respect to a main surface of substrate 250. For example, as shown in FIG. 35C, sidewalls of the portion of nanostructures 255 formed from first semiconductor layers 252A- 252C in region 250P above the top surfaces of STI regions 258 may be more vertical than sidewalls of the portion of nanostructures 255 formed in substrate 250 in region 250P below the top surfaces of STI regions 258.FIG. 35D illustrates the embodiment of FIG. 20B or 31D and 31E, where the nanostructures 255 are thinned after the formation of the STI regions 258 or after the removal of the dummy gate stacks. Portions of the nanostructures 255 in the region 50N formed above and below upper surfaces of the STI regions 258 may include sidewalls inclined at different angles with respect to a main surface of the substrate 250. For example, sidewalls of the portions of nanostructures 255 in region 50N formed below the top surfaces of STI regions 258 and formed in substrate 250 may be more vertical than sidewalls of the portions of nanostructures 255 in region 50N formed above the top surfaces of STI regions 258 and formed in second semiconductor layers 254A- 254C.Portions of the nanostructures 255 in the region 250P formed above and below the top surfaces of the STI regions 258 may include side walls inclined at different angles with respect to a main surface of the substrate 250 and having a step difference of widths. For example, as shown in FIG. 35D, sidewalls of the portions of nanostructures 255 in region 250P formed above the top surfaces of STI regions 258 (e.g., portions of nanostructures 255 formed in first semiconductor layers 252A- 252C) may be more vertical than sidewalls of the portions of nanostructures 255 in region 50P formed below the top surfaces of STI regions 258 (e.g., portions of nanostructures 255 formed in substrate 250). Further, there may be a step difference between widths of the portions of the nanostructures 255 formed below the top surfaces of the STI regions 258 and the portions of the nanostructures 255 formed above the top surfaces of the STI regions 258, where the portions of the nanostructures 255 formed below the top surfaces of the STI regions 258 have greater widths than widths of the portions of the nanostructures 255 formed above the top surfaces of the STI regions 258.As discussed above, forming the first semiconductor layers 252A- 252C having a gradient germanium concentration and thinning the first semiconductor layers 252A- 252C using an etching process having a higher etch rate with increasing germanium concentration results in the first semiconductor layers 252A- 252C having rectangular profiles and improves control of the process used to etch the nanostructures 255 in the region 250N and the region 250P. The first semiconductor layers 252A- 252C are then used as channel regions in the region 250P. Including channel regions formed of the first semiconductor layers 252A- 252C in NSFETs results in better gate control, reduced nanostructure width variation, and reduced DIBL.The invention is defined by the main claim and the subordinate claims. The dependent claims represent further embodiments of the invention.

Claims

A method comprising: forming a semiconductor substrate (50) including epitaxial silicon germanium in a first region (50P) of the semiconductor substrate and silicon in a second region (50N) of the semiconductor substrate, wherein forming the semiconductor substrate comprises: providing a silicon substrate, forming an opening in the silicon substrate, and forming the epitaxial silicon germanium in the opening, wherein a ratio of an atomic percentage of germanium at an upper surface of the epitaxial silicon germanium to an atomic percentage of germanium at a lower surface of the epitaxial silicon germanium is in the range of about 1:2 to about 1:8; forming a first semiconductor fin (55) in the first region of the semiconductor substrate (50), and forming a second semiconductor fin (55) in the second region of the semiconductor substrate, wherein: a germanium concentration of a first portion of the first semiconductor fin (55) is greater than a germanium concentration of a second portion of the first semiconductor fin, a first distance between the first portion of the first semiconductor fin (55) and a main surface of the semiconductor substrate (50) is less than a second distance between the second portion of the first semiconductor fin (55) and the main surface of the semiconductor substrate; and the method further comprises: trimming the first semiconductor fin (55), wherein: the first portion of the first semiconductor fin is trimmed at a greater rate than the second portion of the first semiconductor fin, and after trimming the first semiconductor fin (55), a first angle between a sidewall of the first semiconductor fin and a main surface of the semiconductor substrate (50) is closer to the perpendicular than a second angle between a sidewall of the second semiconductor fin (55) and the main surface of the semiconductor substrate.The method of claim 1, wherein a third angle between a sidewall of the first semiconductor fin (55) and the main surface of the semiconductor substrate (50) before trimming the first semiconductor fin is different from the first angle between the sidewall of the first semiconductor fin and the main surface of the semiconductor substrate after trimming the first semiconductor fin.The method of claim 1 or 2, wherein a ratio of a trim rate of the first portion of the first semiconductor fin (55) to a trim rate of the second portion of the first semiconductor fin is greater than 1 and less than or equal to 3.The method of any preceding claim, wherein trimming the first semiconductor fin (55) comprises exposing the first semiconductor fin to an oxidizing agent.The method of any one of claims 1 to 3, wherein trimming the first semiconductor fin (55) comprises exposing the first semiconductor fin to an oxidizing agent and then exposing the first semiconductor fin to a base or an acid in a cyclic process.The method of any preceding claim, further comprising forming a shallow trench isolation region (58) surrounding at least a third portion of the first semiconductor fin (55), the first semiconductor fin trimmed after forming the shallow trench isolation region.The method of any of claims 1 to 5, further comprising forming a shallow trench isolation region (58) surrounding at least a third portion of the first semiconductor fin (55), wherein the first semiconductor fin is trimmed prior to forming the shallow trench isolation region.The method of any of claims 1 to 5, further comprising: forming a dummy gate over the first semiconductor fin (55); and removing the dummy gate to expose the first semiconductor fin (55), wherein the first semiconductor fin is trimmed after removing the dummy gate.A semiconductor device, comprising: a semiconductor substrate (50); a first semiconductor fin (55) over the semiconductor substrate (50), the first semiconductor fin comprising silicon germanium, wherein a germanium concentration of the first semiconductor fin decreases with increasing distance from the semiconductor substrate; a second semiconductor fin (55) over the semiconductor substrate (50), the second semiconductor fin comprising silicon, wherein a first angle between a sidewall of the first semiconductor fin (55) and a main surface of the semiconductor substrate is closer to the perpendicular than a second angle between a sidewall of the second semiconductor fin and the main surface of the semiconductor substrate; a gate stack (100, 102) over the first semiconductor fin (55); and a source / drain region (92) at least partially within the first semiconductor fin (55) adjacent to the gate stack (100, 102); wherein a ratio of an atomic percentage of germanium in a first portion of the first semiconductor fin (55) to an atomic percentage of germanium in a second portion of the first semiconductor fin is from 1:2 to 1:8.The semiconductor device of claim 9, wherein the first angle is 85° to 95°.The semiconductor device according to claim 9 or 10, wherein the second angle is from 70° to 85° or from 95° to 120°.The semiconductor device of any of claims 9 to 11, wherein the first portion has a first width, wherein the second portion has a second width, and wherein the second width is less than 1 nm greater than the first width.The semiconductor device of any of claims 9 to 12, further comprising a shallow trench isolation region (58) surrounding a third portion of the first semiconductor fin (55), wherein a ratio of an uppermost width of a fourth portion of the first semiconductor fin extending over the shallow trench isolation region to a lowermost width of the fourth portion of the first semiconductor fin (55) is from 0.8 to 1.2.The semiconductor device according to claim 13, wherein the ratio of the uppermost width of the fourth portion of the first semiconductor fin to the lowermost width of the fourth portion of the first semiconductor fin (55) is from 0.9 to 1.1.The semiconductor device according to any one of claims 9 to 12, further comprising a shallow trench isolation region (58) surrounding a third portion of the first semiconductor fin (55), the first semiconductor fin having a step change in width at an upper surface of the shallow trench isolation region.The semiconductor device according to any one of claims 13 to 15, wherein the first semiconductor fin (55) has first straight side walls above the upper surface of the shallow trench isolation region (58) and second straight side walls below the upper surface of the shallow trench isolation region, wherein a third angle between the first straight side walls and the main surface of the semiconductor substrate (50) is closer to the perpendicular than a fourth angle between the second straight side walls and the main surface of the semiconductor substrate.A semiconductor device, comprising: a first channel region (252A) over a semiconductor substrate (250), the first channel region comprising silicon germanium, the first channel region having a first width; a second channel region (252B) over the first channel region (252A), the second channel region comprising silicon germanium, the second channel region having a lower germanium concentration than the first channel region, the second channel region having a second width; a third channel region (254A) over the semiconductor substrate (250), the third channel region comprising silicon, the third channel region having a third width; a fourth channel region (254B) over the third channel region (254A), the fourth channel region comprising silicon, the fourth channel region having a fourth width, a difference between the first width and the second width being less than a difference between the third width and the fourth width; and a gate stack (300, 302) surrounding the first channel region (252A) and the second channel region (252B), wherein the first channel region (252A) and the second channel region (252B) are channel regions of a first field effect transistor and the third channel region (254A) and the fourth channel region (254B) are channel regions of a further field effect transistor, and the first and the further field effect transistors are nanofoil, nanowire or gate-all-around field effect transistors; and wherein a ratio of an atomic percentage of germanium at an upper surface of the first channel region (252A) to an atomic percentage of germanium at a lower surface of the first channel region is in a range from about 1:2 to about 1:3, and a ratio of an atomic percentage of germanium at an upper surface of the second channel region (252B) to an atomic percentage of germanium at a lower surface of the second channel region is also in the range from about 1:2 to about 1:3.The semiconductor device of claim 17, wherein the first channel region (252A) has a gradient germanium concentration that decreases as the distance from the semiconductor substrate (250) increases, and wherein the second channel region (252B) has a gradient germanium concentration that decreases as the distance from the semiconductor substrate increases.The semiconductor device according to claim 17 or 18, wherein a ratio of the second width to the first width is from 0.9 to 1.1.The semiconductor device according to claim 17 or 18, wherein a ratio of the fourth width to the third width is greater than or equal to 0.64 and less than 1.0.

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