Multiple trench Schottky diode

Abstract

Multiple trench Schottky diode, featuring: a semiconductor substrate (1); a back metal layer (2) arranged on one side of the semiconductor substrate (1); an epitaxial layer (3) arranged on one side of the semiconductor substrate (1) opposite the back metal layer (2) and comprising a cell region (3a) and a termination region (3b), wherein the epitaxial layer (3) comprises: a termination trench structure (32) located at the junction of the cell area (3a) and the termination area (3b); a first trench structure (33) located in the termination area (3b) and spaced apart from the termination trench structure (32), wherein the first trench structure (33) has a first width (w1); a second trench structure (34) located in the termination area (3b) and spaced apart from the first trench structure (33), wherein the second trench structure (34) has a second width (w2) that is smaller than the first width (w1); and a third trench structure (35) located in the termination area (3b) and spaced apart from the second trench structure (34), wherein the third trench structure (35) has a third width (w3) which is smaller than the second width (w2); a dielectric interlayer (4) located in the termination region (3b) and stacked on the termination trench structure (32), the first trench structure (33), the second trench structure (34) and the third trench structure (35), wherein a first dielectric interlayer trench is formed in the region of the first trench structure (33), a second dielectric interlayer trench is formed in the region of the second trench structure (34) and a third dielectric interlayer trench is formed in the region of the third trench structure (35); a first metal layer (5) located in the cell region (3a) and stacked on the termination trench structure (32), wherein the first metal layer (5) extends from the cell region (3a) to the interface between the second trench structure (34) and the third trench structure (35), and wherein a first metal layer trench is formed in the region of the first dielectric interlayer trench and a second metal layer trench is formed in the region of the second dielectric interlayer trench; a passivation layer (6) which is partially located in the cell region (3a) and is stacked on the first metal layer (5), wherein the passivation layer (6) which extends to the termination region (3b) is located on the first metal layer (5) and in the third dielectric-interlayer trench, and wherein a first passivation layer trench is formed in the region of the first metal layer (5), a second passivation layer trench is formed in the region of the second metal layer trench, and a third passivation layer trench is formed in the region of the third dielectric-interlayer trench; and a second metal layer (7) located in the cell area (3a) and lying on the first metal layer (5) and the passivation layer (6), the second metal layer (7) extending to the termination area (3b) and partially lying on the first passivation layer trench.

Description

[0001] The invention relates to a Schottky diode, in particular a multiple trench Schottky diode.

[0002] From US 2020 / 0127145A1, a multi-trench Schottky diode is known, comprising: a semiconductor substrate; a backplate metal layer arranged on one side of the semiconductor substrate; an epitaxial layer arranged on one side of the semiconductor substrate opposite the backplate metal layer, comprising a cell region and a termination region; and wherein the epitaxial layer comprises: a termination trench structure arranged at the junction of the cell region and the termination region; a first trench structure located in the termination region and spaced apart from the termination trench structure, the first having a first width; a second trench structure located in the termination region and spaced apart from the first trench structure, the second having a second width that is smaller than the first width; and a third trench structure.a dielectric intermediate layer, a metal layer, and a passivation layer.

[0003] Further embodiments of a multi-trench Schottky diode are known from DE 10 2014 115 174 A1 and US 2013 / 0 270 668 A1.

[0004] An ideal rectifier typically exhibits characteristics such as low forward voltage drop, high reverse breakdown voltage, and zero leakage current. Schottky diodes, which utilize metal-semiconductor junctions as Schottky barriers, possess the characteristics of low forward voltage drop and high-speed switching. Therefore, they are widely used in power rectifier devices. However, Schottky diodes still suffer from the drawbacks of low reverse voltage and high reverse leakage current, which limits their application.

[0005] Schottky diodes can be divided into conventional planar Schottky diodes and trench Schottky diodes. Planar Schottky diodes are primarily formed by layering semiconductors and metals, resulting in a stacked structure that often necessitates trade-offs between forward voltage drop and leakage current. Therefore, increasing the breakdown voltage without increasing the leakage current is a major area of ​​research.

[0006] Trench Schottky diodes are primarily filled with polysilicon after trenches have been etched into the silicon crystal layer. This allows the polysilicon in the trenches to effectively dissipate drift electrons in the drift region, thus distributing the electric field evenly. Therefore, trench Schottky diodes exhibit a lower forward voltage drop (low VF) and a lower reverse leakage current (low IR) than conventional planar Schottky diodes.

[0007] As inFig. As shown in Figure 1, a Trench Schottky diode PA100 has a semiconductor substrate PA1, a back metal layer PA2, an epitaxial layer PA3, a dielectric layer PA4, a first metal layer PA5, a passivation layer PA6 and a second metal layer PA7.

[0008] The back metal layer PA2 is formed on the back side of the semiconductor substrate PA1. The epitaxial layer PA3 is formed on the front side of the semiconductor substrate PA1 and has a cell region PA3a and a termination region PA3b, both adjacent to each other. The epitaxial layer PA3 further comprises several cell structures PA31, of which only two are shown in the drawing, a termination trench structure PA32, and a guard ring structure PA33. The cell structures PA31 are spaced apart from each other within cell region PA3a, with the termination trench structure PA32 located at the junction of cell region PA3a and termination region PA3b and positioned at a distance from the cell structures PA31 adjacent to termination region PA3b. The guard ring structure PA33 is adjacent to the termination trench structure PA32.

[0009] The dielectric layer PA4 is located in the termination region PA3b and rests on the termination trench structure PA32 and the protective ring structure PA33. The first metal layer PA5 is located in the cell region PA3a and rests on the epitaxial layer PA3. Furthermore, the first metal layer PA5 extends into the termination region PA3b and rests on the dielectric layer PA4. The passivation layer PA6 lies on the first metal layer PA5 and extends from the cell region PA3a to the dielectric layer PA4 in the termination region PA3b. The second metal layer PA7 lies on the first metal layer PA5 and the passivation layer PA6 and extends from the cell region PA3a into the termination region PA3b.

[0010] In the conventional trench Schottky diode PA100, the first metal layer PA5 and the second metal layer PA7 extend into the termination region PA3b to increase the reverse voltage. Additionally, the epitaxial layer PA3 is equipped with the guard ring structure PA33 to disperse the potential. However, due to the limited potential buffer capacity of the guard ring structure PA33, the charge of the trench Schottky diode PA100 is still slightly concentrated in the edge termination region and is prone to premature failure.

[0011] The invention is based on the objective of avoiding the aforementioned defects and creating a multi-trench Schottky diode that can reduce the accumulation of surface charge through structural changes and avoid premature breakdown.

[0012] This problem is solved according to the invention by a multiple trench Schottky diode having the features specified in claim 1. Further advantageous embodiments of the invention will become apparent from the features of the dependent claims.

[0013] The invention provides a multiple trench Schottky diode which has the following features: a semiconductor substrate; a back metal layer that is arranged on one side of the semiconductor substrate; an epitaxial layer located on one side of the semiconductor substrate opposite the back metal layer and comprising a cell region and a termination region, wherein the epitaxial layer comprises the following: a termination trench structure located at the junction of the cell area and the termination area; a first trench structure located in the termination area and spaced apart from the termination trench structure, wherein the first trench structure has a first width; a second trench structure located in the termination area and spaced apart from the first trench structure, the second trench structure having a second width that is smaller than the first width; and a third trench structure located in the termination area and spaced apart from the second trench structure, wherein the third trench structure has a third width that is smaller than the second width; a dielectric interlayer located in the termination region and stacked on the termination trench structure, the first trench structure, the second trench structure and the third trench structure, wherein a first dielectric interlayer trench is formed in the region of the first trench structure, a second dielectric interlayer trench in the region of the second trench structure and a third dielectric interlayer trench in the region of the third trench structure; a first metal layer located in the cell region and stacked on the termination trench structure, wherein the first metal layer extends from the cell region to the interface between the second trench structure and the third trench structure, and wherein a first metal layer trench is formed in the region of the first dielectric interlayer trench and a second metal layer trench is formed in the region of the second dielectric interlayer trench; a passivation layer that is partially located in the cell region and stacked on the first metal layer, wherein the passivation layer extending to the termination region is located on the first metal layer and in the third dielectric interlayer pit, and wherein a first passivation layer pit is formed in the region of the first metal layer, a second passivation layer pit in the region of the second metal layer pit, and a third passivation layer pit in the region of the third dielectric interlayer pit; and a second metal layer located in the cell area and lying on top of the first metal layer and the passivation layer, with the second metal layer extending to the termination area and partially lying on top of the first passivation layer trench.

[0014] According to the invention, the ratio of the first width, the second width and the third width is 7:5:3.

[0015] According to the invention, the dielectric intermediate layer comprises a tetraethyl orthosilicate film [TEOS] and a borophosphosilicate glass film [BPSG], wherein the tetraethyl orthosilicate film is located in the termination region and lies on the epitaxial layer, and wherein the borophosphosilicate glass film is located in the termination region and lies on the tetraethyl orthosilicate film.

[0016] According to the invention, the epitaxial layer is further provided with a plurality of cell trench structures, each of which has the following features: a gate oxide layer that forms within the cell; and a low-doped polysilicon layer formed in a trench bounded by the gate oxide layer.

[0017] According to the invention, the termination trench structure further comprises the following: a gate oxide layer that is formed in the cell area and the terminal area; and a low-doped polysilicon layer formed in a trench bounded by the gate oxide layer.

[0018] According to the invention, the first metal layer comprises a nickel-platinum alloy layer which is stacked on the epitaxial layer and is in electrical contact with the low-doped polysilicon layer.

[0019] According to the invention, the first metal layer further comprises a titanium metal layer, a titanium-tungsten alloy layer and an aluminum metal layer, wherein the titanium metal layer is stacked on the nickel-platinum alloy layer and the dielectric intermediate layer and extends from the cell region to the interface between the second trench structure and the third trench structure in the termination region, and wherein the titanium-tungsten alloy layer is stacked on the titanium metal layer, and wherein the aluminum metal layer is stacked on the titanium-tungsten alloy layer.

[0020] According to the invention, the second metal layer comprises a titanium metal layer, a nickel metal layer, and a silver metal layer, wherein the titanium metal layer is stacked on the first metal layer and the passivation layer, and wherein the titanium metal layer extends from the cell region into the termination region and is partially stacked on the passivation layer grave, and wherein the nickel metal layer is stacked on the titanium metal layer, and wherein the silver metal layer is stacked on the nickel metal layer.

[0021] According to the invention, the epitaxial layer is further provided with a plurality of cell trench structures located in the cell area.

[0022] In summary, the multi-trench Schottky diode according to the invention is provided in the termination region with the first, second, and third trench structures, wherein the first metal layer extends to the interface between the second and third trench structures, thereby effectively dispersing the electric field in the termination region and preventing excessive concentration of the electric field on the surface of the termination region. By gradually reducing the widths of the first, second, and third trench structures, the potential of the termination region can be effectively increased, thereby effectively preventing premature breakdown voltage.

[0023] The invention and its embodiments are explained in more detail below with reference to the drawing. The drawing shows: Fig. 1 a section through a conventional Trench Schottky diode; Fig. 2 a section through a preferred embodiment of a multiple trench Schottky diode according to the invention; Fig. 3 a schematic diagram of the potential distribution curve of the multiple trench Schottky diode according to the invention; and Fig. 4 a schematic diagram of the potential curve of the multiple trench Schottky diode according to the invention.

[0024] As from the Fig. As can be seen in Figure 2, a multi-trench Schottky diode according to the invention comprises a semiconductor substrate 1, a back metal layer 2, an epitaxial layer 3, a dielectric interlayer 4 [ILD, abbreviation for inter layer dielectric] and a first metal layer 5, a passivation layer 6 and a second metal layer 7.

[0025] The semiconductor substrate 1 has a back side 11 and a front side 12, which are arranged oppositely. The semiconductor substrate 1 is a heavily N-doped silicon crystal layer. The back metal layer 2 is formed on the back side 11 of the semiconductor substrate 1. The epitaxial layer 3 is formed on the front side 12 of the semiconductor substrate 1 and is provided with a cell region 3a and a termination region 3b. The epitaxial layer 3 is a lightly N-doped silicon crystal layer. The light doping of the epitaxial layer 3 refers to the heavy doping of the semiconductor substrate 1. The epitaxial layer 3 has several cell trench structures 31 [however, only one of them is labeled in the drawing] and a termination trench structure 32, a first trench structure 33, a second trench structure 34, and a third trench structure 35.

[0026] The cell trench structures 31 are spaced apart from one another in cell region 3a. Each cell trench structure 31 has a gate oxide layer 311 and a low-doped polysilicon layer 312. The low-doped polysilicon layer 312 is filled into a trench bounded by the gate oxide layer 311. The termination trench structure 32 is located at the junction of cell region 3a and the termination region 3b. That is, the termination trench structure 32 is located between cell region 3a and the termination region 3b. In the illustrated embodiment, the termination trench structure 32 further comprises a gate oxide layer 321 and two low-doped polysilicon layers 322. In the drawing, only one of the polysilicon layers 322 is labeled. The gate oxide layer 321 is located between cell region 3a and the termination region 3b. The two low-doped polysilicon layers 322 are formed on both sides of the gate oxide layer 321.In practice, the gate oxide layer 321 and the low-doped polysilicon layers 322 are formed by first creating a trench on the surface of the epitaxial layer 3 and then oxidizing the inner wall of the trench to form the gate oxide layer 321. The polysilicon is then filled into the trench, resulting in the two polysilicon layers 322. Subsequently, the two low-doped polysilicon layers 322 are formed on either side of the gate oxide layer 321.

[0027] The first trench structure 33 is located in termination region 3b and is spaced apart from the termination trench structure 32. The first trench structure 33 has a first width w1. The first trench structure 33 comprises a gate oxide layer 331 and two low-doped polysilicon layers 332. In the drawing, only one of the low-doped polysilicon layers 332 is labeled. The gate oxide layer 331 is located in termination region 3b, with the two low-doped polysilicon layers 332 arranged on either side of the gate oxide layer 331. The second trench structure 34 is located in termination region 3b and is spaced apart from the first trench structure 33. The second trench structure 34 has a second width w2, which is smaller than the first width w1. The second trench structure 34 comprises a gate oxide layer 341 and two low-doped polysilicon layers 342.In the drawing, only one of the low-doped polysilicon layers 342 is labeled. The gate oxide layer 341 is located in the termination region 3b, with the two low-doped polysilicon layers 342 arranged on either side of the gate oxide layer 341. The third trench structure 35 is located in the termination region 3b and is spaced apart from the second trench structure 34. The third trench structure 35 has a third width that is smaller than the second width w2. The third trench structure 35 comprises a gate oxide layer 351 and two low-doped polysilicon layers 352. In the drawing, only one of the low-doped polysilicon layers 352 is labeled. The gate oxide layer 351 is located in the termination region 3b, with the two low-doped polysilicon layers 352 arranged on either side of the gate oxide layer 351.

[0028] The ratio of the first width w1, the second width w2, and the third width w3 is 7:5:3. In this embodiment, the first width w1 is, for example, 14 µm, the second width w2 is 10 µm, and the third width is 6 µm. The distance between the first trench structure 33 and the second trench structure 34 is 2.8 µm, and the distance between the second trench structure 34 and the third trench structure 35 is also 2.8 µm.

[0029] The dielectric interlayer 4 comprises a tetraethyl orthosilicate film 41 [TEOS] and a borophosphosilicate glass film 42 [BPSG]. The tetraethyl orthosilicate film 41 is located in the termination region 3b and lies on the termination trench structure 32, the first trench structure 33, the second trench structure 34, and the third trench structure 35 of the epitaxial layer 3. The tetraethyl orthosilicate film 41 is provided with a first tetraethyl orthosilicate trench [unlabeled] in the region of the first trench structure 33, with a second tetraethyl orthosilicate trench [unlabeled] in the region of the second trench structure 34, and with a third tetraethyl orthosilicate trench [unlabeled] in the region of the third trench structure 35. The borophosphosilicate glass film 42 is located in the termination area 3b and lies on the first, second and third tetraethyl orthosilicate pit of the tetraethyl orthosilicate film 41.The borophosphosilicate glass film 42 is provided in the area of ​​the first trench structure 33 with a first dielectric interlayer trench [not labelled], in the area of ​​the second trench structure 34 with a second dielectric interlayer trench [not labelled], in the area of ​​the third trench structure 35 with a third dielectric interlayer trench [not labelled].

[0030] The first metal layer 5 comprises a nickel-platinum alloy layer 51, a titanium metal layer 52, a titanium-tungsten alloy layer 53, and an aluminum metal layer 54. The nickel-platinum alloy layer 51 is located in cell region 3a, lies on the epitaxial layer 3, and is in electrical contact with the lightly doped polysilicon layers 322. The titanium metal layer 52 lies on the nickel-platinum alloy layer 51 and the borophosphosilicate glass film 42 of the dielectric interlayer 4 and extends from cell region 3a to the interface between the second trench structure 34 and the third trench structure 35 in the termination region 3b. Furthermore, a first and a second titanium metal layer trench [not labeled] of the titanium metal layer 52 are formed in the region of the first and second dielectric interlayer trenches, respectively.The titanium-tungsten alloy layer 53 lies on the titanium metal layer 52 and extends from cell region 3a to the boundary between the second trench structure 34 and the third trench structure 35 in the terminal region 3b. Furthermore, a first and a second titanium-tungsten alloy layer trench [not labeled] of the titanium-tungsten alloy layer 53 are formed in the region of the first and second titanium metal layer trenches, respectively. The aluminum metal layer 54 lies on the titanium-tungsten alloy layer 53 and extends from cell region 3a to the boundary between the second trench structure 34 and the third trench structure 35 in the terminal region 3b. Furthermore, a first and a second aluminum metal layer trench [not labeled] of the aluminum metal layer 54 are formed in the region of the first and second titanium-tungsten alloy layer trenches, respectively.

[0031] The passivation layer 6, which is partially located in cell region 3a, lies on the aluminum metal layer 54 of the first metal layer 5. The passivation layer 6 extends from cell region 3a to the termination region 3b and is stacked on the first metal layer 5 and in the third dielectric interlayer pit. Furthermore, a first, a second, and a third metal layer pit [not labeled] of the passivation layer 6 are formed in the region of the first, the second metal layer pit, and the third dielectric interlayer pit, respectively. In the illustrated embodiment, the passivation layer 6 is a silicon nitride layer.

[0032] The second metal layer 7 comprises a titanium metal layer 71, a nickel metal layer 72, and a silver metal layer 73. The titanium metal layer 71, located in cell region 3a, is stacked on the aluminum metal layer 54 of the first metal layer 5 and the passivation layer 6. The titanium metal layer 71 extends from cell region 3a into the end region 3b and is partially stacked on the passivation layer trench. The nickel metal layer 72, located in cell region 3a, is stacked on the titanium metal layer 71. The nickel metal layer 72 extends from cell region 3a to the first passivation layer trench in end region 3b and lies on top of the titanium metal layer 71. The silver metal layer 73, located in cell region 3a, is stacked on the nickel metal layer 72.The silver metal layer 73 extends from cell area 3a to the first passivation layer trench in the final area 3b and lies on the nickel metal layer 72.

[0033] The curve C1 in Fig. 3 is in relation to the distribution of the electric field of the in Fig. Figure 1 shows the conventional Trench Schottky diode PA100, with curve C2 in Fig. 3 with regard to the distribution of the electric field of the in Fig. The multi-trench Schottky diode according to the invention is shown in Figure 2. The higher electric field of curve C1 at 0 to 10 µm is due to the cell structures PA31 located in cell region PA3a. However, since the first metal layer PA5 extends to the termination region PA3b, charges are concentrated at the edge of the first metal layer PA5, which again increases the electric field of curve C1 at the measurement position of approximately 25 µm. Compared to the conventional trench Schottky diode, the first metal layer 5 of the multi-trench Schottky diode 100 according to the invention extends to the boundary between the second trench structure 34 and the third trench structure 35 in termination region 3b.Since the first and second metal layer trenches of the first metal layer 5 are formed in the region of the first trench structure 33 and the second trench structure 34, respectively, the electric field of the multiple trench Schottky diode 100 according to the invention can be reduced from 10 to 14 µm at the measuring position corresponding to the first metal layer trench and from 26 to 30 µm at the measuring position corresponding to the second metal layer trench, so that the electric field of the entire termination region 3b is dispersed without excessive concentration. Because the electric field in the termination region 3b is dispersed due to the fact that the first metal layer 5 extends to the interface between the second trench structure 34 and the third trench structure 35 in the termination region 3b, the strong electric field can be effectively kept away from the cell trench structure 31 in cell region 3a.This prevents the Schottky contact of the cell trench structure 31 from being disturbed by a strong electric field.

[0034] The curve C3 in Fig. 4 is in relation to the potential change of the in Fig. Figure 1 shows the conventional Trench Schottky diode PA100, with curve C4 in Fig.Figure 4 illustrates the potential change of the multiple trench Schottky diode 100 according to the invention. Since the guard ring structure PA33 of the trench Schottky diode PA100 is located at the measurement position of 10 to 20 µm, the potential of curve C1 is kept below 50 V. However, after passing the guard ring structure PA33, the potential changes drastically to almost 250 V, which can easily lead to premature breakdown in practice. Because the first width w1 of the first trench structure 33, the second width w2 of the second trench structure 34, and the third width of the third trench structure 35 gradually decrease, and the first metal layer 5 extends to the interface between the second trench structure 34 and the third trench structure 35, the potential of the multiple trench Schottky diode 100 according to the invention can be gradually increased, thereby effectively preventing premature breakdown.

[0035] In contrast to the conventional trench Schottky diode 100, in which the first metal layer and the second metal layer extend to the termination region to increase the reverse voltage, which causes the surface charge to easily accumulate on the surface of the epitaxial layer, the multiple trench Schottky diode 100 according to the invention is provided in the termination region 3b with the first trench structure 33, the second trench structure 34 and the third trench structure 35, wherein the first metal layer 5 extends to the interface between the second trench structure 34 and the third trench structure 35, thereby enabling the electric field in the termination region to be effectively dispersed, thus avoiding an excessive concentration of the electric field on the surface of the termination region.By gradually reducing the widths of the first trench structure, the second trench structure, and the third trench structure, the potential of the termination area can be gradually and effectively increased, thereby effectively avoiding premature breakthrough stress. Reference symbol list PA100 Trench Schottky Diode PA1 semiconductor substrate PA2 back metal layer PA3 epitaxial layer PA3a cell area PA3b Completion Area PA31 Cell structure PA32 termination trench structure PA33 protective ring structure PA4 dielectric layer PA5 first metal layer PA6 passivation layer PA7 second metal layer 100 Multi-trench Schottky diodes 1 Semiconductor substrate 11 Back 12 Front 2 Back metal layer 3 Epitaxial layer 3a Cell area 3b Final Area 31 Cell trench structure 311 Gate oxide layer 312 low-doped polysilicon layer 32 Termination trench structure 321 Gate oxide layer 322 low-doped polysilicon layer 33 first trench structure 331 Gate oxide layer 332 low-doped polysilicon layer 34 second trench structure 341 Gate oxide layer 342 low-doped polysilicon layer 35 third trench structure 351 Gate oxide layer 352 low-doped polysilicon layer 4 Dielectric intermediate layer 41 Tetraethyl orthosilicate film 42 Borophosphosilicate glass film 5 first metal layer 51 Nickel-platinum alloy layer 52 Titanium metal layer 53 Titanium-tungsten alloy layer 54 Aluminum metal layer 6 Passivation layer 7 second metal layer 71 Titanium metal layer 72 Nickel metal layer 73 Silver metal layer w1 first width w2 second width w3 third width C1, C2, C3, C4 curve

Claims

[1] Multiple trench Schottky diode, comprising: a semiconductor substrate (1); a back metal layer (2) arranged on one side of the semiconductor substrate (1); an epitaxial layer (3) arranged on one side of the semiconductor substrate (1) opposite the back metal layer (2) and comprising a cell region (3a) and a termination region (3b), wherein the epitaxial layer (3) comprises: a termination trench structure (32) located at the junction of the cell area (3a) and the termination area (3b); a first trench structure (33) located in the termination area (3b) and spaced apart from the termination trench structure (32), wherein the first trench structure (33) has a first width (w1); a second trench structure (34) located in the termination area (3b) and spaced apart from the first trench structure (33), wherein the second trench structure (34) has a second width (w2) that is smaller than the first width (w1); and a third trench structure (35) located in the termination area (3b) and spaced apart from the second trench structure (34), wherein the third trench structure (35) has a third width (w3) which is smaller than the second width (w2); a dielectric interlayer (4) located in the termination region (3b) and stacked on the termination trench structure (32), the first trench structure (33), the second trench structure (34) and the third trench structure (35), wherein a first dielectric interlayer trench is formed in the region of the first trench structure (33), a second dielectric interlayer trench is formed in the region of the second trench structure (34) and a third dielectric interlayer trench is formed in the region of the third trench structure (35); a first metal layer (5) located in the cell region (3a) and stacked on the termination trench structure (32), wherein the first metal layer (5) extends from the cell region (3a) to the interface between the second trench structure (34) and the third trench structure (35), and wherein a first metal layer trench is formed in the region of the first dielectric interlayer trench and a second metal layer trench is formed in the region of the second dielectric interlayer trench; a passivation layer (6) which is partially located in the cell region (3a) and is stacked on the first metal layer (5), wherein the passivation layer (6) which extends to the termination region (3b) is located on the first metal layer (5) and in the third dielectric-interlayer trench, and wherein a first passivation layer trench is formed in the region of the first metal layer (5), a second passivation layer trench is formed in the region of the second metal layer trench, and a third passivation layer trench is formed in the region of the third dielectric-interlayer trench; and a second metal layer (7) located in the cell area (3a) and lying on the first metal layer (5) and the passivation layer (6), the second metal layer (7) extending to the termination area (3b) and partially lying on the first passivation layer trench. [2] Multiple trench Schottky diode according to claim 1, characterized by, that the ratio of the first width (w1), the second width (w2) and the third width (w3) is 7:5:

3. [3] Multiple trench Schottky diode according to claim 1 or 2, characterized by , that the dielectric intermediate layer (4) comprises a tetraethyl orthosilicate film (41) [TEOS] and a borophosphosilicate glass film (42) [BPSG], wherein the tetraethyl orthosilicate film (41) is located in the termination region (3b) and lies on the epitaxial layer (3), and wherein the borophosphosilicate glass film (42) is located in the termination region (3b) and lies on the tetraethyl orthosilicate film (41). [4] Multiple trench Schottky diode according to any one of claims 1 to 3, characterized by , that the epitaxial layer (3) is further provided with a plurality of cell trench structures (31), each of which has the following features: a gate oxide layer (311) formed in the cell region (3a); and a low-doped polysilicon layer (312) formed in a trench bounded by the gate oxide layer (311). [5] Multiple trench Schottky diode according to any one of claims 1 to 4, characterized by , that the termination trench structure (32) further exhibits the following: a gate oxide layer (321) formed in the cell region (3a) and the terminal region (3b); and a low-doped polysilicon layer (322) formed in a trench bounded by the gate oxide layer (321). [6] Multiple trench Schottky diode according to claim 5, characterized by , that the first metal layer (5) has a nickel-platinum alloy layer (51) which is stacked on the epitaxial layer (3) and is in electrical contact with the low-doped polysilicon layer (322). [7] Multiple trench Schottky diode according to claim 5 or 6, characterized by, that the first metal layer (5) further comprises a titanium metal layer (52), a titanium-tungsten alloy layer (53) and an aluminum metal layer (54), wherein the titanium metal layer (52) is stacked on the nickel-platinum alloy layer (51) and the dielectric intermediate layer (4) and extends from the cell region (3a) to the interface between the second trench structure (34) and the third trench structure (35) in the termination region (3b), and wherein the titanium-tungsten alloy layer (53) is stacked on the titanium metal layer (52), and wherein the aluminum metal layer (54) is stacked on the titanium-tungsten alloy layer (53). [8] Multiple trench Schottky diode according to any one of claims 1 to 7, characterized by, that the second metal layer (7) comprises a titanium metal layer (71), a nickel metal layer (72) and a silver metal layer (73), wherein the titanium metal layer (71) is stacked on the first metal layer (5) and the passivation layer (6), and wherein the titanium metal layer (71) extends from the cell region (3a) into the termination region (3b) and is partially stacked on the passivation layer trench, and wherein the nickel metal layer (72) is stacked on the titanium metal layer (71), and wherein the silver metal layer (73) is stacked on the nickel metal layer (72).

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