Hall sensors with a three-dimensional structure and method for manufacturing

Abstract

Structure for a Hall sensor, wherein the structure comprises: a semiconductor body comprising a first surface and a side wall (16, 66) chamfered towards the first surface, defining a Hall surface (35) that intersects the first surface; a first well (22) in the semiconductor body, wherein the first well (22) comprises a first section (30) and a second section (26), wherein the first section (30) is positioned partly below the first surface and partly below the Hall surface (35), and the second section (26) is positioned below the first surface of the semiconductor body and extends along the beveled side wall (16, 66); a second well (24) in the semiconductor body, wherein the second well (24) comprises a first section (32) which is arranged laterally partially between the second section (26) of the first well (22) and the Hall surface (35), wherein the first well (22) has a first conductivity type, and the second well (24) has a second conductivity type of a polarity opposite to the first conductivity type; and a plurality of contacts in the semiconductor body, wherein the plurality of contacts comprise a first contact (38) and a second contact (40) coupled to the first section (30) of the first well (22) below the first surface of the semiconductor body.

Description

BACKGROUND

[0001] The present invention relates to integrated circuits and semiconductor device manufacturing, and in particular structures for a Hall sensor and methods for forming a structure for a Hall sensor.

[0002] Hall sensors are common types of sensing components found in various commercial products, such as household appliances, gaming systems, construction equipment, utility meters, and motor vehicles, and are based on the detection of a magnetic field. A magnetic field is a vector quantity characterized by a position-dependent field strength and a field direction. According to Lorentz's law of force, a magnetic field can exert a force on moving charged particles. A Hall sensor relies on the generation of a voltage difference (i.e., a Hall voltage) across an electrical conductor, which is created by a combination of a current flowing in the conductor and a magnetic field with a field direction perpendicular to the current.Conventional Hall sensors, which are planar devices, exhibit low sensitivity when detecting a magnetic field with a field direction parallel to the substrate surface on which the Hall sensor is formed. Hall sensor elements formed on inclined substrate surfaces are known from JP 2005-129 792 A and JP 2005-129 792 A. Furthermore, a Hall sensor element is known from DE 10 2016 109 883 A1, which has a Hall effect region formed within a three-dimensional shell structure made of semiconductor material. Hall structures with vertically oriented grooves for separating corresponding contacts are also known from JP 2005-259 803 A and JP 2016-134 533 A.

[0003] Improved structures for a Hall sensor and methods for forming a structure for a Hall sensor are needed. BRIEF SUMMARY

[0004] According to one embodiment of the invention, a structure for a Hall sensor is provided. The structure comprises a semiconductor body having a first surface and a side wall chamfered to the first surface, defining a Hall surface that intersects the upper surface. The structure further comprises a first well in the semiconductor body, a second well in the semiconductor body, and a plurality of contacts in the semiconductor body. The first well comprises a first section and a second section, wherein the first section is positioned partially below the first surface and partially below the Hall surface, and the second section is positioned below the first surface of the semiconductor body and extends along the chamfered side wall.The second well comprises a first section that is laterally partially located between the second section of the first well and the Hall surface, wherein the first well has a first conductivity type, and the second well has a second conductivity type of a polarity opposite to the first conductivity type. The plurality of contacts comprises a first contact and a second contact that are coupled to the first section of the first well below the first surface of the semiconductor body.

[0005] According to a further embodiment of the invention, a method for forming a structure for a Hall sensor is provided. The method comprises forming a first well in a semiconductor body having a first surface and a side wall chamfered to the first surface, defining a Hall surface that intersects the upper surface. The first well comprises a first section positioned partly below the first surface and partly below the Hall surface, and the first well comprises a second section below the first surface of the semiconductor body extending along the chamfered side wall.The method further comprises forming a second well in the semiconductor body, wherein the second well includes a first section that is partially located laterally between the second section of the first well and the Hall surface, the first well having a first conductivity type, and the second well having a second conductivity type of opposite polarity to the first conductivity type. The method further comprises forming a plurality of contacts in the semiconductor body. The plurality of contacts is coupled to the section of the well below the upper surface of the semiconductor body. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings, which are incorporated into and form part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain these embodiments. In the drawings, the same reference numerals refer to the same features in the different views. Fig. Figure 1 is a top view of a structure for a Hall sensor in an initial manufacturing stage of a processing method according to embodiments of the invention. Fig. 2 is a cross-sectional view along a line 2-2 in the Fig. 1. Fig. Figure 3 is a top view of the structure for the Hall sensor at a manufacturing stage following the Fig. 1. Fig. Figure 4 is a cross-sectional view along a line 4-4 in the Fig. 3. Fig. Figure 5 is a top view of the structure for the Hall sensor at a manufacturing stage following the Fig. 3. Fig. Figure 6 is a cross-sectional view along a line 6-6 in the Fig. 5. Fig. Figure 7 is a top view of a structure for a Hall sensor according to alternative embodiments of the invention. DETAILED DESCRIPTION

[0007] With reference to the Fig. 1, Fig. 2 and according to embodiments of the invention, a groove 10 is formed as a cavity or trench in a substrate 12. The substrate 12 can be a bulk wafer composed of a single-crystal semiconductor material (e.g., single-crystal silicon), and in one embodiment, the substrate 12 can have a lightly doped p-type conductivity. In one embodiment, the groove 10 can be formed by lithography and etching processes. For this purpose, an etch mask 14 is formed over a top surface of the substrate 12. The etch mask 14 can be a hard mask that is structured by lithography and etching processes to define an opening of a given area at an intended location for the groove 10. The groove 10 is etched into the substrate 12 using one or more etching processes with the existing etch mask 14. Portions of the substrate 12 that are not covered by the etch mask 14 are removed by the etching process.

[0008] The groove 10 in the substrate 12 can have a cross-sectional profile that is generated by the choice of etchant. In one embodiment, the groove 10 can have a V-shaped cross-sectional profile. For example, the etchant can be a wet chemical etchant, such as a solution containing tetramethylammonium hydroxide (TMAH), a solution containing potassium hydroxide (KOH), or a solution containing ethylenediamine and pyrocatechol (EDP). The etchant can exhibit selectivity with respect to a crystal orientation of the semiconductor material of the substrate 12, with different etch rates occurring along different crystalline directions. The difference in the etch rates generates the shape of the groove 10.For example, if the substrate 12 contains

[100] -oriented silicon, the (100) planes are etched at a significantly higher rate than the (111) planes, resulting in a self-limiting etching process that forms the groove 10 in which the vertical etch rate is significantly greater than the lateral etch rate.

[0009] The cross-sectional profile of the substrate 12 surrounding the groove 10 comprises side walls 16 extending from an upper surface 11 of the substrate 12 to a surface of the substrate at the groove bottom 18. The side walls 16 define surfaces that are angled or chamfered relative to a plane containing an upper surface 11 of the substrate 12. In an embodiment in which the substrate 12 contains

[100] -oriented silicon having a diamond crystal lattice, the side walls 16 can be chamfered relative to the plane containing the upper surface 11 at an angle of inclination of about 35°, which is consistent with the angle of a normal to the

[111] planes relative to the

[100] surface normal. The side walls 16 penetrate from the upper surface 11 of the substrate 12 to a given depth into the substrate 12 and cut the groove bottom 18, which is arranged laterally between the opposing side walls 16.

[0010] A surface of the substrate 12 exposed at the groove base 18 may be contained in a plane parallel to a plane containing the upper surface 11 of the substrate 12. Each of the side walls 16 intersects the surface at the groove base 18 at a corner 17 extending along a lower edge of the side wall 16. The respective corners 17 are located along opposite sides of the groove base 18, which extends laterally from one corner 17 to the opposite corner 17. Each of the side walls 16 also intersects the upper surface 11 of the substrate 12 at a corner 15 extending along an upper edge of the side wall 16. The surface of the substrate 12 at the groove bottom 18 can be rectangular around a perimeter defined by the corners 17, and the upper surface 11 of the substrate 12 surrounding the entrance to the groove 10 can likewise have a rectangular shape around a perimeter defined by the corners 15.

[0011] With reference to the Fig. 3, Fig. 4, in which the same reference signs refer to the same features in the Fig. 1, Fig. In a subsequent manufacturing stage, the etching mask 14 is removed, and shallow trench insulation areas 20 are formed that surround the groove 10. The shallow trench insulation areas 20 may contain a dielectric material, such as silicon dioxide, which is deposited by chemical vapor deposition into trenches etched in the substrate 12 by a masked etching process, polished, and freed from polishing. The shallow trench insulation areas 20 are dimensionally slightly larger (e.g., in length and width) than the groove 10, so that the corners 15 are surrounded by the shallow trench insulation areas 20. Because of the dimensional difference, portions 13 of the substrate 12 are located as strips on the upper surface 11 between the corners 15 and the shallow trench insulation areas 20. The upper surface 11 of these portions 13 of the substrate 12 may be flat and planar.

[0012] Wells 22, 24, exhibiting conductivity types of opposite polarity, are formed in the substrate 12 beneath the surfaces on the side walls 16 and in the portions 13 of the substrate 12 beneath the upper surface 11. Well 22 can be formed by introducing a dopant of one conductivity type, for example, by ion implantation, into a portion of the substrate 12 beneath each side wall 16 of the groove 10 and into the portions 13 of the substrate 12 surrounding the groove 10. Well 24 can be formed by introducing a dopant of the opposite conductivity type, for example, by ion implantation, into portions of the substrate 12 beneath each side wall 16 and into the portions 13 of the substrate 12 surrounding the groove 10. Respective structured implantation masks can be used to define the selected sites for the tubs 22, 24, and are stripped after each of the tubs 22, 24 has been formed.In one embodiment, the tub 22 can be formed before the tub 24 is formed.

[0013] In one embodiment, the semiconductor material of well 22 can comprise an n-type dopant (e.g., phosphorus or arsenic) effective for imparting n-type conductivity, and the semiconductor material of well 24 can comprise a p-type dopant (e.g., boron) effective for imparting p-type conductivity. Implantation conditions (e.g., kinetic energy and dose) are selected to form each of wells 22, 24 with a desired doping profile and doping concentration. In another embodiment, wells 22, 24 can be constituted by a moderately doped semiconductor material formed by a selection of the implantation conditions. Located below the upper surface 11, wells 22, 24 each extend to a given depth into the substrate 12 relative to the upper surface 11.In one embodiment, the trays 22, 24 can extend to the same depths into the substrate 12 relative to the upper surface 11.

[0014] The tray 22 comprises sections 26 and 28, which extend as strips down the side walls 16 of the groove 10 in the substrate 12 and are also located in the parts 13 of the substrate 12. The tray 22 also comprises a section 30, which extends as a strip down the side walls 16 of the groove 10 in the substrate 12 and is also located in the parts 13 of the substrate 12 on the upper surface 11. Section 30 may have larger dimensions than either section 26 or 28. The tray 24 also comprises sections 32 and 34, which extend as strips down the side walls 16 of the groove 10 and are also located in the parts 13 of the substrate 12 on the upper surface 11. Section 32 of tub 24 is positioned laterally between section 26 and section 30 of tub 22, and section 34 of tub 24 is positioned laterally between section 28 and section 30 of tub 22.

[0015] The surface of the substrate 12 at the groove base 18 is masked during both implantations forming the wells 22 and 24. Therefore, the portion of the substrate 12 below the groove base 18 retains its original conductivity (e.g., a lightly doped p-type conductivity). The wells 22 and 24 terminate at the corners 17 because the surface of the substrate 12 at the groove base 18 is masked during the implantations forming the wells 22 and 24. During the implantation forming well 22 and the implantation forming well 24, portions of the side walls 16 around the perimeter of sections 26 and 28 may also be masked. Therefore, the substrate 12 below these portions of the side walls 16 also retains the original conductivity of the substrate 12. The wells 22 and 24 may contain moderately doped semiconductor material.

[0016] With reference to the Fig. 5, Fig. 6, in which the same reference signs refer to the same features in the Fig. 3, Fig. 4, and in a subsequent manufacturing stage, processing continues in parallel to form respective Hall sensors on each of the side walls 16. The following discussion deals with the formation of the Hall sensor on one of the side walls 16, whereby it is understood that another Hall sensor is formed on the other of the side walls 16.

[0017] In a portion of section 30 of the well 22, a doped region 36 is formed, and contacts 38, 40 are formed as discrete doped regions within the doped region 36. The contacts 38, 40 exhibit a conductivity type of polarity opposite to that of the doped region 36. The doped region 36 and the contacts 38, 40 are located in part 13 of the substrate 12. The doped region 36 extends to a shallower depth into the substrate 12 than the well 22, such that part of the well 22 remains below the doped region 36. The contacts 38, 40 are coupled to the portion of the well 22 below the doped region 36, which in turn couples the contacts 38, 40 to section 30 of the well 22 below the side wall 16. Part of the doped area 36 is positioned between contact 38 and contact 40 to provide electrical insulation.The doped area 36 has the same conductivity type, but a higher dopant concentration than sections 32 and 34.

[0018] In the portions of sections 26 and 28 of the well 22 located in the portions 13 of the substrate 12 on the upper surface 11, contacts 42 and 44 are formed as doped regions. Contacts 42 and 44 have the same conductivity type as sections 26 and 28, but with a higher dopant concentration, and are each coupled to sections 26 and 28 of the well 22. In the portions of the substrate 12 at the groove bottom 18, contacts 46 and 48 are formed as doped regions. Contact 46 couples section 26 of well 22 with section 30 of well 22. Contact 48 couples section 28 of well 22 with section 30 of well 22. Contacts 46 and 48 have the same conductivity type as sections 26 and 28, but with a higher dopant concentration. A doped region 50 is also formed in the part of the substrate 12 exposed at the groove bottom 18.The doped area 50 has a conductivity type opposite to that of contacts 46, 48.

[0019] The doped regions 36, 50 can be formed by introducing a dopant, for example by ion implantation, at selected sites in the substrate 12. A structured implantation mask can be used to define the selected sites for the doped regions 36, 50 and is stripped after implantation. In an embodiment where the well 22 is an n-type semiconductor material and the well 24 is a p-type semiconductor material, the semiconductor material representing the doped regions 36, 50 can contain a p-type dopant, which is effective in imparting p-type conductivity, and can be heavily doped. Implantation conditions are selected to form each of the doped regions 36, 50 with a desired doping profile and concentration.

[0020] The contacts 38, 40, 42, 44, 46, 48 can be formed by introducing a dopant, for example by ion implantation, at selected sites in the substrate 12. A structured implantation mask can be used to define the selected sites for the contacts 38, 40, 42, 44, 46, 48 and is stripped after implantation. In an embodiment where the well 22 is an n-type semiconductor material and the well 24 is a p-type semiconductor material, the semiconductor material representing the contacts 38, 40, 42, 44, 46, 48 can contain an n-type dopant that is effective in imparting n-type conductivity and can be heavily doped. Implantation conditions are selected to form each of the doped areas 36, 50 with a desired doping profile and doping concentration.

[0021] The portion of section 30 of the tub 22 below the side wall 16 is bounded by the doped area 36, ​​the doped area 50, section 32 of the tub 24, and section 34 of the tub 24. These boundaries define a Hall surface 35 of a given region (e.g., length and width) on the surface of the side wall 16. The Hall surface 35 can extend over the full height of the side wall 16 from corner 15 to corner 17, and the Hall surface 35 has a width, w, that extends from one of the sections 32 of the tub 24 to the opposite section 34 of the tub 24. The Hall surface 35 is contained in a plane which is inclined at an angle relative to the upper surface 11 of the substrate 12 and which has a vertical component relative to a plane which contains the upper surface 11 of the substrate 12.

[0022] In the representative embodiment, the groove 10 is etched into the substrate 12 before the wells 22, 24 of opposite conductivity types are formed in the substrate 12. In an alternative embodiment, the groove 10 can be etched into the substrate 12 after the wells 22, 24 of opposite conductivity types have been formed in the substrate 12, followed by the formation of the doped regions 36, 50 and the contacts 38, 40, 42, 44, 46, 48.

[0023] In use, a bias potential can be applied between terminals provided by contact 38 and contact 44 to create a current flowing in the well 22. A magnetic field with a field direction that intersects the Hall surface 35 at the side wall 16 generates a Hall voltage. The Hall surface 35 defines the sensing surface of the Hall sensor. The interaction between the current and the magnetic field generates a potential difference that is detected at the Hall voltage between terminals provided by contact 42 and contact 40. Due to the chamfer of the side walls 16, which provides a non-planar geometry, the Hall sensor can detect a magnetic field characterized by a field direction parallel or nearly parallel to the upper surface 11 of the substrate 12 with greater sensitivity than a conventional Hall sensor.

[0024] With reference to the Fig. 7, in which identical reference signs refer to identical features in the Fig.5, and according to alternative embodiments, the Hall sensor can be formed using a semiconductor fin 64 projecting from the upper surface 11 of the substrate 12, instead of the groove 10, which is recessed as a cavity relative to the upper surface 11 of the substrate 12. The side walls 66 of the semiconductor fin 64 and the upper surface 68 of the semiconductor fin 64 can be used to form the wells 22, 24, the doped areas 36, 50, and the contacts 38, 40, 42, 44, 46, 48 of the Hall sensor. Similar to the side walls 16 of the groove 10, the side walls 66 of the semiconductor fin 64 are inclined or angled relative to a plane containing the upper surface 11 of the substrate 12. Part of the upper surface 11 of the substrate 12 surrounds a base of the semiconductor fin 64. The upper surface 68 of the semiconductor fin 64 can be contained in a plane that is parallel to a plane of the upper surface 11 of the substrate 12.Each of the side walls 66 intersects the upper surface 68 at a corner 62 extending along an upper edge of the side wall 66. Each of the side walls 66 also intersects the upper surface 11 of the substrate 12 at a corner 60 extending along a lower edge of the side wall 66. The upper surface 68 of the semiconductor fin 64 may be rectangular at the corners 62, and the semiconductor fin 64 may have a similar rectangular shape at the corners 62.

[0025] The Hall surface 35 can extend over the full height of each side wall 66 from corner 15 to corner 17, and the Hall surface 35 has a width extending from one of the sections 32 of the well 24 to the opposite section 34 of the well 24. The Hall surface 35 is contained in a plane that is inclined relative to the upper surface 68 of the semiconductor fin 64 and that has a vertical component relative to a plane containing the upper surface 68 of the semiconductor fin 64.

[0026] The processes described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (that is, as a single wafer containing multiple unpackaged chips), as bare die chips, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either an intermediate or a final product. The final product can be any product that incorporates integrated circuit chips, such as computer products with a central processing unit or smartphones.

[0027] References herein to expressions modified by an approximation language, such as "about," "approximately," and "essentially," are not to be limited to the specified precise value. The approximation language may correspond to the precision of an instrument used to measure the value and, unless otherwise specified depending on the precision of the instrument, may indicate + / - 10% of the stated value(s).

[0028] References herein to terms such as "vertical," "horizontal," etc., are made for illustrative purposes only and not to limit or establish a frame of reference. The term "horizontal," as used herein, is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction perpendicular to the horizontal, as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0029] A feature "connected" or "coupled" to another feature can be directly connected or coupled to the other feature, or one or more intervening features can be present. A feature can be "directly connected" or "directly coupled" to another feature if no intervening features are present. A feature can be "indirectly connected" or "indirectly coupled" to another feature if at least one intervening feature is present. A feature "at" or "contacting" another feature can be directly at or in direct contact with the other feature, or one or more intervening features can be present. A feature can be "directly at" or in "direct contact" with another feature if no intervening features are present.A feature can be “indirectly related” or “indirect contact” with another feature if at least one intervening feature is present.

Claims

[1] Structure for a Hall sensor, wherein the structure comprises: a semiconductor body comprising a first surface and a side wall (16, 66) chamfered towards the first surface, defining a Hall surface (35) that intersects the first surface; a first well (22) in the semiconductor body, wherein the first well (22) comprises a first section (30) and a second section (26), wherein the first section (30) is positioned partly below the first surface and partly below the Hall surface (35), and the second section (26) is positioned below the first surface of the semiconductor body and extends along the beveled side wall (16, 66); a second well (24) in the semiconductor body, wherein the second well (24) comprises a first section (32) which is arranged laterally partially between the second section (26) of the first well (22) and the Hall surface (35), wherein the first well (22) has a first conductivity type, and the second well (24) has a second conductivity type of a polarity opposite to the first conductivity type; and a plurality of contacts in the semiconductor body, wherein the plurality of contacts comprise a first contact (38) and a second contact (40) coupled to the first section (30) of the first well (22) below the first surface of the semiconductor body. [2] Structure according to claim 1, wherein the semiconductor body is a semiconductor substrate (12), and the chamfered side wall (16, 66) extends from the first surface of the semiconductor substrate (12) into the semiconductor substrate (12) to define part of a groove (10). [3] Structure according to claim 2, wherein the semiconductor substrate (12) comprises a second surface exposed at a bottom (18) of the groove (10), and the Hall surface (35) on the chamfered side wall (16, 66) and the second surface of the semiconductor substrate (12) intersect at a corner (17). [4] Structure according to claim 2, wherein the Hall surface (35) on the beveled side wall (16, 66) and the first surface of the semiconductor substrate (12) intersect at a corner (15). [5] Structure according to claim 1, further comprising: a semiconductor substrate (12) having an upper surface (11), wherein the semiconductor body is a semiconductor fin (64) projecting away from the upper surface (11) of the semiconductor substrate (12), wherein the first surface is an upper surface (68) of the semiconductor fin (64), and the Hall surface (35) on the beveled side wall (16, 66) is inclined at an angle relative to the upper surface (68) of the semiconductor fin (64). [6] Structure according to claim 5, wherein the Hall surface (35) on the beveled side wall (16, 66) and the upper surface (11) of the semiconductor substrate (12) intersect at a corner (60). [7] Structure according to claim 5, wherein the Hall surface (35) on the beveled side wall (16, 66) and the upper surface (68) of the semiconductor fin (64) intersect at a corner (62). [8] Structure according to any one of claims 1 to 7, wherein the second tub (24) has the first section (32) and a second section (34) which each extend along the beveled side wall (16), wherein the Hall surface (35) is positioned laterally on the beveled side wall (16, 66) between the first section (32) of the second tub (24) and the second section (34) of the second tub (24). [9] Structure according to claim 1, wherein the first well (22) comprises a third section (28) below the first surface (11) of the semiconductor body, which extends into the semiconductor body below the beveled side wall (16, 66), and the second well (24) comprises a second section (34) which is positioned laterally partially between the third section (28) of the first well (22) and the Hall surface (35). [10] Structure according to claim 9, wherein the plurality of contacts comprise a third contact (42) and a fourth contact (44) in the semiconductor body, the plurality of contacts have the first conductivity type with a higher dopant concentration than the first well (22), the third contact (42) is coupled to the second section (26) of the first well (22) at the first surface (11) of the semiconductor body, and the fourth contact (44) is coupled to the third section (28) of the first well (22) at the first surface (11) of the semiconductor body. [11] Structure according to claim 10, further comprising: a doped region (36) in the semiconductor body at the first surface, wherein the doped region (36) has the second conductivity type, and the doped region (36) includes a portion that is positioned to insulate the first contact (38) from the second contact (44). [12] Structure according to claim 11, wherein the semiconductor body is a semiconductor substrate (12), the Hall surface (35) on the chamfered side wall (16) extends from the first surface (11) of the semiconductor substrate (12) into the semiconductor substrate (12) to define part of a groove (10), the semiconductor substrate comprises a second surface exposed at a bottom (18) of the groove (10), and furthermore a doped area (50) is positioned in the semiconductor substrate (12) below the second surface. [13] Structure according to claim 11, further comprising: a semiconductor substrate (12) having an upper surface (11), wherein the semiconductor body is a semiconductor fin (64) projecting away from the upper surface (11) of the semiconductor substrate (12), the first surface is an upper surface (68) of the semiconductor fin (64), the Hall surface (35) on the beveled side wall (16, 66) is inclined at an angle relative to the upper surface (68) of the semiconductor fin (64), and a doped region (50) is positioned in the semiconductor substrate (12) below the upper surface (11). [14] Method for forming a structure for a Hall sensor, the method comprising: Forming a first well (22) in a semiconductor body comprising a first surface and a side wall (16, 66) beveled towards the first surface, defining a Hall surface (35) that intersects the first surface, wherein the first well (22) comprises a first section (30) positioned partly below the first surface and partly below the Hall surface (35), and wherein the first well (22) comprises a second section (26) below the first surface of the semiconductor body extending along the beveled side wall (16, 66); - Forming a second well (24) in the semiconductor body, wherein the second well (24) comprises a first section (32) that is arranged laterally partially between the second section (26) of the first well (22) and the Hall surface (35), wherein the first well (22) has a first conductivity type, and the second well (24) has a second conductivity type of a polarity opposite to the first conductivity type; and Forming a plurality of contacts (38, 40) in the semiconductor body, wherein each of the plurality of contacts (38, 40) is coupled to the first section (30) of the first well (22) under the first surface of the semiconductor body. [15] Method according to claim 14, wherein the semiconductor body is a semiconductor substrate (12), and further comprising: Etching a groove (10) in the semiconductor substrate (12), wherein the beveled side wall (16, 66) extends from the first surface of the semiconductor substrate (12) into the semiconductor substrate (12) to define part of the groove (10). [16] Method according to claim 15, wherein the semiconductor substrate (12) comprises a second surface exposed at a bottom (18) of the groove (10), the Hall surface (35) on the beveled side wall (16, 66) and the second surface of the semiconductor substrate (12) intersect at a first corner (15), and the Hall surface (35) on the beveled side wall (16, 66) and the second surface of the semiconductor substrate (12) intersect at a second corner (17). [17] The method of claim 14, further comprising: Structuring a semiconductor fin (64) projecting away from an upper surface (11) of a semiconductor substrate (12), wherein the first surface is an upper surface (68) of the semiconductor fin (64), and the Hall surface (35) on the beveled side wall (16, 66) is inclined at an angle relative to the upper surface (68) of the semiconductor fin (64). [18] Method according to claim 14, wherein the second tub (24) has the first section (32) and a second section (34) extending along the beveled side wall (16, 66), and the Hall surface (35) is positioned laterally on the beveled side wall (16, 66) between the first section (32) of the second tub (24) and the second section (34) of the second tub (24).

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