Stacked transistor chip package with source coupling

Abstract

A package (100) which has: • a first transistor chip (102) having a first source pad (104); • a second transistor chip (106) having a second source pad (108) and stacked with the first transistor chip (102) at an interface region (110); • wherein the interface region (110) denotes a connection region between the first transistor chip (102) and the second transistor chip (106) in a region where the transistor chips (102, 106) face each other; • a carrier (120) on which the first transistor chip (102) is mounted; and • an electrically conductive first clip (122) which is arranged at least partially in the interface region (110) between the first transistor chip (102) and the second transistor chip (106); • wherein the first source pad (104) and the second source pad (108) are coupled at the interface region (110); • wherein a first gate pad (112) of the first transistor chip (102) and a second gate pad (114) of the second transistor chip (106) are arranged at the interface region (110); • wherein the first transistor chip (102) has a first drain pad (116) on a main surface of the first transistor chip (102) facing away from the interface region (110), and the second transistor chip (106) has a second drain pad (118) on a main surface of the second transistor chip (106) facing away from the interface region (110), • wherein the first clip (122) has a first coupling section (126) which couples the first source pad (104) and the second source pad (108) to the carrier (120); • wherein the first clip (122) has a second coupling section (128) which couples the first gate pad (112) and the second gate pad (114) to the carrier (120), • wherein the first coupling section (126) and the second coupling section (128) are arranged on two opposite sides of the first clip (122); • an electrically conductive second clip (124) which couples the second drain pad (118) to the carrier (120); • wherein the second clip (124) has a further coupling section (132, 134) which couples the second drain pad (118) to the carrier (120); • wherein the second clip (124) has a plate-shaped section (130) on the second drain pad (118) and two opposite coupling sections (132, 134) extending downward from the plate-shaped section (130) for coupling the plate-shaped section (130) to the carrier (120), • wherein the coupling sections (126, 128, 132, 134) are arranged on different sides of the carrier (120).

Description

BackgroundTechnical area

[0001] Various embodiments generally relate to a package and a method of manufacturing a package. Description of the state of the art

[0002] Packages can be defined as typically encapsulated electronic components with electrical connections extending from the encapsulation. For example, packages can be connected to an electronic peripheral, such as mounted on a printed circuit board, or mounted on a heat sink, and connected to a larger system via connectors.

[0003] Packaging costs are a significant driver for the industry. Related to these are performance, size, and reliability. Packaging solutions are diverse and must address the requirements of a specific application.

[0004] US 2005 / 0 224 945 A1 discloses a power semiconductor package comprising a first MOSFET chip and a second MOSFET chip. The first chip is oriented such that a source pad and a gate pad are arranged on the top side of the chip. In contrast, the second chip is oriented such that the source pad and the gate pad are arranged on the bottom side of the chip. The source pads of the two chips are coupled to a common source terminal, which protrudes from a sealing resin body for electrical contact.

[0005] US 2014 / 0 063 744 A1 discloses a power FET comprising a lead frame including a pad, a first lead, and a second lead, a first metal clip including a plate, an extension, and a fin. The plate and the extension are spaced from the pad of the lead frame, and the fin is connected to the pad. A stack comprises a first n-channel FET die with the drain terminal on one surface and the source and gate terminals on the opposite surface, the drain terminal being attached to the pad and the source terminal being attached to a second clip connected to the first lead.The stack includes a second n-channel FET chip having the source terminal on one surface and the drain and gate terminals on the opposite surface, the source terminal being attached to the second clip and its drain terminal being attached to the first clip.

[0006] DE 10 2018 129 689 A1 discloses a semiconductor package having a plurality of half-bridge arrangements, each comprising a metallic line, a first power transistor die attached to a first side of the metallic line, and a second power transistor die arranged beneath the first power transistor die and attached to a second side of the metallic line opposite the first side. Each metallic line has a notch exposing one or more bond pads on a side of the second power transistor die attached to the metallic line. The semiconductor package further includes a control die configured to control the power transistor dies. Each power transistor die, each metallic line, and the control die are embedded in a molding compound.Bond wire connections are provided between the control die and the one or more bond pads on the side of every second power transistor die exposed by the notch in the corresponding metallic line.

[0007] Packages containing power semiconductor chips, in particular, can generate a significant amount of heat during operation. This can limit reliability and performance. Summary

[0008] There may be a need for a package with good reliability and performance.

[0009] According to the invention, a package is provided which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface region, wherein the first source pad and the second source pad are coupled at the interface region.

[0010] According to the invention, a method for manufacturing a package is provided, the method comprising stacking a first transistor chip having a first source pad and a second transistor chip having a second source pad at an interface region, and coupling the first source pad and the second source pad at the interface region.

[0011] According to the invention, a package with a vertical stack of two source-coupled transistor chips is provided. Surprisingly, simulations have shown that stacked transistor chips with mutual source coupling are characterized by lower heat generation and, in particular, exhibit significantly lower power dissipation than a comparable design with drain coupling (compare, for example, Fig. 48 and Fig. 49). Without wishing to be bound by any specific theory, it is presently believed that a common-source design does not severely affect transient currents through opposing outer portions of the package. Highly advantageously, undesirable high-loss regions and hot spots can be efficiently suppressed by means of the source coupling of the stacked transistor chips. Consequently, a package with stacked source-coupled transistor chips can have very low thermal resistance and increased current gain. As a result, a resulting package exhibits efficient heat dissipation and heat distribution, and consequently, improved thermal reliability and performance. A package according to an exemplary embodiment can also have increased current carrying capacity and high power output.Thus, a package according to exemplary embodiments may be extremely suitable, in particular, for power semiconductor applications where a considerable amount of heat may be generated by the transistor chips during operation of the package. Synergistically, vertical stacking of the transistor chips may result in a compact package design with short electrical paths, resulting in lower losses and high electrical transmission quality. Furthermore, a common-source architecture may advantageously expose both drain pads on two opposite outer sides of the stack of transistor chips, which may promote double-sided cooling via both large-area drain pads. This may further contribute to efficient heat dissipation away from the stacked transistor chips.Furthermore, the described package design may enable the provision of relatively large transistor chips that are stacked to still achieve a small footprint of the entire package. Description of further exemplary embodiments

[0012] Further exemplary embodiments of the package and the method are explained below.

[0013] In the context of the present application, the term "package" may refer in particular to electronic devices that may include semiconductor chips, for example, mounted on and / or in a carrier, wherein the carrier comprises or consists of a single part, multiple parts connected via an encapsulation or other package components, a subassembly of carriers, or a carrier laminate. The components of the package may optionally be at least partially encapsulated by means of an encapsulation or embedded in a laminate.

[0014] In the context of the present application, the term "transistor chip" may in particular refer to a device comprising a semiconductor material, for example, a power semiconductor chip or an active electronic device, which performs a transistor function. In particular, the transistor chip may have at least one integrated circuit element in the form of a transistor structure in the semiconductor material. The semiconductor chip may be a bare die or may already be packaged or encapsulated. Transistor chips implemented according to exemplary embodiments may, for example, be formed using silicon technology, gallium nitride technology, silicon carbide technology, etc.

[0015] In the context of the present application, the term "source pad" can in particular refer to an electrically conductive structure that functions as a terminal coupled to a source region of a transistor, in particular a field-effect transistor. Other pads of a transistor chip are a drain pad (i.e., another electrically conductive structure that functions as a terminal coupled to a drain region of the transistor) and a gate pad (i.e., yet another electrically conductive structure that functions as a terminal coupled to a gate region of the transistor). Illustratively, a control signal is to be applied to the gate pad to adjust an electrical conductivity or non-conductivity between the source pad and the drain pad.In particular, the first transistor chip and the second transistor chip may be field effect transistors, for example metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs).

[0016] In the context of the present application, the term "stacked transistor chips" may, in particular, refer to an arrangement of transistor chips vertically stacked on top of one another, with or without an intermediate structure between the stacked transistor chips. In particular, the top-side transistor chip may be provided in a flip-chip configuration, in which the source pad and the gate pad are oriented downwards, whereas the drain pad is oriented upwards. The bottom-side transistor chip may be arranged with the source pad and the gate pad oriented upwards, whereas the drain pad may be oriented downwards.

[0017] In the context of the present application, the term “interface region” may in particular refer to a transition region or a connection region between the transistor chips in a region where the transistor chips face each other.

[0018] According to the invention, a first gate pad of the first transistor chip and a second gate pad of the second transistor chip are arranged at the interface region. Thus, the source pads and the gate pads can be arranged side by side on the same main surface of the respective transistor chip and thus coplanar. Such a configuration can keep the package compact. The gate pads of the transistor chips may or may not be coupled to each other.

[0019] In one embodiment, the first gate pad is coupled to the second gate pad. Such a configuration allows a single control signal to be applied to the gates of both transistor chips. Thus, both gate pads can be controlled jointly.

[0020] In another embodiment, the first gate pad and the second gate pad are configured to be separately controllable. Thus, such an embodiment enables separate individual control of the gates of the two transistor chips. As a result, the gates of the transistor chips can be operated individually, which can be advantageous, for example, for refined control in power steering applications. The option to operate the gate pads of the transistor chips separately can increase flexibility for a circuit designer and can involve advantageous redundancy in the package. Clearly, separate gate connections provide the freedom to decide whether the transistor chips should be controlled exactly identically or individually and therefore optionally differently.

[0021] According to the invention, the first transistor chip has a first drain pad on a main surface of the first transistor chip that faces away from the other main surface corresponding to the interface region. Additionally or alternatively, the second transistor chip may have a second drain pad on a main surface of the second transistor chip that faces away from the other main surface corresponding to the interface region. By arranging the drain pads of the two transistor chips on two opposite main surfaces of the chip stack, heat can be efficiently dissipated from the transistor chip stack by means of a double-sided cooling architecture, i.e., via the outer drains. This can further improve the thermal reliability and the electrical performance of the package.

[0022] In one embodiment, the first drain pad covers substantially the entire main surface of the first transistor chip. Additionally or alternatively, the second drain pad may cover substantially the entire main surface of the second transistor chip. If the source pad and the gate pad are arranged side by side on the same main surface of the respective transistor chip (which experiences vertical current flow) facing the interface region, the entire opposite main surface of the transistor chip is available for the drain pad. Advantageously, this also means that substantially the entire outer main surface of each of the transistor chips can be used for heat dissipation via the drain. Covering the entire surface by the respective drain pad can therefore further increase thermal reliability.

[0023] In one embodiment, the first drain pad is thermally coupled to an exterior of the package for heat dissipation. Additionally or alternatively, the second drain pad can be thermally coupled to an exterior of the package for heat dissipation. Efficient heat dissipation can be further promoted by establishing a thermally conductive path from the respective drain pad to an outer surface of the package. A configuration in which such thermal paths are established for both opposing drain pads is particularly advantageous.

[0024] In one embodiment, the first drain pad and the second drain pad are electrically coupled to each other. Thus, a single drain connection can be created for the package.

[0025] In one embodiment, the first transistor chip and the second transistor chip are connected to function as a single common transistor. Instead of providing one transistor chip, stacking two transistor chips with corresponding pads at least partially coupled in pairs may make it possible to create a package with relatively large chips yet a small footprint. Advantageously, the source pads of the stacked transistor chips may be coupled to each other, the drain pads of the stacked transistor chips may be coupled to each other, and the gate pads of the stacked transistor chips may either be coupled to each other or may be separately controllable. In particular, separate control of the gate pads of the two stacked transistor chips, which function as a common single transistor, increases design freedom and enables sophisticated control of the package.

[0026] In one embodiment, the first transistor chip and the second transistor chip have identical shapes and dimensions. Thus, only a single type of transistor chip is sufficient to create such a package.

[0027] In another embodiment, the first transistor chip and the second transistor chip have different shapes and / or dimensions. Thus, an individual, separate design of the transistor chips is possible to refine the package configuration according to a specific application.

[0028] According to the invention, the package comprises a carrier (in particular a lead frame) on which the first transistor chip is mounted. In the context of the present application, the term "carrier" can in particular refer to a support structure (which is preferably, but not necessarily, electrically conductive) which serves as a mechanical support for the transistor chip and which can also contribute to the electrical connection between the transistor chip(s) and the periphery of the package. In other words, the carrier can fulfill a mechanical support function and an electrical connection function. A carrier can comprise or consist of a single part, multiple parts connected via an encapsulation or other package components, or a subassembly of carriers.

[0029] For example, the carrier may comprise a stack comprising a central electrically insulating and thermally conductive layer (e.g., a ceramic layer) covered on both opposite main surfaces by a respective electrically conductive layer (e.g., a copper layer or an aluminum layer, wherein the respective electrically conductive layer may be a continuous or a patterned layer). For example, such a stack-like carrier may be a Direct Copper Bonding (DCB) substrate or a Direct Aluminum Bonding (DAB) substrate. However, the carrier may also be configured as an Active Metal Brazing (AMB) substrate or as a patterned metal plate (e.g., a lead frame).

[0030] According to the invention, the package comprises an electrically conductive first clip which is at least partially arranged in the interface region between the first transistor chip and the second transistor chip, i.e., sandwiched therebetween. A clip may be a three-dimensionally curved plate-shaped metallic structure configured to establish electrical contact between electrically conductive structures arranged at different vertical levels. A clip may be embodied as a single integral structure or as an arrangement comprising a plurality of island-shaped structures. Said first clip may be partially arranged between the lower transistor chip and the upper transistor chip and may function to conduct electrical signals between chip pads in the interface region and to a portion of the package outside the stacked transistor chips.

[0031] According to the invention, the first clip has a first coupling section that couples the first source pad and the second source pad to the carrier. Since the first source pad and the second source pad are electrically coupled to each other, a common first coupling section of the first clip may be sufficient for both source pads.

[0032] According to the invention, the first clip has a second coupling section that couples the first gate pad and the second gate pad to the carrier. The first coupling section and the second coupling section can be separate electrically conductive structures, which allows the source pads to be electrically separated from the gate pads.

[0033] According to the invention, the first coupling section and the second coupling section are arranged on two opposite sides or on two or three adjacent sides of the first clip. Thus, a source signal, on the one hand, and one or two gate signals, on the other hand, can be conducted along different paths defined by the respective coupling section of the first clip and can therefore be spatially separated. In one configuration, two opposite sides of the first clip can be used to conduct the electrical signals. In another configuration, three adjacent sides of the first clip can be used to conduct the electrical signals.

[0034] According to the invention, the package comprises a second electrically conductive clip which couples the second drain pad to the carrier. A central portion of the second clip can be arranged over a central portion of the first clip and on top of the upper transistor chip. By taking this measure, a drain signal can be conducted between the bottom-side carrier and the top-side drain pad of the top-side transistor chip. At the same time, the described second clip path can establish an additional thermal path which conducts heat between the top-side drain pad and the carrier, for example a copper lead frame. This can further improve the thermal performance of the package. The central portion of the second clip can preferably be flat, which can additionally promote heat dissipation to a top side of the package.

[0035] According to the invention, the second clip has a plate-shaped section on the second drain pad and one or more (preferably at least two opposing) coupling sections extending downward for coupling the plate-shaped section to the carrier. Providing a plurality of inclined or curved coupling sections can ensure low-impedance conduction of the drain signals and the realization of multiple thermal paths for cooling.

[0036] In a corresponding embodiment, the method may include mounting the first transistor chip on a carrier, connecting an electrically conductive first clip between the interface region and the carrier, mounting the second transistor chip on the first clip, and subsequently connecting an electrically conductive second clip between a top side of the second transistor chip and the carrier. Such a manufacturing method is simple and direct and enables the packages to be produced with high throughput on an industrial scale.

[0037] In one embodiment, the package comprises an encapsulation that encapsulates at least a portion of the first transistor chip and at least a portion of the second transistor chip. For example, such an encapsulation may be a molding compound or a soft encapsulation. In the context of the present application, the term "encapsulation" may in particular refer to a substantially electrically insulating and preferably thermally conductive material that surrounds at least a portion of the transistor chips to provide mechanical protection, electrical insulation, and optionally contribute to heat dissipation during operation.

[0038] In one embodiment, the encapsulation may be applied by overmolding the transistor chips and optionally the one or more clips and / or a carrier. Advantageously, a top clip may subsequently be exposed beyond the encapsulation by grinding. Keeping the top surface of the top clip exposed may also be accomplished by foil-assisted molding, i.e., by covering the top surface of the clip with a temporary foil directly during encapsulation.

[0039] In one embodiment, an upper main surface of the second clip is exposed beyond the encapsulation. By exposing the upper main surface of the second clip to a surrounding area of the package, the heat dissipation capability of the second clip can be further enhanced. For example, this can allow a heat sink (e.g., a cooling plate with cooling fins) to be connected to an exposed surface of the second clip. Optionally, a thermal interface material (TIM) can be applied to the exposed surface of the second clip.

[0040] In another embodiment, the package comprises a first laminate in which the first transistor chip is embedded, a second laminate in which the second transistor chip is embedded, and a connection structure, in particular a solder structure, which is arranged in the interface region between the first laminate and the second laminate and is configured to couple the first transistor chip to the second transistor chip. Accordingly, the method may comprise embedding the first transistor chip in a first laminate, embedding the second transistor chip in a second laminate, and subsequently connecting the first laminate to the second laminate by means of an electrically conductive connection structure, in particular a solder structure. A laminate may be a connected layer stack of metallic layers or structures (for example, made of copper) and dielectric layers or structures (for example, made of prepreg).For example, such a laminate may be a printed circuit board (PCB) laminate. Instead of being molded, the respective transistor chips may be pressed, preferably assisted by heat, inside the respective laminate, i.e., between different laminated layers. The connection structure between the first and the second laminate may, for example, be a solder structure (in particular for diffusion soldering), a sintered structure, or an adhesive (in particular an electrically conductive glue). Other connection techniques may also be implemented. The connection structure may comprise a single integral structure or a plurality of (e.g., three or four) island-shaped substructures for different pads. By connecting the laminate-embedded transistor chips by means of a connection structure therebetween, an extremely compact configuration can be achieved.Advantageously, the embedding of the chips can be carried out separately for each of the two laminates before the finished laminates can be connected by means of the connecting structure, preferably by soldering.

[0041] In another embodiment, the package comprises a laminate in which the first transistor chip is embedded, an encapsulation (in particular a molding compound) in which the second transistor chip is encapsulated, and an interconnect structure, in particular a lead frame, arranged in the interface region between the laminate and the encapsulation and configured to couple the first transistor chip to the second transistor chip. In such an embodiment, a hybrid package can be fabricated with a molding compound-encapsulated transistor chip and a PCB-embedded other transistor chip using an interconnect structure therebetween.Such a hybrid can synergistically combine the advantages of encapsulation (particularly keeping manufacturing costs low and resulting in highly suitable heat dissipation properties) and chip embedding (leading to a compact configuration, particularly in a vertical direction). As an alternative to a patterned metal plate, such as a lead frame, the aforementioned interconnect structure can also be embodied as a solder structure or similar. A lead frame can implement source coupling (and optionally gate coupling).

[0042] In one embodiment, the package comprises a metallic structure for coupling the first transistor chip to the second transistor chip. For example, the metallic structure may comprise at least one of the group consisting of at least one continuous metal layer (e.g., a copper foil), at least one patterned metal layer (e.g., a patterned copper foil), at least one vertical metal element (e.g., a via or a pillar), and at least one electrically conductive clip (i.e., a bent and patterned metal plate). Other metallic interconnect structures may also be possible. For example, such metallic structures may be integrated into the above-mentioned laminates. Additionally or alternatively, such metallic structures may be at least partially encapsulated in a molding compound or other encapsulant.Furthermore, such metallic structures can additionally or alternatively be arranged outside a laminate and / or an encapsulation. With a clip-like metallic structure, another hybrid package can be manufactured by combining PCB-embedded chips with a top-side clip.

[0043] In one embodiment, a portion of the metallic structure connects a top surface of the second transistor chip to a bottom surface of the package and partially extends to laterally enclose the first transistor chip and the second transistor chip. For example, the metallic structure may be configured to encompass or laterally surround a laminate and / or encapsulation for connecting the transistor chips.

[0044] In one embodiment, the package comprises a third transistor chip and a fourth transistor chip stacked on the third transistor chip, wherein the third transistor chip and the fourth transistor chip are arranged laterally with respect to the first transistor chip and the second transistor chip. By arranging a plurality of dual-chip stacks (each comprising two stacked transistor chips) side by side, the package can be easily and freely scaled to any desired number of transistor chips. For example, the various dual-chip stacks can be electrically and functionally connected, e.g., by means of individual and / or shared clips. Together, they can function either as a single transistor or as an array of connected transistors.When multiple dual-chip stacks are connected, even more complex circuits can be created, such as an inverter, a half-bridge, a full-bridge, or a B6 bridge. Advantageously, the described package architecture is freely scalable horizontally and can be expanded according to the requirements of a specific application. In particular, multiple dual-chip stacks can be connected using the same (especially first and second) clip(s). It is also possible for more than two transistor chips to be stacked on top of each other.

[0045] In one embodiment, at least one of the first transistor chip and the second transistor chip is configured for vertical current flow. In particular, the electrical current can flow between a pad on a lower main surface of the respective transistor chip through the semiconductor material of the respective transistor chip to another pad on an upper main surface of the respective transistor chip.

[0046] In one embodiment, the transistor chips may form at least one of the group consisting of a controller circuit, a driver circuit, and a power semiconductor circuit. All of these circuits may be integrated into chips. For example, a corresponding power semiconductor application may be realized by means of the chips, wherein integrated circuit elements of such a power semiconductor chip may comprise at least one transistor (in particular a MOSFET, metal-oxide semiconductor field-effect transistor, or an insulated-gate bipolar transistor, IGBT), at least one diode, etc. In particular, circuits may be produced which fulfill a half-bridge function, a full-bridge function, etc.

[0047] In one embodiment, the package is configured as a power converter, particularly one of an AC / DC power converter and a DC / DC power converter. However, other electronic applications may also be possible, such as inverters, etc.

[0048] A semiconductor substrate, i.e., a silicon substrate, can be used as the substrate or wafer for the transistor chips. Alternatively, a silicon oxide or other insulating substrate can be provided. It is also possible to implement a germanium substrate or a III-V semiconductor material. For example, exemplary embodiments can be implemented using GaN or SiC technology.

[0049] Furthermore, exemplary embodiments may use standard semiconductor processing technologies, for example, suitable etching technologies (including isotropic and anisotropic etching technologies, in particular plasma etching, dry etching, wet etching), patterning technologies (which may involve lithographic masks), deposition technologies (for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), sputtering, etc.).

[0050] The foregoing and other objects, features and advantages will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are designated by like reference numerals. Short description of the drawings

[0051] The accompanying drawings, which are included to provide a further understanding of example embodiments and constitute a part of the specification, illustrate example embodiments.

[0052] In the drawings: Fig. 1 shows a cross-sectional view of a package according to an exemplary embodiment. Fig. 2 shows a flowchart of a method for manufacturing a package according to an exemplary embodiment. Fig. 3 to Fig. 5 and Fig. 7 and Fig. 8 show various views of a package according to another exemplary embodiment. Fig. 6 shows a circuit diagram of the package. Fig. 9 to Fig. 11 show various views of a package according to another exemplary embodiment. Fig. 12 shows a method flow for manufacturing a package according to another exemplary embodiment. Fig. 13 and Fig. 14 show various views of a model for simulating a temperature behavior of a package according to another exemplary embodiment. Fig. 15 and Fig. 16 shows results of the simulation of the temperature behavior. Fig. 17 to Fig. 19 and Fig. 21 show various views of a package according to another exemplary embodiment. Fig. 20 shows a circuit diagram of the package mentioned. Fig. 22 to Fig. 24 show various views of a package according to another exemplary embodiment. Fig. 25 to Fig. 30 show a package according to another exemplary embodiment. Fig. 31 to Fig. 35 show different views of components of a package which is Fig. 36, according to an exemplary embodiment. Fig. 37 to Fig. 40 show a package according to another exemplary embodiment. Fig. 41 and Fig. 42 compare various packages according to other exemplary embodiments. Fig. 43 shows a manufacturing process and Fig. 44 shows a received package according to another exemplary embodiment. Fig. 45 to Fig. 47 show packages according to other example embodiments. Fig. 48 shows a simulated power loss density distribution of a source-coupled package according to an exemplary embodiment. Fig. Figure 49 shows a simulated power loss density distribution of a drain-coupled package. Detailed description

[0053] The representation in the drawing is schematic and not to scale. Before describing exemplary embodiments in more detail with reference to the figures, some general considerations are summarized on the basis of which exemplary embodiments were developed.

[0054] According to an exemplary embodiment, a package is provided configured as a stacked transistor chip device having a common source connection between the transistor chips midway between the transistor chips. A corresponding interface region between the transistor chips, which establishes the source connection, may be provided, for example, with a common clip or a common connection layer (e.g., a lead frame, a solder layer, etc.).

[0055] Such a common-source architecture can advantageously lead to lower heating than a comparable common-drain architecture. This has been confirmed by simulations. Such an architecture can distribute the current more evenly spatially and can thus avoid hot spots, which lead to an undesirable local increase in ohmic resistance. Furthermore, the source coupling in an interface region between stacked transistor chips can make it possible to use exposed entire drain regions for cooling and heat dissipation, preferably via two opposite main surfaces of the package. Furthermore, the source coupling architecture can advantageously reduce the drain-source on-resistance (RDSon) of the transistor chips. Illustratively, RDSon can describe a total resistance between the drain and the source in a MOSFET when the MOSFET is "turned on".: on) and can be the basis for a maximum current rating of the MOSFET. Furthermore, a common-source configuration allows the package to be configured with a high degree of symmetry and allows current flow to be balanced more easily than with a common-drain configuration.

[0056] According to a first aspect of the disclosure, a stacked-parallel MOSFET package is provided. Parallel MOSFETs may be particularly suitable for loads with high power requirements. Furthermore, parallel MOSFET circuits may have the advantage of lower thermal resistance due to distributed current channels, which allow for less than a maximum rated current, thus reducing heating and its induced resistance. Furthermore, a parallel MOSFET package may enable increased current gain.

[0057] Conventional parallel MOSFET applications require two or more separate MOSFET devices mounted on separate areas on a board. This design requires significant board space. Consequently, such a conventional approach is also prone to current and thermal imbalance.

[0058] According to an exemplary embodiment, a stacked transistor chip configuration is provided that can benefit from PN half-bridge MOSFETs to save board space. In particular, an exemplary embodiment provides a parallel MOSFET circuit in a stacked configuration. Such an architecture can lead to increased current carrying capacity and higher power output. Advantageously, a corresponding package can generate less heat because distributed current channels can enable maximum rated current flow, reducing heating and its induced resistance. Furthermore, an exemplary embodiment can lead to enhanced heat dissipation through double-sided cooling, which is made possible by exposing the drain pads to the outside due to the central source coupling.Furthermore, appropriate cooling can be further enhanced by implementing a top clip that is connected on both sides to lower conductors of a carrier. Illustratively, heat can also be dissipated via these side paths or sidewalls and to the vias through the lower conductors. As a result of such an architecture, current gain can increase and a small footprint can be achieved. Advantageously, a corresponding package design is scalable, as one or more additional dual-chip stacked MOSFETs can be added laterally. Preferably, middle and top clips can be connected on both sides to a carrier (e.g., a lead frame) in a bridge configuration, resulting in a highly stable structure and consistent with an appropriate bond line thickness.

[0059] Furthermore, parallel MOSFET circuitry in a stacked configuration can improve the package's current-carrying capacity. Effective chip size can be increased, thereby reducing drain-source on-resistance (RDSon) while maintaining a small footprint. Top-side cooling can be implemented to further improve heat dissipation. Furthermore, a top clip can also be connected to a frame to dissipate heat toward the frame and vias. Middle and top clips can be connected to a lead frame on both sides in a bridge configuration, resulting in a more stable structure and consistent interconnect line thickness. Advantageously, the described package configuration is freely scalable, as multiple two-layer stacked MOSFETs can be added laterally.In yet another embodiment, more than two transistor chips (and in particular, a plurality of stacked transistor chip pairs) may be stacked vertically. Furthermore, exemplary embodiments may achieve lower on-resistance per PCB area by stacking two (or more) identical MOSFETs in one package.

[0060] Furthermore, a built-in double-sided cooling function may advantageously be provided to manage higher power density via a second heat dissipation path on the top side. Cooling may be further enhanced by a thick top clip connected to lower conductors, which may be connected to thermal vias in a PCB. Furthermore, higher current carrying capacity may be achieved by avoiding small solder joint areas. As a result, electromigration limitation may be substantially eliminated.

[0061] Advantageously, the described package concept is freely scalable horizontally and depending on the required performance. Specifically, multiple stacked MOSFETs can be combined in one package depending on the required number of switches. Consequently, even more sophisticated electronic circuits can be constructed on this basis.

[0062] In conclusion, an integrated parallel MOSFET circuit can be provided in a stacked package configuration, which reduces the footprint requirement. Advantageously, the fabrication of such a package may require only a relatively small board space. The resulting package is neither susceptible to current imbalance nor susceptible to thermal imbalance. In particular, a parallel MOSFET circuit can be provided in which two MOSFETs are arranged in an opposed vertical array, with a first MOSFET facing a second MOSFET, for improved current carrying capacity. In addition, an effective chip size can be increased, thereby reducing the RDSon while maintaining a small footprint. Separate gate connections can either be shortened (to create a common gate) for a simultaneous turn-on state of the two MOSFETs.Alternatively, the package can be equipped with separate gates, where the first MOSFET can be "on" while the second MOSFET can be "off", or the first MOSFET is "off" while the second MOSFET is "on".

[0063] According to a second aspect of the disclosure, stacked embedded chips may be provided as discrete devices.

[0064] In particular, a discrete device concept is provided whose features significantly reduce resistance and inductance values than conventional single-chip and multi-chip devices. To this end, a stacked embedded chip discrete device concept is disclosed in which two or more chips are embedded in a PCB-like package (i.e., using chip embedding technology). This may allow for even larger chips to be accommodated compared to stacked die devices employing leadframe technology.

[0065] In one embodiment, the transistor chips can be positioned one above the other parallel to a ground plane. One or both transistor chips can be flipped and electrically connected (in particular with a parallel connection) to the common drain, source, and gate paths. Advantageously, the source pads of the stacked transistor chips can be connected in an interface region between the transistor chips.

[0066] An upper and lower drain path in a stacked dual-chip configuration can have different lengths. In particular, the upper path can be longer. Since this can imbalance the current flow through the field-effect transistors (the upper transistor chip may be underloaded and the lower transistor chip may be overloaded), this phenomenon can be advantageously reduced by increasing the cross-sectional area of the upper drain path.

[0067] Furthermore, a common source path in the package can also have a large cross-sectional area, as it carries twice the current of any drain path. A corresponding package can result in a smoother current density distribution with lower peak values and, consequently, a further reduction in package resistance.

[0068] Further advantages of the second aspect are the options for achieving an ultra-low RDSon value of the package. Furthermore, a significant reduction in conduction losses, up to twofold compared to single-chip devices, can be achieved. In addition, an ultra-low package inductance and a reduction in switching losses can be achieved. Furthermore, a lower package resistance can be achieved compared to benchmark packages. The described package architecture is further compatible with double-sided cooling (i.e., via a top and a bottom) and allows for further enhancement of heat dissipation via the option of attaching one or more heat sinks. Embodiments can also result in smooth electrical current distribution in the package and at chip-package interfaces.Furthermore, a very slow increase in package resistance with frequency can be achieved compared to benchmark packages. Furthermore, counter-directed current paths can ensure low radiation emissions. Exemplary embodiments can also improve the electrical performance of the package.

[0069] According to a preferred embodiment of the second aspect, a stacked embedded die discrete device may be provided. The inclusion and parallel connection of two twin transistor dies may reduce the overall drain-source on-resistance of the device by two times compared to a single-die lateral discrete device. The use of die embedding technology may enable the inclusion of larger die (compared to stacked-die discrete devices based on leadframe technology) and may significantly reduce package resistance. A modular approach implemented in a package according to an exemplary embodiment may enable devices with two or more embedded transistor dies to be manufactured.Bidirectional current flows, combined with large areas and a small overall device thickness, can provide very low parasitic inductance and a slow increase in device resistance with frequency. Thermal properties can be enhanced using double-sided cooling.

[0070] Fig. 1 shows a cross-sectional view of a package 100 according to an exemplary embodiment.

[0071] The package 100 shown includes a first transistor chip 102. The first transistor chip 102 has a first source pad 104, a first gate pad 112, and a first drain pad 116. Furthermore, the package 100 includes an inverted second transistor chip 106 having a second source pad 108, a second gate pad 114, and a second drain pad 118. The second transistor chip 106 is stacked on the first transistor chip 102 at an interface region 110. Furthermore, the first source pad 104 and the second source pad 108 are coupled at the interface region 110.

[0072] Fig. 2 shows a flowchart 200 of a method for manufacturing a package 100 according to an exemplary embodiment. The reference numerals used for the following description of the manufacturing method refer to the embodiment of Fig. 1.

[0073] As indicated by block 202, the method of manufacturing package 100 includes stacking first transistor chip 102, having a first source pad 104, and second transistor chip 106, having a second source pad 108, at an interface region 110. As indicated by block 204, the method may further include coupling first source pad 104 and second source pad 108 at interface region 110.

[0074] Fig. 3 to Fig. 5 and Fig. 7 and Fig. 8 show various views of a package 100 according to another exemplary embodiment. Fig. 6 shows a circuit diagram of the package 100.

[0075] The package 100 shown comprises a first transistor chip 102, which is embodied as a MOSFET and can be manufactured, for example, in silicon technology. The first transistor chip 102 has a first source pad 104, a first gate pad 112, and a first drain pad 116, wherein the configuration of Fig. 1. Furthermore, the package 100 comprises a second transistor chip 106 arranged over the first transistor chip 102 and having a second source pad 108, a second gate pad 114, and a second drain pad 118, again referring to the configuration of Fig. 1. The second transistor chip 106 may also be embodied as a MOSFET and may be fabricated, for example, using silicon technology. For example, the transistor chips 102, 106 may be identical in shape, dimensions, and functionality. Each of the first transistor chip 102 and the second transistor chip 106 is configured for vertical current flow, i.e., through the semiconductor material of the respective chip 102, 106 between their opposing main surfaces.

[0076] Advantageously, the first source pad 104 and the second source pad 108 are coupled to each other at an interface region 110. The interface region 110 refers to the portion of the package between the interconnected main surfaces of the transistor chips 102, 106. In other words, the transistor chips 102, 106 can be source-coupled at the position of their physical coupling. This can significantly improve the heat dissipation capability of the package 100. The first gate pad 112 of the first transistor chip 102 and the second gate pad 114 of the second transistor chip 106 are also arranged next to each other at the interface region 110 and laterally spaced with respect to the coupled source pads 104, 108. The first drain pad 160 is arranged at a main surface of the first transistor chip 102 that faces away from the interface region 110.Accordingly, the second drain pad 118 is arranged at a main surface of the second transistor chip 106 which faces away from the interface region 110.

[0077] As shown, the first transistor chip 102 is mounted, preferably by soldering, on a carrier 120, which may be embodied as a lead frame (i.e., a patterned metal plate, e.g., made of copper). More specifically, the first drain pad 116 at the lower major surface of the first transistor chip 102 may be soldered to an upper surface of the carrier 120.

[0078] An electrically conductive first clip 122 may be partially sandwiched between the interface region 110 and the carrier 120. Furthermore, the first clip 122 has a first coupling section 126 that couples the first source pad 104 and the second source pad 108 to the carrier 120. In addition, the first clip 122 has a second coupling section 128 that couples the first gate pad 112 and the second gate pad 114 to the carrier 120. As best shown in Fig. 3 and Fig. 4, the first coupling section 126 and the second coupling section 128 are arranged on two opposite sides of the first clip 122. As best shown in Fig. 8, the first clip 122 may comprise three island-shaped substructures, ie the curved metallic plate-like first coupling section 126 to be arranged in the interface region 110, and two additional metal structures constituting the second coupling section 128.

[0079] Additionally, the package 100 includes an electrically conductive second clip 124 having a substantially flat first portion mounted on a top surface of the second transistor chip 106 and a second portion connecting the first portion to the carrier 120. The second clip 124 electrically and thermally couples the second drain pad 118 to the carrier 120. As previously mentioned, the second clip 124 has the first portion, embodied as a plate-shaped section 130, on the second drain pad 118. Furthermore, the aforementioned second portion of the second clip 126 includes two opposing coupling sections 132, 134 extending downward from the plate-shaped section 130 for coupling the plate-shaped section 130 to the carrier 120. Unlike the first clip 122, the second clip 124 is embodied here as a single integral metallic structure, as best shown in Fig. 8 can be seen.

[0080] The first drain pad 116 is electrically and thermally connected to a lower main surface of the first transistor chip 102 via the electrically and thermally conductive carrier 120. The second drain pad 118 is electrically and thermally connected to the second drain pad 118 via the electrically and thermally conductive second clip 124 in combination with the carrier 120. In particular, this configuration electrically couples the drain pads 116, 118 to each other. Advantageously, the first drain pad 116 covers substantially the entire lower main surface of the first transistor chip 102. Accordingly, the second drain pad 118 covers substantially the entire upper main surface of the second transistor chip 106. This exposes both large-area drain pads 116, 118 at or near the opposite main surfaces of the package 100. Thus, the first drain pad 116 is thermally coupled to an exterior of the package 100 for heat dissipation.At the same time, the second drain pad 118 is also thermally coupled to an exterior of the package 100 for heat dissipation. This results in double-sided cooling and therefore highly efficient heat dissipation during operation of the power semiconductor-type package 100.

[0081] As only in Fig. 8, the package 100 can be overmolded by means of a molding compound-like encapsulation 136, ie, a molding compound. The encapsulation 136 encapsulates the first transistor chip 102 and the second transistor chip 106, as well as parts of the clips 122, 124 and a part of the carrier 120. As shown by means of an opening 137 in the encapsulation 136 of Fig. As indicated in Figure 8, an upper major surface of the second clip 124 remains exposed after encapsulation. Consequently, an upper major surface of the second clip 124 is exposed beyond the encapsulation 136. This may advantageously promote heat dissipation via the top surface of the package 100.

[0082] Referring again to Fig. 8, solder structures 164 may be provided between the carrier 120 and the first transistor chip 102, between the first transistor chip 102 and the first clip 122, between the first clip 122 and the second transistor chip 106, and between the second transistor chip 106 and the second clip 124 for making solder connections.

[0083] Now specifically on Fig. 6, G1 denotes the gate of the first transistor chip 102, S1 denotes the source of the first transistor chip 102, and D1 denotes the drain of the first transistor chip 102. Similarly, G2 denotes the gate of the second transistor chip 106, S2 denotes the source of the second transistor chip 106, and D2 denotes the drain of the second transistor chip 106. As shown, the first gate pad 112 may be coupled to the second gate pad 114 such that a single control signal may be applied to both gate pads 112, 114. As also Fig. 6, the first transistor chip 102 and the second transistor chip 106 are connected to function as a single common transistor. The package 100 is thus configured as a stacked parallel MOSFET package. A control signal for controlling the single common transistor can be applied via a gate terminal 160. A resulting signal at the drain pads 116, 118 can be supplied to a load 162, for example, a motor.

[0084] Advantageously, the package 100 with the vertically stacked source-coupled transistor chips 102, 106 generates only a limited amount of heat, thereby significantly suppressing unwanted hot spots. Consequently, the package 100 with its stacked source-coupled transistor chips 102, 106 has low thermal resistance and high current gain, making it perfectly suited for power semiconductor applications with high thermal reliability and high performance. The current carrying capacity and power output of the package 100 are also excellent. At the same time, the vertical stacking of the transistor chips 102, 106 results in an extremely compact package 100. Arranging the substantially full-area drain pads 116, 118 close to two opposing outer major surfaces of the package 100 enables double-sided cooling to further improve heat dissipation capability.

[0085] Fig. 9 to Fig. 11 show various views of a package according to another exemplary embodiment.

[0086] The embodiment of Fig. 9 to Fig. 11 differs from the previously described embodiment in particular by the additional provision of a third transistor chip 152 and a fourth transistor chip 154 stacked on the third transistor chip 152. The arrangement of the source pad, the drain pad, and the gate pad of the third transistor chip 152 may be identical to that of the first transistor chip 102. The arrangement of the source pad, the drain pad, and the gate pad of the fourth transistor chip 154 may be identical to that of the second transistor chip 106. The stack comprising the third transistor chip 152 and the fourth transistor chip 154 may be arranged laterally to the other stack comprising the first transistor chip 102 and the second transistor chip 106. An additional first clip 122 may be provided for the stack of transistor chips 152, 154 and may be identical to the first clip 122 used for the transistor chips 102, 106.The second clip 124 may spatially extend to span and connect all of the transistor chips 102, 106, 152, 154 in the manner described above for the transistor chips 102, 106. Thus, as best shown in FIG. Fig. 11, a first stack of the first transistor chip 102 and the second transistor chip 106, and a second stack of the third transistor chip 152 and the fourth transistor chip 154, share the second clip 124 to thereby create a particularly compact configuration.

[0087] Fig. 9 to Fig. 11 demonstrate that the package design is freely scalable according to exemplary embodiments. Multiple two-chip stacks of MOSFETs can be arranged side by side or side by side, according to the requirements of a particular application.

[0088] Fig. 12 shows a process flow for manufacturing a package 100 according to another exemplary embodiment.

[0089] A block 210 denotes solder screen printing onto the carrier. A block 212 denotes bonding of the lower chip. A block 214 denotes solder stencil printing onto the lower chip. A block 216 denotes bonding of the first clip to the lower chip. A block 218 denotes solder stencil printing onto the first clip. A block 220 denotes upper flip chip die bonding. A block 222 denotes solder stencil printing onto the upper chip. A block 224 denotes bonding of the second clip to the upper chip. A block 226 denotes reflow soldering. A block 228 denotes flux cleaning. A block 230 denotes plasma processing. A block 232 denotes wire bonding. Block 234 indicates coating with a morphological adhesion promoter. Block 236 indicates the beginning of the line quality control.A block 238 denotes mold casting. A block 240 denotes subsequent curing of the molding compound. A block 242 denotes chemical deburring. A block 244 denotes water jet treatment. A block 246 denotes tin plating. A block 248 denotes visual inspection. A block 250 denotes laser marking. A block 252 denotes package sawing. A block 254 denotes end of line quality control. A block 256 denotes transport for testing.

[0090] Fig. 13 and Fig. 14 show various views of a model for simulating a temperature behavior of a package 100 according to an exemplary embodiment. Fig. 15 and Fig. 16 shows the results of the simulation of the temperature behavior. The result of the thermal simulation according to Fig. 13 to Fig. 16 is that the packages 100 according to exemplary embodiments show improved thermal characteristics compared to benchmark packages.

[0091] Fig. 17 to Fig. 19 and Fig. 21 show various views of a package 100 according to another exemplary embodiment. Fig. 20 shows a circuit diagram of the package 100.

[0092] A major difference between the design of Fig. 17 to Fig. 21, compared to Fig. 3 to Fig. 8, is that according to Fig. 17 to Fig. 21, the first gate pad 112 and the second gate pad 114 are configured to be separately controllable. Instead of providing a single gate terminal 160, as in Fig. 6 are according to Fig. 20, two separate gate terminals 160A, 160B are provided. This allows independent application of a first gate signal to be applied to the gate of the first transistor chip 102 and a second gate signal to be applied to the gate of the second transistor chip 106.

[0093] How best in Fig. As can be seen in Figure 17, the first coupling section 126 of the first clip 122 is arranged on two opposite sides of the first clip 122. The second coupling section 128 is arranged on another side of the first clip 122 between the two opposite sides.

[0094] Fig. 22 to Fig. 24 show various views of a package 100 according to another exemplary embodiment.

[0095] A major difference between the design of Fig. 22 to Fig. 24, compared to Fig. 17 to Fig. 21, is that according to Fig. 22 to Fig. 24, an adhesive layer 166 is arranged between two stacked pieces 122A, 122B of the first clip 122. Such an adhesive layer 166 can be made of a non-conductive or a conductive adhesive. This makes it possible to provide a two-piece first clip 122, with the pieces 122A, 122B being connected to one another by means of the adhesive material.

[0096] Fig. 25 to Fig. 30 show a package 100 according to another exemplary embodiment. Fig. 25 and Fig. 26 show various three-dimensional views of the package 100. Fig. 27 is a side view from a viewing direction A, which is shown in Fig. 25 is shown. Fig. 28 is another side view from a viewing direction B, which in Fig. 25 is shown. Fig. 29 is a semi-transparent view showing the positions of the transistor chips 102, 106 in the package 100. Fig. Figure 30 is another side view. Fig. 25 to Fig. 28 a stacked embedded twin chip embodiment of the package 100. Fig. 29 and Fig. 30 show the positions of the transistor chips 102, 106 in the package 100.

[0097] The Package 100, which is Fig. 25 to Fig. 30, comprises a first laminate 138 in which the first transistor chip 102 is embedded. The first laminate 138 with the embedded first transistor chip 102 may be embodied as a printed circuit board (PCB) with the first transistor chip 102 inside, processed by die embedding. Further, a second laminate 140 is provided in which the second transistor chip 106 is embedded. The second laminate 140 with the embedded second transistor chip 106 may be embodied as another printed circuit board (PCB) with the second transistor chip 106 inside, processed by die embedding.

[0098] More specifically, each of the laminates 138, 140 comprises dielectric layers 170 (e.g., prepreg layers), which are preferably pressed together at an elevated temperature with metallic structures 150 to thereby form the respective bonded laminate 138, 140. The metallic structures 150 may comprise horizontally patterned copper layers and vertical copper vias. By means of the metallic structures 150, the respective transistor chips 102, 106, and in particular their source, drain, and gate pads, may be electrically connected. Inter alia, the metallic structures 150 may couple the transistor chips 102, 106, for example, in the manner described in Fig. 6 or Fig. 20 is shown.

[0099] The two PCBs may be connected by means of an interconnect structure 142, which is embodied as a solder structure. The interconnect structure 142 is disposed between the first laminate 138 and the second laminate 140 and is configured to couple the first transistor chip 102 to the second transistor chip 106.

[0100] To produce the package 100 according to Fig. 25 to Fig. 30, the first transistor chip 102 may be embedded in the first laminate 138. Separately, the second transistor chip 106 may be embedded in the second laminate 140. Subsequently, the first laminate 138 may be solder-connected to the second laminate 140 by means of the electrically conductive connection structure 142, which is embodied as a solder structure.

[0101] In Fig. 25 to Fig. 28, a source path is designated by reference numeral 174, a drain path is designated by reference numeral 176, and a gate path is designated by reference numeral 178.

[0102] The Package 100 according to Fig. 25 to Fig. 30 has two modules in the form of laminates 138, 140 on the top and bottom, respectively, which are connected by means of the solder-like connection structure 142. The details of a process flow for manufacturing the package 100 are shown in Fig. 31 to Fig. 36. The excellent electromagnetic performance of package 100 was confirmed by three-dimensional simulations. According to these simulation results, package 100 has low resistance. This result can be achieved by doubling the total active area in the twin-chip package 100.

[0103] Fig. 31 to Fig. 35 show different views of a package 100, compare Fig. 25 to Fig. 30, which according to Fig. 36, according to another exemplary embodiment.

[0104] Show more details Fig. 31 and Fig. 32 a three-dimensional view or a top view of the first laminate 138, which serves as a lower module for producing the package 100 according to Fig. 25 to Fig. 30 is used. Fig. 33, Fig. 34 and Fig. 35 show a side view, a three-dimensional view and a top view, respectively, of the second laminate 140, which serves as an upper module for producing the package 100 according to Fig. 25 to Fig. 30 is used. Illustratively, the second laminate 140 may be a simplified and reversed clone of the first laminate 138. Fig. Figure 36 shows how the laminates 138, 140 are connected by means of a solder-like connecting structure 142.

[0105] Fig. 37 to Fig. 40 show a package 100 according to another exemplary embodiment. The package 100 according to Fig. 37 to Fig. 40 can be described as a stacked embedded twin chip discrete device with current flow in four directions.

[0106] Show more details Fig. 37 to Fig. 40 illustrates a package 100 with improved electromagnetic performance by utilizing four-way current flow. Four-way current flow can increase effective cross-sectional area and thus significantly reduce package resistance. Additionally, crossover and oppositely directed currents flowing within package 100 can reduce its parasitic inductance.

[0107] Fig. 41 and Fig. 42 compare various packages 100 according to other exemplary embodiments. The packages 100 according to Fig. 41 and Fig. 42 are modifications or other possible footprint types of the package architecture according to Fig. 37 to Fig. 40.

[0108] The Package 100 according to Fig. 41 has a more compact footprint than the Package 100 according to Fig. 37 to Fig. 40 and experiences a three-dimensional current flow. The package 100 according to Fig. 42 has a lower resistance than the package 100 according to Fig. 37 to Fig. 40.

[0109] Fig. 43 shows a manufacturing process and Fig. 44 shows a received package 100 according to another exemplary embodiment.

[0110] The manufacturing process according to Fig. 43 is similar to the manufacturing process described above with reference to Fig. 36 is described. Fig. 43 shows that the interconnect structure 142 may comprise a plurality of separate island-shaped substructures 142A, 142B, 142C, for example, different portions of solder material. For example, the substructures 142A, 142B, 142C may be applied to an upper major surface of the laminate 138 or a lower major surface of the laminate 140 before the laminates 138, 140 are joined together by soldering the island-shaped substructures 142A, 142B, 142C.

[0111] How Fig. 43, each of the laminates 138, 140 may be provided with metallic structures 150 of the type described above. As in Fig. 44, these metallic structures 150 cooperate to couple the first transistor chip 102 to the second transistor chip 106. In the illustrated embodiment, the metallic structure 150 may comprise continuous and / or patterned metal layers as well as vertical metal elements (e.g., pillars or vias). As shown, a portion of the metallic structures 150 connects a top surface of the second transistor chip 106 in the second laminate 140 to a bottom surface of the first laminate 138 of the package 100. In this context, the portion of the metallic structure 150 extends to laterally surround the embedded first transistor chip 102 and the embedded second transistor chip 106.

[0112] Thus, the package includes 100 according to Fig. 44 shows two modules (lower and upper) in the form of laminates 138, 140, each having an embedded transistor chip 102, 106. Each laminate 138, 140 can be manufactured separately. The laminates 138, 140 can then be connected, for example, by soldering using the interconnect structure 142.

[0113] The embodiment of Fig. 44 is based on component embedding technology. To reduce ohmic resistance and improve heat dissipation, the metallic structures 150 may include a thick metal layer (e.g., a copper foil having a thickness of 150 µm) on an upper main surface of the package 100. More generally, the thick metal layer may, for example, have a thickness in a range of 100 µm to 200 µm.

[0114] Fig. 45 shows a package 100 according to another exemplary embodiment. The embodiment of Fig. 45 differs from the embodiment according to Fig. 44 in particular that, according to Fig. 45, a metal plate (in particular copper) is provided as the uppermost metallic structure 150 instead of a copper layer. The copper plate may have a thickness of 250 µm. More generally, the metal plate may, for example, have a thickness in the range of 200 µm to 500 µm. This metal plate-like metallic structure 150 may be connected to an upper main surface of the package 100 by means of a solder structure 180.

[0115] Fig. 46 shows a package 100 according to yet another exemplary embodiment. The embodiment of Fig. 46 differs from the embodiment according to Fig. 44 in particular that, according to Fig. 46, the second transistor chip 106 is encapsulated in a molding compound-like encapsulation 146 instead of being embedded in a laminate. Furthermore, the metallic structures 150 according to Fig. 46 has a clip 182 encapsulated in the encapsulation 146 to promote cooling and to establish electrical coupling between the transistor chips 102, 106.

[0116] More precisely, the embodiment of Fig. 46 comprises a laminate 138 of the type described above, in which the first transistor chip 102 is embedded. A molding compound represents the encapsulation 146 in which the second transistor chip 106 is encapsulated. An interconnect structure 142 between the transistor chips 102, 106 is embodied here as a lead frame, i.e., a patterned metal plate. The second transistor chip 106 is mounted on the interconnect structure 142. The interconnect structure 142 is arranged between the laminate 138 and the molding compound-like encapsulation 146 and is configured to couple the first transistor chip 102 to the second transistor chip 106. Like the second transistor chip 106, the clip 182, which represents the uppermost metallic structure 150, is also encapsulated in the encapsulation 146. The clip 182 contributes to an electrical coupling between the transistor chips 102, 106.Furthermore, an upper main surface of the clip 182 is exposed beyond the encapsulation 146 to thereby enable cooling also via an upper main surface of the package 100. The clip 182 may have a thickness of 250 µm. More generally, the metal clip 182 may, for example, have a thickness in the range of 200 µm to 500 µm. The package 100 is illustrated in FIG. Fig. 46 from a combination of chip embedding and lead frame technologies.

[0117] Fig. 47 shows a package 100 according to yet another exemplary embodiment. The embodiment of Fig. 47 differs from the embodiment according to Fig. 46 in particular that, according to Fig. 47, no leadframe-like connection structure 142 is provided between the first transistor chip 102 and the second transistor chip 106. In contrast, a thick metal layer 184 is provided between the first transistor chip 102 and the second transistor chip 106. The thick metal layer 184 contributes to both electrical coupling and thermal coupling between the transistor chips 102, 106. For example, the metal layer 184 may have a thickness in the range of 100 µm to 200 µm.

[0118] Fig. 48 shows a simulated power loss density distribution of a source-coupled package 100 according to an exemplary embodiment. Fig. 49 shows a simulated power loss density distribution of a drain-coupled package 300. For example only, the power loss density distribution simulation of packages 100 according to exemplary embodiments is shown using the example of the package 100 of Fig. 48, which belongs to the package architecture of Fig. 37 to Fig. 40. Conclusions regarding the thermal reliability and electrical performance of such packages 100 also apply to other embodiments disclosed herein.

[0119] Compare more precisely Fig. 48 and Fig. 49 the power loss density distribution behavior of stacked embedded chip discrete devices with a common-source architecture according to an exemplary embodiment (compare Fig. 48) versus a common-drain approach (compare Fig. 49). In other words, a spatial distribution of ohmic losses over the shown main surface of the packages 100, 300 in Fig. 48 and Fig.49. As shown, the common-source design has an advantage from the standpoint of electrical performance. In the common-source design (in the example of a chip-embedded embodiment), the current distribution in the upper layer is more homogeneous. The common-drain design has a cut in the upper layer (due to the gate path 178), which leads to concentrated areas of current density and increases the package resistance compared to the common-source design. The common-source design has a cut in the middle layers (common path), which does not affect the equalizing currents through the lower and upper layers and the transistor chips 102, 106. Critical regions 302 of the package 300 are significantly less pronounced in the package 100.

[0120] Furthermore, the parallel connection of the transistor chips 102, 106 reduces the current flowing through each of them. Thus, the heat generation in each transistor chip 102, 106 is significantly lower compared to conventional approaches, while passing the same total current. Packages 100 according to exemplary embodiments may allow for higher current to be conducted than conventional packages with the same safety constraints. It can be concluded that, in particular, packages 100 that utilize four-way current flow not only exhibit a significant reduction in device resistance but also very low package parasitics. Simulations performed over a range of frequencies have also advantageously shown only a slow increase in package resistance with frequency.This, together with a very low inductance, makes the Packages 100 particularly suitable for the medium frequency range (especially up to 10 MHz).

Claims

[1] A package (100) which comprises: • a first transistor chip (102) having a first source pad (104); • a second transistor chip (106) having a second source pad (108) and stacked with the first transistor chip (102) at an interface region (110); • wherein the interface region (110) denotes a connection region between the first transistor chip (102) and the second transistor chip (106) in a region where the transistor chips (102, 106) face each other; • a carrier (120) on which the first transistor chip (102) is mounted; and • an electrically conductive first clip (122) which is arranged at least partially in the interface region (110) between the first transistor chip (102) and the second transistor chip (106); • wherein the first source pad (104) and the second source pad (108) are coupled at the interface region (110); • wherein a first gate pad (112) of the first transistor chip (102) and a second gate pad (114) of the second transistor chip (106) are arranged at the interface region (110); • wherein the first transistor chip (102) has a first drain pad (116) on a main surface of the first transistor chip (102) facing away from the interface region (110), and the second transistor chip (106) has a second drain pad (118) on a main surface of the second transistor chip (106) facing away from the interface region (110), • wherein the first clip (122) has a first coupling section (126) which couples the first source pad (104) and the second source pad (108) to the carrier (120); • wherein the first clip (122) has a second coupling section (128) which couples the first gate pad (112) and the second gate pad (114) to the carrier (120), • wherein the first coupling section (126) and the second coupling section (128) are arranged on two opposite sides of the first clip (122); • an electrically conductive second clip (124) which couples the second drain pad (118) to the carrier (120); • wherein the second clip (124) has a further coupling section (132, 134) which couples the second drain pad (118) to the carrier (120); • wherein the second clip (124) has a plate-shaped section (130) on the second drain pad (118) and two opposite coupling sections (132, 134) extending downward from the plate-shaped section (130) for coupling the plate-shaped section (130) to the carrier (120), • wherein the coupling sections (126, 128, 132, 134) are arranged on different sides of the carrier (120). [2] The package (100) according to claim 1, comprising one of the following features: the first gate pad (112) is coupled to the second gate pad (114); the first gate pad (112) and the second gate pad (114) are configured to be separately controllable. [3] The package (100) of claim 1 or 2, wherein the first transistor chip (102) and the second transistor chip (106) are connected to function as a single common transistor. [4] The package (100) according to any one of claims 1 to 3, comprising one of the following features: the first transistor chip (102) and the second transistor chip (106) have an identical shape and dimensions; the first transistor chip (102) and the second transistor chip (106) have different shapes and / or dimensions. [5] The package (100) according to any one of claims 1 to 4, comprising an encapsulation (136), in particular a molding compound, which encapsulates at least a part of the first transistor chip (102) and at least a part of the second transistor chip (106). [6] The package (100) according to any one of claims 1 to 5, comprising: a first laminate (138) in which the first transistor chip (102) is embedded; a second laminate (140) in which the second transistor chip (106) is embedded; and a connection structure (142), in particular a solder structure, which is arranged in the interface region (110) between the first laminate (138) and the second laminate (140) and is configured to couple the first transistor chip (102) to the second transistor chip (106). [7] The package (100) according to any one of claims 1 to 6, comprising: a laminate (138) in which the first transistor chip (102) is embedded; an encapsulation (146) in which the second transistor chip (106) is encapsulated; and a connection structure (142), in particular a lead frame, which is arranged in the interface region (110) between the laminate (138) and the encapsulation (146) and is configured to couple the first transistor chip (102) to the second transistor chip (106). [8] The package (100) according to claim 6 or 7, comprising a metallic structure (150) for coupling the first transistor chip (102) to the second transistor chip (106). [9] The package (100) of claim 8, wherein the metallic structure (150) comprises at least one of the group consisting of at least one continuous metal layer, at least one patterned metal layer, at least one vertical metal element, and at least one electrically conductive clip (182). [10] The package (100) according to claim 8 or 9, wherein a part of the metallic structure (150) connects a top side of the second transistor chip (106) to a bottom side of the package (100) and extends partially such that the first transistor chip (102) and the second transistor chip (106) are laterally enclosed. [11] The package (100) according to any one of claims 1 to 10, comprising a third transistor chip (152) and a fourth transistor chip (154) stacked on the third transistor chip (152), wherein the third transistor chip (152) and the fourth transistor chip (154) are arranged laterally with respect to the first transistor chip (102) and the second transistor chip (106). [12] A method of manufacturing a package (100), the method comprising: • Stacking a first transistor chip (102) having a first source pad (104) and a second transistor chip (106) having a second source pad (108) at an interface region (110); and • coupling the first source pad (104) and the second source pad (108) at the interface region (110); • wherein the interface region (110) denotes a connection region between the first transistor chip (102) and the second transistor chip (106) in a region where the transistor chips (102, 106) face each other; • wherein the first transistor chip (102) has a first drain pad (116) on a main surface of the first transistor chip (102) facing away from the interface region (110), and the second transistor chip (106) has a second drain pad (118) on a main surface of the second transistor chip (106) facing away from the interface region (110); • Mounting the first transistor chip (102) on a carrier (120); • Arranging an electrically conductive first clip (122) at least partially in the interface region (110) between the first transistor chip (102) and the second transistor chip (106), the first clip (122) having a first coupling section (126) which couples the first source pad (104) and the second source pad (108) to the carrier (120); • Arranging a first gate pad (112) of the first transistor chip (102) and a second gate pad (114) of the second transistor chip (106) at the interface region (110); • wherein the first clip (122) has a first coupling section (126) which couples the first source pad (104) and the second source pad (108) to the carrier (120); • wherein the first clip (122) has a second coupling section (128) which couples the first gate pad (112) and the second gate pad (114) to the carrier (120), • wherein the first coupling section (126) and the second coupling section (128) are arranged on two opposite sides of the first clip (122); • an electrically conductive second clip (124) which couples the second drain pad (118) to the carrier (120); • wherein the second clip (124) has a further coupling section (132, 134) which couples the second drain pad (118) to the carrier (120); • wherein the second clip (124) has a plate-shaped section (130) on the second drain pad (118) and two opposite coupling sections (132, 134) extending downward from the plate-shaped section (130) for coupling the plate-shaped section (130) to the carrier (120), • wherein the coupling sections (126, 128, 132, 134) are arranged on different sides of the carrier (120). [13] The method according to claim 12, wherein the method comprises: Embedding the first transistor chip (102) in a first laminate (138); Embedding the second transistor chip (106) in a second laminate (140); and subsequently connecting the first laminate (138) to the second laminate (140) by means of an electrically conductive connecting structure (142), in particular a soldering structure, in the interface region (110).

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