EUV photomasks and manufacturing methods for them

Abstract

Reflective mask, featuring: a substrate (10); a reflective multilayer (15) arranged on the substrate (10); a cover layer (20) arranged on the reflective multilayer (15); and an absorber layer (25) arranged on the top layer (20), wherein the absorber layer (25) has a CrN layer and wherein the CrN layer has a Cr phase and a Cr2N phase.

Description

RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US patent application No. 63 / 045,444, filed on June 29, 2020, the entire contents of which are incorporated into the present application by reference. BACKGROUND

[0002] Photolithography processes are among the most crucial in semiconductor manufacturing. Photolithography methods include ultraviolet lithography, deep ultraviolet lithography, and extreme ultraviolet lithography (EUVL). The photomask is an important component in photolithography processes. It is essential to produce EUV photomasks, which exhibit high contrast, with a high-reflectivity portion and a high-absorption portion. US 2013 / 0260292 A1 describes a method and apparatus for producing a reflective mask comprising a substrate, a reflective multilayer, a cover layer, and an absorber layer. US 2016 / 0238925 A1 describes a reflective mask and a method for producing a semiconductor apparatus. WO 2020 / 175354 A1 and DE 10 2020 102 450 A1 describe a reflective mask and methods for its production. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying figures. It is emphasized that, in accordance with industry practice, various elements are not shown to scale and are for illustrative purposes only. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1A, Fig. 1B, Fig. 1C, Fig. 1D and Fig. Figure 1E shows EUV photomask blanks according to embodiments of the present disclosure. Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E and Fig. Figures 2F schematically represent a method for producing an EUV photomask according to an embodiment of the present disclosure. Fig. 3A, Fig. 3B, Fig. 3C, Fig. 3D and Fig. Figure 3E schematically represents a method for producing an EUV photomask according to an embodiment of the present disclosure. Fig. Figure 4 shows a cross-sectional view of an EUV photomask according to embodiments of the present disclosure. Fig. 5A, Fig. 5B and Fig. Figure 5C shows cross-sectional views of a multilayer structure of an absorber layer according to another embodiment of the present disclosure. Fig. Figure 6 shows a cross-sectional view of an EUV photomask according to embodiments of the present disclosure. Fig. Figure 7 shows a flowchart of the production of a mask blank for an EUV photomask according to embodiments of the present disclosure. Fig. Figure 8A shows a flowchart of a process for manufacturing a semiconductor device, and Fig. 8B, Fig. 8C, Fig. 8D and Fig. Figure 8E shows a sequential manufacturing process of a method for manufacturing a semiconductor device according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0004] It is understood that the following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not to be understood as limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired properties of the device.Furthermore, the following description of a first element positioned above or on top of a second element may include embodiments in which the first and second elements are in direct contact, and also embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements may not be in direct contact. For the sake of simplicity and clarity, various elements may be shown at different scales.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used in this document to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative terms are intended to encompass, in addition to the orientation shown in the figures, other orientations of the device during use or operation. The device may be oriented in a different way (rotated by 90 degrees or in other orientations), and the spatially relative terms used in this document may be interpreted accordingly. In addition, the term "made of" may mean either "comprising" or "consisting of."In the present disclosure, a phrase “one of A, B and C” means “A, B and / or C” (A, B, C; A and B; A and C; B and C; or A, B and C) and does not mean one element of A, one element of B and one element of C, unless otherwise described.

[0006] Embodiments of the present disclosure provide a method for manufacturing an EUV photomask. In particular, the present disclosure provides methods for preventing or suppressing damage to a conductive backside layer of an EUV photomask. The present disclosure solves the problem underlying the application through the subject matter of the claims.

[0007] EUV lithography (EUVL) uses scanners that employ light in the extreme ultraviolet (EUV) range with wavelengths from approximately 1 nm to 100 nm, for example, 13.5 nm. The mask is a crucial component of an EUVL system. Since optical materials are not transparent to EUV radiation, EUV photomasks are reflective. Circuit structures are formed within an absorber layer positioned above the reflective structure. The absorber exhibits low EUV reflectivity, for example, less than 3–5%.

[0008] The present disclosure provides an EUV-reflective photomask with a weakly reflective (highly absorbing) absorber structure.

[0009] Fig. 1A and Fig. Figure 1B shows an EUV-reflective photomask blank according to an embodiment of the present disclosure. Fig. 1A is a top view (seen from above), and Fig. 1B is a cross-sectional view along the X direction.

[0010] In some embodiments, the EUV photomask with circuit structures is manufactured from an EUV photomask blank 5. The EUV photomask blank 5 comprises a substrate 10, a multilayer Mo / Si stack 15 consisting of several alternating silicon and molybdenum layers, a cover layer 20, a protective layer 22, an absorber layer 25, a first hard mask layer 30, and a second hard mask layer 32. Furthermore, as shown in Fig. As shown in Figure 1B, a conductive backside layer 45 is formed on the back side of the substrate 10. In some embodiments, as shown in Fig. As shown in Figure 1B, an oxide layer 27 is formed on the upper surface of the absorber layer 25. In other embodiments, as shown in Fig. In 1D representation, no oxide layer is formed on the upper surface of the absorber layer 25.

[0011] In some embodiments, the substrate 10 is made of a material with low thermal expansion. In some embodiments, the substrate is made of a glass or quartz with low thermal expansion, for example, molten silicon dioxide or molten quartz. In some embodiments, the glass substrate with low thermal expansion transmits light in the visible wavelength range, a portion of the infrared wavelengths near the visible spectrum (near-infrared), and a portion of the ultraviolet wavelengths. In some embodiments, the glass substrate with low thermal expansion absorbs extreme ultraviolet wavelengths and low ultraviolet wavelengths near the extreme ultraviolet. In some embodiments, the size of the substrate 10 is 152 mm × 152 mm, with a thickness of about 20 mm. In other embodiments, the size of the substrate 10 is less than 152 mm × 152 mm and greater than or equal to 148 mm × 148 mm.The shape of substrate 10 is square or rectangular.

[0012] In some embodiments, the functional layers above the substrate (the multilayer Mo / Si stack 15, the cover layer 20, the protective layer 22, the absorber layer 25, the first hard mask layer 30, and the second hard mask layer 32) are narrower than the substrate 10. In some embodiments, the size of the functional layers ranges from approximately 138 mm × 138 mm to 142 mm × 142 mm. In some embodiments, the functional layers are square or rectangular when viewed from above.

[0013] In other embodiments, as in Fig. As shown in Figure 1C, the protective layer 22, the absorber layer 25, the first hard mask layer 30, and the second hard mask layer 32 are smaller in size, in the range of approximately 138 mm × 138 mm to 142 mm × 142 mm, than the substrate 10, the multilayer Mo / Si stack 15, and the cover layer 20. The smaller size of one or more of the functional layers can be achieved by using a frame-shaped cover having an opening in the range of approximately 138 mm × 138 mm to 142 mm × 142 mm during the formation of the respective layers, for example, by sputtering. In other embodiments, all layers above the substrate 10 are the same size as the substrate 10.

[0014] In some embodiments, the multilayer Mo / Si stack 15 comprises approximately 30 to approximately 60 alternating silicon and molybdenum layers. In certain embodiments, approximately 40 to approximately 50 alternating silicon and molybdenum layers are formed. In some embodiments, the reflectivity is higher than approximately 70% for relevant wavelengths, e.g., 13.5 nm. In some embodiments, the silicon and molybdenum layers are formed by chemical vapor deposition (CVD), plasma-enhanced electrochemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), or any other suitable film formation process. Each silicon or molybdenum layer is approximately 2 nm to approximately 10 nm thick. In some embodiments, the silicon and molybdenum layers are approximately the same thickness. In other embodiments, the silicon and molybdenum layers are of varying thicknesses.Molybdenum layers of varying thicknesses are used. In some embodiments, the thickness of each silicon layer is approximately 4 nm, and the thickness of each molybdenum layer is approximately 3 nm.

[0015] In other embodiments, the multilayer stack 15 comprises alternating molybdenum and beryllium layers. In some embodiments, the number of layers in the multilayer stack 15 ranges from about 20 to about 100, although any number of layers is permissible as long as sufficient reflectivity is maintained to image the target substrate. In some embodiments, the reflectivity is higher than about 70% for relevant wavelengths, e.g., 13.5 nm. In some embodiments, the multilayer stack 15 comprises about 30 to about 60 alternating layers of Mo or Be. In other embodiments of the present disclosure, the multilayer stack 15 comprises about 40 to about 50 alternating layers of Mo or Be.

[0016] The top layer 20 is arranged over the Mo / Si multilayer 15 to prevent oxidation of the multilayer stack 15 in some embodiments. In some embodiments, the top layer 20 is made of ruthenium, a ruthenium alloy (e.g., RuNb, RuZr, RuZrN, RuRh, RuNbN, RuRhN, RuV, or RuVN), or a ruthenium-based oxide (e.g., RuO₂, RuNbO, RiVO₄, or RuON) and has a thickness of approximately 2 nm to approximately 10 nm. In certain embodiments, the thickness of the top layer 20 is in the range of approximately 2 nm to approximately 5 nm. In some embodiments, the top layer 20 has a thickness of 3.5 nm ± 10%. In some embodiments, the top layer 20 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition (e.g., sputtering) or any other suitable film formation process.In other embodiments, a Si layer is used as a cover layer 20.

[0017] In some embodiments, a protective layer (intermediate layer) 22 is formed between the top layer 20 and the absorber layer 25. In some embodiments, the protective layer 22 serves to protect the top layer 20. In some embodiments, the protective layer 22 contains: a Ta-based material such as TaB, TaO, TaBO, or TaBN; silicon; a silicon-based compound (e.g., silicon dioxide, SiN, SiON, or MoSi); ruthenium; or a ruthenium-based compound (Ru or RuB). In some embodiments, the protective layer 22 has a thickness of approximately 2 nm to approximately 20 nm. In some embodiments, the protective layer 22 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation process.In some embodiments, the protective layer 22 serves as an etch stop layer during a structuring process of the absorber layer.

[0018] In other embodiments, the intermediate layer 22 is a photocatalytic layer that can catalyze the conversion of hydrocarbon residues formed on the photomask to CO2 and / or H2O using EUV radiation. This results in in-situ self-cleaning of the mask surface. In some embodiments, oxygen and hydrogen gases are introduced into the EUV chamber of the EUV scanner system to maintain the chamber pressure (e.g., at approximately 2 Pa). The chamber background gas can serve as an oxygen source. In addition to its photocatalytic function, the photocatalytic layer is designed to exhibit sufficient durability and resistance to various chemicals and chemical processes, such as cleaning and etching.Ozonated water, used to fabricate the EUV-reflective mask in a subsequent process, can damage the Ru-based top layer 20, leading to a significant reduction in EUV reflectivity. Furthermore, after oxidation of Ru, Ru oxide is readily etched away with an etchant, such as Cl₂ or CF₄ gas. In some embodiments, the photocatalytic layer contains one or more of titanium dioxide (TiO₂), tin oxide (SnO), zinc oxide (ZnO), and cadmium sulfide (CdS). The thickness of the photocatalytic layer 22 ranges from about 2 nm to about 10 nm in some embodiments and from about 3 nm to about 7 nm in others. If the thickness is too small, the photocatalytic layer may not adequately serve as an etch-stop layer. If the thickness is too large, the photocatalytic layer may absorb the EUV radiation.

[0019] The absorber layer 25 is arranged above the intermediate layer (protective layer) 22. In embodiments of the present disclosure, the absorber layer 25 contains a chromium-based material.

[0020] According to the invention, a CrN layer is used as the absorber layer 25. When the CrN layer is used, the amount of nitrogen in some embodiments is in the range of about 16 atomic percent to about 40 atomic percent. According to the invention, the CrN absorber layer has a Cr and a Cr₂N phase. When the amount of nitrogen is in the range of about 33 atomic percent to about 40 atomic percent, the CrN absorber layer has a Cr₂N and a CrN phase. The phases can be viewed by electron energy loss spectroscopy (EELS), transmission electron microscopy (TEM), and / or X-ray diffraction (XRD) analysis. In some embodiments, the two phases form a solid solution.

[0021] In some embodiments, the nitrogen concentration in the absorber layer 25 is not uniform. In some embodiments, the nitrogen concentration in the middle or center of the absorber layer 25 is higher than at a surface region of the absorber layer 25. In some embodiments, the CrN absorber layer contains one or more foreign substances other than Cr and N in an amount of less than about 5 atomic percent. In some embodiments, the absorber layer 25 also contains one or more elements of Co, Te, Hf, and / or Ni.

[0022] In some embodiments, the thickness of the absorber layer 25 is in a range of about 20 nm to about 50 nm, and in other embodiments it is in a range of 35 nm to about 46 nm.

[0023] In some embodiments, an antireflective layer (not shown) is optionally arranged over the absorber layer 25. In some embodiments, the antireflective layer is made of silicon oxide and has a thickness of approximately 2 nm to approximately 10 nm. In other embodiments, a TaBO layer with a thickness in the range of approximately 12 nm to approximately 18 nm is used as the antireflective layer. In some embodiments, the thickness of the antireflective layer is in the range of approximately 3 nm to approximately 6 nm. In some embodiments, the antireflective layer is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation process.

[0024] In some embodiments, the oxide layer 27 contains one or more Cr₂O₃ or CrO₂. In some embodiments, the oxide layer 27 is formed during the manufacturing process for a mask blank. In some embodiments, the thickness of the oxide layer 27 is in the range of approximately 1 nm to approximately 3 nm. In some embodiments, as described in Fig. In 1D representation, no oxide layer is formed.

[0025] In some embodiments, the first hard mask layer 30 is arranged above the oxide layer 27. In some embodiments, the first hard mask layer 30 is formed above the antireflective layer. In some embodiments, the first hard mask layer 30 is made of a Ta-based material such as TaB, TaO, TaBO, or TaBN. In other embodiments, the hard mask layer 30 is made of silicon, a silicon-based compound (e.g., silicon dioxide, SiN, SiON, or MoSi), ruthenium, or a ruthenium-based compound (Ru or RuB). In some embodiments, the first hard mask layer 30 is made of the same or a similar material as the protective layer 22. In some embodiments, the first hard mask layer 30 has a thickness of approximately 2 nm to approximately 20 nm.In some embodiments, the first hard mask layer 30 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition or any other suitable film formation process.

[0026] In some embodiments, the second hard mask layer 32 is arranged over the first hard mask layer 30. In some embodiments, the second hard mask layer 32 is made of one or more of GaN, CrON, CrCON, silicon dioxide, SiCO, and / or yttrium oxide. In some embodiments, the second hard mask layer 32 has a thickness of about 2 nm to about 20 nm. In some embodiments, the second hard mask layer 32 is smaller or larger than the thickness of the first hard mask layer. In some embodiments, the second hard mask layer 32 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation process.

[0027] In some embodiments, the second hard mask layer 32 is made of a material that exhibits a higher etch rate for a chlorine- and oxygen-containing plasma than a material of the first hard mask layer 30. In some embodiments, the first hard mask layer 30 is made of a material that exhibits a higher etch rate for a fluorine-containing plasma than a material of the second hard mask layer 32.

[0028] In some embodiments, one or more of the functional layers above the substrate (the multilayer Mo / Si stack 15, the cover layer 20, the protective layer 22, the absorber layer 25, the oxide layer 27, the first hard mask layer 30 and the second hard mask layer 32) have a polycrystalline structure (e.g. nanocrystalline structure) or an amorphous structure.

[0029] In some embodiments, a conductive backside layer 45 is arranged on a second main surface of the substrate 10, which faces the first main surface of the substrate 10 on which the Mo / Si multilayer 15 is formed. In some embodiments, the conductive backside layer 45 is made of TaB (tantalum boride) or another Ta-based conductive material. In some embodiments, the tantalum boride is crystalline. Crystalline tantalum borides include TaB, Ta5B6, Ta3B4, and TaB2. In other embodiments, the tantalum boride is polycrystalline or amorphous. In other embodiments, the conductive backside layer 45 is made of a Cr-based conductive material (CrN or CrON). In some embodiments, the layer resistance of the conductive backside layer 45 is less than or equal to 20 Ω / □.In certain embodiments, the layer resistance of the conductive backsheet 45 is greater than or equal to 0.1 Ω. In some embodiments, the surface roughness Ra of the conductive backsheet 45 is less than or equal to 0.25 nm. In certain embodiments, the surface roughness Ra of the conductive backsheet 45 is greater than or equal to 0.05 nm. Furthermore, in some embodiments, the flatness of the conductive backsheet 45 is less than or equal to 50 nm (within the EUV photomask). In some embodiments, the flatness of the conductive backsheet 45 is greater than 1 nm. The thickness of the conductive backsheet 45 is in the range of approximately 50 nm to approximately 400 nm in some embodiments. In other embodiments, the conductive backsheet 45 has a thickness of approximately 50 nm to approximately 100 nm. In certain embodiments, the thickness is in the range of approximately 65 nm to approximately 75 nm.In some embodiments, the conductive backside layer 45 is formed by atmospheric chemical vapor deposition (CVD), low-pressure CVD, plasma-enhanced CVD, laser-enhanced CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), physical vapor deposition including thermal evaporation, laser beam evaporation, electron beam evaporation, ion beam-enhanced evaporation and sputtering, or any other suitable film formation process. In cases of CVD, the source gases in some embodiments comprise TaCl5 and BCl3.

[0030] In some embodiments, as in Fig. Figure 1E shows a substrate protection layer 12 formed between the substrate 10 and the multilayer stack 15. In some embodiments, the substrate protection layer 12 is made of Ru or a Ru compound such as RuO, RuNb, RuNbO, RuZr, and RuZrO. In some embodiments, the substrate protection layer 12 is made of the same material as, or a different material than, the cover layer 20. The thickness of the substrate protection layer 12 in some embodiments is in the range of approximately 2 nm to approximately 10 nm.

[0031] Fig. Figures 2A-2F and 3A-3E schematically illustrate a method for producing an EUV photomask for use in extreme ultraviolet lithography (EUVL). It is understood that for additional embodiments of the method before, during, and after the steps described in Figures 2A-2F and 3A-3E, the following steps are required: Fig. Additional operations are provided for in the processes shown in sections 2A-3E, and some of the operations described below may be replaced or omitted. The order of the operations / processes may be interchangeable.

[0032] In the production of an EUV photomask, as described in Fig. 2A shows a first photoresist layer 35 formed over the second hard mask layer 32 of the EUV photomask blank, and the photoresist layer 35 is, as in Fig. 2B is shown, selectively exposed to actinic radiation EB. Before the first photoresist layer 35 is formed, the EUV photomask blank is subjected to inspection in some embodiments. The selectively exposed first photoresist layer 35 is developed to, as shown in Fig. Figure 2C shows the formation of a structure 40 in the first photoresist layer 35. In some embodiments, the actinic radiation EB is an electron beam or an ion beam. In some embodiments, the structure 40 corresponds to a structure of semiconductor device features, for the formation of which the EUV photomask is used in subsequent processes. In some embodiments, the thickness of the first photoresist layer on the second hard mask layer 32 is in the range of about 500 nm to about 1000 nm.

[0033] Next, the structure 40 in the first photoresist layer 35 is extended into the second hard mask layer 32, thereby forming a structure 41 in the second hard mask layer 32 that exposes sections of the first hard mask layer 30, as shown in Fig. The structure 41, which extends into the second hard mask layer 30, is formed, in some embodiments, by etching with a suitable wet or dry etching agent that is selective for the first hard mask layer 30. In some embodiments, a plasma dry etching process using a chlorine-containing gas (e.g., Cl₂, HCl, BCl, and CCl₄) and an oxygen-containing gas (e.g., O₂) is used to structure the second hard mask layer 32. In some embodiments, the material of the first hard mask layer 30 is selected to have a higher etch resistance (a lower etch rate) compared to the plasma dry etching process using chlorine and oxygen, and the etching essentially ends at the first hard mask layer 30.After the structure 41 has been formed in the second hard mask layer 32, the first photoresist layer 35 is removed by a photoresist stripper to expose the upper surface of the second hard mask layer 32, as shown in . Fig. 2E is evident.

[0034] Next, the structure 41 in the second hard mask layer 32 is extended into the first hard mask layer 30, thereby exposing sections of the oxide layer 27, as shown in Fig. 2F is evident. The structure 41, which extends into the first hard mask layer 30, is formed, in some embodiments, by etching with a suitable wet or dry etching agent that is selective for the oxide layer 27. In some embodiments, a plasma dry etching process using a fluorine-containing gas (e.g., hydrogen fluoride (CF4, CHF3, etc.) and SF6) is used to structure the first hard mask layer 30. In some embodiments, the material of the absorber layer 25 is selected to have a higher etch resistance (lower etch rate) compared to the plasma dry etching process using fluorine, and the etching essentially terminates at the oxide layer 27.

[0035] Then the structure 41 in the first and second hard mask layers 30, 32 is extended into the absorber layer 25, thereby forming a structure 42 in the absorber layer 25, which exposes sections of the intermediate layer 22, as shown from Fig. 3A. The oxide layer 27 and the absorber layer 25 are etched using a suitable wet or dry etching agent that is selective for the first hard mask layer 30 and / or the intermediate layer 22. In some embodiments, a plasma dry etching process using a chlorine-containing gas (e.g., Cl₂, HCl, BCl, and CCl₄) and an oxygen-containing gas (e.g., O₂) is used to structure the absorber layer 25. In some embodiments, the material of the intermediate layer 22 is selected to have a higher etch resistance (a lower etch rate) compared to the plasma dry etching process using chlorine and oxygen, and the etching essentially terminates at the intermediate layer 22. In some embodiments, as in Fig. Figure 3A shows the removal of the second hard mask layer 32 during the etching of the oxide layer 27 and the absorber layer 25. In particular, if the second hard mask layer 32 is made of a chromium-based material (e.g., CrON or CrCON), it is removed during the etching of the oxide layer 27 and the absorber layer 25. If the second hard mask layer 32 remains after the etching of the absorber layer 25, some embodiments perform an additional removal process of the second hard mask layer 32 by suitable wet or dry etching.

[0036] Then the first hard mask layer 30 is removed together with part of the absorber layer 25 at the lower end of the structure openings, as shown in Fig. Figure 3B shows that in some embodiments, wet etching and / or dry etching is used. In some embodiments, a plasma dry etching process using a fluorine-containing gas (e.g., hydrogen fluoride (CF4, CHF3, etc.) and SF6) is used to remove the first hard mask layer 30 and the intermediate layer 22. In particular, if the first hard mask layer 30 is made of the same or a similar material as the intermediate layer 22, the first hard mask layer 30 is removed together with the intermediate layer 22. In some embodiments, the material of the top layer 20 is selected to have a higher etch resistance (a lower etch rate) compared to the plasma dry etching process using fluorine, and the etching essentially ends at the top layer 20.

[0037] As in Fig. As shown in Figure 3C, a second photoresist layer 50 is formed above the absorber layer 25, which fills the structure 42 in the absorber layer 25. The second photoresist layer 50 is selectively exposed to actinic radiation such as an electron beam, an ion beam, or UV radiation. The selectively exposed second photoresist layer 50 is developed to form a structure 55 in the second photoresist layer 50, as shown in Figure 3C. Fig. Figure 3C illustrates this. Structure 55 corresponds to a black border surrounding the circuit structures. A black border is a frame-shaped area created by removing each of the multiple layers on the EUV photomask in the region surrounding a circuit structure area. It is created to prevent the exposure of adjacent areas when printing an EUV photomask onto a wafer. The width of the black border varies from approximately 1 mm to approximately 5 mm in some embodiments.

[0038] Next, the structure 55 in the second photoresist layer 50 is extended into the oxide layer 27, the absorber layer 25, the optional intermediate layer 22, the cover layer 20 and the Mo / Si multilayer 15, resulting in a structure 57 (see Fig. 3E) is formed in the oxide layer 27, the absorber layer 25, the intermediate layer 22, the cover layer 20 and the Mo / Si multilayer 15, which exposes sections of the substrate 10, as shown in Fig. The 3D structure is visible. In some embodiments, the structure 57 is formed by etching using one or more wet or dry etching agents that are selective for each of the layers being etched. In some embodiments, plasma dry etching is used.

[0039] Then the second photoresist layer 50 is removed using a suitable photoresist stripper to expose the upper surface of the oxide layer 27, as shown in Fig. As can be seen in Figure 3E. The black border structure 57 in the oxide layer 27, the absorber layer 25, the intermediate layer 22, the top layer 20, and the Mo / Si multilayer 15 defines a black border of the photomask in some embodiments of the disclosure. Furthermore, the photomask undergoes a cleaning process, an inspection, and, if necessary, is repaired to provide a finished photomask.

[0040] Fig. Figure 4 is a cross-sectional view of a finished EUV photomask according to embodiments of the present disclosure. In some embodiments, the EUV photomask has circuit structures 42, as described in Fig. Figure 4 shows a substrate 10, a multilayer Mo / Si stack 15 consisting of several alternating layers of silicon or molybdenum, a cover layer 20, a structured absorber layer 25, and a structured oxide layer 27. Furthermore, a black edge structure 57 is formed in the oxide layer 27, the absorber layer 25, the intermediate layer 22, the cover layer 20, and the Mo / Si multilayer 15, and a conductive backside layer 45 is formed on the back side of the substrate 10. In some embodiments, the structured absorber layer 25 has a CrN layer or a nitrogen-rich CrON or CrCON layer with a nitrogen content in the range of approximately 10 atomic percent to approximately 30 atomic percent in some embodiments.

[0041] Fig. 5A, Fig. 5B and Fig. Figure 5C shows cross-sectional views of a multilayer structure of an absorber layer according to another embodiment of the present disclosure. It is understood that for additional embodiments of the method, additional processes before, during, and after processes that are described by Fig. 2A-3E are shown, and some of the processes described below may be substituted or omitted. The sequence of the processes may be interchangeable. Materials, configurations, processes, and / or dimensions as explained in relation to the preceding embodiments may be applied to the following embodiments, and a detailed description thereof may be omitted. The embodiment of Fig. 5A, Fig. 5B and Fig. 5C is for a mask blank, as it is in Fig. The 1D representation determines where no oxide layer is formed on the absorber layer 25. Fig. 5A shows a structure after the hard mask layer 30, which is similar Fig. The 2F structure is present. The etching of the first hard mask layer 30 essentially ends at the absorber layer 25.

[0042] Then the absorber layer 25 is formed by using the structured first and second hard mask layers as in Fig. 5B is shown structured. In some embodiments, as in Fig. As shown in Figure 5B, the second hard mask layer 32 is removed during the etching of the absorber layer 25. In some embodiments, if the intermediate layer 22 is made of the same or a similar material as the first hard mask layer 30, the etching essentially ends at the intermediate layer 22. Then, as shown in Figure 5B, the second hard mask layer 32 is removed during the etching of the absorber layer 25. In some embodiments, if the intermediate layer 22 is made of the same or a similar material as the first hard mask layer 30, the etching essentially ends at the intermediate layer 22. Fig. 5C shows the first hard mask layer 30 together with a part of the intermediate layer 22 removed at the lower end of the opening structures of the absorber layer 25.

[0043] Fig. Figure 6 shows a cross-sectional view of a finished EUV photomask according to embodiments of the present disclosure. In some embodiments, the EUV photomask has circuit structures 42, as described in Fig. Figure 6 shows a substrate 10, a multilayer Mo / Si stack 15 consisting of several alternating layers of silicon and molybdenum, a cover layer 20, and a structured absorber layer 25. Furthermore, a black edge structure 57 is formed in the absorber layer 25, the cover layer 20, and the Mo / Si multilayer 15, and a conductive back side layer 45 is formed on the back side of the substrate 10. In some embodiments, the structured absorber layer 25 has a CrN layer.

[0044] In general, a chromium-based material (CrN, CrON, or CrCON) exhibits a high EUV absorption coefficient (extinction coefficient) k. For example, CrN has a k-value of 0.0387, which is higher than the k-value (0.031) of TaBN and the k-value (0.027) of TaBO. Accordingly, it is possible to reduce the thickness of the absorber layer (e.g., from 70 nm for TaBN to 46 nm for CrN), thereby suppressing three-dimensional effects of the structured absorber layer. However, a CrN layer is difficult to etch due to its low etch rate. Thus, directly structuring the CrN layer can result in a poor structural profile, which impairs the resolution of EUV lithography. In the present embodiments, two hard mask layers are used to structure the absorber layer, and since the thickness of each of the hard mask layers is relatively thin (2-20 nm), it is possible to control the structural profile of the etched structures.Thus, it is possible to obtain a good structural profile with a higher etch rate and a higher EUV absorption coefficient.

[0045] Fig. Figure 7 shows a flowchart of the production of a mask blank for an EUV photomask according to embodiments of the present disclosure.

[0046] In some embodiments, a multilayer stack 15 is formed over a substrate 10 in S701. Then, in S702, a cover layer 20 is formed on the multilayer stack 15, and in S703, a protective layer 22 is formed on the cover layer 20. Next, in S704, an absorber layer 25 is formed on the cover layer. Afterward, in S705 and S706, a first hard mask layer 30 and a second hard mask layer 32, respectively, are formed. In some embodiments, an oxide layer 27 is formed by oxidation after the absorber layer 25 has been formed and before the hard mask layers. If the hard mask layers are formed after the absorber layer has been formed, without interrupting the vacuum, no oxide layer is formed on the upper surface of the absorber layer 25 in some embodiments.

[0047] Fig. Figure 8A shows a flowchart of a process for manufacturing a semiconductor device, and Fig. 8B, Fig. 8C, Fig. 8D and Fig. Figure 8E shows a sequential fabrication process of the method for manufacturing a semiconductor device according to embodiments of the present disclosure. A semiconductor substrate or other suitable substrate to be structured for the formation of an integrated circuit is provided. In some embodiments, the semiconductor substrate contains silicon. Alternatively or additionally, the semiconductor substrate contains germanium, silicon germanium, or another suitable semiconductor material such as a Group III-V semiconductor material. In Figure S801 of Fig. 8A A target layer to be structured is formed over the semiconductor substrate. In certain embodiments, the target layer is the semiconductor substrate. In some embodiments, the target layer comprises: a conductive layer such as a metallic layer or a polysilicon layer; a dielectric layer such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide; or a semiconductor layer such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed over an underlying structure such as insulating structures, transistors, or wiring. In S802 of Fig. 8A A photoresist layer is formed above the target layer, as shown in Fig. As can be seen in Figure 8B. The photoresist layer is sensitive to radiation from the exposure source during a subsequent photolithography exposure process. In the present embodiment, the photoresist layer is sensitive to EUV light used in the photolithography exposure process. The photoresist layer can be formed over the target layer by spin coating or another suitable method. The applied photoresist layer can further be fired to drive off solvents in the photoresist layer. See Figure 803 of Fig. 8A the photoresist layer is structured using an EUV-reflective mask as shown above, as in Fig. Figure 8B illustrates this process. Structuring the photoresist layer involves performing a photolithography exposure process using an EUV exposure system and the EUV mask. During the exposure process, the IC design structure defined on the EUV mask is mapped onto the photoresist layer to form a latent structure. Structuring the photoresist layer further includes developing the exposed photoresist layer to form a structured photoresist layer with one or more openings. In an embodiment where the photoresist layer is a positive-tone photoresist layer, the exposed portions of the photoresist layer are removed during the development process. Structuring the photoresist layer may also include other process steps, such as different firing steps at various stages.For example, a post-exposure firing process (PEB process) can be implemented after the photolithography exposure process and before the development process.

[0048] S804 of Fig. 8A the target layer is structured using the structured photoresist layer as an etch mask, as shown in Fig. 8D is shown. In some embodiments, structuring the target layer involves applying an etching process to the target layer using the structured photoresist layer as an etch mask. The portions of the target layer exposed within the openings of the structured photoresist layer are etched, while the remaining portions are protected from etching. Furthermore, the structured photoresist layer can be removed by wet stripping or plasma ashing, as shown in Fig. 8E is shown.

[0049] In the present embodiments, two hard mask layers are used to structure the absorber layer, and since the thickness of each hard mask layer is relatively small (2–20 nm), it is possible to control the structural profile of the etched structures. Thus, it is possible to obtain a good structural profile with a higher etch rate and a higher EUV absorption coefficient. Furthermore, since a CrN layer has a higher EUV absorption coefficient, it is possible to reduce the thickness of the absorber layer, which in turn suppresses three-dimensional effects in EUV lithography.

[0050] It is understood that this document does not necessarily discuss all advantages, no particular advantage is required for all embodiments or examples, and other embodiments or examples may offer other advantages. According to one aspect of the present application, a reflective mask comprises a substrate, a reflective multilayer arranged on the substrate, a cover layer arranged on the reflective multilayer, and an absorber layer arranged on the cover layer. The absorber layer comprises a CrN layer. In one or more of the preceding and following embodiments, the thickness of the absorber layer is in the range of 20 nm to 50 nm. In one or more of the preceding and following embodiments, the absorber layer comprises a CrN layer with a nitrogen concentration of 16 atomic percent to 40 atomic percent.According to the invention, the CrN layer comprises a Cr phase and a Cr₂N phase. In one or more of the preceding and following embodiments, the CrN layer comprises a Cr₂N phase and a CrN phase. In one or more of the preceding and following embodiments, the reflective mask further comprises an intermediate layer arranged on the top layer. In one or more of the preceding and following embodiments, the intermediate layer contains at least one of TaB, TaO, TaBO or TaBN, silicon, a silicon-based compound, ruthenium or a ruthenium-based compound. In one or more of the preceding and following embodiments, the intermediate layer contains at least one of titanium dioxide (TiO₂), tin oxide (SnO), zinc oxide (ZnO) or cadmium sulfide (CdS).In one or more of the preceding and following embodiments, the outer circumference of the absorber layer is smaller than the outer circumference of the substrate in plan view. In one or more of the preceding and following embodiments, the outer circumference of the absorber layer is in the range of 138 mm × 138 mm to 142 mm × 142 mm in plan view, and the outer circumference of the substrate is in the range of 148 mm × 148 mm to 152 mm × 152 mm in plan view.

[0051] According to another aspect of the present disclosure, a reflective mask comprises a substrate, a reflective multilayer arranged on the substrate, a cover layer arranged on the reflective multilayer, an absorber layer arranged on the intermediate layer, and a chromium oxide layer arranged on the absorber layer. The absorber layer comprises a chromium-nitrogen (CrN) layer. In one or more of the preceding and subsequent embodiments, the chromium oxide layer comprises Cr₂O₃ or CrO₂. In one or more of the preceding and subsequent embodiments, the chromium oxide layer has a thickness in the range of 1 nm to 3 nm. In one or more of the preceding and subsequent embodiments, the reflective mask further comprises an intermediate layer arranged on the cover layer.In one or more of the preceding and following embodiments, the intermediate layer contains at least one of TaB, TaO, TaBO or TaBN.

[0052] According to another aspect of the present disclosure, a reflective mask blank for an EUV mask comprises a substrate, a reflective multilayer arranged on the substrate, a cover layer arranged on the reflective multilayer, an intermediate layer arranged on the cover layer, an absorber layer arranged on the cover layer, a first hard mask layer arranged over the absorber layer, and a second hard mask layer arranged on the first hard mask layer. In one or more of the preceding and following embodiments, the second hard mask layer is made of a material having a higher etch rate for a chlorine- and oxygen-containing plasma than a material of the first hard mask layer.In one or more of the preceding and following embodiments, the first hard mask layer is made of a material that exhibits a higher etch rate for a fluorine-containing plasma than a material of the second hard mask layer. In one or more of the preceding and following embodiments, the absorber layer comprises a CrN layer.

[0053] According to another aspect of the present disclosure, a photoresist layer is formed over a mask blank in a process for producing a reflective mask. The mask blank comprises a substrate, a reflective multilayer on the substrate, a cover layer on the reflective multilayer, an intermediate layer on the cover layer, an absorber layer on the intermediate layer, a first hard mask layer over the absorber layer, and a second hard mask layer on the first hard mask layer, wherein the absorber layer 25 is made of CrN, and wherein the CrN layer formed comprises a Cr phase and a Cr₂N phase.The photoresist layer is patterned, the second hard mask layer is patterned using the patterned photoresist layer, the first hard mask layer is patterned using the patterned second resist layer, and the absorber layer is patterned using the patterned first hard mask layer and the patterned second hard mask layer. In one or more of the preceding and following embodiments, a first plasma dry etching process using a chlorine-containing gas and an oxygen-containing gas is applied when patterning the second hard mask layer. In one or more of the preceding and following embodiments, the second hard mask layer is made of a material that has a higher etch rate during plasma dry etching than a material of the first hard mask layer.In one or more of the preceding and following embodiments, a second plasma dry etching process using a chlorine-containing gas and an oxygen-containing gas is applied during the structuring of the absorber layer. In one or more of the preceding and following embodiments, the structured second hard mask layer is removed during the second plasma dry etching process. In one or more of the preceding and following embodiments, a first plasma dry etching process using a fluorine-containing gas is applied during the structuring of the first hard mask layer. In one or more of the preceding and following embodiments, the first hard mask layer is made of a material that exhibits a higher etch rate during plasma dry etching than a material of the second hard mask layer.In one or more of the preceding and following embodiments, the intermediate layer is structured using a second plasma dry etching process with a fluorine-containing gas after the absorber layer has been structured. In one or more of the preceding and following embodiments, the intermediate layer is made of a material that exhibits a higher etch rate during the second plasma dry etching process than the material of the second hard mask layer. In one or more of the preceding and following embodiments, the structured first hard mask layer is removed during the second plasma dry etching process.

[0054] According to another aspect of the present disclosure, a photoresist layer is formed over a mask blank in a process for producing a reflective mask. The mask blank comprises a substrate, a reflective multilayer on the substrate, a cover layer on the reflective multilayer, an intermediate layer on the cover layer, an absorber layer on the intermediate layer, a first hard mask layer over the absorber layer, and a second hard mask layer on the first hard mask layer, wherein the absorber layer 25 is made of CrN, and wherein the CrN layer formed comprises a Cr phase and a Cr₂N phase.The photoresist layer is patterned, the second hard mask layer is patterned using the patterned photoresist layer, the first hard mask layer is patterned using the patterned second resist layer, the absorber layer is patterned using the patterned first hard mask layer and the patterned second hard mask layer, and the first hard mask layer is removed. The second hard mask layer and the absorber layer have a chromium-based compound, and the first hard mask layer and the intermediate layer have a ta-based compound. In one or more of the preceding and following embodiments, the second mask layer is made of CrON or CrCON, and the absorber layer is made of CrN, CrON with a nitrogen concentration of 10 atomic percent to 30 atomic percent, or CrCON with a nitrogen concentration of 10 atomic percent to 30 atomic percent.In one or more of the preceding and following embodiments, the first hard mask layer is made of TaBO, Ta2O5, TaO2, TaO, or Ta2O, and the intermediate layer is made of TaBO, Ta2O5, TaO2, TaO, or Ta2O. In one or more of the preceding and following embodiments, the second hard mask layer is removed during the structuring of the absorber layer. In one or more of the preceding and following embodiments, a portion of the intermediate layer is structured during the removal of the first hard mask layer.

[0055] According to another aspect of the present disclosure, a photoresist layer is formed over a mask blank in a process for producing a reflective mask. The mask blank comprises a substrate, a reflective multilayer on the substrate, a cover layer on the reflective multilayer, an intermediate layer on the cover layer, an absorber layer on the intermediate layer, an oxide layer on the absorber layer, a first hard mask layer on the oxide layer, and a second hard mask layer on the first hard mask layer, wherein the absorber layer 25 is made of CrN, and wherein the CrN layer formed comprises a Cr phase and a Cr₂N phase.The photoresist layer is structured, the second hard mask layer is structured using the structured photoresist layer, the first hard mask layer is structured using the structured second resist layer, the oxide layer and the absorber layer are structured using the structured first and second hard mask layers, and the intermediate layer is structured. In one or more of the preceding and subsequent embodiments, the second hard mask layer and the absorber layer comprise a material that exhibits a higher etch rate in plasma dry etching using a chlorine-containing gas and an oxygen-containing gas than a material of the first hard mask layer and a material of the intermediate layer.In one or more of the preceding and following embodiments, the thickness of each of the first and second hard mask layers is in the range of 2 nm to 20 nm. In one or more of the preceding and following embodiments, the second hard mask layer contains GaN, SiCO, or yttrium oxide. In one or more of the preceding and following embodiments, the oxide layer contains Cr₂O₃ or CrO₂.

[0056] The preceding description outlines features of several embodiments or examples to help those skilled in the art better understand the aspects of this disclosure. Those skilled in the art should recognize that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same benefits as the embodiments or examples presented in this document. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of protection of this disclosure and that they can make various changes, substitutions, and modifications therein without deviating from the nature and scope of protection of this disclosure.

Claims

[1] Reflective mask, featuring: a substrate (10); a reflective multilayer (15) arranged on the substrate (10); a cover layer (20) arranged on the reflective multilayer (15); and an absorber layer (25) arranged on the top layer (20), wherein the absorber layer (25) has a CrN layer and wherein the CrN layer has a Cr phase and a Cr2N phase. [2] Reflective mask according to claim 1, wherein the thickness of the absorber layer (25) is in a range of 20 nm to 50 nm. [3] Reflective mask according to claim 1 or 2, wherein the absorber layer (25) has a CrN layer with a nitrogen concentration of 16 atomic % to 40 atomic %. [4] Reflective mask according to one of the preceding claims, further comprising an intermediate layer (22) arranged on the top layer (20). [5] Reflective mask according to claim 4, wherein the intermediate layer (22) contains at least one of TaB, TaO, TaBO or TaBN, silicon, a silicon-based compound, ruthenium or a ruthenium-based compound. [6] Reflective mask according to claim 4, wherein the intermediate layer (22) contains at least one of titanium dioxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) or cadmium sulfide (CdS). [7] Reflective mask according to one of the preceding claims, wherein in a top view the size of an outer circumference of the absorber layer (25) is smaller than the size of an outer circumference of the substrate (10). [8] Method for producing a reflective mask according to any one of claims 1 to 7, wherein the method comprises: Forming a photoresist layer (35) over a mask blank (5), wherein the mask blank (5) comprises a substrate (10), a reflective multilayer (15) on the substrate (10), a cover layer (20) on the reflective multilayer (15), an intermediate layer (22) on the cover layer (20), an absorber layer (25) on the intermediate layer (22), a first hard mask layer (30) over the absorber layer (25) and a second hard mask layer (32) on the first hard mask layer (30); Structuring the photoresist layer (35); Structuring the second hard mask layer (32) using the structured photoresist layer (35, 40); Structuring the first hard mask layer (30) using the structured photoresist layer (35, 40); Removal of the photoresist layer (35); Structuring the absorber layer (25) using the structured first hard mask layer (30) and the structured second hard mask layer (32) and removing the second hard mask layer (32); and Structuring the intermediate layer (22) and removing the first hard mask layer (30), wherein the second hard mask layer (32) and the absorber layer (25) contain a Cr-based compound and the first hard mask layer (30) and the intermediate layer (22) contain a Ta-based compound and wherein the absorber layer (25) is made of CrN and wherein the CrN layer formed has a Cr phase and a Cr2N phase. [9] Method according to claim 8, wherein the second mask layer (32) is made of CrON or CrCON. [10] Method according to claim 8 or 9, wherein the first hard mask layer (30) is made of TaBO, Ta2O5, T-a80,Ta zO,-, TaO2, TaO or Ta2O is produced and the intermediate layer (22) is produced from TaBO, Ta2O5, TaO2, TaO or Ta2O. [11] Method according to any one of claims 8 to 10, wherein the second hard mask layer (32) is removed during the structuring of the absorber layer (25). [12] Method according to any one of claims 8 to 11, wherein during the removal of the first hard mask layer (30) a part of the intermediate layer (22) is structured. [13] Method for producing a reflective mask according to any one of claims 1 to 7, wherein the method comprises: Forming a photoresist layer (35) over a mask blank (5), wherein the mask blank (5) comprises a substrate (10), a reflective multilayer (15) on the substrate (10), a cover layer (20) on the reflective multilayer (15), an intermediate layer (22) on the cover layer (20), an absorber layer (25) on the intermediate layer (22), an oxide layer (27) on the absorber layer (25), a first hard mask layer (30) on the oxide layer (27) and a second hard mask layer (32) on the first hard mask layer (30); Structuring the photoresist layer (35); Structuring the second hard mask layer (32) using the structured photoresist layer (35, 40); Structuring the first hard mask layer (30) using the structured photoresist layer (35, 40); Removal of the photoresist layer (35); Structuring the oxide layer (27) and the absorber layer (25) using the structured first hard mask layer (30) and the structured second hard mask layer (32) and removing the second hard mask layer (32); and Structuring the intermediate layer (22) and removing the first hard mask layer (30), wherein the absorber layer (25) is made of CrN and wherein the CrN layer formed has a Cr phase and a Cr2N phase. [14] Method according to claim 13, wherein the second hard mask layer (32) and the absorber layer (25) comprise a material which has a higher etch rate in plasma dry etching using a chlorine-containing gas and an oxygen-containing gas than a material of the first hard mask layer (30) and a material of the intermediate layer (22). [15] Method according to claim 14, wherein the thickness of each of the first and second hard mask layers (30, 32) is in a range of 2 nm to 20 nm. [16] Method according to claim 14 or 15, wherein the second hard mask layer (32) contains GaN, SiCO or yttrium oxide. [17] Method according to any one of claims 14 to 16, wherein the oxide layer (27) contains Cr2O3 or CrO2.

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