System and method for operating a switching converter at low load

Abstract

Switching converter (300, 1100) for providing an output voltage, wherein the switching converter has the following: an inductor (130) coupled to a first circuit breaker (110) and a second circuit breaker (120) at a switching node, wherein the first circuit breaker (110) is configured to magnetize the inductor (130) and the second circuit breaker (120) is configured to demagnetize the inductor (130); an error amplifier (164) designed to provide a control signal, a signal generator (350, 1150) configured to receive the control signal and to generate a modulated signal with a pulse width that is variable between a minimum pulse width value and a maximum pulse width value, wherein the signal generator (350, 1150) comprises a comparator (420) configured to compare a ramp voltage with the control signal to provide a first logic signal, and a pulse width generator (440) configured to provide a second logic signal; and a control device designed to to control the first and second circuit breakers (110, 120) based on the modulated signal; and Upon identifying that the modulated signal has the minimum pulse width value, a reverse current (240) flowing from the inductor (130) through the second power switch (120) is increased to prevent the output voltage from rising above a setpoint; wherein the control device includes an adapter circuit (810, 910, 1270) designed to generate an adapter current using the first logic signal and the second logic signal; wherein the matching current is increased from a value in a previous cycle when the first logic signal is activated before the second logic signal is deactivated, and wherein the matching current is decreased from a value in the previous cycle when the first logic signal is activated after the second logic signal is deactivated.

Description

Technical area

[0001] The present disclosure relates to a system and a method for operating a switching converter. In particular, the present disclosure relates to a method for controlling the operation of a synchronous rectifier switch of a switching converter under low-load conditions. background

[0002] Switching converters, such as buck (step-down), boost (step-up), or buck-boost (step-down-step-up) converters, operate based on the cyclical magnetization and demagnetization of an inductor, which are associated with the respective increase and decrease of the inductor current. The control of the magnetization and demagnetization phases relies on a pair of circuit breakers, often referred to as the main breaker and the synchronous rectifier breaker. In operation, the main breaker is used to increase the inductor current, and the synchronous rectifier breaker is used to decrease it. Such switching converters depend on the precise timing of the main breaker and the synchronous rectifier breaker's operation; when one is open, the other is closed, and vice versa.

[0003] Such DC-DC converters can operate under various load conditions. When operating under low-load conditions, conventional converters are configured to switch off the synchronous rectifier switch at a point when the inductor current drops to a predetermined value. If the predetermined value is set to zero, the converter can only supply a positive current to the load, and the output voltage increases with each cycle. A pulse-hopping technique can be implemented to prevent the output voltage from rising above a certain level. However, pulse-hopping techniques are not suitable for applications requiring fixed switching frequencies. Alternatively, the predetermined value can be set to a negative value to ensure regulation of the output voltage even when no load current is present. This approach, however, reduces the system's efficiency.

[0004] US Patent 2006 / 0 119 340 A1 describes a power converter 70 designed to prevent operation at a switching frequency within an audible frequency range. The power converter 70 includes a timeout timer 22, a zero-crossing comparator circuit 72, and a zero-crossing shifter circuit 76.

[0005] US patent 2018 / 0 234 014 A1 describes a peak current control boost converter capable of operating in a forced continuous line mode. The boost converter operates in four phases.

[0006] US 2010 / 0 283 442 A1 describes a step-down switching regulator equipped with a PWM comparator 23, a reverse current detection comparator 24 and a timer circuit 26 for determining the turn-on time of the rectifier transistor SW2. Summary

[0007] It is a function of the disclosure to address one or more of the aforementioned limitations. According to a first aspect of the disclosure, a switching converter for providing an output voltage is provided, wherein the switching converter has an inductor coupled to a first power switch and a second power switch at a switching node, the first power switch being configured to magnetize the inductor and the second power switch being configured to demagnetize the inductor; a signal generator being configured to generate a modulated signal with a pulse width variable between a minimum value and a maximum value; and a control device being configured to control the first and second power switches based on the modulated signal.and to increase a reverse current flowing from the inductor through the second power switch to prevent the output voltage from rising above a setpoint upon identification that the modulated signal has the minimum pulse width value. For example, the signal generator may include a voltage-to-pulse converter.

[0008] Optionally, the switching converter includes a feedback circuit configured to generate a control signal to adjust the pulse width based on the output voltage, with the control device configured to increase the reverse current upon identifying that the control signal is configured to reduce the pulse width. For example, the control signal can be an amplified fault voltage.

[0009] Optionally, the control device is designed to provide a control signal for controlling an amount of the return flow and an adjustment signal for adjusting the control signal.

[0010] Optionally, the control device is designed to generate the matching signal based on one or more signals generated by the signal generator.

[0011] Optionally, the control device includes a reference generator configured to produce a reference voltage associated with a certain amount of reverse current. For example, the reference voltage can correspond to a reverse current level above which the second circuit breaker should be switched off (open).

[0012] Optionally, the reference generator is configured to generate the matching signal and to adjust the reference voltage using the matching signal.

[0013] Optionally, the control device includes a comparator designed to compare a voltage at the switching node with the reference voltage in order to generate the control signal.

[0014] Optionally, the matching signal is a matching current, with the reference generator having a matching circuit to generate the matching current.

[0015] Optionally, the signal generator includes a ramp generator configured to provide a ramp voltage based on a base voltage; and a comparator configured to compare the ramp voltage with the control signal to provide an initial logic signal. For example, the initial logic signal can be configured to switch the modulated signal from a high state, such as a logic 1, to a low state, such as a logic 0.

[0016] Optionally, the matching circuit is configured to generate the matching current based on a difference between the base voltage and the control signal.

[0017] Optionally, the signal generator includes a pulse width generator configured to provide a second logic signal, with the matching circuit configured to generate the matching current based on the first logic signal and the second logic signal. For example, the second logic signal can be configured to switch the modulated signal from a low state, for example a logic 0, to a high state, for example a logic 1.

[0018] Optionally, the matching circuit includes a counter that is coupled to a power source.

[0019] Optionally, the signal generator includes a storage device configured to generate the modulated signal based on the first logic signal and the second logic signal, wherein the matching circuit is configured to generate the matching current based on the first logic signal, the second logic signal, and the modulated signal. For example, the storage device can be a latch or a flip-flop.

[0020] Optionally, the adapter circuit includes a charge pump coupled to a voltage-to-current converter.

[0021] Optionally, the control device includes a delay circuit coupled to the signal generator; the delay circuit being configured to delay the control signal based on the matching signal.

[0022] Optionally, the matching signal is a matching current, with the delay circuit including a matching circuit for generating the matching current.

[0023] Optionally, the switching converter is designed for operation with a constant switching frequency.

[0024] According to a second aspect of the disclosure, a method for controlling a switching converter is provided, the converter having an inductor coupled to a first power switch and a second power switch at a switching node, wherein the first power switch is configured to magnetize the inductor and the second power switch is configured to demagnetize the inductor; wherein the method comprises generating a modulated signal with a pulse width variable between a minimum value and a maximum value; controlling the first and second power switches based on the modulated signal to regulate an output voltage of the switching converter; and upon identifying that the modulated signal has the minimum pulse width value, increasing a reverse current flowing from the inductor through the second power switch to prevent the output voltage from rising above a setpoint.

[0025] Optionally, the method includes providing a control signal to control the amount of the return flow and generating an adjustment signal to adapt the control signal.

[0026] Optionally, the method includes providing a reference voltage associated with a quantity of the reverse current and adjusting the reference voltage using the matching signal.

[0027] Optionally, the method includes a delay of the control signal using the adaptation signal.

[0028] Optionally, the inductor provides an inductor current that oscillates between valley and peak values, which vary for different load conditions; with the return current corresponding to a valley inductor current.

[0029] The options described in relation to the first aspect of revelation are also common to the second aspect of revelation. Brief description of the drawings

[0030] The revelation is described in more detail below by way of example and with reference to the accompanying drawings, in which: Fig. 1A is a diagram of a conventional buck or step-down switching converter; Fig. 1B is a diagram of the pulse width of a PWM signal generated as a function of the amplified error voltage; Fig. 2 a flowchart of the method for operating a switching converter according to the disclosure; Fig. 3. A diagram of a circuit for implementing the method of Fig. 2 is; Fig. 4 is a diagram of a voltage-pulse-width converter; Fig. 5A a diagram of an adaptive reverse current limit reference generator for use with the circuit of Fig. 3 is; Fig. 5B a reverse current adaptor for use in the diagram of Fig. 5A is; Fig. 6A and Fig. 6B line diagrams are those that illustrate the operation of the return flow adjuster of Fig. 5B display; Fig. 7. A simulation of the inductor current under a low-load condition and under a normal-load condition using the circuit of the Fig. 5A and Fig. 5B is; Fig. 8 a diagram of another adaptive reverse current limit reference generator for use with the circuit of Fig. 3 is; Fig. 9 a diagram of another adaptive reverse current limit reference generator for use with the circuit of Fig. 3 is; Fig. 10. A simulation of the inductor current under a low-load condition and under a normal-load condition using the circuit of Fig. 9 is; Fig. 11 a diagram of another circuit for implementing the method of Fig. 2 is; Fig. 12 a diagram of an adaptive delay for use with the circuit of Fig. 11 is. Description

[0031] Fig. Figure 1A shows a conventional switching converter, such as a DC-DC step-down converter. The converter 100 includes a main switch MS 110, which is coupled to a synchronous rectifier switch SR 120. The main switch 110 and the synchronous rectifier switch 120 are coupled at a switching node LX.

[0032] An inductor 130 couples the switching node LX to the output node. An output stage control device 140, which includes drivers, is provided to control the main switch 110 or the synchronous rectifier switch 120. The output of the converter is coupled to the input of the output stage control device 140 via a feedback loop provided by an output voltage sensor 162, an error amplifier 164, and a voltage-to-pulse-width converter 150. The voltage sensor 162 can be implemented as a resistor-based voltage divider. The error amplifier 164 has a first input, such as an inverting input, for receiving a feedback voltage VFB from the output voltage sensor 162 and a second input, such as a non-inverting input, for receiving a reference voltage VREF.The error amplifier 164 is provided with suitable gain phase characteristics to control the DC-DC converter in a stable manner.

[0033] The voltage-to-pulse-width converter 150 has a first input for receiving an amplified error voltage VEA from the error amplifier 164 and a second input for receiving an oscillating signal with a period TSW from the oscillator 166.

[0034] The output stage control device 140 has a first input for receiving a pulse width modulation (PWM) signal from the voltage-to-pulse-width converter 150, a second input for receiving a reverse current limit (RLIM) signal from a reverse current limit signal generator 180, and two outputs for controlling the main switch 110 and the synchronous rectifier switch 120, respectively. The output stage control device 140 includes a first driver for controlling the main switch 110 and a second driver for controlling the synchronous rectifier switch. The output stage 140 may also include a logic circuit for receiving the PWM and RLIM signals and a timing circuit to prevent cross-conduction of the main switch and the synchronous rectifier switch.

[0035] The switching converter 100 is also equipped with a reverse current limit reference generator 170 for providing a limit reference voltage VRLIM for the reverse current limit signal generator 180. The reverse current limit signal generator 180 has a first input coupled to the switching node LX, a second input coupled to the output of the reference current limit generator 170, and an output for providing the reverse limit signal RLIM to the output stage control device 140.

[0036] In operation, the voltage output VOUT provided by the switching converter 100 is detected by the voltage sensor 162 and supplied as feedback voltage VFB to the error amplifier 164. The error amplifier 164 compares the feedback voltage VFB with a reference voltage VREF and generates an output voltage VEA, which is then supplied to the voltage-to-pulse-width converter 150.

[0037] The voltage-to-pulse converter 150 receives an oscillating signal with period TSW from the oscillator 166 and generates a pulse-width modulation (PWM) signal with a frequency of 1 / TSW. The PWM signal is then fed to the output stage control device 140, which controls the main switch 110 or the synchronous rectifier switch 120. The main switch 110 is switched on depending on the PWM signal. When the main switch 110 is switched on, the synchronous rectifier switch is switched off, and when the main switch is switched off, the synchronous rectifier switch is fully or partially switched on.

[0038] When the main switch 110 is turned on, a current IL increases, flowing through the inductor and to the output. When the main switch 110 is turned off and the synchronous rectifier switch 120 is turned on, the current IL decreases. To maximize the efficiency of the DC-DC converter under light load conditions, the synchronous rectifier switch 120 should be turned off just before the inductor current IL becomes negative. In this description, the current flowing from the output node to the switching node LX is referred to as the reverse current. The reverse current limit signal generator 180 compares the voltage VLX at the switching node with the limit reference voltage VRLIM provided by the reverse current limit reference generator 170 to generate the reverse current limit signal RLIM. When the output stage control device 140 receives the reverse current limit signal RLIM, it stops the reverse current by turning off (opening) the synchronous rectifier 120.

[0039] Fig. Figure 1B shows the variations in the pulse width TPW of the PWM signal generated by the voltage-to-pulse-width converter 150 as a function of the amplified fault voltage VEA provided by the fault amplifier 164. A minimum pulse width TMIN and a maximum pulse width TMAX are used to control the PWM signal. The maximum pulse width TMAX is less than 100% of the duty cycle. The slope of the pulse width TPW as a function of VEA can be changed depending on various parameters, such as the current flowing through the main switch 110. This is commonly known as current-mode control.

[0040] When the output stage control device 140 stops the reverse current by switching off the synchronous rectifier 120, the DC-DC converter 100 can only supply a positive current to the load. Consequently, under very low load conditions, the current supplied by a minimum pulse width exceeds the load, and the output voltage increases with each cycle. For this reason, a so-called pulse-hopping operation is required to prevent the output voltage from rising above a desired value.

[0041] In pulse-hopping operation, the duty cycle of the main switch 110 is skipped if the amplified fault voltage VEA provided by the fault amplifier 164 is lower than a predetermined voltage. This approach is well suited for regulating the output voltage but is not suitable for applications requiring fixed switching frequencies. Alternatively, the reverse current limit VRLIM can be chosen to allow sufficient reverse current to ensure regulation even when no load current is present. However, using this approach reduces the system's efficiency because it uses more reverse current than is necessary in most conditions.

[0042] Fig. Figure 2 is a flowchart of a method for operating a switching converter according to the disclosure. In step 210, a switching converter is provided. The switching converter includes an inductor coupled to a first power switch and a second power switch at a switching node. The first power switch is configured to magnetize the inductor, and the second power switch is configured to demagnetize the inductor. For example, the second power switch can be a synchronous rectifier transistor. In step 220, a modulated signal is generated. The modulated signal has a pulse width variable between a minimum and a maximum value. In step 230, the first and second power switches are controlled based on the modulated signal to regulate the output voltage.In step 240, the reverse current flowing from the inductor through the second power switch is increased to prevent the output voltage from rising above a setpoint. This is achieved by identifying that the modulated signal has the minimum pulse width value.

[0043] The switching current transformer's inductor exhibits an inductor current that oscillates between valley and peak values. These valley and peak values ​​vary depending on the load conditions. The reverse current corresponds to a valley inductor current. As the load decreases, the negative value of the valley inductor current increases and therefore becomes increasingly negative.

[0044] Using this approach allows for an improvement in the efficiency of the power converter. This can also be achieved when the power converter is operated at a constant switching frequency.

[0045] Fig. Figure 3 is a diagram of a circuit for implementing the method of Fig. 2. The DC-DC converter 300 from Fig. 3 shares several components with the converter 100 from Fig. 1. Similar components were identified with the same reference number and are not described for the sake of brevity.

[0046] In Fig. In section 3, the voltage-to-pulse-width converter 150 was replaced by a voltage-to-pulse-width converter 350, which is configured to provide one or more indicator signals that specify whether the reverse current should be increased, decreased, or held at a certain level in order to maintain regulation of the output voltage of the DC-DC converter with a required minimum amount of reverse current. The reverse current limit reference generator 170 of Fig. 1 was replaced by an adaptive reverse current limit reference generator 370. The adaptive reverse current limit generator 370 has an input for receiving one or more indicator signals from the voltage-to-pulse-width converter 350 and an output for providing an adapted voltage reference limit VRLIM. The nature of the indicator signals can vary depending on the implementation of the adaptive reverse current limit reference generator 370. For example, the indicator signals can include various signals that are either received by or provided by the voltage-to-pulse-width converter 350. For example, the indicator signals can include the amplified fault voltage VEA provided by the fault amplifier, the PWM signal provided by the voltage-to-pulse-width converter, or a ramp signal used in the voltage-to-pulse-width converter 350.

[0047] In circuit 300, the inductor current is detected by sensing the voltage across the synchronous rectifier 120 using the reverse current limit signal generator 180. However, it is obvious that the inductor current can be detected using other techniques. For example, a resistor can be inserted in series with the inductor, and a voltage drop across the resistor can be measured. Alternatively, a current-sensing transformer could be used.

[0048] During operation, when the DC-DC converter 300 operates under low-load conditions, the reverse current is adjusted to the amount required to regulate the output voltage. When the DC-DC converter operates at a constant switching frequency, the reverse current is adjusted to the amount required to regulate the output voltage at that constant switching frequency. This is achieved by controlling when the synchronous rectifier 120 should be switched off. When the DC-DC converter operates under normal or high-load conditions, the reverse current is adjusted to zero, as in typical discontinuous conduction mode (DCM) operation.

[0049] Fig. Figure 4 is a diagram of an example voltage-to-pulse-width converter for use with the converter from Fig. 3. The voltage-to-pulse-width converter 400 comprises a ramp generator 410, a PWM comparator 420, a storage device 430, and a pulse-width generator 440. The ramp generator 410 has an input coupled to the output of the voltage-to-pulse-width converter 400 and an output for providing a ramp signal VRAMP. The PWM comparator 420 has a first input, such as a non-inverting input, for receiving VRAMP, a second input, such as an inverting input, for receiving the amplified error voltage VEA, and an output for providing a comparison signal PWM_CO based on the comparison of VRAMP with VEA, also referred to as the off-trigger signal. The minimum pulse width generator 440 has an input for receiving an oscillator signal and an output for providing a so-called on-trigger signal CK_MIN.

[0050] The memory device 430 has a first input for receiving the PWM_CO signal from the PWM comparator 420, a second input for receiving the CK_MIN signal from the minimum pulse width generator 440, and an output for providing the PWM signal. For example, the memory device 430 can be implemented as a flip-flop, such as an RS (reset-set) latch device. In this case, the PWM_CO signal is provided at the reset input, and CK_MIN is provided at the set input of the RS latch. The trigger signal CK_MIN is synchronous with the oscillator signal and has a pulse width corresponding to the minimum pulse width TMIN. The CK_MIN signal is provided to the RS latch 430 to set the latch and keep the PWM signal high. The ramp generator 410 provides the ramp signal VRAMP, which rises from a base voltage VRB as a function of time while the PWM signal is high.The PWM comparator 420 compares the VRAMP signal with the amplified fault voltage VEA to generate the off-trigger signal PWM_CO. If the VRAMP signal is greater than VEA, the off-trigger signal PWM_CO is applied to the RS latch to reduce the PWM signal. Depending on the specific implementation of the adaptive reverse current limit reference generator 370, the indicator signal can include one or more of the amplified fault voltage VEA, the base voltage signal VRB, the ramp signal VRAMP, the off-trigger signal PWM_CO, the on-trigger signal CK_MIN, and the PWM signal.

[0051] Fig. Figure 5A is a diagram of an adaptive reverse current limit reference generator. The generator 500 includes a reverse current matcher 510 configured to generate a current based on the indicator signals VEA and VRB. The reverse current matcher 510 has a first input for receiving VEA, a second input for receiving VRB, and an output for providing a matching current IA. The output of the reverse current matcher 510 is coupled to the output of a current source 520 and to a resistive component at node A. The resistive component 530 can be selected to exhibit a similar process, voltage, and temperature variation to the on-resistance of the synchronous rectifier switch 120. For example, the resistive component 530 can be a resistor or a transistor with an on-resistance matching that of the synchronous rectifier 120.In operation, the reverse current matcher 510 provides a matching current IA to increase the reverse current as needed to regulate the output voltage of the DC-DC converter. The reverse current matcher 510 compares the amplified fault voltage VEA with the base voltage of the ramp voltage VRB to generate the matching current IA. The matching current IA is then used to match the voltage VRLIM applied at node A. As the matching current IA increases, the voltage VRLIM also increases. Similarly, as the matching current IA decreases, the voltage VRLIM also decreases.

[0052] Fig. Figure 5B shows an exemplary implementation of the reverse current matcher 510. In this example, the reverse current matcher 510 comprises a differential input stage coupled to three current mirrors. It is evident that other types of circuit topologies can be used. The matcher current IA is proportional to the difference VRB-VEA when VEA is less than VRB, and remains zero when VEA is equal to or greater than VRB.

[0053] Fig. Figure 6A shows the variations in the pulse width TPW 610 of the PWM signal generated by the voltage-to-pulse-width converter 350 as a function of the amplified fault voltage VEA. The pulse width 610 is equal to the minimum value TMIN for VEA, which is lower than a voltage slightly higher than VRB.

[0054] Fig. Figure 6B shows the variation of the additional current IA 620 as a function of the amplified fault voltage VEA. If the output voltage VOUT of the DC-DC converter becomes slightly higher than its setpoint due to a lack of reverse current, the amplified fault voltage VEA decreases and at one point becomes lower than the base voltage VRB of the ramp voltage VRAMP. The matching current IA generated by the current matcher 510 begins to increase linearly with a coefficient that depends on the difference between the voltages VEA and VRB. As IA increases, VRLIM increases, and the corresponding amount of reverse current also increases. Finally, the amplified fault voltage VEA converges to a voltage corresponding to the amount of reverse current required for the load condition, and the matching current then remains constant.It is obvious that the ramp voltage VRAMP can be used instead of the base voltage VRB if they are equal at the time when the reverse current limit reference voltage VRLIM is used for comparison.

[0055] Fig. 7 is a simulation of several electrical parameters of the circuit according to Fig. 3, if the adaptive reverse current limit reference generator is configured according to the circuit of Fig. 5 is implemented. Fig. Figure 7 shows simulations of the load current 710, the output voltage 720, the amplified fault voltage VEA 730 of the fault amplifier and the inductor current 740, obtained to increase load conditions as a function of time.

[0056] The peaks and troughs of the inductor current both vary as a function of the load current. Under low-load conditions, for example, for a load current between 0 mA and 4 mA, the peak of the inductor current is a function of the minimum pulse width of the DC-DC converter. The trough of the inductor current, corresponding to the amount of reverse current, is adjusted according to the amplified fault voltage VEA to maintain regulation of the output voltage VOUT. Under higher-load conditions, for example, between 8 mA and 12 mA load current, the trough of the inductor current is controlled to near zero, and the peak of the inductor current is adjusted according to the amplified fault voltage VEA.

[0057] Fig. Figure 8 is a diagram of another adaptive reverse current limit reference generator. The generator 800 includes a reverse current adaptor 810 configured to generate an adaptor current based on two digital display signals. The reverse current adaptor 810 has a first input for receiving the OFF trigger signal PWM_CO, a second input for receiving the ON trigger signal CK_MIN, and an output for providing the adaptor current IA. The output of the reverse current adaptor is coupled to the output of a current source 820 and to a resistor 830 at node A.

[0058] During operation, the matching current IA is increased from a value in the previous cycle when the OFF trigger signal PWM_CO becomes high (i.e., when Vramp > VEA) before the ON trigger signal CK_MIN becomes low. Following the same principle, the matching current IA is decreased from a value in the previous cycle when the OFF trigger signal PWM_CO becomes high after the ON trigger signal CK_MIN becomes low. The reverse current is then adjusted to a minimum amount required to regulate the output voltage of the DC-DC converter for each load condition, and the amplified fault voltage VEA converges to a voltage corresponding to the minimum pulse width TMIN.

[0059] One advantage of this circuit is the fact that the amplified fault voltage VEA remains at a relatively high level compared to the circuit of Fig. 5. In the example of Fig. 5. The voltage VEA is lower than VRB when reverse current is required. In contrast, in the example of Fig. 8. The logic signals PWM_CO and CK_MIN indicate the reverse current, while VEA remains at a level corresponding to the minimum pulse width, which is greater than VRB. As a result, the adaptive reverse current limit reference generator 800 reacts faster to a sudden increase in load current compared to the generator 500. Fig. 5.

[0060] The reverse current matcher 810 can be implemented using various topologies. In the present example, the current matcher 810 comprises a first D-type flip-flop 811, a second D-type flip-flop 812, a counter 813, and a current source 814. The first D-type flip-flop 811 has a data input for receiving the OFF trigger signal PWM_CO, a clock input for receiving the inverse of the ON trigger signal CK_MIN, and an output Q for providing an up count signal. The second D-type flip-flop 812 has a data input for receiving the inverse of the OFF trigger signal PWM_CO, a clock input for receiving the inverse of the ON trigger signal CK_MIN, delayed by an initial delay, and an output Q for providing a down count signal.The counter 813 has a first input for receiving the up-count signal from the first D flip-flop 811, a second input for receiving the down-count signal from the second D flip-flop 812, and a third input for receiving the inverse of the ON trigger signal CK_MIN, delayed by a second delay. The counter 813 also has an output for providing a digital code. The second delay is greater than the first delay. For example, the first delay can be implemented by a first delay line consisting of delay cells 815a and 815b. The second delay can be implemented by a delay line consisting of delay cells 815a, 815b, 815c, and 815d. The current source 814 is connected to the output of the counter 813.In operation, the signals CK_MIN and PWM_CO are used to adapt the digital code that controls the matching current IA provided by the power source 814.

[0061] Fig. Figure 9 is a diagram of another adaptive reverse current limit reference generator. The generator 900 includes a reverse current adaptor 910 configured to generate an adaptor current based on three digital display signals. The reverse current adaptor 910 has a first input for receiving the PWM signal, a second input for receiving the OFF trigger signal PWM_CO, a third input for receiving the ON trigger signal CK_MIN, and an output for providing the adaptor current IA. The output of the reverse current adaptor 910 is connected to the output of a current source 920 and to a resistor 930 at node A.

[0062] In operation, the time difference between a change in the ON trigger signal CK_MIN and a change in the OFF trigger signal PWM_CO is used to improve reverse current control. If the OFF trigger PWM_CO goes high before the ON trigger CK_MIN goes low, with a time difference Δt1, the matching current IA is increased with a positive gradient from a value in the previous cycle. The increase is applied for a duration equal to the time difference Δt1. If the OFF trigger PWM_CO goes high after the ON trigger CK_MIN goes low, with a time difference Δt2, the matching current IA is decreased with a negative gradient from a value in the previous cycle. The decrease is applied for a duration equal to the time difference Δt2.The reverse current is then adjusted to a minimum amount required for proper regulation of the DC-DC converter's output voltage for each load condition, and the error amplifier's output voltage VEA converges to a voltage equal to the minimum pulse width TMIN.

[0063] The reverse current converter 910 can be implemented using various topologies. In the present example, the current converter 910 comprises a control logic circuit, a charge pump, and a voltage-to-current converter. The control logic circuit has a first AND gate 911 and a second AND gate 912. The first AND gate 911 has three inputs for receiving the PWM, PWM_CO, and CK_MIN signals, respectively, and one output for providing a step-up signal. The second AND gate 912 has a first input for receiving the PWM signal, a second input for receiving the inverted CK_MIN signal, and one output for providing a step-down signal. The charge pump comprises a capacitive circuit consisting of a first capacitor 913a connected in series with a second capacitor 913b and a reset switch coupled in parallel with the second capacitor 913b to discharge it.A first current source 914 is coupled to the first capacitor 913a at node B via a first switch 915. A second current source 916 is coupled to the first capacitor 913a via a second switch 917. The first switch 915 is controlled by the upward signal from the control logic circuit and is referred to as the UP switch. Similarly, the second switch 917 is controlled by the downward signal from the control logic circuit and is referred to as the DOWN switch. The voltage-to-current converter comprises a transistor 918 with a first terminal coupled to a current mirror, a second terminal coupled to ground via a resistor 919, and a control terminal, such as a gate terminal, coupled to node B.

[0064] In operation, the indicator signals are used to control the gate voltage V(B) of transistor 918. The current flowing through transistor 918 and resistor 919 is mirrored to the output of the voltage-to-current converter, which is the matching current IA of the reverse current matcher.

[0065] If the OFF trigger PWM_CO becomes high (for example, logic 1) before the ON trigger CK_MIN becomes low (for example, logic 0), the output of the first AND gate 911 is high, while the output of the second AND gate 912 is low. Consequently, the boost switch 915 is turned on (closed) and the buck switch is turned off (open). The first current source 914 provides a source current to charge the capacitive component. The voltage V(B) rises above the threshold of transistor 918, thereby increasing the matching current IA supplied to the resistive components 930.

[0066] When the OFF trigger PWM_CO goes high after the ON trigger CK_MIN goes low, the output of the first AND gate 911 is low, while the output of the second AND gate 912 is high. Consequently, the boost switch is turned off (open) and the buck switch is turned on (closed). The capacitive component discharges, reducing the voltage V(B). This reduces the matching current IA supplied to the resistive components 930.

[0067] To improve the stability and responsiveness of the system, the second capacitor can be discharged by a reset signal RST_P during each cycle. For example, the RST_P signal can be activated after the synchronous rectifier 120 is switched off and before the main switch 110 is switched on. The adaptive reverse current limit reference generator 900 further improves the response time and stability of the system.

[0068] Fig. 10 is a simulation of several electrical parameters of the circuit according to Fig. 3, if the adaptive reverse current limit reference generator is configured according to the circuit of Fig. 9 is implemented. Fig. Figure 10 shows simulations of the load current (1010), output voltage (1020), amplified fault voltage (VEA) (1030), duty cycle (TPW / TSW) (1040), PWM signal, and inductor current (1050). The simulations are intended for conditions with a higher load as a function of time.

[0069] The peaks and troughs of the inductor current both vary as a function of the load current 1010. Under low-load conditions, for example, for a load current between 0 mA and 4 mA, the trough of the inductor current, which corresponds to the amount of reverse current, is adjusted depending on the three indicator signals CK_MIN, PWM_CO, and PWM. The amplified fault voltage VEA 1030 converges to a voltage 1032, which reduces the pulse width of the PWM signal to a minimum value defined by the ON-trigger signal CK_MIN.

[0070] At time t1, the load increases from 0 mA to 4 mA. During this load transient, the amplified fault voltage VEA 1030 rises to maintain regulation of the DC-DC converter's output voltage VOUT. This changes the timing of the OFF trigger signal PWM_CO and, consequently, the pulse width of the PWM signal. The reverse current limit reference generator then gradually adjusts the amount of reverse current until VEA returns to the original voltage 1032, which corresponds to the minimum pulse width of the PWM signal.

[0071] Under conditions with a higher load, for example between 8 mA and 12 mA load current, the valley of the inductor current is controlled to almost zero and the peak of the inductor current is adjusted depending on the amplified fault voltage VEA.

[0072] Fig. Figure 11 is a diagram of another circuit for implementing the method of Fig. 2. The DC-DC converter 1100 from Fig. 11 shares several components with the converter 100 from Fig. 1. Similar components were identified with the same reference number and are not described here for the sake of brevity. Fig. In section 11, the voltage-to-pulse-width converter 150 was replaced by a voltage-to-pulse-width converter 1150, which is configured to provide one or more display signals. An adaptive delay circuit 1110 is provided at the output of the reverse current limit signal generator 180 for delaying RLIM. The adaptive delay circuit 1110 has one or more inputs for receiving display signals, another input for receiving the reverse current limit signal RLIM, and an output for providing the delayed signal RLIM_D. In operation, the delay of the adaptive delay circuit is adjusted depending on the display signals. If the display signals imply a lack of reverse current, the delay is increased. Similarly, the delay is reduced if the display signals imply an excess of reverse current.

[0073] Fig. Figure 12 is an exemplary implementation of an adaptive delay for use with circuit 11. The adaptive delay 1200 comprises a comparator 1210, a capacitor 1220 provided with a discharge switch 1230, a first current source 1240 to provide a current Id, a second current source 1250 to provide a current IB, a resistor 1260, and a reverse current matcher 1270. The reverse current 1270 can be implemented as one of the reverse current matchers that, with respect to the Fig. 5, Fig. 8 and Fig.As described in section 9 above, the reverse current matcher 1270 is coupled to the second current source 1250 and the resistor 1260 at node A. The first current source 1240 is coupled to the capacitor 1220 at node B. The comparator 1210 has a first input coupled to node A, a second input coupled to node B, and an output for providing the delayed signal RLIM_D. In operation, the reverse current matcher provides the matching current IA at node A, thereby varying the voltage at node A. The comparator 1210 compares the voltage at node B with the voltage at node A and generates the delayed signal RLIM_D.

[0074] It is obvious to those skilled in the art that variations of the disclosed arrangements are possible without deviating from the disclosure. Although the proposed method has been described with respect to buck converters, it is obvious that the proposed method can be applied to other types of DC-DC converters. For example, the method can be applied to boost converters or buck-boost converters. Accordingly, the above description of the specific embodiment is only an example and is not intended to limit the scope of the invention. It is obvious to those skilled in the art that minor modifications can be made without significantly altering the described operation.

Claims

[1] Switching converter (300, 1100) for providing an output voltage, wherein the switching converter has the following: an inductor (130) coupled to a first circuit breaker (110) and a second circuit breaker (120) at a switching node, wherein the first circuit breaker (110) is configured to magnetize the inductor (130) and the second circuit breaker (120) is configured to demagnetize the inductor (130); an error amplifier (164) designed to provide a control signal, a signal generator (350, 1150) configured to receive the control signal and to generate a modulated signal with a pulse width that is variable between a minimum pulse width value and a maximum pulse width value, wherein the signal generator (350, 1150) comprises a comparator (420) configured to compare a ramp voltage with the control signal to provide a first logic signal, and a pulse width generator (440) configured to provide a second logic signal; and a control device designed to to control the first and second circuit breakers (110, 120) based on the modulated signal; and Upon identifying that the modulated signal has the minimum pulse width value, a reverse current (240) flowing from the inductor (130) through the second power switch (120) is increased to prevent the output voltage from rising above a setpoint; wherein the control device includes an adapter circuit (810, 910, 1270) designed to generate an adapter current using the first logic signal and the second logic signal; wherein the matching current is increased from a value in a previous cycle when the first logic signal is activated before the second logic signal is deactivated, and wherein the matching current is decreased from a value in the previous cycle when the first logic signal is activated after the second logic signal is deactivated. [2] The switching converter according to claim 1, comprising a feedback circuit configured to generate the control signal for adjusting the pulse width based on the output voltage, wherein the control device is configured to increase the reverse current upon identification that the control signal is configured to reduce the pulse width. [3] The switching converter according to claim 1 or 2, wherein the control device is configured to provide a control signal for controlling an amount of the reverse current, and wherein the matching current is configured to match the control signal. [4] The switching converter according to any one of claims 1 to 3, wherein the control device has a reference generator (370) configured to generate a reference voltage associated with an amount of reverse current. [5] The switching converter according to claim 4, wherein the reference generator (370) is configured to adapt the reference voltage using the matching current. [6] The switching converter according to claim 4 or 5, wherein the control device has a further comparator (180) configured to compare a voltage at the switching node with the reference voltage in order to generate the control signal. [7] The switching converter according to one of claims 4 to 6, wherein the reference generator (370) comprises the matching circuit (810, 910). [8] The switching converter according to one of the preceding claims, wherein the signal generator (350, 1150) has a ramp generator (410) configured to provide the ramp voltage based on a base voltage. [9] The switching converter according to one of the preceding claims, wherein the matching circuit (810, 1270) has a counter (813) which is coupled to a current source (814). [10] The switching converter according to one of the preceding claims, wherein the signal generator (350, 1150) has a storage device (430) configured to generate the modulated signal based on the first logic signal and the second logic signal, wherein the matching circuit (910, 1270) is configured to generate the matching current based on the first logic signal, the second logic signal and the modulated signal. [11] The switching converter according to one of the preceding claims, wherein the matching circuit (910, 1270) comprises a charge pump coupled to a voltage-to-current converter. [12] The switching converter according to any one of claims 3 to 11, wherein the control device has a delay circuit (1110, 1200) coupled to the signal generator (1150); wherein the delay circuit (1110, 1200) is configured to delay the control signal based on the matching current. [13] The switching converter according to claim 12, wherein the delay circuit (1200, 1110) comprises the matching circuit (1270) for generating the matching current. [14] The switching converter according to one of the preceding claims, wherein the switching converter (300, 1100) is configured to operate at a constant switching frequency. [15] Method (200) for controlling a switching converter (300, 1100) comprising an inductor (130) coupled to a first circuit breaker (110) and a second circuit breaker (120) at a switching node, wherein the first circuit breaker (110) is configured to magnetize the inductor (130) and the second circuit breaker (120) is configured to demagnetize the inductor (130); wherein the method comprises: Providing (210) a signal generator (350, 1150) configured to receive a control signal from an error amplifier (164), wherein the signal generator (350, 1150) comprises a comparator (420) configured to compare a ramp voltage with the control signal to provide a first logic signal, and a pulse width generator (440) configured to provide a second logic signal; Generating (220) a modulated signal with a pulse width that varies between a minimum pulse width value and a maximum pulse width value using the signal generator (350, 1150); Controlling (230) the first and second power switches (110, 120) based on the modulated signal to control an output voltage of the switching converter; Providing a matching circuit (810, 910, 1270) designed to generate a matching current using the first logic signal and the second logic signal; and Upon identification (240) that the modulated signal has the minimum pulse width value, increase a reverse current flowing from the inductor (130) through the second power switch (120) to prevent the output voltage from rising above a setpoint; Increasing the adaptor current from a value in a previous cycle when the first logic signal is activated before the second logic signal is deactivated, and decreasing the adaptor current from a value in the previous cycle when the first logic signal is activated after the second logic signal is deactivated. [16] The method according to claim 15, comprising providing a control signal to control an amount of the reverse current, wherein the matching current is configured to match the control signal. [17] The method according to claim 16, comprising providing a reference voltage associated with an amount of reverse current and matching the reference voltage using the matching current. [18] The method according to claim 16 or 17, which includes delaying the control signal using the matching current. [19] The method according to any one of claims 15 to 18, wherein the inductor (130) provides an inductor current that oscillates between valley and peak values ​​that vary for different load conditions; wherein the return current corresponds to a valley inductor current.

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