Thin film transfer using a substrate with an etching stop layer and a diffusion barrier layer

Abstract

Method for forming a semiconductor device, the method comprising: Forming an etch stop layer (17, 207) over a substrate (11, 50, 50A, 50B, 50C, 202, 203); Formation of a first diffusion barrier layer (21, 209) over the etch stop layer (17, 207); Forming a semiconductor device layer above the first diffusion barrier layer (21, 209), wherein the semiconductor device layer (23, 211) includes a transistor; Forming a first interconnection structure (120) over the semiconductor device layer (23, 211) on a front side of the semiconductor device layer (23, 211), wherein the first interconnection structure (120) is electrically coupled to the transistor; Attaching the first intermediate connecting structure (120) to a support (150); Removal of the substrate (11, 50, 50A, 50B, 50C), the etch stop layer (17, 207) and the first diffusion barrier layer (21, 209) after application; and Forming a second interlink structure (136) on a back side of the semiconductor device layer (23, 211) after removal, comprising forming the first diffusion barrier layer (21, 209): Forming a first number of epitaxial silicon layers (12) over the etch stop layer (17, 207); and Forming a second number of partial monolayers with oxygen insertion (14), wherein the second number of partial monolayers with oxygen insertion (14) is nested with the first number of epitaxial silicon layers (12).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. However, with the reduction of minimum feature sizes, additional problems arise that must be addressed.

[0003] US 2018 / 0 061 766 A1 discloses a method for forming a semiconductor device having only semiconductor components with a same first polarity on one side of an insulator layer and only semiconductor components with a different second polarity on an opposite side of the insulator layer, in order to reduce the size and complexity of the integrated circuit and to reduce the process steps associated with the fabrication of the integrated circuit. The method comprises forming an etch stop layer over a substrate, a diffusion barrier layer, and a semiconductor device layer over the diffusion barrier layer.

[0004] From US 2019 / 0 057 959 A1 a semiconductor device is known which has a first level of logic circuits, wherein the logic circuits contain a plurality of first transistors connected to one another by a plurality of metal layers, a thermal insulation layer overlying the first level and a second level of memory circuits, wherein the memory circuits contain an array of memory cells, and wherein the second level overlies the thermal insulation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 illustrates an example of a nanostructure field effect transistor (nano-FET) in a three-dimensional view according to some embodiments. Fig. 2A and Fig. 2B illustrate cross-sectional views of a substrate with an etch stop layer and a diffusion barrier layer according to one embodiment. Fig. 3 illustrates a cross-sectional view of a substrate having an etch stop layer and a diffusion barrier layer according to another embodiment. Fig. 4 illustrates a cross-sectional view of a substrate having an etch stop layer and a diffusion barrier layer according to another embodiment. Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 14D, Fig. 15A, Fig. 15B, Fig. 15C, Fig. 15D, Fig. 15E, Fig. 16A, Fig. 16B, Fig. 16C, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B, Fig. 18C, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B, Fig. 24C, Fig. 25A, Fig. 25B, Fig. 25C, Fig. 26A, Fig. 26B, Fig. 26C, Fig. 27A, Fig. 27B, Fig. 27C, Fig. 28A, Fig. 28B, Fig. 28C, Fig. 29A, Fig. 29B, Fig. 29C, Fig. 30A, Fig. 30B, Fig. 30C, Fig. 31A, Fig. 31B, Fig. 31C, Fig. 32A, Fig. 32B, Fig. 32C, Fig. 33A, Fig. 33B, Fig. 33C, Fig. 33D, Fig. 34A, Fig. 34B and Fig. 34C are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to one embodiment. Fig. 35, Fig. 36A, Fig. 36B and Fig. 37 illustrate a cross-sectional view of a semiconductor package at various stages of manufacturing according to one embodiment. Fig. 38, Fig. 39A, Fig. 39B, Fig. 40 and Fig. 41 illustrate a cross-sectional view of a semiconductor package at various stages of manufacture according to one embodiment. Fig. 42 illustrates a flowchart of a method of forming a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0006] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to facilitate the present invention. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.

[0007] Furthermore, spatial terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for ease of description to describe a relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatial terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial labels used herein may also be interpreted accordingly.Throughout this discussion, the same or a similar reference numeral in different figures refers to the same or a similar element formed by a same or a similar forming process using one or more of the same or similar materials. Furthermore, figures with the same reference numeral but different letters (e.g., .) illustrate the same or a similar element. Fig. 9A, Fig. 9B and Fig. 9C) different views of the same structure at the same manufacturing stage, but along different cross sections.

[0008] According to the invention, a multilayer substrate comprises a sacrificial substrate, an etch stop layer over the sacrificial substrate, a diffusion barrier layer over the etch stop layer, and a semiconductor layer over the diffusion barrier layer. The etch stop layer is formed from a highly doped semiconductor material to provide excellent etch selectivity over the diffusion barrier layer. The diffusion barrier layer comprises alternating layers of silicon and partial monolayers with oxygen insertion, reducing the out-diffusion of the dopant from the etch stop layer into the semiconductor layer of the substrate. As a result, a thin (e.g., <100 nm), high-quality semiconductor layer suitable for forming high-performance semiconductor devices is formed over the diffusion barrier layer.The semiconductor layer can be easily transferred to a workpiece (e.g., a wafer, a carrier, etc.) through a bonding process and a subsequent backside thinning process using selective etching processes enabled by the structure of the substrate.

[0009] Some embodiments discussed herein are described in the context of a die comprising nano-FETs. However, various embodiments may be applied to entire wafers or dies comprising other transistors (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like) instead of or in combination with the nano-FETs.

[0010] Fig. 1 illustrates an example of nano-FETs (e.g., nanowire FETs, nanofoil FETs, or the like) in a three-dimensional view according to some embodiments. The nano-FETs include nanostructures 55 (e.g., nanofoils, nanowires, etc.) over fins 66 on a substrate 50 (e.g., a semiconductor substrate), where the nanostructures 55 serve as channel regions for the nano-FETs. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or a combination thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and between adjacent STI regions 68. Although lower portions of the fins 66 are illustrated as single, continuous materials with the substrate 50, the lower portions of the fins 66 and / or the substrate 50 may comprise a single material or a plurality of materials.In this context, the Finns 66 refer to the part extending between the neighbouring STI regions 68.

[0011] Gate dielectric layers 100 are disposed over top surfaces of the fins 66 and along top surfaces, sidewalls, and bottom surfaces of the nanostructures 55. Gate electrodes 102 are disposed over the gate dielectric layers 100. Epitaxial source / drain regions 92 are disposed on the fins 66 on opposite sides of the gate dielectric layers 100 and the gate electrodes 102.

[0012] Fig. 1 further illustrates reference cross-sections used in later figures. Cross-section AA' is along a longitudinal axis of a gate electrode 102 and, for example, in a direction perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of a nano-FET. Cross-section BB' is parallel to cross-section AA' and extends through the epitaxial source / drain regions 92 of multiple nano-FETs. Cross-section CC' is perpendicular to cross-section AA' and parallel to a longitudinal axis of a fin 66 of the nano-FET and, for example, in a direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Subsequent figures refer to these reference cross-sections for clarity.

[0013] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, or fin field-effect transistors (FinFETs).

[0014] Fig. 2A and Fig. 2B illustrate cross-sectional views of a substrate 50A with an etch stop layer and a diffusion barrier layer according to one embodiment. The substrate 50A, the substrate 50B in Fig. 3 and the substrate 50C in Fig. 4 are various embodiments of the substrate 50 and can be used, for example, in Fig. 1 as the substrate 50 or the substrate 50 in Fig. 5 to 34C can be used.

[0015] With reference to Fig. 2A, the substrate 50A comprises a multilayer substrate including a sacrificial substrate 11 (which may also be referred to as substrate 11). The multilayer structure further includes an etch stop layer 17, a capping layer 19, a diffusion barrier layer 21, and a semiconductor layer 23 (e.g., a layer of epitaxial semiconductor material) formed sequentially over the substrate 11.

[0016] In some embodiments, the substrate is a semiconductor substrate, for example a bulk semiconductor, which may be doped (e.g., with a p- or n-dopant) or undoped. For example, the substrate 11 may be a p - -Substrate or a p + -substrate. As another example, the substrate 11 may have a lower part (e.g., the part under the dashed line 11P in Fig. 2A) which has a p + substrate, and an upper part (e.g. the part above the dashed line 11P in Fig. 2A) which has an epitaxial p - -silicon layer. The substrate 11 may be a wafer, for example, a silicon wafer. In some embodiments, the semiconductor material of the substrate 11 may include silicon; germanium; a compound semiconductor with silicon carbide, a silicon-germanium alloy semiconductor, or combinations thereof.

[0017] In some embodiments, the etch stop layer 17 is a semiconductor material doped with a dopant. The semiconductor material may be, for example, silicon or silicon-germanium, and the dopant may be, for example, boron, phosphorus, arsenic, indium, or antimony. For example, the etch stop layer 17 may be a layer of silicon-germanium (SiGe) doped with boron or a silicon layer doped with boron. The etch stop layer 17 may be formed by a suitable formation method, for example, chemical vapor deposition (CVD). A concentration of the dopant (e.g., boron) in the etch stop layer 17 is, in some embodiments, approximately 2E19 atoms / cm 3 up to about 5E21 atoms / cm 3For example, in an embodiment in which the etch stop layer 17 is boron-doped silicon (also referred to as a Si:B layer), the concentration of boron in the etch stop layer 17 may be about 4E20 atoms / cm 3 As another example, in an embodiment in which the etch stop layer 17 is boron-doped silicon germanium (also referred to as a SiGe:B layer), the concentration of boron in the etch stop layer 17 may be about 2E20 atoms / cm 3A thickness T1 of the etch stop layer 17 may, as an example, be approximately 5 nm to approximately 100 nm. During further processing, the sacrificial substrate 11, the etch stop layer 17, the capping layer 19, and the diffusion barrier layer 21 are removed by one or more etching processes, sometimes in conjunction with mechanical thinning processes, and the etch stop layer 17 functions as an etch stop layer when the portion of the substrate 11 immediately adjacent to the layer 17 is removed by a selective etching process.

[0018] It should be noted that a doped semiconductor layer (e.g., SiGe:B) was used to enhance the performance of the device, for example, improving channel mobility. Therefore, in a conventional design, the doped semiconductor layer can be part of the final product to improve the performance of the formed semiconductor element. However, the doped semiconductor material (e.g., Si:B) of the etch stop layer 17 in the present invention is used as an etch stop layer and removed from the final product. The concentration of the dopant (e.g., boron) in the etch stop layer 17 of the present invention can be orders of magnitude (e.g., dozens of times) higher than that used in a doped semiconductor layer of a conventional design. Such a high doping concentration achieves excellent etch selectivity for the etch stop layer 17. For example, if the substrate 11 (e.g.,When the semiconductor layer 23 (e.g., a silicon substrate) is removed in a subsequent etching process, an etch selectivity of 50 or more is achieved between the substrate 11 and the etch stop layer 17. In other words, the substrate 11 is etched at an etch rate 50 times higher than that of the etch stop layer 17, or even higher. Such high etch selectivity is advantageous for applications in which the semiconductor layer 23 is transferred to another structure. Without the high etch selectivity provided by the disclosed etch stop layer 17, transferring the semiconductor layer 23 may be too time-consuming to be economically feasible. Furthermore, high etch selectivity is advantageous when thickness uniformity of the transferred layer is important to maintain tight device power distributions.However, the high doping concentration in the etch stop layer 17, if not treated, causes the dopant to diffuse out into adjacent layers. The subsequently formed diffusion barrier layer 21 provides protection against the dopant diffusing out of the etch stop layer 17.

[0019] In some embodiments, the capping layer 19, as deposited, is an epitaxial semiconductor layer (e.g., an undoped epitaxial silicon layer) and may be formed by a suitable process such as CVD. The capping layer 19 may act as a buffer layer between the etch stop layer 17 and the diffusion barrier layer 21 to prevent or reduce defects in the epitaxial material of the diffusion barrier layer 21. A thickness of the capping layer 19 is between about 1 nm and about 30 nm in some embodiments.Although the capping layer 19, as deposited, is an undoped layer in some embodiments, the dopant in the etch stop layer 17 diffuses into the capping layer 19 and transforms the capping layer 19 into a doped semiconductor layer, in which case there may be a gradient in the doping concentration in the doped capping layer 19, wherein the doping concentration decreases with increasing distance of the doped capping layer 19 from the etch stop layer 17.

[0020] According to the invention, the diffusion barrier layer 21 is a layer stack comprising silicon layers 12 (see Fig. 2B) with partial oxygen-introduced monolayers 14 nested therebetween. In other words, the diffusion barrier layer 21 comprises alternating layers of silicon layers 12 and partial oxygen-introduced monolayers 14 (which may also be referred to as partial oxygen monolayers or discontinuous oxygen layers). Fig. Figure 2B illustrates an enlarged view of the diffusion barrier layer 21 in a region 10 of Fig. 2A.

[0021] As in Fig. 2B, the diffusion barrier layer 21 includes a first number of silicon layers 12, each of the silicon layers 12 being an undoped epitaxial silicon layer formed, for example, by a CVD process used for epitaxial growth of a semiconductor material. The silicon layer 12 may be formed using a precursor comprising silicon, for example, silane (SiH4), dichlorosilane (DCS), or the like. Each of the silicon layers 12 may, as one example, have a thickness of about 1 nm to about 30 nm. It should be noted that the silicon layers 12 need not have the same thickness, and each of the silicon layers 12 may have any suitable thickness, as will be readily appreciated by one skilled in the art.

[0022] Still referring to Fig. 2B, the diffusion barrier layer 21 further comprises a second number of partial monolayers with oxygen insertion 14. In the illustrated example, the second number is one less than the first number. For example, Fig. 2B, as a non-limiting example, six silicon layers 12 and five partial oxygen-introduced monolayers 14. The number of silicon layers 12 and partial oxygen-introduced monolayers 14 may be any suitable number, as will be readily appreciated by one skilled in the art. A thickness of each of the partial oxygen-introduced monolayers 14 may be less than 0.5 nm. In some embodiments, a concentration of oxygen in each of the second number of partial oxygen-introduced monolayers 14 is several orders of magnitude (e.g., 100 times, 1000 times) higher (or even higher) than a background oxygen concentration level, where the background oxygen concentration level refers to an oxygen level due to unintentional oxygen incorporation, which may originate from the process chamber, a source material, or the wafer surface. The background oxygen concentration level may, for example,depend on the best practices, capabilities and / or requirements for each manufacturing process or product, as would be apparent to a person skilled in the art.

[0023] In some embodiments, each of the partial oxygen-introduced monolayers 14 is an epitaxial silicon layer into which oxygen has been incorporated. Each of the partial oxygen-introduced monolayers 14 may be formed by a same CVD tool used to epitaxially grow the epitaxial silicon layers 12. In some embodiments, a temperature of the CVD process for forming the diffusion barrier layer 12 is between about 400°C and about 800°C. For example, to form a first partial oxygen-introduced monolayer 14, a precursor comprising oxygen (e.g., an oxygen-containing gas) is supplied to the CVD epitaxial tool chamber. The precursor may be carried into the CVD epitaxial tool chamber by a carrier gas, such as H2, N2, or another suitable inert gas.In some embodiments, the oxygen atoms occupy interstitial sites in the silicon lattice to form the partial oxygen-introduced monolayers 14. The above processing to form alternating layers of silicon and partial oxygen-introduced monolayers is repeated until a target number of silicon layers 12 and partial oxygen-introduced monolayers 14 are formed. In some embodiments, the diffusion of the dopant (e.g., boron) of the etch stop layer 17 into adjacent silicon layers (e.g., 23) occurs via an interstitial-mediated mechanism, and therefore the presence of oxygen atoms at the interstitial sites of the partial oxygen-introduced monolayers 14 blocks or reduces dopant diffusion.

[0024] In some embodiments, if the oxygen dosage in the partial monolayer with oxygen insertion 14 is too low, the diffusion barrier layer 21 may not provide sufficient protection against the out-diffusion of the dopant (e.g., boron) from the etch stop layer 17, for example, during subsequent thermal processes, such as an annealing process to activate the dopant in the etch stop layer 17, an annealing process to activate dopants in subsequently formed source / drain regions, or a thermal process in a subsequent deposition process. If the oxygen dosage in the partial monolayer with oxygen insertion 14 is too high, the subsequently formed epitaxial silicon layers 12 may become defective, and high-quality epitaxial material (e.g., 23) for forming high-performance devices may not be formed, as discussed in more detail below.

[0025] In some embodiments, the dosage and / or concentration of oxygen in the partial oxygen-introduced monolayer 14 is selected to enable the formation of a partial oxygen monolayer. Here, the term "partial monolayer" means that the concentration of oxygen in the oxygen-introduced silicon layer 14 is very high (e.g., orders of magnitude or hundreds of times higher than that of a typical oxygen-introduced epitaxial silicon layer used in existing designs) to effectively reduce diffusion of the dopant (e.g., boron) of the etch stop layer 17, but not so high (e.g., as high as a full oxygen monolayer) that the silicon lattice is destroyed.In other words, the partial oxygen monolayer in each of the oxygen-introduced silicon layers 14 enables lattice alignment between an overlying silicon layer 12 and an underlying silicon layer 12. Without lattice alignment, dislocation defects may form in each pair of silicon layer 12 and the partial oxygen-introduced monolayer 14, and a high-quality crystalline semiconductor layer 23 for high-performance devices cannot be formed over the diffusion barrier layer 21. Embodiments of the oxygen-introduced silicon layer 14 are not limited to the example discussed above, but other modifications or variations are also possible, which are intended to be fully within the scope of the present invention.

[0026] Back to Fig. 2A, the semiconductor layer 23 is formed over the diffusion barrier layer 21. The semiconductor layer 23 is a semiconductor epitaxial material, e.g., a silicon epitaxial material formed by a suitable formation method, such as a CVD epitaxial process. During further processing, electrical components, e.g., transistors, are formed in / on the semiconductor layer 23 to form a device layer, and the device layer is then transferred to another semiconductor structure. In an exemplary embodiment, a thickness T2 of the semiconductor layer 23 is less than approximately 100 nm. Without the diffusion barrier layer 21, such a small thickness (e.g., less than 100 nm) may not be achieved because the lower part of the semiconductor layer 23 near the etch stop layer 17 may be covered by out-diffusion of the dopant (e.g.,Boron) from the etch stop layer 17 may become contaminated, and electrical components may need to be formed in an upper portion of the semiconductor layer 23 away from the etch stop layer 17. Therefore, the disclosed diffusion barrier layer 21 enables the formation of a thin semiconductor layer 23 and its use in forming semiconductor devices. The thin semiconductor layer 23, combined with the factor that less etching of the semiconductor layer 23 is required during manufacturing, achieves a smaller total thickness variation (TTV) for the semiconductor layer 23. Furthermore, the thinner semiconductor layer 23 leads to lower material costs and a shorter manufacturing time.

[0027] In some embodiments, the etch stop layer 17 and the diffusion barrier layer 21 are formed in different processing chambers. In some embodiments, the etch stop layer 17, the diffusion barrier layer 21, and the semiconductor layer 23 are formed in the same processing chamber. These and other variations are intended to be fully within the scope of the present invention.

[0028] Fig. 3 illustrates a cross-sectional view of a substrate 50B with an etch stop layer and a diffusion barrier layer according to another embodiment. The substrate 50B is similar to the substrate 50A, but includes a capping layer 15 and a diffusion barrier layer 13 formed beneath the etch stop layer 17. The capping layer 15 and the diffusion barrier layer 13 may be the same or similar to the capping layer 19 and the diffusion barrier layer 21, respectively, and may be formed by a same or similar formation method using one or more of the same or similar materials; therefore, the details are not repeated. In some embodiments, the capping layer 15 may be omitted from the substrate 50B.

[0029] Experiments were conducted to confirm the effectiveness of the diffusion barrier layer 21. For example, a substrate similar to the substrate 50B is provided with an etch stop layer 17 formed of silicon doped with boron (Si:B) and having a boron concentration of 4.5E20 atoms / cm 3 heated in a rapid thermal annealing (RTA) process for about 1.8 seconds at 1090 °C. Compared to a reference substrate without the diffusion barrier layer 21, the substrate 50B with the diffusion barrier layer 21 reduces the diffusion depth of the boron into the semiconductor layer 23 by about 40%.

[0030] Fig. Figure 4 illustrates a cross-sectional view of a substrate 50C with an etch stop layer and a diffusion barrier layer according to another embodiment. The substrate 50C is similar to the substrate 50B in Fig. 3, but has additional layers, such as an etch stop layer 29, capping layers 31, diffusion barrier layers 27 and 33, and an undoped semiconductor layer 25 (e.g., an undoped epitaxial silicon layer). Furthermore, the capping layer 15 is Fig. 3 in the example of Fig. 4 is omitted. The etch stop layer 29 may be the same as or similar to the etch stop layer 17, the capping layer 31 may be the same as or similar to the capping layer 19, and the diffusion barrier layers 27 and 33 may be the same as or similar to the diffusion barrier layers 21 and 13, and therefore the details are not repeated. In some embodiments, a capping layer that is the same as or similar to the capping layer 19 is formed beneath each of the etch stop layers 29 and 17 (e.g., beneath and in physical contact therewith). In one embodiment, the etch stop layers 17 and 29 are boron-doped silicon (e.g., Si:B), the capping layers 31 and 19 are boron-doped silicon (e.g., Si:B), and the undoped semiconductor layer 25 is a layer of undoped epitaxial silicon.

[0031] Fig. 5 to 34C are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to one embodiment. Fig. 5 to 8, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, 29A, 30A, 31A, 32A, 33A and 34A illustrate the reference cross-section A-A' shown in Fig. 1 is illustrated. Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 15D, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B, Fig. 21B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B, Fig. 29B, Fig. 30B, Fig. 31B, Fig. 32B, Fig. 33B and Fig. 34B illustrate the reference cross section B-B' shown in Fig. 1 is illustrated. Fig. 9C, Fig. 10C, Fig. 11C, Fig. 12C, Fig. 13C, Fig. 14C, Fig. 14D, Fig. 15C, Fig. 15E, Fig. 16C, Fig. 17C, Fig. 18C, Fig. 19C, Fig. 20C, Fig. 21C, Fig. 22C, Fig. 23C, Fig. 24C, Fig. 25C, Fig. 26C, Fig. 27C, Fig. 28C, Fig. 29C, Fig. 30C, Fig. 31C, Fig. 32C, Fig. 33C, Fig. 33D and Fig. 34C illustrate the reference cross section C-C' shown in Fig. 1 is illustrated.

[0032] In Fig. 5, a substrate 50 is provided. The substrate 50 may be any of the disclosed embodiments, for example, substrate 50A, substrate 50B, or substrate 50C. For simplicity, details of the substrate 50 may not be illustrated in the following figures.

[0033] Furthermore, Fig. 5, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layers 51 are removed, and the second semiconductor layers 53 are patterned to form channel regions of nano-FETs in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layers 51 may be removed and the second semiconductor layers 53 may be patterned to form channel regions of nano-FETs in the n-region 50N, and the second semiconductor layers 53 may be removed and the first semiconductor layers 51 may be patterned to form channel regions of nano-FETs in the p-region 50P.In some embodiments, the second semiconductor layers 53 may be removed, and the first semiconductor layers 51 may be patterned to form channel regions of nano-FETs in the n-type region 50N, and the first semiconductor layers 51 may be removed, and the second semiconductor layers 53 may be patterned to form channel regions of nano-FETs in the p-type region 50P. In some embodiments, the second semiconductor layers 53 may be removed, and the first semiconductor layers 51 may be patterned to form channel regions of nano-FETs in both the n-type region 50N and the p-type region 50P.

[0034] The multilayer stack 64 is illustrated for illustrative purposes as including three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of the first semiconductor layers 51 and the second semiconductor layers 53. Each of the layers of the multilayer stack 64 may be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.In various embodiments, the first semiconductor layers 51 may be formed from a first semiconductor material suitable for p-nano-FETs, such as germanium or the like, and the second semiconductor layers 53 may be formed from a second semiconductor material suitable for n-nano-FETs, such as silicon, silicon carbon, or the like. The multilayer stack 64 is illustrated for illustrative purposes as having a bottommost semiconductor layer suitable for p-nano-FETs. In some embodiments, the multilayer stack 64 may be formed such that the bottommost layer is a semiconductor layer suitable for n-nano-FETs.

[0035] The first semiconductor materials and the second semiconductor materials may be materials with a high etch selectivity for each other. Accordingly, the first semiconductor layers 51 of the first semiconductor material may be removed without substantially removing the second semiconductor layers 53 of the second semiconductor material, thereby enabling the second semiconductor layers 53 to be patterned to form channel regions of nano-FETs. Similarly, in embodiments in which the second semiconductor layers 53 are removed and the first semiconductor layers 51 are patterned to form channel regions, the second semiconductor layers 53 of the second semiconductor material may be removed without substantially removing the first semiconductor layers 51 of the first semiconductor material, thereby enabling the first semiconductor layers 51 to be patterned to form channel regions of nano-FETs.

[0036] Now with reference to Fig. 6, according to some embodiments, fins 66 are formed in the substrate 50 and nanostructures 55 are formed in the multilayer stack 64. In some embodiments, the nanostructures 55 and the fins 66 may be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively. The etching may be any acceptable etching process, for example, reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. Forming the nanostructures 55 by etching the multilayer stack 64 may further define first nanostructures 52A-52C (collectively referred to as nanostructures 52) from the first semiconductor layers 51 and second nanostructures 54A-54C (collectively referred to as nanostructures 54) from the second semiconductor layers 53.The first nanostructures 52 and the second nanostructures 54 may collectively be referred to as nanostructures 55. In the illustrated embodiment, the fins 66 are formed in the semiconductor layer 23 (see, e.g., FIG. Fig. 2A) of the substrate 50. In some embodiments, the etching process for forming the fins 66 stops before reaching the diffusion barrier layer (e.g., 21 or 33) of the substrate 50, and therefore, the portion of the substrate 50 connected to the fins 66 may correspond to the remaining portions of the semiconductor layer 23 after the etching process.

[0037] The fins 66 and the nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and the nanostructures 55 can be patterned using one or more photolithography processes, including dual patterning or multi-patterning processes. Generally, dual patterning and multi-patterning processes combine photolithography and self-alignment processes, enabling the formation of structures that, for example, have pitches smaller than those otherwise obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process.The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0038] Fig. 6 illustrates the fins 66 in the n-type region 50N and the p-type region 50P as having substantially equal widths for illustrative purposes. In some embodiments, the widths of the fins 66 in the n-type region 50N may be larger or thinner than the fins 66 in the p-type region 50P. Furthermore, although each of the fins 66 and the nanostructures 55 is illustrated as having a constant width throughout, in other embodiments, the fins 66 and / or the nanostructures 55 may have tapered sidewalls such that a width of each of the fins 66 and / or the nanostructures 55 continuously increases in a direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal in shape.

[0039] In Fig. 7, shallow trench isolation (STI) regions 68 are formed adjacent to the fins 66. The STI regions 68 may be formed by depositing an insulating material over the substrate 50, the fins 66, and the nanostructures 55, and between adjacent fins 66. The insulating material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may also be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. An annealing process may be performed once the insulating material is formed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 55.Although the insulating material is illustrated as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a capping layer (not specifically illustrated) may be formed along a surface of the substrate 50, the fins 66, and the nanostructures. A fill material, such as those discussed above, may then be formed over the capping layer.

[0040] A removal process is then applied to the insulating material to remove excess insulating material over the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like, may be used. The planarization process exposes the nanostructures 55 such that the top surfaces of the nanostructures 55 and the insulating material are level after completion of the planarization process.

[0041] The insulating material may then be recessed to form the STI regions 68. The insulating material is recessed such that upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude between adjacent STI regions 68. Further, the top surfaces of the STI regions 68 may have a flat surface, as illustrated, a convex surface, a concave surface (e.g., a bulge), or a combination thereof. The top surfaces of the STI regions 68 may be formed flat, convex, and / or concave by appropriate etching. The STI regions 68 may be recessed using an acceptable etching process, such as one that is selective for the insulating material material (e.g., the insulating material material etches at a faster rate than the material of the fins 66 and the nanostructures 55).For example, oxide removal can be used using dilute hydrofluoric acid (dHF acid).

[0042] The process described above with respect to Fig. 5 to 7 is just one example of how the fins 66 and the nanostructures 55 may be formed. In some embodiments, the fins 66 and / or the nanostructures 55 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or the nanostructures 66. The epitaxial structures may include the alternating semiconductor materials discussed above, for example, the first semiconductor materials and the second semiconductor materials.In some embodiments in which epitaxial structures are grown epitaxially, the epitaxially grown materials may be doped in situ during growth, which may avoid prior and / or subsequent implantation, although in situ and implantation doping may be used together.

[0043] Furthermore, for illustrative purposes only, the first semiconductor layers 51 (and the resulting first nanostructures 52) and the second semiconductor layers 53 (and the resulting second nanostructures 54) are illustrated and discussed herein as having the same materials in the p-type region 50P and the n-type region 50N. Accordingly, in some embodiments, one or both of the first semiconductor layers 51 and the second semiconductor layers 53 may be made of different materials or formed in a different order in the p-type region 50P and the n-type region 50N.

[0044] Furthermore, Fig. 7, suitable wells (not specifically illustrated) may be formed in the fins 66, the nanostructures 55, and / or the STI regions 68. In embodiments with different well types, different implantation steps for the n-region 50N and the p-region 50P may be achieved using a photoresist or other masks (not specifically shown). For example, a photoresist may be formed over the fins 66 and the STI regions 68 in the n-region 50N and the p-region 50P. The photoresist is patterned to expose the p-region 50P. The photoresist may be formed using a spin-on technique and patterned using acceptable photolithography techniques. Once the photoresist is patterned, an implantation of n-type impurities is performed in the p-type region 50P, and the photoresist can act as a mask to essentially prevent the n-type impurities from being implanted into the n-type region 50N.The n-impurity atoms may be phosphorus, arsenic, antimony or the like, which may be present in the region up to a concentration in the range of about 10. 13 atoms / cm 3 up to about 10 14 atoms / cm 3 implanted. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0045] After or before implanting the p-region 50P, a photoresist or other masks (not specifically shown) are formed over the fins 66, the nanostructures 55, and the STI regions 68 in the p-region 50P and the n-region 50N. The photoresist is patterned to expose the n-region 50N. The photoresist may be formed using a spin-on technique and patterned using acceptable photolithography techniques. Once the photoresist is patterned, an implantation of p-type impurities is performed in the n-region 50N, and the photoresist may serve as a mask to prevent the p-type impurities from being implanted into the p-region 50N. The p-type impurities may be boron, boron fluoride, indium, or the like, which may be present in the region to a concentration in the range of about 10 13 atoms / cm 3 up to about 10 14 atoms / cm 3implanted. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0046] After the implantation of the n-type region 50N and the p-type region 50P, annealing may be performed to repair implantation damage and activate the implanted p- and / or n-type impurities. In some embodiments, the growth materials of epitaxial fins may be doped in situ during growth, which may obviate the need for implantation, although in situ and implantation doping may be used together.

[0047] In Fig. 8, a dummy dielectric layer 70 is formed on the fins 66 and / or the nanostructures 55. The dummy dielectric layer 70 may be, for example, silicon dioxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals.The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer 72 may be made of other materials that exhibit high etch selectivity from etching isolation regions. The mask layer 74 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed over the n-type region 50N and the p-type region 50P. Note that the dummy dielectric layer 70 is shown covering only the fins 66 and the nanostructures 55 for illustrative purposes only.In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI regions such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI regions 68.

[0048] Fig. 9A to 21C illustrate various additional steps in the manufacture of the embodiment devices. Fig. 9A to 21C illustrate features in either the n-region 50N or the p-region 50P. In Fig. 9A to 9C, the mask layer 74 (see Fig. 8) using acceptable photolithography and etching techniques to form masks 78. The pattern of the masks 78 can then be transferred to the dummy gate layer 72 and to the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the fins 66. The pattern of the masks 78 can be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76. The dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of respective fins 66.

[0049] In Fig. 10A to 10C, a first spacer layer 80 and a second spacer layer 82 are formed over the structures illustrated in FIGS. 9A to 9C. The first spacer layer 80 and the second spacer layer 82 are subsequently patterned to serve as spacers for forming self-aligned source / drain regions. In Fig. 10A to 10C, the first spacer layer 80 is formed on top surfaces of the STI regions 69; top surfaces and sidewalls of the fins, the nanostructures 55, and the masks 78; and sidewalls of the dummy gates 76 and the dummy gate dielectric 71. The second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 may be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation or deposition by CVD, ALD, or the like. The second spacer layer 82 may be formed from a material with a different etch rate than the material of the first spacer layer 80, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, and deposited by CVD, ALD, or the like.

[0050] After forming the first spacer layer 80 and before forming the second spacer layer 82, implantations for lightly doped source / drain (LDD) regions (not specifically shown) may be performed. In embodiments with different device types, similar to the Fig. 7, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and suitable (e.g., p-type) impurities may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and suitable (e.g., n-type) impurities may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurities may be any of the n-type impurities discussed above, and the p-type impurities may be any of the p-type impurities discussed above. The lightly doped source / drain regions can have a concentration of impurities in the range of about 1 × 10 15 atoms / cm 3 up to about 1 × 10 19 atoms / cm 3Annealing can be used to repair implantation damage and activate the implanted impurities.

[0051] In Fig. 11A to 11C, the first spacer layer 80 and the second spacer layer 82 are etched to form first spacers 81 and second spacers 83. As discussed in more detail below, the first spacers 81 and the second spacers 83 serve to self-align subsequently formed source / drain regions and to protect sidewalls of the fins 66 and / or the nanostructure 55 during further processing. The first spacer layer 80 and the second spacer layer 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like.In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can serve as an etch stop layer when patterning the second spacer layer 82, and such that the second spacer layer 82 can serve as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etch process, wherein the first spacer layer 80 serves as an etch stop layer, while remaining portions of the second spacer layer 82 form second spacers 83, as shown in FIG. Fig. 11B. Therefore, the second spacers 83 serve as a mask when etching exposed parts of the first spacer layer 89 to thereby form first spacers 81, as shown in Fig. 8B and Fig. 8C illustrates.

[0052] As in Fig. 11B, the first spacers 81 and the second spacers 83 are deposited on sidewalls of the fins 66 and / or the nanostructures 55. As shown in Fig. As illustrated in Figure 11C, the second spacer layer 82 may be removed from above the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71, and the first spacers 81 are deposited onto sidewalls of the masks 78, the dummy gates 76, and the dummy gate dielectrics 60. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71.

[0053] It should be noted that the above description generally describes a process for forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be used, different step sequences may be used (e.g., the first spacers 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, and / or the like. Furthermore, the n- and p-type devices may be formed using different structures and steps.

[0054] In Fig. 12A to 12C, according to some embodiments, first recesses 86 and second recesses 87 are formed in the fins 66, the nanostructures 55, and the substrate 50. Epitaxial source / drain regions are then formed in the first recesses 86, and first epitaxial materials and epitaxial source / drain regions are then formed in the second recesses 87. The first recesses 86 and the second recesses 87 may extend through the first nanostructures 52 and the second nanostructures 54 and into the substrate 50. As shown in Fig. 12B, the top surfaces of the STI regions 68 may be flush with the bottom surfaces of the first recesses 86. In various embodiments, the fins 66 may be etched such that bottom surfaces of the first recesses 86 are disposed below the top surfaces of the STI regions 68 or the like. Bottom surfaces of the second recesses 87 may be disposed below the bottom surfaces of the first recesses 86 and the top surfaces of the STI regions 68. The first recesses 86 and the second recesses 87 may be formed by etching the fins 66, the nanostructures 55, and the substrate 50 using anisotropic etching processes such as RIE, NBE, or the like. The first spacers 81, the second spacers 83 and the masks 78 mask portions of the fins 66, the nanostructures 55 and the substrate 50 during the etching processes used to form the first recesses 86 and the second recesses 87.A single etch process or multiple etch processes may be used to etch each layer of the nanostructures 55 and / or the fins 66. Timed etch processes may be used to stop the etching after the first recesses 86 and the second recesses 87 have reached desired depths. The second recesses 87 may be etched using the same processes used to etch the first recesses 86 and an additional etch process before or after etching the first recesses 86. In some embodiments, regions corresponding to the first recesses 86 may be masked while the additional etch process for the second recesses 87 is performed.

[0055] In Fig. 13A to 13C, portions of sidewalls of the layers of the multilayer stack 64 formed from the first semiconductor materials (e.g., the first nanostructures 52) exposed by the first recesses 86 and the second recesses 87 are etched to form sidewall recesses 88. Although sidewalls of the first nanostructures 52 are adjacent to the sidewall recesses 88 in Fig. 13C as being straight, the sidewalls may also be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like. In an embodiment in which the first nanostructures 52 comprise, for example, SiGe and the second nanostructures 54 comprise, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch sidewalls of the first nanostructures 52.

[0056] In Fig. 14A to 14D, first inner spacers 90 are formed in the sidewall recess 88. The first inner spacers 90 can be formed by depositing an inner spacer layer (not specifically illustrated) over structures shown in Fig. 13A to 13C. The first inner spacers 80 serve as separation features between subsequently formed source / drain regions and a gate structure. As discussed in more detail below, source / drain regions and epitaxial materials are formed in the first recesses 86 and the second recesses 87, while the first nanostructures 52 are replaced with corresponding gate structures.

[0057] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer may comprise a material such as silicon nitride or silicon oxynitride, although any suitable material, such as low dielectric constant (low-k) materials with a k value of less than about 3.5, may be used. The inner spacer layer may then be anisotropically etched to form the first inner spacers 90. Although outer sidewalls of the first inner spacers 90 are illustrated as being flush with sidewalls of the second nanostructures 54, the outer sidewalls of the first inner spacers 90 may extend beyond or be recessed from the sidewalls of the second nanostructures 54.

[0058] Although the outer side walls of the first inner spacers 90 in Fig. 14C are illustrated as being straight, the outer side walls of the first inner spacers 90 may be concave or convex. As an example, Fig. 14D illustrates an embodiment in which sidewalls of the first nanostructures 52 are concave, outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from sidewalls of the second nanostructures 54. The inner spacer layer may be etched by an anisotropic etch process, such as RIE, NBE, or the like. The first inner spacers 90 may be used to prevent damage to subsequently formed source / drain regions (e.g., the epitaxial source / drain regions 92 discussed above with respect to FIGS. 12A to 12E) by subsequent etch processes, for example, etch processes used to form gate structures.

[0059] In Fig. 15A to 15E, first epitaxial materials 91 are formed in the second recesses 87, and epitaxial source / drain regions 92 are formed in the first recesses 86 and the second recesses 87. In some embodiments, the first epitaxial materials 91 may be sacrificial materials that are subsequently covered by backside vias (e.g., the backside vias 130 described below with respect to Fig. 32A to 32C). As discussed in Fig. 15B to 15E, the top surfaces of the first epitaxial materials 91 may be flush with bottom surfaces of the first recesses 86. However, in some embodiments, the top surfaces of the first epitaxial materials 91 may be disposed above or below the bottom surfaces of the first recesses 86. The first epitaxial materials 91 may be epitaxially grown in the second recesses 87 using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The first epitaxial materials 91 may comprise any acceptable material, for example, silicon germanium or the like.The first epitaxial materials 91 may be made of materials with high etch selectivity for materials of the epitaxial source / drain regions 92, the substrate 50 and the dielectric layers (e.g., the STI regions 68 and the second dielectric layers 125, which are described below with reference to FIG. Fig. 24A to 24C). Accordingly, the first epitaxial materials 91 can be removed and replaced with the backside vias without significantly removing the epitaxial source / drain regions 92 and dielectric layers.

[0060] The epitaxial source / drain regions 92 are then formed in the first recesses 86 and over the first epitaxial materials 91 in the second recesses 87. In some embodiments, the epitaxial source / drain regions 92 may exert mechanical stress on the second nanostructures 54 to thereby improve performance. As shown in Fig. 15C, the epitaxial source / drain regions 92 are formed in the first recesses 86 and the second recesses 87 such that each dummy gate 76 is disposed between respective adjacent pairs of the epitaxial source / drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the first inner spacers 90 are used to separate the epitaxial source / drain regions 92 from the nanostructures 55 by an appropriate lateral distance so that the epitaxial source / drain regions 92 are not short-circuited to subsequently formed gates of the resulting nano-FETs.

[0061] The epitaxial source / drain regions 92 in the n-type region 50N, e.g., the NMOS region, may be formed by masking the p-type region 50P, e.g., the PMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 and the second recesses 87 in the n-type region. The epitaxial source / drain regions 92 may comprise any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructures 54 are silicon, the epitaxial source / drain regions 92 may comprise materials that impart tensile strain to the second nanostructures 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 may have surfaces elevated from respective top surfaces of the nanostructures 55 and may have facets.

[0062] The epitaxial source / drain regions 92 in the p-type region 50P, e.g., the PMOS region, can be formed by masking the n-type region 50N, e.g., the NMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 and the second recesses 87 in the p-type region 50P. The epitaxial source / drain regions 92 can comprise any acceptable material suitable for p-type nanoFETs. For example, if the first nanostructures 52 are silicon germanium, the epitaxial source / drain regions 92 can comprise materials that exert compressive strain on the first nanostructures 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 92 may also have surfaces that are elevated from respective surfaces of the multilayer stack 56 and may have facets.

[0063] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may have dopants implanted to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, and may then be annealed. The source / drain regions may have a concentration of impurities in the range of approximately 1 × 10 19 atoms / cm 3 up to about 1 × 10 21 atoms / cm 3 The n- and / or p-type impurities for source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0064] As a result of the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the top surfaces of the epitaxial source / drain regions 92 have facets that extend laterally beyond the sidewalls of the nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of a same nano-FET to merge, as shown by Fig. 15B. In other embodiments, adjacent epitaxial source / drain regions 92 may remain separated after completion of the epitaxial process, as shown by Fig. 15D. In the Fig. 15B and Fig. In the embodiments illustrated in FIG. 15D, the first spacers 81 may be formed on top of the STI regions 68 to thereby block epitaxial growth. In some other embodiments, the first spacers 81 may cover portions of the sidewalls of the nanostructures 55 to further block epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers 81 may be adjusted to remove the spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0065] The epitaxial source / drain regions 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed from different semiconductor materials and doped with different doping concentrations. In some embodiments, the first semiconductor material layer 92A may have a doping concentration that is lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C.In embodiments in which the epitaxial source / drain regions 92 include three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0066] Fig. 15E illustrates an embodiment in which sidewalls of the first nanostructures 52 are concave, outer sidewalls of the first inner spacers 90 are concave, and the first inner spacers 90 are recessed from sidewalls of the second nanostructures 54. As in Fig. 15E, the epitaxial source / drain regions 92 may be formed in contact with the first inner spacers 90 and extend beyond the sidewalls of the second nanostructures 54.

[0067] In Fig. 16A to 16C, a first interlayer dielectric (ILD) 96 is deposited over the structures illustrated in FIGS. 15A to 15C. The first ILD 96 may be formed from a dielectric material and deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may also be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the masks 78, and the first spacers 81.The CESL 94 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, with a different etch rate than the material of the overlying first ILD 96.

[0068] In Fig. 17A to 17C, a planarization process, such as CMP, may be performed to level the first ILD 96 with the top surfaces of the dummy gates 76 or the masks 78. The planarization process may also remove the masks 78 on the dummy gates 76 and portions of the first spacers 81 along the sidewalls of the masks 78. After the planarization process, the top surfaces of the dummy gates 76, the first spacers 81, and the first ILD 96 are leveled within process variations. Accordingly, the top surfaces of the dummy gates 76 are exposed through the first ILD 96. In some embodiments, the masks 78 may remain, in which case the planarization process levels the top surface of the first ILD 96 with the top surfaces of the masks 78 and the first spacers 81.

[0069] In Fig. 18A to 18C, the dummy gates 76 and the masks 78, if present, are removed in one or more etching steps to form third recesses 98. Portions of the dummy gate dielectrics 60 in the third recesses 98 are also removed. In some embodiments, the dummy gates 76 and the dummy gate dielectrics 60 are removed by an anisotropic dry etching process. For example, the etching process may comprise a dry etching process using reactant gas(es) that selectively etches the dummy gates 76 at a faster rate than the first ILD 96 or the first spacers 81. Each of the third recesses 98 exposes or overlies portions of nanostructures 55 that serve as channel regions in later completed nano-FETs. Portions of the nanostructures 55 serving as the channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92.During removal, the dummy gate dielectrics 60 can be used as etch stop layers when the dummy gates 76 are etched. The dummy gate dielectrics 60 can then be removed after the dummy gates 76 are removed.

[0070] In Fig. 19A to 19C, the first nanostructures 52 are removed to extend the third recesses 98. The first nanostructures 52 may be removed by performing an isotropic etching process, such as wet etching or the like, using etchants selective for the materials of the first nanostructures 52, while the second nanostructures 54, the substrate 50, and the STI regions 68 remain relatively unetched compared to the first nanostructures 52. In embodiments where the first nanostructures 52 comprise, for example, SiGe, and the second nanostructures 54A-54C comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructures 52.

[0071] In Fig. 20A to 20C, gate dielectric layers 100 and gate electrodes 102 for replacement gates are formed. The gate dielectric layers 100 are conformally deposited into the third recesses 98. The gate dielectric layers 100 may be formed on top surfaces and sidewalls of the substrate 50, as well as on top surfaces, sidewalls, and bottom surfaces of the second nanostructures 54. The gate dielectric layers 100 may also be deposited on top surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the STI regions 68, as well as on sidewalls of the first spacers 81 and the first inner spacers 90.

[0072] According to some embodiments, the gate dielectric layers 100 include one or more dielectric layers, such as oxide, metal oxide, the like, or combinations thereof. For example, in some embodiments, the gate dielectrics may include a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers 100 include a high-k dielectric material, and in these embodiments, the gate dielectric layers 100 may have a k value greater than about 7.0, and they may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers 100 may be the same or different in the n-type region 50N and the p-type region 50P.The formation methods of the gate dielectric layers 100 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0073] The gate electrodes 102 are each deposited over the gate dielectric layers 100 and fill the remaining portions of the third recesses 98. The gate electrodes 102 may comprise a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Although, for example, single-layer gate electrodes 102 are Fig. 17A and Fig. 17C, the gate electrodes 102 may include any number of cap layers, any number of work function tuning layers, and a fill material. Any combination of the layers forming the gate electrodes 102 may be deposited into the n-type region 50N between adjacent ones of the second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and into the p-type region 50P between adjacent ones of the first nanostructures 52.

[0074] The formation of the gate dielectric layers 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layers 100 in each region may be formed from the same materials, and the formation of the gate electrodes 102 may occur simultaneously, such that the gate electrodes in each region may be formed from the same materials. In some embodiments, the gate dielectric layers 100 in each region may be formed by different processes, such that the gate dielectric layers 100 may be different materials and / or have a different number of layers, and the gate electrodes 102 in each region may be formed by different processes, such that the gate electrodes 102 may be different materials and / or have a different number of layers.Different masking steps can be used to mask and expose appropriate regions when different processes are used.

[0075] After filling the third recesses 98, a planarization process, such as CMP, may be performed to remove excess portions of the gate dielectric layers 100 and the material of the gate electrodes 102, which are excess portions above the top surface of the first ILD 96. The remaining portions of material of the gate electrodes 102 and the gate dielectric layers 100 thus form replacement gate structures of the resulting nano-FETs. The gate electrodes 102 and the gate dielectric layers 100 may collectively be referred to as "gate structures."

[0076] In Fig. 21A to 21C, the gate structures (which include the gate dielectric layers 100 and the corresponding overlying gate electrodes 102) are recessed, such that recesses are formed directly above the gate structures and between opposing portions of the first spacers 81. Gate masks 104 comprising one or more layers of dielectric material, for example, silicon nitride, silicon oxynitride, or the like, are filled into the recesses, followed by a planarization process for removing excess portions of the dielectric material extending over the first ILD 96. Subsequently formed gate contacts (for example, the gate contacts 114, which will be described below with reference to Fig. 20A to 20C) penetrate through the gate masks 104 to contact the top surfaces of the recessed gate electrodes 102.

[0077] As further shown by Fig. As illustrated in Figures 21A through 21C, a second ILD 106 is deposited over the first ILD 96 and over the gate masks 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the ILD 106 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like.

[0078] In Fig. 22A to 22C, the second ILD 106, the first ILD 96, the CESL 94, and the gate masks 104 are etched to form fourth recesses 108 exposing surfaces of the epitaxial source / drain regions 92 and / or the gate structures. The fourth recesses 108 may be formed by etching using an anisotropic etch process, such as RIE, NBE, or the like. In some embodiments, the fourth recesses 108 may be etched through the second ILD 106 and the first ILD 96 using a first etch process; etched through the gate masks 104 using a second etch process; and then etched through the CESL 94 using a third etch process. A mask, such as a photoresist, may be formed and patterned over the second ILD 106 to mask portions of the second ILD 106 from the first etch process and the second etch process.In some embodiments, the etch process may overetch, and therefore the fourth recesses 108 may extend into the epitaxial source / drain regions 92 and / or the gate structures, and a bottom of the fourth recesses 108 may be level with (e.g., at the same level or at the same distance from the substrate 50) or below (e.g., closer to the substrate 50) the epitaxial source / drain regions 92 and / or the gate structures. Although. Fig. 22C, the fourth recesses 108 are illustrated as exposing the epitaxial source / drain regions 92 and the gate structures in a same cross-section, the epitaxial source / drain regions 92 and the gate structures may be exposed in different cross-sections in various embodiments to thereby reduce the risk of short-circuiting subsequently formed contacts.

[0079] After the formation of the fourth recesses 108, first silicide regions 110 are formed over the epitaxial source / drain regions 92. In some embodiments, the first silicide regions 110 are formed by first depositing a metal (not specifically illustrated) capable of reacting with the semiconductor materials of the underlying epitaxial source / drain regions 92 (e.g., silicon, silicon-germanium, germanium) to form silicide or germanide regions, for example, nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys, over the exposed portions of the epitaxial source / drain regions 92 and subsequently performing a thermal annealing process to form the first silicide regions 110. The unreacted portions of the deposited metal are then removed, for example, by an etching process.Although the first silicide regions 110 are referred to as silicide regions, the first silicide regions 110 may also be germanide regions or silicon-germanide regions (e.g., regions comprising silicide and germanide). In one embodiment, the first silicide regions 110 comprise TiSi and have a thickness in a range of about 2 nm to about 10 nm.

[0080] In Fig. 23A to 23C, source / drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed in the fourth recesses 108. The source / drain contacts 112 and the gate contacts 114 may each include one or more layers, such as barrier layers, diffusion layers, and fill materials. For example, in some embodiments, the source / drain contacts 112 and the gate contacts 114 each include a barrier layer and a conductive material and are each electrically coupled to an underlying conductive feature (e.g., a gate electrode 102 and / or a first silicide region 110). The gate contacts 114 are electrically coupled to the gate electrodes 102, and the source / drain contacts 112 are electrically coupled to the first silicide regions 110. The barrier layer may comprise titanium, titanium nitride, tantalum, tantalum nitride or the like.The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, for example, CMP, may be performed to remove excess material from the surfaces of the second ILD 106. The epitaxial source / drain regions 92, the second nanostructures 54, and the gate structures (including the gate dielectric layers 100 and the gate electrodes 102) may collectively be referred to as transistor structures 109. The transistor structures 109 may be formed in a device layer, wherein a first interconnect structure (such as the front-side interconnect structure 120, described below with reference to FIG. Fig. 24A to 24C) is formed over a front side thereof, and a second interconnect structure (such as the rear interconnect structure 136 discussed below with respect to Fig. 34A to 34C) is formed over a backside thereof. Although the device layer is described as including nano-FETs, other embodiments may include a device layer with other types of transistors (e.g., planar FETs, FinFETs, thin film transistors (TFTs), or the like).

[0081] Although Fig. 23A to 23C illustrate a source / drain contact 112 extending to each of the epitaxial source / drain regions 92, the source / drain contacts 112 may be omitted from certain of the epitaxial source / drain regions 92. For example, as will be explained in more detail below, conductive features (e.g., backside vias or power rails) may subsequently be applied through a backside of one or more of the epitaxial source / drain regions 92. For these specific epitaxial source / drain regions 92, the source / drain contacts 112 may be omitted or may be dummy contacts connected to overlying conductive lines (e.g., the first conductive features 122 described below with reference to Fig. 24A to 24C) are not electrically connected.

[0082] Fig. 24A to 34C illustrate intermediate steps for forming front-side interconnect structures and back-side interconnect structures on the transistor structures 109. The front-side interconnect structures and the back-side interconnect structures may each include conductive features electrically connected to the nano-FETs formed on the substrate 50. The Fig. The process steps described in Figures 24A to 34C can be applied to both the n-type region 50N and the p-type region 50P. As previously mentioned, the backside conductive feature (e.g., a backside via or a power rail) can be connected to one or more of the epitaxial source / drain regions 92. Accordingly, the source / drain contacts 112 can optionally be omitted from the epitaxial source / drain regions 92.

[0083] In Fig. 24A to 24C, a front-side interconnect structure 120 is formed on the second ILD 106. The front-side interconnect structure 120 may be referred to as a front-side interconnect structure because it is formed on a front side of the transistor structures 109 (e.g., a side of the transistor structures 109 on which active devices are formed).

[0084] The front-side interconnect structure 120 may include one or more layers of first conductive features 122 formed in one or more stacked first dielectric layers 124. Each of the stacked first dielectric layers 124 may include a dielectric material, such as a low-k dielectric material, an ultra-low-k (ELK) dielectric material, or the like. The first dielectric layers 124 may be deposited using a suitable process, such as CVD, ALD, PVD, PECVD, or the like.

[0085] The first conductive features 122 may include conductive lines and conductive vias that interconnect the layers of conductive lines. The conductive vias may extend through respective ones of the first dielectric layers 124 to provide vertical connections between layers of conductive lines. The first conductive features 122 may be formed by any suitable process, for example, a damascene process, a double damascene process, or the like.

[0086] In some embodiments, the first conductive features 122 may be formed using a damascene process in which a respective first dielectric layer 124 is patterned using a combination of photolithography and etching techniques to form trenches corresponding to the desired structure of the first conductive features 122. An optional diffusion barrier and / or adhesion layer may be deposited, and the trenches may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like.In one embodiment, the first conductive features 122 may be formed by depositing a seed layer of copper or a copper alloy and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the respective first dielectric layer 124 and to planarize surfaces of the first dielectric layer 124 and the first conductive features 122 for further processing.

[0087] Fig.24A to 24C illustrate five layers of first conductive features 122 and first dielectric layers 124 in front-side interconnect structure 120. However, it should be understood that front-side interconnect structure 120 may include any number of first conductive features 122 disposed within any number of first dielectric layers 124. Front-side interconnect structure 120 may be electrically connected to gate contacts 114 and source / drain contacts 112 to form functional circuitry. In some embodiments, the functional circuitry formed by the front-side interconnect structure may include logic circuitry, memory circuitry, image sensor circuitry, or the like.

[0088] In Fig. 25A to 25C, a carrier substrate 150 (which may also be referred to as a carrier) is bonded to a top surface of the front-side interconnect structure 120 by a first bonding layer 152A and a second bonding layer 152B (collectively referred to as bonding layer 152). The carrier substrate 150 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), or the like. The carrier substrate 150 may provide structural support during further processing steps and in the finished device.

[0089] In various embodiments, the support substrate 150 may be bonded to the front-side interconnect structure 120 using a suitable technique, such as dielectric-to-dielectric bonding or the like. The dielectric-to-dielectric bonding may include depositing the first bonding layer 152A onto the front-side interconnect structure 120. In some embodiments, the first bonding layer 152A may comprise silicon oxide (e.g., high-density plasma (HDP) oxide or the like) deposited by CVD, ALD, PVD, or the like. The second bonding layer 152B may also be an oxide layer formed on a surface of the support substrate 150 prior to bonding, for example, using CVD, ALD, PVD, thermal oxidation, or the like. Other suitable materials may also be used for the first bonding layer 152A and the second bonding layer 152B.

[0090] The dielectric-to-dielectric bonding process may further include applying a surface treatment to one or more of the first bonding layer 152A and the second bonding layer 152B. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water or the like) that may be applied to one or more of the bonding layers 152. The carrier substrate 150 is then aligned with the front-side interconnect structure 120, and the two are pressed against each other to initiate pre-bonding of the carrier substrate 150 to the front-side interconnect structure 120.

[0091] Furthermore, in Fig. 25A to 25C, after bonding the carrier substrate 150 to the front-side interconnect structure 120, the device may be turned over so that a backside of the transistor structures 109 faces upwards. The backside of the transistor structures 109 may refer to a side opposite the front side of the transistor structures 109 on which the active components are formed. It should be noted that a detailed structure of the substrate 50, which is the same as the substrate 50B of Fig. 3 is, in Fig. 25A to 25C as a non-limiting example. It will be readily apparent to one skilled in the art that other embodiments of the substrate 50 (e.g., 50A, 50C) may also be used.

[0092] In Fig. 26A to 26C, portions of the substrate 50 distal from the support substrate 150, such as the substrate 11 (e.g., a silicon substrate), the diffusion barrier layer 13, and the capping layer 15, are selectively removed by an etching process using an etchant selective for the materials of the substrate 11, the diffusion barrier layer 13, and the capping layer 15. For example, a combination of a mechanical wafer thinning process and an etching process using a mixture of hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH), and TMAH as the etchant may be performed to selectively remove the substrate 11, the diffusion barrier layer 13, and the capping layer 15 and expose the etch stop layer 17.

[0093] In Fig. 27A to 27C, the etch stop layer 17 is selectively removed by an etching process using an etchant selective for the material of the etch stop layer 17. For example, for an etch stop layer 17 comprising silicon germanium (e.g., SiGe:B), an etching process using a mixture of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH) can be performed to selectively remove the etch stop layer 17. After the selective etching of the etch stop layer 17, the capping layer 19 is exposed.

[0094] In Fig. 28A to 28C, a planarization process, for example, CMP, is performed to remove the capping layer 19 and the diffusion barrier layer 21. The semiconductor layer 23 is exposed after the planarization process. Fig. The processing steps shown in Figures 25A to 28C illustrate the transfer of the device layer (which includes the semiconductor layer 23 and the electrical components, such as transistors, formed thereon) and the front-side interconnect structure 120 to the carrier substrate 150.

[0095] It should be noted that in the processing steps of Fig. 25A to 28C, the substrate 50B is used as an example. A person of ordinary skill in the art, after reading this description, will be able to adapt the processing steps for other types of substrates (e.g., 50A and 50C). Consider, for example, an example in which the substrate 50 has the structure of the substrate 50C of Fig. 4. In particular, consider an example in which the etch stop layers 17 / 29 and the capping layers 19 / 31 are boron-doped silicon (Si:B) and the undoped semiconductor layer 25 is undoped epitaxial silicon. The following processing steps may be followed to transfer the device layer and the front-side interconnect structure 120 to the support substrate 150: A first portion of the substrate 11 distal from the support substrate 150 may be removed by a grinding process. Next, a second portion of the substrate 11, which is exposed after the grinding process, may be removed by etching using a mixture of hydrofluoric acid (HF), nitric acid (HNO3), and acetic acid (CH3COOH). Next, an etching process using TMAH is performed to selectively remove the remaining part of the substrate 11 and the diffusion barrier layer 13.Next, an etching process using a mixture of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH) is performed to selectively remove the etch stop layer 17 and the capping layer 19. Next, an etching process using TMAH is performed to selectively remove the diffusion barrier layer 21, the undoped semiconductor layer 25, and the diffusion barrier layer 27. Next, an etching process using a mixture of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH) is performed to selectively remove the etch stop layer 29 and the capping layer 31. A CMP process may next be performed to remove the diffusion barrier layer 33 and expose the semiconductor layer 23.

[0096] In Fig. 29A to 29C, a thinning process may be applied to the semiconductor layer 23 of the substrate 50. The thinning process may include a planarization process (e.g., CMP), an etch-back process, a combination thereof, or the like. The thinning process may expose surfaces of the first epitaxial materials 91 to the front-side interconnect structure 120. Furthermore, after the thinning process, a portion of the semiconductor layer 23 of the substrate 50 may remain above the gate structures (e.g., the gate electrodes 102 and the gate dielectric layers 100) and the nanostructures 55. As shown in Fig. 29A to 29C, back surfaces of the substrate 50, the first epitaxial materials 91, the STI regions 68, and the fins 66 may be level with each other after the thinning process.

[0097] In Fig. 30A to 30C, remaining portions of the fins 66 and the substrate 50 are removed and replaced with a second dielectric layer 125. The fins 66 and the substrate 50 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. The etching process may be one that is selective to the material of the fins 66 and the substrate 50 (e.g., etches the material of the fins 66 and the substrate 50 at a faster rate than the material of the STI regions 68, the gate dielectric layers 100, the epitaxial source / drain regions 92, and the first epitaxial materials 91). After etching the fins 66 and the substrate 50, the surfaces of the STI regions 68, the gate dielectric layers 100, the epitaxial source / drain regions 92 and the first epitaxial materials 91 may be exposed.

[0098] Then, the second dielectric layer 125 is deposited on the backside of the transistor structures 109 in recesses formed by removing the fins 66 and the substrate 50. The second dielectric layer 125 may be deposited over the STI regions 68, the gate dielectric layers 100, and the epitaxial source / drain regions 92. The second dielectric layer 125 may physically contact the surfaces of the STI regions 68, the gate dielectric layers 100, the epitaxial source / drain regions 92, and the first epitaxial materials 91. The second dielectric layer 125 may be substantially similar to the second ILD 106 described above with respect to Fig. 21A to 21C. For example, the second dielectric layer 125 may be formed from a similar material and using a similar process as the second ILD 106. As in Fig. 30A to 30C, a CMP process or the like may be used to remove material of the second dielectric layer 125 such that the top surfaces of the second dielectric layer 125 are flush with the top surfaces of the STI regions 68 and the first epitaxial materials 91.

[0099] In Fig. 31A to 31C, the first epitaxial materials 91 are removed to form fifth recesses 128, and second silicide regions 129 are formed in the fifth recesses 128. The first epitaxial materials 91 may be removed by a suitable etching process, which may be an isotropic etching process, for example, a wet etching process. The etching process may have a high etch selectivity for materials of the first epitaxial materials 91. Accordingly, the first epitaxial materials 91 may be removed without significantly removing materials of the second dielectric layer 125, the STI regions 68, or the epitaxial source / drain regions 92. The fifth recesses 128 may expose sidewalls of the STI regions 68, back surfaces of the epitaxial source / drain regions 92, and sidewalls of the second dielectric layer 125.

[0100] The second silicide regions 129 may then be formed in the fifth recesses 128 on backsides of the epitaxial source / drain regions 92. The second silicide regions 129 may be substantially similar to the first silicide regions 110 previously described with respect to Fig. 22A to 22C. For example, the second silicide regions 129 may be formed from a similar material and using a similar process as the silicide regions 110.

[0101] In Fig. 32A to 32C, backside vias 130 are formed in the fifth recesses 128. The backside vias 130 may extend through the second dielectric layer 125 and the STI regions 68 and may be electrically coupled to the epitaxial source / drain regions 92 by the second silicide regions 129. The backside vias 130 may be similar to the source / drain regions 112 previously described with respect to Fig. 23A to 23C. For example, the backside vias 130 may be formed from a similar material and using a similar process as the source / drain regions 112.

[0102] In Fig. 33A to 33D, conductive lines 134 and a third dielectric layer 132 are formed over the second dielectric layer 125, the STI regions 68, and the backside vias 130. The third dielectric layer 132 may be similar to the second dielectric layer 125. For example, the third dielectric layer 132 may be formed from a similar material and using a similar process as the second dielectric layer 125.

[0103] The conductive lines 134 are formed in the third dielectric layer 132. Forming the conductive lines 134 may include patterning recesses in the third dielectric layer 132, for example, using a combination of photolithography and etching processes. A pattern of the recesses in the third dielectric layer 132 may correspond to a pattern of the conductive lines 134. The conductive lines 134 are then formed by depositing a conductive material into the recesses. In some embodiments, the conductive lines 134 include a metal layer, which may be a single layer or a composite layer having a plurality of sublayers formed from different materials. In some embodiments, the conductive lines 134 may include copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, or the like.An optional diffusion barrier and / or adhesion layer may be deposited prior to filling the recesses with the conductive material. Suitable materials for the barrier / adhesion layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or the like. The conductive lines 134 may be formed, for example, using CVD, ALD, PVD, plating, or the like. The conductive lines 134 are physically and electrically coupled to the epitaxial source / drain regions 92 through the backside vias 130 and the second silicide regions 129. A planarization process (e.g., CMP, grinding, etching back, or the like) may be performed to remove excess portions of the conductive lines 134 formed over the third dielectric layer 132.

[0104] In some embodiments, the conductive lines 134 are power rails, which are conductive lines that connect the epitaxial source / drain regions 92 to a reference voltage, a supply voltage, or the like. Advantages may be achieved by arranging power rails on a backside of the resulting semiconductor die rather than on a frontside of the semiconductor die. For example, a gate density of the nano-FETs and / or interconnect densities of the front-side interconnect structure 120 may be increased. Furthermore, the backside of the semiconductor die may accommodate wider power rails, reducing resistance and increasing the efficiency of supplying power to the nano-FETs. For example, a width of the conductive lines 134 may be at least twice a width of first-level conductive lines (e.g., the first conductive features 122) of the front-side interconnect structure 120.

[0105] Fig. 33D illustrates an embodiment in which the epitaxial source / drain regions 92 to which the backside vias 130 are electrically coupled have heights greater than the epitaxial source / drain regions 92 that are not electrically coupled to the backside vias 130. The heights of the epitaxial source / drain regions 92 may be selected by controlling the depths of the first recesses 86 and the second recesses 87 and / or controlling the thickness of the first epitaxial materials 91.Forming the epitaxial source / drain regions 92 that are not electrically coupled to the backside vias 130 with heights smaller than the epitaxial source / drain regions 92 that are electrically coupled to the backside vias 130 results in the epitaxial source / drain regions 92 that are not electrically coupled to the backside vias 130 being separated from the conductive lines 134 by a greater thickness of the second dielectric layer 125. This provides better separation of the epitaxial source / drain regions 92 that are not coupled to the backside vias 130 from the conductive lines 134 and improves device performance.

[0106] In Fig. 34A to 34C, remaining portions of a backside interconnect structure 136 are formed over the third dielectric layer 132 and the conductive lines 134. The backside interconnect structure 136 may be referred to as a backside interconnect structure because it is formed on a backside of the transistor structures 109 (e.g., a side of the transistor structures 109 opposite the side of the transistor structure on which active devices are formed). The backside interconnect structure 136 may include the second dielectric layer 125, the third dielectric layer 132, the backside vias 130, and the conductive lines 134.The backside interconnect structure 136 may further include conductive lines 140A-140C (collectively referred to as conductive lines 140) and conductive vias 139A-139C (collectively referred to as conductive vias 139) formed in fourth dielectric layers 138A-138F (collectively referred to as fourth dielectric layers 138). The conductive vias 139 may extend through respective ones of the fourth dielectric layers 138 to provide vertical connections between layers of the conductive lines 140. The conductive lines 140, the conductive vias 139, and the fourth dielectric layers 138 of the backside interconnect structure 136 may be formed using the same or similar process(es) or material(s) as the corresponding structures in the frontside interconnect structure 120, and therefore, the details will not be repeated.The number of fourth dielectric layers 138 shown in . Fig. 34A to 34C is a non-limiting example, and any suitable number of fourth dielectric layers 138 may be used in backside interconnect structure 136.

[0107] Still referring to Fig. 34A to 34C, a passivation layer 144, under-bump metallurgy (UBM) structures 146, and external connectors 148 are formed over the backside interconnect structure 136. The passivation layer 144 may comprise polymers such as PBO, polyimide, BCB, or the like. Alternatively, the passivation layer 144 may comprise inorganic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. The passivation layer 144 may be deposited, for example, by CVD, PVD, ALD, or the like.

[0108] The UBMs 146 are formed through the passivation layer 144 to the conductive lines 140 in the backside interconnect structure 136, and the external connectors 148 are formed on the UBMs 146. The UBMs 146 may include one or more layers of copper, nickel, gold, or the like formed by a plating process or the like. The external connectors 148 (e.g., solder balls) are formed on the UBMs 146. Forming the external connectors 148 may include disposing solder balls on exposed portions of the UBMs 146 and reflowing the solder balls. In some embodiments, forming the external connectors 148 includes performing a plating step to form solder regions over the topmost conductive lines 140C and then reflowing the solder regions.The UBMs 146 and external connectors 148 can be used to provide input / output connections to other electrical components, such as other device dies, distribution structures, printed circuit boards (PCBs), motherboards, or the like. The UBMs 146 and external connectors 148 can also be referred to as rear input / output pads, which provide signal, supply voltage, and / or ground connections to the nano-FETs described above.

[0109] Fig. 35, Fig. 36A, Fig. 36B and Fig. 37 illustrate a cross-sectional view of a semiconductor package at various stages of manufacturing according to one embodiment. Fig. 35, Fig. 36A, Fig. 36B and Fig. 37 illustrate the transfer of a semiconductor die 216 to a wafer 218 using a substrate with an etch stop layer and a diffusion barrier layer. The wafer 218 may also be referred to as a workpiece. The term workpiece may be used herein as a generic term to refer, for example, to a wafer, a carrier substrate, or the like.

[0110] With reference to Fig. 35, a substrate 202 is bonded to the wafer 218. The substrate 202 is similar to the substrate 50B of Fig. 3. The substrate 202 comprises a sacrificial substrate 203, an etch stop layer 207, diffusion barrier layers 205 and 209 on a top and a bottom of the etch stop layer 207, and a semiconductor layer 211. The sacrificial substrate 203, the etch stop layers 207, the diffusion barrier layers 205 and 209, and the semiconductor layer 211 correspond to the sacrificial substrate 11, the etch stop layers 17, the diffusion barrier layers 13 and 21, and the semiconductor layer 23, respectively, of Fig. 3. In an exemplary embodiment, the sacrificial substrate 203 is a silicon substrate, the etch stop layer 207 is a boron-doped silicon layer (e.g., Si:B) or a boron-doped silicon-germanium layer (e.g., SiGe:B), the diffusion barrier layers 205 and 209 are layer stacks comprising alternating layers of silicon and partial monolayers with oxygen insertion, and the semiconductor layer 211 is a silicon layer.

[0111] As in Fig. 35, a semiconductor die 216 is formed in / on the semiconductor layer 211. The semiconductor die 216 has die connectors 215 formed on its front side and a passivation layer 213 around the die connectors 215. The wafer 218 has a substrate 221, conductive pads 219, and a passivation layer 217 over the top of the substrate 221 around the conductive pads 219. The wafer 218 may have conductive lines and vias electrically coupled to the conductive pads 219. In the example of Fig. 35, the substrate 202 is bonded to the wafer 218 by hybrid bonding, although any other suitable bonding technique, such as bonding and the use of microbumps, may be used.

[0112] In Fig. 36A, the substrate 202 is thinned from the backside, for example, using etching, grinding, combinations thereof, or the like. The backside thinning process may include processing steps that are the same or similar to those previously described with respect to Fig. 25A to 28C, so the details are not repeated. After the backside thinning process, the sacrificial substrate 203, the etch stop layers 207, and the diffusion barrier layers 205 and 209 are removed, and the semiconductor die 216 remains bonded to the wafer 218. A thickness T3 of the semiconductor die 216 is less than about 100 nm in some embodiments. Such a small thickness (e.g., <100 nm) of the semiconductor die 216 is achieved by using the substrate 202 with the etch stop layer 207 and the diffusion barrier layers 205 / 209. As previously mentioned, one advantage of the thin thickness is a reduced total thickness variation (TTV) (e.g., a flatter top surface) for the semiconductor die 216, which facilitates die stacking when additional layers of semiconductor dies are stacked over the semiconductor die 216, as described below with reference to Fig. 37 discussed.

[0113] In example of Fig. 36A, the semiconductor die 216 transferred to the wafer 218 comprises a single-layer substrate, for example, the semiconductor layer 211, which is a thin layer (e.g., ≤ 100 nm) with reduced TTV. In some embodiments, such as in Fig. 36B, the substrate 202 may be used to transfer a semiconductor die 216 having a stacked or multi-layer substrate structure, for example, a substrate structure with the semiconductor layer 211 (e.g., a thin layer with reduced TTV and a thickness of less than 100 nm) formed on a substrate 212, wherein the substrate 212 may be thicker than the semiconductor layer 211. One skilled in the art will readily appreciate that advantages associated with transferring a die with the thin semiconductor layer 211 reduced TTV onto the wafer 218, such as advantages for forming 3D IC packages, apply to both die structures shown in Fig. 36A and Fig. 36B are illustrated.

[0114] In Fig. 37, a dielectric material 223 (e.g., a molding material or a gap-filling material) is formed over the top surface of the wafer 218 around the semiconductor die 216. A planarization process, such as CMP, may be performed to remove excess portions of the dielectric material 223 from the top surface of the semiconductor die 216 and achieve a coplanar top surface between the semiconductor die 216 and the dielectric material 223. Fig. 35, Fig. 36A, Fig. 36B and Fig. 37 therefore illustrate processing steps for forming a 3D IC package by bonding a semiconductor die to a wafer and performing a backside thinning process, wherein the backside thinning process is enabled by the embodiment substrate with the etch stop layer and the diffusion barrier layer. The processing steps of Fig. 35 to 37 may be repeated to attach additional layers of semiconductor die to the structure of Figure 37, as will be readily appreciated by one skilled in the art.

[0115] Fig. 38, Fig. 39A, Fig. 39B, Fig. 40 and Fig. 41 illustrate a cross-sectional view of a semiconductor package at various stages of manufacture according to one embodiment. Fig. 38, Fig. 39A, Fig. 39B and Fig. 37 illustrate processing steps for forming a 3D IC package by wafer-to-wafer bonding and backside thinning, wherein the backside thinning process is enabled by the embodiment substrates with the etch stop layer and the diffusion barrier layer.

[0116] In Fig. 38, a wafer 230A is bonded to the wafer 218. The wafer 218 is the same or similar to the wafer 218 of Fig. 35. The wafer 230A has a sacrificial substrate 231, an etch stop layer 235, diffusion barrier layers 233 / 237, and a semiconductor layer 239. The sacrificial substrate 231, the etch stop layer 235, the diffusion barrier layers 233 / 237, and the semiconductor layer 239 correspond to the sacrificial substrate 11, the etch stop layers 17, the diffusion barrier layers 13 and 21, and the semiconductor layer 23 of Fig. 3. A plurality of semiconductor dies are formed in / on semiconductor layer 239, with die connectors 243 and a passivation layer 241 being formed on a front side of wafer 230A. In some embodiments, wafer 230A is bonded to wafer 218 using a hybrid bonding process. Other suitable bonding techniques, such as microbump bonding, may also be used to bond wafer 230A to wafer 218.

[0117] In Fig. 39A, a backside thinning process is performed to remove the sacrificial substrate 231, the etch stop layer 235, and the diffusion barrier layers 233 / 237. The semiconductor layer 239 of the wafer 230A with the plurality of semiconductor dies remains bonded to the wafer 218. The backside thinning process may include process steps that are the same as or similar to those previously described with respect to Fig. 25A to 28C, so the details are not repeated. After the backside thinning process, a thickness of the semiconductor layer 239 is thinner than about 100 nm in some embodiments.

[0118] In the example of Fig. 39A, portions of wafer 230A (e.g., semiconductor layer 239) transferred to wafer 218 have a single-layer structure. In other embodiments, such as in Fig. 39B, the wafer 230A has a stacked or multi-layer structure, for example, a structure with a thin semiconductor layer 239 (e.g., with a thickness of less than 100 nm) with reduced TTV formed on another semiconductor layer 238, wherein the semiconductor layer 238 may be thicker than the semiconductor layer 239. One skilled in the art will readily appreciate that advantages associated with transferring the wafer 230A with the thin semiconductor layer 239 with reduced TTV, such as advantages for forming 3D IC packages, apply to both die structures shown in Fig. 39A and Fig. 39B are illustrated.

[0119] In Fig. 40 the processing steps of Fig. 38 and Fig. 39A to attach additional wafers (e.g., 230B, 230C, 230D, 230E, and 230F) to the structure of Fig. 39A. It should be noted that each of the additional wafers may have a structure that is the same as or similar to that of wafer 230A in Fig. 38, and after its attachment (e.g., bonding) to an underlying wafer, each of the additional wafers undergoes a backside thinning process such that only the semiconductor layer with the semiconductor die remains attached to the underlying wafer. Although not shown, each of the wafers (e.g., 230A to 230F) may have through-substrate vias (TSV) for electrical connection to an overlying and / or underlying wafer. The transferred wafers (e.g., 230A - 230F) in Fig. 40 are illustrated as a non-limiting example to have the same structure as wafer 230A in Fig. 39A. It is easy for a person skilled in the art to recognize that the transferred wafers in Fig. 40 has the same structure as wafer 230A in Fig. 39B.

[0120] After attaching the desired number of wafers, a dicing process is carried out, e.g., along dicing regions 229 to separate the structure from Fig. 40 into a plurality of individual 3D IC packages. Fig. 41 illustrates a single 3D IC package after the singulation process. The 3D IC package of Fig. 41 includes a semiconductor die 228 corresponding to a portion of wafer 218, a plurality of semiconductor dies 240A, 240B, 240C, 240D, 240E, and 240F, each of semiconductor dies 240A, 240B, 240C, 240D, 240E, and 240F corresponding to a portion of a respective wafer (e.g., 230A, 230B, 230C, 230D, 230E, or 230F). The disclosed embodiment substrates with the etch stop layer and diffusion barrier layer facilitate stacking the multiple wafers by enabling the transfer of a thin semiconductor layer through a backside thinning process.

[0121] Embodiments can achieve advantages. For example, by including both the etch stop layer and the diffusion barrier layer, the disclosed embodiment substrates achieve excellent etch selectivities while simultaneously reducing the out-diffusion of the dopant from the etch stop layer. As a result, a thin (e.g., <100 nm) high-quality semiconductor layer (e.g., semiconductor epitaxial material) suitable for forming a high-performance device can be formed in the disclosed substrates. After forming electrical components (e.g., transistors) in the semiconductor layer, the semiconductor layer can be easily transferred to a workpiece (e.g., a carrier, a wafer, a substrate) through a backside thinning process.The disclosed structures and methods are well suited for applications requiring the transfer of a semiconductor device layer, such as super power rail (SPR) applications. In SPR applications, silicon-on-insulator (SOI) substrates can be used to transfer device layers. However, SOI substrates are expensive. The current description provides cost-effective alternatives to the expensive SOI substrates. Additional advantages include reduced TTV of the transferred thin film, enabling stacking of multiple device layers to form 3D IC devices or packages for improved integration density.

[0122] Fig. 42 illustrates a flowchart of a method 1000 for manufacturing a semiconductor device according to some embodiments. It is understood that the Fig. 42 is merely one example of many possible embodiments. Many changes, alternatives, and modifications will be apparent to one of ordinary skill in the art. For example, various steps described in Fig. 42 are added, removed, replaced, rearranged or repeated.

[0123] With reference to Fig.42, at block 1010, an etch stop layer is formed over a substrate. At block 1020, a first diffusion barrier layer is formed over the etch stop layer. At block 1030, a semiconductor device layer is formed over the first diffusion barrier layer, the semiconductor device layer comprising a transistor. At block 1040, a first interconnect structure is formed over the semiconductor device layer on a front side of the semiconductor device layer, the first interconnect structure being electrically coupled to the transistor. At block 1050, the first interconnect structure is attached to a carrier. At block 1060, after attachment, the substrate, the etch stop layer, and the first diffusion barrier layer are removed. At block 1070, after removal, a second interconnect structure is formed on a back side of the semiconductor device layer.

[0124] According to the invention, a method for forming a semiconductor device comprises: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer comprising a transistor; forming a first interconnect structure over the semiconductor device layer on a front side of the semiconductor device layer, the first interconnect structure being electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after attachment; and forming a second interconnect structure on a back side of the semiconductor device layer after removal.In one embodiment, forming the etch stop layer comprises forming a first semiconductor material doped with a dopant. In one embodiment, the first semiconductor material is silicon or silicon-germanium, and the first dopant is boron, phosphorus, arsenic, indium, or antimony. In one embodiment, a concentration of the first dopant in the first semiconductor material is about 2E19 atoms / cm3 to about 5E21 atoms / cm3. 3. According to the invention, forming the first diffusion barrier layer comprises: forming a first number of epitaxial silicon layers over the etch stop layer; and forming a second number of partial oxygen-introduced monolayers, wherein the second number of partial oxygen-introduced monolayers are interleaved with the first number of epitaxial silicon layers. In one embodiment, the second number is one less than the first number. In one embodiment, each of the second number of partial oxygen-introduced monolayers is a silicon layer with oxygen incorporated into the silicon layer. In one embodiment, a concentration of oxygen in each of the second number of partial oxygen-introduced monolayers is several orders of magnitude higher than a background oxygen concentration level.In one embodiment, forming the semiconductor device layer comprises: forming a semiconductor epitaxial material over the first diffusion barrier layer; and forming the transistor in the semiconductor epitaxial material. In one embodiment, forming the second interconnect structure comprises: forming a dielectric layer on the backside of the semiconductor device layer; and forming a power supply line in the dielectric layer. In one embodiment, the method further comprises forming a second diffusion barrier layer over the substrate prior to forming the etch stop layer, wherein the second diffusion barrier layer is formed between the substrate and the etch stop layer.In one embodiment, the method further comprises: forming a first silicon capping layer between the second diffusion barrier layer and the etch stop layer; and forming a second silicon capping layer between the etch stop layer and the first diffusion barrier layer.

[0125] According to the invention, a method for forming a semiconductor device comprises: forming an etch stop layer over a substrate, the etch stop layer comprising a first semiconductor material doped with a first dopant; forming a first diffusion barrier layer over the etch stop layer, the first diffusion barrier layer comprising silicon layers interleaved with discontinuous oxygen layers; epitaxially forming a second semiconductor material over the first diffusion barrier layer; forming a transistor in the second semiconductor material; forming a first interconnect structure over the second semiconductor material; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after attachment.In one embodiment, the method further comprises, prior to forming the etch stop layer, forming a second diffusion barrier layer over the substrate such that the second diffusion barrier layer is between the substrate and the etch stop layer, wherein the second diffusion barrier layer comprises silicon layers interleaved with discontinuous oxygen layers. In one embodiment, the method further comprises forming a silicon capping layer between the etch stop layer and the first diffusion barrier layer.In one embodiment, the first interconnect structure is electrically coupled to a first surface of a source / drain region of the transistor, the method further comprising: forming a second interconnect structure on a backside of the transistor after the removal, the second interconnect structure being electrically coupled to a second surface of the source / drain region opposite the first surface. In one embodiment, the method further comprises forming a silicon capping layer between the etch stop layer and the first diffusion barrier layer.

[0126] According to the invention, a method for forming a semiconductor device comprises: forming a doped semiconductor layer over a substrate; forming a diffusion barrier layer over the doped semiconductor layer, the diffusion barrier layer comprising alternating epitaxial silicon layers and partial oxygen monolayers; forming a device layer having a transistor over the diffusion barrier layer; and transferring the device layer to a workpiece, wherein transferring comprises bonding the device layer to the workpiece; and removing the substrate, the doped semiconductor layer, and the diffusion barrier layer after bonding. In one embodiment, the method further comprises forming a first interconnect structure over the device layer prior to transferring, the device layer being bonded to the workpiece by the first interconnect structure.In one embodiment, removing the substrate, the doped semiconductor layer, and the diffusion barrier layer comprises: selectively removing the substrate and the doped semiconductor layer using a first etching process; and selectively removing the diffusion barrier layer after the first etching process using a second etching process different from the first etching process.

[0127] Features of several embodiments have been discussed above to enable one skilled in the art to better understand aspects of the present invention. One skilled in the art should recognize that they can readily use the present invention as a basis for designing or modifying other processes and structures to achieve the same objectives and / or obtain the same advantages of the embodiments presented herein.

Claims

[1] A method of forming a semiconductor device, the method comprising: Forming an etch stop layer (17, 207) over a substrate (11, 50, 50A, 50B, 50C, 202, 203); Forming a first diffusion barrier layer (21, 209) over the etch stop layer (17, 207); Forming a semiconductor device layer over the first diffusion barrier layer (21, 209), the semiconductor device layer (23, 211) comprising a transistor; Forming a first interconnection structure (120) over the semiconductor device layer (23, 211) on a front side of the semiconductor device layer (23, 211), wherein the first interconnection structure (120) is electrically coupled to the transistor; Attaching the first interconnect structure (120) to a carrier (150); Removing the substrate (11, 50, 50A, 50B, 50C), the etch stop layer (17, 207) and the first diffusion barrier layer (21, 209) after attachment; and Forming a second interconnection structure (136) on a backside of the semiconductor device layer (23, 211) after the removal, wherein forming the first diffusion barrier layer (21, 209) comprises: Forming a first number of epitaxial silicon layers (12) over the etch stop layer (17, 207); and Forming a second number of partial oxygen-introduced monolayers (14), wherein the second number of partial oxygen-introduced monolayers (14) are interleaved with the first number of epitaxial silicon layers (12). [2] The method of claim 1, wherein forming the etch stop layer (17, 207) comprises forming a first semiconductor material doped with a dopant. [3] The method of claim 2, wherein the first semiconductor material is silicon or silicon-germanium, and the first dopant is boron, phosphorus, arsenic, indium or antimony. [4] The method according to claim 2 or 3, wherein a concentration of the first dopant in the first semiconductor material is about 2E19 atoms / cm 3 up to about 5E21 atoms / cm 3 amounts. [5] A method according to any one of claims 1 to 4, wherein the second number is one less than the first number. [6] The method of any one of claims 1 to 5, wherein each of the second plurality of partial oxygen-incorporated monolayers (14) is a silicon layer (12) with oxygen incorporated into the silicon layer (12). [7] The method of claim 6, wherein a concentration of oxygen in each of the second number of partial oxygen-introduced monolayers (14) is several orders of magnitude higher than a background oxygen concentration level. [8] The method according to any one of claims 1 to 7, wherein forming the first semiconductor device layer (23, 211) comprises: forming a semiconductor epitaxial material over the first diffusion barrier layer (21, 209); and Forming the transistor in the semiconductor epitaxial material. [9] The method of any one of claims 1 to 8, wherein forming the second interconnect structure (136) comprises: Forming a dielectric layer (132) on the back side of the semiconductor device layer (23, 211); and Forming a power supply line in the dielectric layer (132). [10] The method of any one of claims 1 to 9, further comprising forming a second diffusion barrier layer (13, 205) over the substrate (11, 50, 50A, 50B, 50C, 202, 203) prior to forming the etch stop layer (17, 207), wherein the second diffusion barrier layer (13, 205) is formed between the substrate (11, 50A, 50B, 50C, 202, 203) and the etch stop layer (17, 207). [11] The method of claim 10, further comprising: Forming a first silicon capping layer (15) between the second diffusion barrier layer (13, 205) and the etch stop layer (17, 207); and Forming a second silicon capping layer (19) between the etch stop layer (17, 207) and the first diffusion barrier layer (21, 209). [12] A method of forming a semiconductor device, the method comprising: Forming an etch stop layer (17, 207) over a substrate (11, 50, 50A, 50B, 50C, 202, 203), the etch stop layer (17, 207) comprising a first semiconductor material doped with a first dopant; Forming a first diffusion barrier layer (21, 209) over the etch stop layer, the first diffusion barrier layer (21, 209) comprising silicon layers (12) interleaved with discontinuous oxygen layers; epitaxially forming a second semiconductor material over the first diffusion barrier layer (21, 209); forming a transistor in the second semiconductor material; Forming a first interconnect structure (120) over the second semiconductor material; Attaching the first interconnect structure (120) to a carrier (150); Removing the substrate (11, 50, 50A, 50B, 50C, 202, 203), the etch stop layer (17, 207) and the first diffusion barrier layer (21, 209) after attachment. [13] The method of claim 12, further comprising, prior to forming the etch stop layer (17, 207), forming a second diffusion barrier layer (13, 205) over the substrate (11, 50, 50A, 50B, 50C, 202, 203) such that the second diffusion barrier layer (13, 205) is between the substrate (11, 50, 50A, 50B, 50C, 202, 203) and the etch stop layer (17, 207), the second diffusion barrier layer (13, 205) comprising silicon layers interleaved with discontinuous oxygen layers. [14] The method of claim 12 or 13, further comprising forming a silicon capping layer (19) between the etch stop layer (17, 207) and the first diffusion barrier layer (21, 209). [15] The method of any one of claims 12 to 14, wherein the first interconnect structure (120) is electrically coupled to a first surface of a source / drain region (92) of the transistor, the method further comprising: Forming a second interconnect structure (136) on a backside of the transistor after the removal, wherein the second interconnect structure (136) is electrically coupled to a second surface of the source / drain region (92) opposite the first surface. [16] The method of any one of claims 12 to 14, further comprising forming a silicon capping layer (19) between the etch stop layer (17, 207) and the first diffusion barrier layer (21, 209). [17] A method of forming a semiconductor device, the method comprising: Forming a doped semiconductor layer over a substrate (11, 50, 50A, 50B, 50C, 202, 203); Forming a diffusion barrier layer (21, 209) over the doped semiconductor layer, the diffusion barrier layer (21, 209) comprising alternating epitaxial silicon layers (12) and partial oxygen monolayers (14); Forming a device layer (23, 211) having a transistor over the diffusion barrier layer (21, 209); and Transferring the device layer (23, 211) to a workpiece (218), wherein the transferring comprises: Bonding the device layer (23, 211) to the workpiece (218); and Removing the substrate (11, 50, 50A, 50B, 50C, 202, 203), the doped semiconductor layer and the diffusion barrier layer (21, 209) after bonding. [18] The method of claim 17, further comprising forming a first interconnect structure (120) over the device layer (23, 211) prior to transferring, wherein the device layer (23, 211) is bonded to the workpiece (218) through the first interconnect structure (120). [19] The method of claim 17 or 18, wherein removing the substrate (11, 50, 50A, 50B, 50C, 202, 203), the doped semiconductor layer (23, 211) and the diffusion barrier layer (21, 209) comprises: selectively removing the substrate (11, 50, 50A, 50B, 50C, 202, 203) and the doped semiconductor layer using a first etching process; and selectively removing the diffusion barrier layer (21, 209) after the first etching process using a second etching process different from the first etching process.

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