System and method for dual-port communication and power supply

Abstract

Embodiments for dual-port communication and power supply for single-wire applications are described. Embodiments of single-wire bridge devices are disclosed to provide a dual-port connection for two single-wire masters to communicate with each other in a multi-voltage system while enabling intermittent charging voltage. The configuration can be used to set a bidirectional passthrough mode, allowing level-shifted fast logic signals to be passed through the two single-wire connections. A timer can also be configured to expire the passthrough mode from edge inactivity. Power can be supplied directly from one of the connections for operation, eliminating the need for external power when no local power is available.If a local power supply is available, the other single-wire connection provides local access and pass-through mode. Such configurations make it easier for a two-contact solution to serve as both a communication channel and a power supply for battery charging.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit under 35 USC §119(e) of provisional application No. 62 / 960,580, entitled "SYSTEM AND METHOD FOR DUAL-PORT COMMUNICATION AND POWER DELIVERY," filed January 13, 2020, which names Wuguang Liu and Stewart Merkel as inventors, and claims the benefit of non-provisional application No. 17 / 132,340, entitled "SYSTEM AND METHOD FOR DUAL-PORT COMMUNICATION AND POWER DELIVERY," filed December 23, 2020, which applications are hereby incorporated by reference in their entirety. BACKGROUND: Technical field

[0002] The present invention relates generally to communication and power supply, and a method for implementing the same for single-wire applications. B. Background of the invention

[0003] In single-wire applications, a power management unit assists in maintaining communication between a first electronic device and a second electronic device via a single-wire I / O interface. The single-wire I / O interface can serve as an input port, output port, and / or power supply port, allowing the overall I / O interface to be simplified. Such a configuration is advantageous for various applications, particularly for devices that are small in size and do not require high data rates.

[0004] Various efforts have been made to improve communication and power supply methods for single-wire applications. Since the single-wire I / O interface is shared as a data communication channel and a power channel between two electronic devices, the interface must be managed to avoid conflicts in interface usage, especially when both devices are masters. A first electronic device and a second electronic device can also communicate via a single-wire I / O interface in a multi-voltage system, which requires the I / O interface to be adaptive during operation. For example, a circuit is known from US 2009 / 0243695 A1 that enables interoperability between circuits operated with different voltages and logic levels. Isolation is achieved via the resistance of transistor circuits, level adaptation via a divider network. Two coupled circuits, e.g.A master and a slave can thus operate with different voltages. The circuit requires only one "read only" and one "input / output" pin, thereby reducing resource requirements. US 7,099,970 B1 discloses an apparatus and a method for improving a one-wire bus. A translator is used between a master and one or more slave devices. The translator monitors the data stream and inserts known data at a predetermined position. It comprises a primary one-wire bus for communication with the master and at least one secondary one-wire bus for communication with one or more slave devices. Finally, DE 11 2015 004 994 T5 discloses a system with multiple units, each unit having a common-mode voltage terminal, an upstream communication terminal, and a downstream communication terminal.A first unit can generate currents at the uplink terminal corresponding to a plurality of bits. A second unit can receive these currents at the downlink terminal while maintaining a constant voltage level. The voltage level can correspond to the common-mode voltage.

[0005] Accordingly, it would be desirable to have an improved system for communication and power supply between electronic devices and a method for its implementation for single-wire applications. SUMMARY OF THE INVENTION

[0006] Embodiments of the invention relate to communication and power supply in single-wire applications.

[0007] In one or more embodiments, the dual-port circuit is a slave bridge that provides two single-wire connections for two single-wire masters to communicate with each other in a multi-voltage system. Each single-wire connection shares a buffer for transmitting data. Additionally, the dual-port circuit may support a bidirectional passthrough mode, allowing level-shifted fast logic signals of, for example, up to 512 kbps to pass through the two single-wire connections. A dedicated timer may be configurable to terminate passthrough mode due to edge inactivity. This can be configured for simplex (one direction only) or half-duplex (devices alternately transmit and receive) UART-to-UART communication when passing large amounts of data.A status byte can be used to know when the buffers are full and the logical idle state of the two single-wire connections. During operation, power can be drawn directly from a single-wire IOA connection, eliminating the need for an external power supply when no local power supply is available. When a local power supply is available, the single-wire IOA connection provides local access and passthrough mode. In one or more embodiments, the single-wire IOA connection is tolerant to 5 V to allow charging power over a single-wire bus. This can be accomplished with a comparator to detect when the voltage on the single-wire IOA connection is greater than a predetermined voltage, e.g., 4 V. The predetermined voltage is typically greater than the operating voltage (e.g., 3.3 V) on the single-wire connection IOA for data communication.

[0008] In one or more embodiments, a single-wire bus system is disclosed that includes a dual-port circuit as a slave bridge device. The hardware configuration, transaction sequence, and single-wire signaling (signal types and timing) of the single-wire bus system are each described. One or more single-wire protocols define bus transactions regarding the bus state during specific time slots initiated on the falling edge of synchronization pulses from the bus master. In one or more embodiments, a single-wire bus has only a single line; therefore, each device on the bus must drive the bus at the appropriate time. To simplify this, each device connected to the single-wire bus can have open-drain or tri-state outputs. In one or more embodiments, the idle state for the single-wire bus is set high.If a transaction needs to be paused, it is desirable to leave the bus idle so the transaction can continue. If this does not occur and the bus remains low for more than a predetermined time, one or more devices on the bus are reset.

[0009] In one or more embodiments, protocols for accessing the dual-port circuitry via either an IOA or IOB single-wire port are disclosed. The protocols may include initialization, a ROM function command, a device function command, and transaction / data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Reference is made to exemplary embodiments of the present invention illustrated in the accompanying figures. These figures are intended to be illustrative rather than restrictive. While the present invention will be described generally in connection with these embodiments, it is not intended to limit the scope of the present invention to the specific features of the embodiments shown and described. Figure (“FIG.”) 1 shows a block diagram of a first electronic device in communication with a second electronic device via a single-wire I / O bus. Fig. 2 shows an exemplary block diagram of a dual-port circuit coupled between two single-wire host circuits, according to various embodiments of the invention. Fig.3 shows an exemplary block diagram of a dual-port circuit coupled in a multi-voltage system according to various embodiments of the invention. Fig. 4 shows a simplified block diagram of a dual-port circuit in an application of a Bluetooth earphone in communication with a charging case, according to various embodiments of the invention. Fig. 5 shows a detailed block diagram of a dual-port circuit in an application of true wireless stereo (TWS) earphones in communication with a charging case, according to various embodiments of the invention. Fig. 6A shows an exemplary schematic diagram of a dual-port circuit for single-wire applications according to various embodiments of the invention. Fig. 6B shows an alternative schematic diagram of a dual-port circuit for single-wire applications according to various embodiments of the invention. Fig. 7 shows an exemplary bit diagram of a ROM ID for a dual-port circuit according to various embodiments of the invention. Fig. 8 shows a diagram of a PIO output timing according to various embodiments of the invention. Fig. 9 shows a diagram for read / write timing according to various embodiments of the invention. Fig. 10 shows an initialization sequence required to begin communication with the dual-port circuit, according to various embodiments of the invention. Fig. 11 shows an exemplary process diagram for a ROM function instruction flow for single-wire applications according to various embodiments of the invention. Fig. 12 shows a process diagram for a device function command flow for single-wire applications according to various embodiments of the invention. Fig. 13 shows a state diagram for the operation of the dual-port circuit according to various embodiments of the invention. Fig. 14 shows a noise suppression scheme according to various embodiments of the invention.

[0011] One skilled in the art will recognize that various implementations and embodiments of the invention may be made in accordance with the description. All such implementations and embodiments are intended to fall within the scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In the following description, for purposes of explanation, specific details are set forth in order to provide an understanding of the invention. However, it will be apparent to one skilled in the art that the invention may be practiced without these details. Furthermore, one skilled in the art will recognize that the embodiments of the present invention described below may be implemented in various forms, such as as a method, apparatus, system, device, or method on a tangible, computer-readable medium.

[0013] Components or modules shown in diagrams illustrate exemplary embodiments of the invention and are intended to avoid obscuring the invention. It is also understood that, within this discussion, these components may be described as separate functional units, which may include subunits, but those skilled in the art will recognize that various components or portions thereof may be divided into separate components or integrated together, including integration into a single system or component. It should be noted that functions or operations discussed herein may be implemented as components. Components may be implemented in software, hardware, or a combination thereof.

[0014] Furthermore, connections between components or systems within the figures are not intended to be limited to direct connections. Rather, data between those components may be modified, reformatted, or otherwise altered by intermediate components. Additional or fewer connections may also be used. It should also be noted that the terms "coupled," "connected," or "communicatively coupled" include direct connections, indirect connections via one or more intermediate devices, and wireless connections.

[0015] Reference in the specification to "one embodiment," "one embodiment," "one preferred embodiment," "these embodiments," or "embodiments" means that a particular feature, structure, characteristic, or function described in connection with the embodiment may be included in at least one embodiment or more than one embodiment of the invention. Also, the occurrences of the above phrases in various places in the specification do not necessarily all refer to the same embodiment or embodiments.

[0016] The use of certain terms in various places in the description is for illustrative purposes and should not be construed as limiting. A service, feature, or resource is not limited to a single service, feature, or resource. The use of these terms may refer to a grouping of related services, features, or resources, which may be distributed or aggregated. The terms "comprise," "having," "comprising," and "comprising" are open-ended terms, and any lists that follow are examples and are not intended to be limited to the items listed.

[0017] Furthermore, one skilled in the art should recognize that: (1) certain steps may be performed optionally; (2) steps may not be limited to the specific order given herein; (3) certain steps may be performed in different orders; and (4) certain steps may be performed concurrently.

[0018] Fig.1 is a block diagram of a first electronic device 110 in communication with a second electronic device 120 via a single-wire I / O bus 115. In one or more embodiments, the first electronic device 110 acts as the master device, while the second electronic device 120 acts as the slave device. The single-wire bus 115 can have only a single line. Therefore, it is important that each device on the bus drives it at an appropriate time. To facilitate this, in one or more embodiments, each device connected to the single-wire bus has open-drain or tri-state outputs. In one or more embodiments, the idle state for the single-wire bus is set high. If, for any reason, a transaction must be paused, the bus must be left in the idle state if the transaction is to continue. If this does not happen and the bus is idle for more than a certain time, e.g.If the bus voltage remains low (e.g., for 15.5 µs, the overdrive speed), one or more devices on the bus may be reset. Despite the name "single-wire," all devices can also have a second wire, or a ground connection, to allow return current to flow through the data wire. Communication occurs when a master device or a slave device momentarily disconnects the bus from V. PUP downwards, ie the pull-up resistor (R PUP ) to ground via its output MOSFET.

[0019] In certain situations, single-wire communication can be implemented between a master and a slave, with the master initiating activity on the bus, thus simplifying the avoidance of collisions on the bus. Protocols for detecting collisions can be built into the master's software. After a collision, the master can retry the communication. If two single-wire masters wish to communicate, a single-wire slave bridge device or circuit may be required to establish the connection between the two single-wire masters. Fig.2 shows an exemplary block diagram of a dual-port circuit 230 coupled between two single-wire host devices or circuits 210 and 220, according to various embodiments of the invention. In one or more embodiments, the dual-port circuit 230 is a slave bridge device that includes a first single-wire input / output port (hereinafter IOA) 231 and a second single-wire input / output port (hereinafter IOB) 232, which are in communication with the host circuits 210 and 220 via the IOA connection 233 and the IOB connection 234, respectively. The dual-port circuit 230 may further include additional general-purpose input / output ports (PIOA, PIOB, or PIOC, as in Fig. 2). The IOA port can be used to control the V DDPower supply during idle times for the IOA connection 233 and store energy in an internal parasitic capacitor. In one or more embodiments, the IOA connection 233 and the IOB connection 234 may include a diode for each connection instead of a resistor, with the anode side coupled to the dual-port circuit 230.

[0020] In one or more embodiments, the dual-port circuit 230 further includes a token pin 235 configured to indicate which single-wire input / output port receives the communication token to coordinate communication between the two single-wire input / output ports. When the token pin is set to a first logic level (e.g., a logic low), the IOA connection is set for single-wire communication; when the token pin is set to a second logic level (e.g., a logic high) opposite the first logic level, the IOB connection is set for single-wire communication. In one or more embodiments, the token pin 235 may include a low-frequency clock signal (TOK F), while the dual-port circuit 230 operates in a passthrough mode that allows level-shifted high-speed logic signals (of, for example, up to 512 kbps) to pass through the two single-wire connections. A dedicated timer can also be configured to exit passthrough mode due to edge inactivity. This can be useful for simplex (one-way only) or half-duplex (devices alternately transmit and receive) UART-to-UART communication when transferring large amounts of data.

[0021] In one or more embodiments, the dual-port circuit 230 may further include a current sink port 236 that may be coupled to receive a voltage V L to supply the requirements of the internal digital circuitry and receive the IOA / IOB pin source in passthrough mode. V L can be between 1.71 V and 5.25 V.

[0022] In one or more embodiments, the dual-port circuit 230 may further include a charger disable (CD) port, which may also function as a universal input / output port (e.g., sharing the CD port is sharing with the PIOC port, as in Fig.2). The CD port may be floating (i.e., non-conducting) when the IOA port 231 is nominally below a threshold voltage (e.g., 4 V). Otherwise, the CD port is actively low to activate a charger 240 by switching a controllable switch 237 (e.g., a P-type transistor, an N-type transistor, an N-channel transistor, a P-channel transistor, etc.) when IOA is above 4 V. The PMOS transistors shown in the drawings are for illustrative purposes to describe the present application and do not limit the choice of switch. One of ordinary skill in the art will understand that other types of switches (e.g., N-type, N-channel, P-type, P-channel, BJT switches) may also be applicable to one or more embodiments of the present invention.

[0023] In one or more embodiments, the dual-port bridge circuit may be applied in a multi-voltage system for single-wire communication. Fig.3 shows an exemplary block diagram of a dual-port circuit coupled in a multi-voltage system including a first device 310 and a second device 320, according to various embodiments of the invention. The first device 310 includes a first microcontroller (MCU) 312 operating at 3.3 V, while the second device 320 includes a second microcontroller (MCU) 322 operating at 1.8 V. A dual-port circuit 324, integrated into the second device 320, is coupled between the first MCU and the second MCU. The dual-port circuit 324 includes a first single-wire port IOA in communication with the first MCU 312 via a first single-wire bus 325 and a second single-wire port IOB in communication with the second MCU 322 via a second single-wire bus 326.The dual-port circuit 324 allows the first device 310 (or the first MCU 312) and the second device 320 (or the second MCU 322) to have single-wire communication even though they operate at different voltages.

[0024] Fig.4 is an exemplary block diagram 400 of a dual-port circuit in an application of a Bluetooth earbud 420 in communication with a charging case 410 according to various embodiments of the invention. The charging case 410 includes a first microcontroller (MCU) 412 for charging and I / O control. The Bluetooth earbud 420 includes a circuit (e.g., a Bluetooth audio chip) 422 and a dual-port circuit 424. The dual-port circuit 424 includes a first single-wire port IOA in communication with the first MCU 412 via a first single-wire bus 425 and a second single-wire port IOB in communication with the circuit 422 via a second single-wire bus 426. The first single-wire bus 425 can function either as a communication channel for data exchange or as a charging path.The first MCU 412 has an enable port (EN) coupled to control a controllable switch 414 that switchably couples the first single-wire bus 425 to a 5V voltage source for charging the Bluetooth earphone 420. Once the voltage of the first single-wire bus 425 is raised to 5V, a charger disable (CD) port in the dual-port circuit 424 is pulled low to turn on a controllable switch 430 (e.g., a PMOS switch), thereby connecting the 5V voltage source to a battery charger 440 for battery charging enablement. When the first single-wire bus 425 functions as a communication channel for data exchange, the first single-wire bus 425 is decoupled from the 5 V voltage source by turning off the controllable switch 414 and is operatively coupled to a 3.3 V voltage source for data communication between a GPIO port of the first MCU 412 and a single-wire I / O port (IOA) of the dual-port circuit 424.

[0025] Similar to the Fig. 2, the dual-port circuit 424 also has a second single-wire input / output port (IOB) in communication with the Bluetooth audio chip 422 via the IOB connection 426, which is operatively coupled to a 1.8 V voltage source. The dual-port circuit 424 may further include additional general-purpose input / output ports (PIOA, PIOB, or PIOC) and a token pin (in Fig. 4 not shown) configured to indicate which single-wire input / output port is enabled for communication.

[0026] Fig.5 shows a detailed block diagram 500 of a dual-port circuit in an application of a true wireless stereo (TWS) earbud 520 in communication with a charging case 510 according to various embodiments of the invention. It should be noted that some of the illustrated blocks (i.e., heart rate, temperature, etc.) may be optional, and the drawing is not limited to the elements shown. Communication may support a universal asynchronous receiver / transmitter (UART) pass-through mode between the earbud 520 and the charging case 510. The charging case 510 may include a charging battery 515 to provide charging power to the earbud 520. The charging case 510 may be powered by an external power source via a USB interface 516, which may also be coupled to the charging battery 515 via an internal battery charger 517 for charging the charging battery 515. The basic layout of the block diagram 500 can be similar to the block diagram 400 in Fig.4. In addition, in Fig. 4, the 5V power supply used to power the single-wire charging / IO connection 525 for charging purposes may come from a 5V DC-DC boost converter circuit 514. Alternatively, the power supply used to power the single-wire charging / IO connection may be obtained directly from the charging battery 515. The MCU 512 may further include additional GPIO pins to receive additional information, e.g., for detecting the charging case lid, the battery status of the left earbud, the battery status of the right earbud, etc. In one or more embodiments, the Fig. 5 has a single one-wire interface (single wire interface) for communication with the earphone 520 and the earphone 560, as shown in Fig.5. In one or more embodiments, earbud 520 and earbud 560 may alternatively or simultaneously receive the charging voltage. One of ordinary skill in the art will understand that charging case 510 may be modified to include additional single-wire interface(s) to support communication with multiple earbuds (e.g., a left earbud and a right earbud). For example, charging case 510 may charge multiple earbuds simultaneously, or alternatively, include single-wire data communication with multiple earbuds simultaneously or alternatively. Such a modification should still be within the scope of the invention.

[0027] In one or more embodiments, the dual-port circuit 524 includes a first single-wire input / output (IOA) port that communicates with the charging box 510 via the one-wire charging / IO connection 525. Once the dual-port circuit 524 detects the voltage at the single-wire charging / IO connection 525 being higher than a predetermined threshold (e.g., >4 V), a charge disable (CD) port in the dual-port circuit 524 is pulled low to turn on a controllable switch 530, thereby connecting the 5 V voltage source to a battery charger 540 for charging the battery 550, which may be a lithium-ion battery. In one or more embodiments, the Bluetooth audio chip 522 may communicate with the battery charger 540 via an I2C interface to exchange information such as charging current, battery status, etc.The audio chip 522 may also receive an interrupt request (or IRQ) from the battery charger 540 when one or more parameters exceed certain thresholds. For example, the internal battery 515 in the charging case 510 may have a battery capacity (e.g., 1000-2000 mAh) that may be greater than a battery capacity (e.g., 60-150 mAh) of a battery (e.g., battery 550) in the left earbud, the right earbud, or both.

[0028] The dual-port circuit 524 also includes a second single-wire input / output port (IOB) that communicates with the Bluetooth audio chip 522 via an IOB connection. The dual-port circuit 524 may further include additional general-purpose input / output ports (PIOA, PIOB, or PIOC) and may use one of the GPIO pins (e.g., the PIOA pin, as shown in Fig.5) for UART communication with the Bluetooth audio chip 522 via a GPIO pin (e.g., GPIO3) in the chip 522.

[0029] Fig. 6A is an exemplary schematic diagram of a dual-port circuit 600 for single-wire applications according to various embodiments of the invention. The dual-port circuit 600 has eight ports or pins: a first one-wire I / O pin (IOA) 611 for a first one-wire connection (single wire), a second one-wire I / O pin (IOB) 612 for a second one-wire connection (single wire), a ground pin 613, a charge standard (CD) pin 614 (which can also function as a GPIO pin: PIOC), a token pin 615, a first GPIO pin (PIOA) 616, a second GPIO pin (PIOB) 617, and a V L -Pin 618 for receiving a low voltage V L .

[0030] Internally, the dual-port circuit 600 may further include a collection of function instructions 620 (which may include single-wire ROM function instructions and device function instructions), a pass-through model controller 630, a register 640, a voltage regulator 650, and a voltage comparator 660. In one or more embodiments, each single-wire connection shares an 8-byte ROMID 622, a global configuration byte, and a data buffer 626 (e.g., an 8-byte buffer) to carry all data, all of which may be accessed via the function instructions 620. Additionally, each single-wire connection may share a status byte, three configurable open-drain GPIO pins. The status byte, the POI information, and the configuration byte may be stored in the register, which may be accessed by the function instructions 620. The voltage regulator 650 may be switchable with the low voltage V L or the voltage V DDbe coupled on the IOA connection and have a regulated output voltage V REG which is used to power the internal circuit and for voltage comparison.

[0031] In one or more embodiments, the dual-port circuit 600 provides an interface to enable charging power switching via a single-wire bus, dual single-wire master communication, GPIO expansion, and timing-limited logic level translation. An integrated comparator 660 can be used to measure the voltage on the IOA connection (V DD ) with a predetermined voltage (V REG ) and switch the charging power or the single-wire IOA access accordingly. In one or more embodiments, a voltage divider is applied to determine the V DDto a desired voltage level suitable as input to the comparator 660. The dual-port circuit 600 can, if desired, operate the IOA connection with an internal parasitic supply, while the IOB single-wire connection with a low-power supply source (V L ) can be operated. The parasitic supply provides access to all registers, to the ROMID and to status information, regardless of whether the V L is present. A data buffer 626 is used to exchange data between the two IOA and IOB single-wire connections. Three general-purpose I / O pins (PIOA / B / C) can provide GPIO expansion for additional functions. The level translation direction can also be selected through a single-wire connection, allowing serial logic data to be passed between the IOA and IOB at higher rates, e.g., up to 512 kbps.

[0032] Fig.Figure 6B shows an alternative schematic diagram of a dual-port circuit for single-wire applications according to various embodiments of the invention. Except for minor differences, the dual-port circuit 670 is similar to that shown in Fig. 6A. One difference is that in the dual-port circuit 670, the function instructions 620 output a PTM signal 672. When the PTM signal 672 is high, a pass-through device (e.g., an nMOS switch 674) is turned on to enable bidirectional UART communication between the IOA and IOB via a connection 676. The IOA high-side to IOB low-side level translation can be achieved by setting the gate of the nMOS 674 to the low-side V L supply. In one or more embodiments, the IOA pull-up voltage V PUPA in pass-through mode may be greater than or equal to V LFurthermore, in the dual-port circuit 670, the IOA pin 611 and the IOB pin 612 may be coupled to the function instructions 620 via a buffer 681 and a buffer 682, respectively, with the outputs of these two buffers being coupled to the function instructions 620. Furthermore, in the dual-port circuit 670, the token pin 615 is coupled to the function instructions 620 via a token pin buffer 683 and an nMOS token pin 684, with the input of the token pin buffer 683 being connected to the function instructions 620. Token operation

[0033] In one or more embodiments, the dual-port circuit detects the voltage at the IOA / IOB connections and automatically switches the communication token between the connections. The selection of the IOA or IOB connection is controlled by the token pin 615. This pin indicates which single-wire side receives the communication token. In one or more embodiments, a logic low on the token pin represents the IOA side, while a logic high represents the IOB side. In one or more embodiments, the token pin 615 provides a low-frequency clock (TOK F ) while in pass-through mode. Additionally, an impedance test can be performed using software if necessary.

[0034] In one or more embodiments, each single-wire connection shares an 8-byte buffer for transferring data. Additionally, the two single-wire connections share an 8-byte ROMID, a global configuration byte, a status byte, and three configurable open-drain GPIO pins. Each ROMID is a unique 64-bit registration number programmed into the device at the factory. The configuration byte can be used to set a bidirectional passthrough mode, allowing level-shifted, high-speed logic signals of up to 512 kbps to be passed through the two single-wire connections. The status byte can be used to know when the buffers are full and what the logic idle state of the two single-wire connections is. Power is supplied for operation directly through a single-wire IOA connection, eliminating the need for an external power supply when a local power supply is unavailable.When local power is available, the single-wire IOB connection provides local access and pass-through mode.

[0035] In one or more embodiments, the dual-port circuit 600 includes a unique ROM ID that is 64 bits long. The ROM ID can provide traceability for the dual-port circuit. The first 8 bits are a single-wire standard character. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits, as shown in Fig. 7. In one or more embodiments, the single-wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates. The polynomial can be expressed as X 8 +X 5 +X 4 +1.

[0036] There are several device function commands that can be summarized in Table 1. Within a flowchart for device function commands (in Fig. 13), the data transfer during writing and reading is checked by a cyclic redundancy check (CRC) of the multi-bit type (e.g. CRC-16) 624. Table 1. Summary of device function commands command Description type Write configuration General configuration Global Read configuration General configuration Global Write buffer Write buffer memory Read buffer Read buffer memory Read status Read status Generally PIO letter PIO Write conductive or floating access PIO reading PIO Read Logic State access Write start value Write to the start value register Generally Read start value Read the start value register Generally

[0037] In one or more embodiments, the write configuration command is used to set the configuration register. The write configuration sets the global configuration for the device. The SEL bit can be useful in selecting the pin mode between CD and PIOC. Comparator functionality is standard for detecting when a charge supply is detected on the IOA pin or when IOA is a single-wire connection. Additionally, a level-shifted passthrough mode (PTM bit) may be available if simplex or half-duplex UART communication between IOA and IOB pins is desired. The level shifter can have communication at up to 512 kbps until a passthrough mode timer expires if the IOA / IOB pins are not active. When activity is detected on the IOA / IOB bus, the timer is reset to the value set in the seed register (SVAL bits) to maintain the connection.In normal single-wire operation, some applications may require interrupt support when buffers have been written. This is accomplished by setting PIOA / B with the BUFA / B flags, which are output with inverted logic. Therefore, when the BUFA / B flags are set to '1', the PIOA / B pins are conductive. When the BUFA / B flags are not set, the PIOA / B pins are non-conductive. In one or more embodiments, some restrictions, such as a requirement that the VL supply be present in passthrough mode, may be applied to the write configuration command. Table 2. Write configuration parameter byte BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X PULL-UP QM PTM BUFBPE BUFAPE SEL

[0038] Table 2 shows parameter bits for the write configuration command, and Table 3 shows a write configuration sequence. Details of some parameter bits are described below.

[0039] Bit 0: Select (SEL). When set to 1, the PIOC pin function is active. When set to 0 (default), the CD pin function is active.

[0040] Bit 1: BUFA port enable (BUFAPE). When set to 1, the PIOA pin outputs the inverted logic of the BUFA flag in the status register. When set to 0 (default), the PIOA pin is normal access.

[0041] Bit 2: BUFB port enable (BUFBPE). When set to 1, the PIOB pin outputs the inverted logic of the BUFB flag in the status register. When set to 0 (default), the PIOB pin is normal access.

[0042] Bit 3: Passthrough Mode (PTM). When set to 1, PTM is enabled, and the timer begins monitoring the IOA / IOB pins for activity (i.e., falling edge transitions) and asserts a clock on the TOKEN pin. The timer is reset to the starting value for each falling edge activity to maintain PTM. If no activity occurs, PTM automatically returns to normal single-wire operation, and the PTM bit returns to 0 after the timer expires. When set to 0 (default), passthrough mode is disabled, and the timer is used to monitor the IOA pin for the IOA pin's transition to the "logic low" state. A falling edge on IOA sets the timer to its starting time value. When the timer expires and confirms that a logic low is still present, the IOB link will pass the token (i.e., no other falling edge transition has occurred).As long as the IOA connection has the token, the timer will continue to iterate and test whether the IOA connection status remains "logic low." However, if another falling edge transition occurs before the timer expires, the logic state will exit to the corresponding state (e.g., IOA connection status "idle logic high") when the timer expires. For more details on the status, see the TWS truth table.

[0043] Bit 4: Quiet Mode (QM). When set to 1, QM is enabled and the timer begins monitoring the IOA pin for activity (i.e., falling edge transitions) and asserts a logic high on the TOKEN pin. The timer is reset to the starting value for each falling edge IOA pin activity to maintain QM. If no other falling edge IOA activity occurs, the QM automatically returns to normal single-wire operation, and the QM bit returns to 0 when the timer expires.

[0044] Bit 5: Pull-Up (PULL-UP). In one or more embodiments, when set to 1, a 5M pull-up resistor is connected from the IOA connection to VL. When set to 0 (default), the pull-up resistor is disconnected from VL, and the same resistor becomes a pull-down to ground. This way, the IOA pin does not float when not connected to a device, and the single-wire IOB connection has access. Table 3. Write configuration sequence Reset Presence impulse <ROM auswählen> TX: Command 11h (Write configuration) TX: Parameters (Write Configuration) RX: CRC16 (inverted of command, parameter) Reset

[0045] In one or more embodiments, the read configuration command is used to read the configuration register to confirm settings. Table 4 and Table 5 show parameter bits and a sequence for the read configuration command, respectively. Table 4. Read configuration parameter byte BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X X PULL-UP QM PTM BUFBPE BUFAPE SEL Table 5. Read configuration sequence Reset Presence impulse <ROM auswählen> TX: Command 22h (Read Buffer) RX: Read configuration RX: CRC16 (inverted, command, and data) Reset

[0046] Details of the parameter bits of the read configuration command are described below.

[0047] Bit 0: Select (SEL). Read bit status.

[0048] Bit 1: BUFA port activation (BUFAPE). Read bit status. Bit 2: BUFB port activation (BUFBPE). Read bit status.

[0049] Bit 3: Pass-through mode (PTM). Read bit status.

[0050] Bit 4: Quiet Mode (QM). Read bit status.

[0051] Bit 5: Pull-Up (PULL-UP). Reads whether the pull-up resistor is connected (1) or not connected (0).

[0052] In one or more embodiments, the write buffer command is used to write a temporary value to the volatile buffer 626, which is used to transfer bytes to / from the single-wire IOA or IOB connection. In one or more embodiments, the buffer length is set to 8d if the byte length (BLEN) > 8d. A BLEN of zero may imply that no data needs to be loaded. The IOA or IOB connection can only write to the buffer if it has the token. During operation, flags for BUFA or BUFB are set in the read status register. Table 6. Write buffer parameter byte BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 BLEN

[0053] Table 6 shows parameter bits for the write buffer command, and Table 7 shows a sequence for the write buffer. In one or more embodiments, BLEN ranges from 1 to a maximum length of 8. Table 7. Write buffer sequence Reset Presence impulse <ROM auswählen> TX: Command 33h (Write Buffer) TX: Parameters (BLEN) TX: Data (1 to 8 bytes are written) RX: CRC16 (inverted of command, parameter, data) Reset

[0054] In one or more embodiments, the read buffer command is used to read the buffer from the single-wire IOA or IOB connection. In one or more embodiments, the read value is 8d if the byte length (BLEN) > 8d. A BLEN of zero cannot return any data. In one or more embodiments, the read buffer length byte is similar to the write buffer parameter byte shown in Table 6, where BLEN specifies the number of bytes to read.

[0055] Table 8 shows a sequence for the write buffer. In one or more embodiments, BLEN ranges from 1 to the maximum length number of 8. Table 8. Read buffer sequence Reset Presence impulse <ROM auswählen> TX: Command 44h (Read Buffer) RX: Byte length (BLEN) RX: Data (1 to 8d bytes) RX: CRC16 (Inverted, Command, Byte Length, and Data) Reset

[0056] The Read Status command reads whether the buffer has been written and the logical state of the single-wire IOA connection and the IOB connection. This command is used to receive status information. It provides a way to know whether the IOA connection should read the buffer or whether the IOB connection should read the buffer. It is also used to check the logical status of the IOA / IOB connections and whether the comparator has detected the charging voltage on the IOA connection. When the buffer is read, the BUFB and BUFA flags are cleared. Table 9 and Table 10 show the status byte and a sequence for the Read Status command, respectively. Table 9. Status byte BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 X TRST TOKS CMPS IOBS IOAS BUFB BUFA

[0057] Bit 0: Buffer A Flag (BUFA). Indicates that the buffer has been written by the IOA connection.

[0058] Bit 1: Buffer B Flag (BUFB). Indicates that the buffer has been written by the IOB connection.

[0059] Bit 2: IOA state (IOAS). Logic state of the IOA pin.

[0060] Bit 3: IOB state (IOBS). Logic state of an AND gate with IOB and VL pins as inputs.

[0061] Bit 4: Comparator state (CMPS). Output state of the comparator. This can be used to detect charging voltage at the IOA pin (1) and no charging voltage at the IOA pin (0).

[0062] Bit 5: Token state (TOKS). Logic state of the TOKEN pin. Changes when in the PTM.

[0063] Bit 6: Timer Reset (TRST). When logic low, this indicates that the timer has restarted with the start value. Table 10. Read status sequence Reset Presence impulse <ROM auswählen> TX: Command 55h (Read Status) RX: Status byte RX: CRC16 (inverted, command, status byte) Reset

[0064] In one or more embodiments, the PIO write command sets the directed open-drain PIO pin to a conducting or non-conducting, high-impedance state. To turn on the output transistor, the corresponding bit value is 0. To turn off the output transistor (non-conducting), the bit is set to 1. In this way, the bit transmitted as the new PIO output state arrives at the PIO pin in its true form. In one or more embodiments, the actual PIO transition to the new state may be delayed by t REH +t P from the rising edge of the MS bit of the inverted PIO byte, as shown in Fig. 8 is shown.

[0065] In one or more embodiments, to protect the transmission from data errors, the master device or circuit sets an upper nibble to the complement of the lower nibble in the PIO output byte. If the transmission was error-free, the PIO state changes. During the PIO write operation, the dual-port circuit sets the PIO output state. If the CD pin is set in the configuration register, the PIOCS bit has no effect.

[0066] Table 11 and Table 12 show the PIO output byte and a PIO write sequence, respectively. Table 11. PIO output byte BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 PIOCS PIOBS PIOAS 0 PIOCS PIOBS PIOAS

[0067] Bit 0: PIO-A output state (PIO-AS). Set this bit to 0 for conducting (logic low) or 1 for non-conducting (high impedance or logic high with external pull-up).

[0068] Bit 1: PIOB output state (PIOBS). Set this bit to 0 for conducting (logic low) or 1 for non-conducting (high impedance or logic high with external pull-up).

[0069] Bit 2: PIOC output state (PIOCS). Set this bit to 0 for conducting (logic low) or 1 for non-conducting (high impedance or logic high with external pull-up). Table 12. PIO write sequence Reset Presence impulse <ROM auswählen> TX: Command 66h (write PIO) TX: Parameter (PIO output byte) RX: CRC16 (Inverted of, Command, Parameter) Reset

[0070] In one or more embodiments, the PIO read command reads the input logic state of the PIO pins. To protect the transmission from data errors, the masters expect the upper nibble to be equal to the complement of the lower nibble in the PIO input byte. If the CD pin is set in the configuration register, the PIOCL bit represents this logic level.

[0071] Table 13 and Table 14 show the PIO input byte and a PIO read sequence, respectively. Table 13. PIO input byte BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1 PIOCL PIOBL PIOAL 0 PIOCL PIOBL PIOAL

[0072] Bit 0: PIOA level (PIOAL). Provides the logical status of the PIOA pin.

[0073] Bit 1: PIOB Level (PIONL). Provides the logical status of the PIOB pin.

[0074] Bit 0: PIOC level (PIOCL). Provides the logical status of the PIOC pin. Table 14. PIO read sequence Reset Presence impulse <ROM auswählen> TX: Command 77h (Read PIO) RX: PIO input byte RX: CRC16 (inverted from command, PIO input byte) Reset

[0075] In one or more embodiments, the write seed command is used to set the seed value of the timer to be decremented. The timer uses this value upon initial startup or when a repetition is required.

[0076] Table 15 and Table 16 show the write configuration parameter byte and a write timeout value sequence, respectively. Table 15. Write configuration parameter byte BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TVAL

[0077] Bits 7: 0: Timeout value (TVAL). Sets the timeout value for the timer. In one or more embodiments, the timeout value can be expressed as Timeout = TVAL × 2 ms. For example, for 8-bit TVAL, the maximum timer duration is set to 512 ms. Table 16. Write timeout sequence Reset Presence impulse <ROM auswählen> TX: Command 88h (Write timeout value) TX: Parameters (TVAL) RX: CRC16 (inverted of command, parameter) Reset

[0078] In one or more embodiments, the read timeout value command is used to read the timeout value register to confirm settings. The read configuration parameter byte may be similar to the write configuration parameter byte shown in Table 15. Table 17 shows a read configuration parameter byte. Table 17. Read timeout value sequence Reset Presence impulse <ROM auswählen> TX: Command 99h (Read timeout value) RX: Read timeout value RX: CRC16 (inverted, command, length byte, and data) Reset Forms of pass-through operation

[0079] In one or more embodiments, in a passthrough mode (timer enabled), the dual-port circuit 600 may act as a bidirectional open-drain level shifter. This may be accomplished by two inverted gate paths 632 and 634 to provide bidirectional level translation between IOA and IOB connections with the mode enabled in the configuration register, e.g., by setting the PTM bit to 1. The direction of passthrough operation may be controlled by a passthrough regulator 630 integrated into the dual-port circuit 600 to selectively enable a desired inverted gate path 632 or 634 via switches SW1 or SW2. When the input is logic high, the corresponding open-drain N-FET is non-conductive. When the input is logic low, the corresponding open-drain N-FET conducts. In one or more embodiments, the dual-port circuit requires 600 external pull-up resistors of IOA V DDand IOB V L , enabling open-drain output operation. In one or more embodiments, one or more internal circuits may assist with logic state transitions for an IOA connection by removing the internal parasitic capacitance in the PTM. Description of the power supply

[0080] In one or more embodiments, the IOA pin 611 is used to control the V DD -Dissipate power during idle times for the IOA connection and store energy in the internal parasitic capacitor. In pass-through mode, V L used to supply the requirements of the internal digital circuitry and the IOA / IOB pin source. In one or more embodiments, V L in the range of 1.71 V to 5.25 V.

[0081] In one or more embodiments, the dual-port circuit is a slave bridge that provides two single-wire connections for two single-wire masters to communicate with each other in a multi-voltage system. Each single-wire connection shares a buffer for transmitting data. Additionally, the dual-port circuit may support a bidirectional passthrough mode that allows level-shifted fast logic signals, e.g., up to 512 kbps, to pass between the two single-wire connections. A dedicated timer may be configured to terminate passthrough mode due to edge inactivity. This may be configured for simplex (one direction only) or half-duplex (devices alternately transmit and receive) UART-to-UART communication when passing large amounts of data.A status byte can be used to know when the buffers are full and the logical idle state of the two single-wire connections. Operation can draw power directly from a single-wire IOA connection, eliminating the need for an external power supply when local power is unavailable. When local power is available, the single-wire IOA connection provides local access and passthrough mode. In one or more embodiments, the single-wire IOA connection is tolerant to 5 V to allow charging power over a single-wire bus. This can be accomplished with a comparator to detect when the voltage at the single-wire IOA connection is greater than a predetermined voltage, e.g., 4 V. The predetermined voltage is typically greater than the operating voltage (e.g., 3.3 V) at the single-wire connection IOA for data communication.

[0082] In one or more embodiments, a single-wire bus system is disclosed that includes a dual-port circuit as a slave bridge device. The system includes aspects of hardware configuration, transaction sequencing, and single-wire signaling (signal types and timing). One or more single-wire protocols define bus transactions in terms of the bus state during specific time slots initiated on the falling edge of synchronization pulses from the bus master. In one or more embodiments, a single-wire bus has only a single line; therefore, each device on the bus must drive the bus at the correct time. To simplify this, each device connected to the single-wire bus can have open-drain or tri-state outputs. Both single-wire ports (IOA and IOB) of the dual-port circuit are open drain with internal circuitry that Fig.1. In one or more embodiments, the idle state for the single-wire bus is set high. If a transaction needs to be paused, it is desirable for the bus to remain in the idle state so that the transaction can continue. If this does not occur and the bus remains low for more than a predetermined time, e.g., 15.5 µs (override speed), one or more devices on the bus are reset.

[0083] In one or more embodiments, the protocol for accessing the dual-port circuitry via either an IOA or IOB single-wire port may include an initialization, a ROM function command, a device function command, and a transaction / data. initialization

[0084] In one or more embodiments, transactions on the single-wire bus begin with an initialization sequence. The initialization sequence may consist of a reset pulse sent by a bus master, followed by presence pulses sent by the slaves. The presence pulse informs the bus master that the dual-port circuit is on the bus and ready for operation. Single-wire signaling and timing

[0085] To ensure data integrity, the dual-port circuit may require strict protocols that may consist of four types of signals on a single line: a reset sequence with a reset pulse and a presence pulse, write zero, write one, and read data. In one or more embodiments, the bus master initiates all falling edges except the presence pulse. The dual-port circuit can communicate at override speed when passthrough mode is not enabled.

[0086] In one or more embodiments, to go from idle to active, the voltage on the single-wire line must be from V PUP below the threshold V TL To go from active to idle, the voltage must drop from V ILMAX starting above the threshold V TH The time it takes for the voltage to reach this increase is Fig.9 as ε; and its duration depends on the pull-up resistor used (R PUP ) and the capacity of the connected single-wire network. The voltage V ILMAX is relevant for the dual-port circuit when a logic level is determined without triggering any events.

[0087] Fig. Figure 10 shows an initialization sequence to begin communication with the dual-port circuit. A reset pulse followed by a presence pulse indicates that the dual-port circuit is ready to receive data when the correct ROM and device function command is given. If a bus master uses slew rate control on the falling edge, it may need to hold the line for t RSTL +t F be pulled down to compensate for the edge. In one or more embodiments, the t RSTL not more than 80 µs.

[0088] In one or more embodiments, a bus master, after releasing the line, enters receive mode. The single-wire bus is pulled to V via the pull-up resistor or, in the case of a special driver chip, via the active circuit. PUP In one or more embodiments, the single-wire bus is pulled to V by the pull-up resistor. PUP If the threshold V TH is exceeded, the dual-port circuit waits and then sends a presence pulse by pulling the line low. To detect a presence pulse, the master must check the logic state of the single-wire line at t MSP test.

[0089] In one or more embodiments, the dual-port circuit is immediately after the expiration of t RSTH ready for data communication. In a network with a mixed population, t RSTHmay be extended to at least 48 µs at overdrive speed to accommodate other single-wire circuits or devices. Read / write time slots

[0090] In one or more embodiments, data communication with the dual-port circuit takes place in time slots, each carrying a single bit. Write time slots transport data from the bus master to the slave. In read time slots, data is transferred from a slave to a master. Fig. Figure 9 shows the definitions of the write and read time slots.

[0091] In one or more embodiments, communication begins with the master pulling the data line low. When the voltage on the single-wire line falls below the threshold V TLfalls, the dual-port circuit starts its internal timer, which determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. Master-to-slave

[0092] In one or more embodiments, for a write-once time slot, the voltage on the data line must be V TH -Threshold before the write-one low time t W1LMAX has expired. For a write zero time slot, the voltage on the data line must be below V TH -Threshold remain until the write zero low time t W0LMIN has expired. For reliable communication, the voltage on the data line should be constant throughout the entire window t W0L or t W1L V ILMAX After the V TH threshold has been exceeded, the dual-port circuit requires a recovery time tREC before it is ready for the next time slot. Slave-to-Master

[0093] In one or more embodiments, a data read window begins as a write-one time slot. The voltage on the data line remains below V TL until the read low time t RL has expired. During the t RL window, if the dual-port circuit responds with a 0, it begins pulling the data line low. Its internal timing generator determines when this pull-down ends and the voltage rises again. If the dual-port circuit responds with a 1, the data line is not held low at all, and the voltage rises as soon as t RL is over.

[0094] In one or more embodiments, the sum of t RL+ δ (rise time) on the one hand and the internal timing generator of the dual-port circuit on the other hand, a main sampling window (t MSRMIN are MSRMAX ), in which the master performs a read from the data line. In one or more embodiments, for the most reliable communication, t RL may be as short as is permissible, and the master may need to be close to t MSRMAX , but not later. After reading from the data line, the master waits until t SCHLlTZ has expired. This may provide sufficient recovery time t REC so that the dual-port circuit prepares for the next time slot. It should be noted that the t specified here REC only applies to a single dual-port circuit connected to a single-wire line. For multi-device configurations, t RECmay need to be extended to accommodate the additional single-wire circuit or device input capacitance. Alternatively, an interface that performs active pull-up during the single-wire recovery time, such as the dedicated single-wire line drivers, can be used. Single-wire ROM instructions

[0095] In one or more embodiments, once a bus master detects a presence, it can issue one or more ROM function commands supported by the dual-port circuit. In one or more embodiments, the ROM function commands are 8 bits long. Fig.Figure 11 illustrates an exemplary ROM function flow process according to one or more embodiments of the present invention. The process includes determining the output of the Read ROM command 1102, determining the output of the Match ROM command 1104, determining the output of the Search ROM command 1106, determining the output of the Skip ROM command 1108, and determining the output of the Resume command 1110. A descriptive list of these ROM function commands in Fig. 11 follows in the following sections, and the commands are summarized in Table 18 shown below. Table 18. Summary of single-wire ROM commands ROM FUNCTION COMMAND DESCRIPTION Search ROM Search for a device Read-ROM Read ROM from the device (single-drop) Match ROM Select a device by ROM number Skip ROM Select only device on single wire Resume Select device with RC bit set Overdrive Skip ROM Set all devices to overdrive Overdrive Match ROM Set the device to override with the ROM

[0096] Search ROM: When a system initially boots up, the bus master may not know the number of devices on the single-wire bus or their ROM ID numbers. By exploiting the wired-AND property of the bus, the master can identify the ID of all slave devices using a process of elimination. For each bit in the ID number, the bus master issues a triplet of time slots, starting with the least significant bit. In the first slot, each slave device participating in the search issues the true value of its ID number bit. In the second slot, each slave device participating in the search issues the complemented value of its ID number bit. In the third slot, the master writes the true value of the bit to be selected. Any slave devices that do not match the bit written by the master no longer participate in the search. If both bits read are zero, the master knows that slave devices exist with two states of the bit.By selecting which state to write, the bus master branches the search tree. After a complete pass, the bus master knows the ROM ID number of a single device. Additional passes identify the ID numbers of the remaining devices.

[0097] Read-ROM: The Read-ROM command allows the bus master to read ROM information, such as an 8-bit standard character, a unique 48-bit serial number, and an 8-bit CRC from a ROM integrated into the dual-port circuit. This command may only be used when a single slave is on the bus. If more than one slave is present on the bus, a data collision occurs if all slaves attempt to transmit simultaneously (open drain results in a wired-AND result). The resulting standard character and 48-bit serial number result in a CRC mismatch.

[0098] Match ROM: The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific dual-port circuit on a multi-drop bus. Only the dual-port circuit that exactly matches the 64-bit ROM sequence will respond to the subsequent device function command. All other slaves wait for a reset pulse. This command can be used with a single device or multiple devices on the bus.

[0099] Skip ROM: This command can save time in a single-drop bus system by allowing the bus master to access the device functions without specifying the 64-bit ROM ID. If more than one slave is present on the bus and, for example, a Read command is issued following the Skip ROM command, a data collision will occur on the bus if multiple slaves transmit simultaneously (open-drain pulldowns produce a wired AND result).

[0100] Resume: To maximize data throughput in a multi-drop environment, the Resume command is available. This command checks the status of the RC bit and, if set, transfers control directly to the device function commands, similar to a Skip ROM command. One way to set the RC bit is to successfully execute the Match ROM, Search ROM, or Overdrive Match ROM command. Once the RC bit is set, the device can be accessed repeatedly via the Resume command. Accessing another device on the bus clears the RC bit, preventing two or more devices from responding to the Resume command at the same time. Device function commands

[0101] After a 1-wire reset / presence cycle and a ROM function command sequence are successful, a device function command can be accepted. Fig.Figure 13 shows a process diagram for a device function command flow for single-wire applications according to various embodiments of the invention. A descriptive list of these device function commands in Fig. 13 follows in the sections following the summary shown above in Table 1.

[0102] Fig. Figure 13 is a process diagram for device function command flow for single-wire applications according to various embodiments of the invention. The process starts with the ROM function flow diagram shown in Fig.11. In step 1202, a master (device or circuit) sends a device function command. In step 1204, the write command byte verification is checked. In response to the verification acknowledgement (Y), the process proceeds to step 1206, where the master transmits one or more parameter / data bytes. Subsequently, in step 1208, the master receives a CRC-16 (the inverse of the command, and parameter / data).

[0103] In response to a non-verification (N) for step 1204, the process proceeds to step 1210, where the read command byte verification is checked. In response to a verification affirmation (Y) for step 1210, the process proceeds to step 1212, where the master receives one or more data bytes. Next, in step 1214, the master receives a CRC-16 (the inverse of the command and data).

[0104] In response to a non-verification (N) for step 1210, or after step 1208 or step 1214, the process proceeds to step 1216, where a master transmit reset is verified. If a master transmit reset is not the case, the process proceeds to step 1218, where the master receives one or more "1"s, and then returns to step 1216 to reverify the master transmit reset. If a master transmit reset is the case, the process proceeds to the ROM function flowchart in step 1220. State diagram

[0105] In view of the above description, Fig.13 shows a state diagram for the operation of the dual-port circuit, according to one or more embodiments of the invention. The state diagram begins with a power-on reset (POR). In step 1302, a check is made to determine whether a charging supply is present at the IOA connection. The check can be implemented by comparing whether the voltage on the IOA connection is greater than a threshold voltage V CMP (e.g., 4 V). In response to a yes, the process proceeds to step 1304, where the IOA connection is set to "state of charge" and the IOB connection is set to single-wire operation (by setting the token pin to "1" with the CD pin set to low "0"), and then returns to step 1302 for re-verification.

[0106] In response to no charging supply being present on the IOA link, the process proceeds to step 1306, where it checks whether the QM bit is set. If so, the process proceeds to step 1322, where the IOA link is set to "quiet mode," where the QM bit is set to 1, a timer begins monitoring the IOA pin for activity, and the IOA link is set to single-wire operation (by setting the Token pin high and the CD pin high). After step 1322, the process proceeds to single-wire communication on the IOA link, checking in step 1328 whether a falling edge occurred before the time expires. In response to the timer expiring before another falling IOA edge is received, the process proceeds to step 1334 with the QM bit cleared and then returns to step 1302.In response to the falling IOA edge before the timer expires, the process proceeds to the timer reset and then back to step 1322.

[0107] If step 1306 is negative, the process proceeds to step 1308, where it is verified whether the passthrough mode (PTM) is set. If so, the process proceeds to step 1324, where the IOA / IOB connection is set to a "passthrough mode" with the Token pin clocking and the CD pin set high. After step 1324, the process proceeds to passthrough communication on IOA / IOB connections, verifying in step 1330 whether a falling edge has occurred before a passthrough mode timer expires. In response to the timer expiring before receiving another falling IOA or IOB edge, the process proceeds to step 1336 with the PTM bit cleared and then back to step 1302. In response to the falling edge of IOA or IOB before the timer expiring, the process proceeds to the timer reset and then back to step 1324.

[0108] If no from step 1308, the process proceeds to step 1310, where it is verified whether the pull-up bit is set. If yes, the process starts a timer and continues to step 1326, where the IOA connection is put into an "impedance check state" via a pull-up and the IOB connection is set to "single-wire operation" (where the Token pin is set to 1 and the CD pin is set to 1). Following step 1326, the process proceeds to single-wire communication over the IOB connection, where it is verified in step 1332 whether a falling edge has occurred before a timer for the IOB single-wire communication expires. In response to the timer expiring before receiving another falling IOB edge, the process proceeds to step 1338, clearing the pull-up and restoring the pull-down, and then returns to step 1302.In response to the falling IOB edge before the timer expires, the process proceeds to the timer reset and then back to step 1326.

[0109] If no from step 1310, the process proceeds to step 1312, where it is verified whether the IOA connection is at a logic idle high. If yes for step 1312, the process proceeds to step 1314, where the IOA connection is set in a "single-wire operation" (setting the Token pin to 0 and the CD pin to 1). If not, for step 1312, the process proceeds to step 1315 to verify whether a charge supply is present at the IOA connection. Verification can be implemented by comparing whether the voltage on the IOA connection is greater than a threshold voltage V CMP(e.g., 4 V). In response to a yes to step 1315, the process proceeds to step 1304. In response to a no to step 1315, the process proceeds to step 1306. After step 1314, the timer begins with a falling edge on the IOA connection. In step 1316, it is verified whether IOA is logic low for the entire time period. In response to a logic low IOA during the entire time period in 1316, the process proceeds to step 1318, where the IOA connection is set to single-wire operation and the IOA connection is observed (by setting the Token pin to 1 and setting the CD pin to 1), and then proceeds to step 1320, where it is verified whether the IOA connection is logic high. In response to an IOA that is not logic low during the entire time period 1316, the process proceeds to step 1314.In response to the IOA link being at logic high at step 1320, the process returns to the beginning at step 1302. In response to the IOA link not being at logic high at step 1320, the process returns to step 1318 to continue single-wire operation on the IOB link. Improved network behavior

[0110] In one or more embodiments, in a single-wire environment, line termination is possible during transients controlled by the bus master (single-wire driver). Single-wire networks are therefore susceptible to noise from various sources. Depending on the physical size and topology of the network, reflections from endpoints and branch points may add up or cancel each other to some extent. Such reflections are visible as signal distortion or ringing on the single-wire communication line. Noise coupled to the single-wire line from external sources can also cause signal distortion. An error during the rising edge of a timeslot can cause a slave device to lose synchronization with the master and, consequently, can cause a search ROM instruction to deadlock or a device-specific function instruction to abort.

[0111] For better performance in network applications, the dual-port circuit uses a single-wire front end that is less sensitive to noise. In one or more embodiments, the IOA / IOB single-wire front end has hysteresis and a rising edge hold delay. Fig. 14 shows a noise suppression scheme according to various embodiments of the invention.

[0112] When going from low to high, if the line is above V TH increases, but not below V TL falls, the error is filtered, as shown by line 1402 in the figure. The holding delay for rising edges (nominally 100 ns), t REH , filters out interference below V TL fall before t REH has expired, as shown by line 1404. In fact, the device does not see the initial increase, and the t REH -Delay is reset when the line is below V TLIf the line after t REH under V TL falls, the signal interference is not filtered and is used as the beginning of a new time slot, as shown by line 1406.

[0113] In one or more embodiments, the falling edge of the presence pulse has a controlled slew rate independent of the time slot to reduce ringing. The fall delay may be specified by t FPD be specified.

[0114] Embodiments of the present invention can be implemented in various applications, including, but not limited to, TWS earbuds and a charging case, a communication bridge between two hosts, dual-controlled general-purpose input / output ports, low-voltage single-rail level translation with tracking ID, and use cases with charging power over a 1-wire bus, etc. Benefits of the implementation may include enabling advanced TWS features while maintaining the two-contact solution, detecting earbud insertion into a charging case, the ability to dissipate power from the single-wire IOA connection, detecting power-on pulses and a 64-bit identification number (ROM ID) available for reading upon insertion when the charging state is disabled, detecting a dead battery in the charging case by earbuds, and available GPIO pins for optional functions in accessories.The ability to forward status information between the charging case and earbuds, a pass-through mode for fast firmware updates between hosts at up to 512 kbps, a 5 V specification on a single-wire IOA pin for switching the available charging power, a minimal dual 1-wire interface for low cost and interface complexity, the ability to operate in a multi-voltage system, communication with two hosts each with two digital signals at 90 kbps, high ESD immunity due to a single-wire IOA pin, etc.

[0115] In one or more embodiments, with respect to power-on presence pulse detection, a power-on presence function may be maintained by detecting whether charging power is present at the first single-wire connection (IOA). When charging power is applied to the IOA, the device (e.g., an earbud) integrated into the dual-port single-wire circuit may skip its power-on presence; otherwise, when the device is placed in a charging case, a power-on presence is generated.

[0116] Those skilled in the art will appreciate that the foregoing examples and embodiments are exemplary and do not limit the scope of the present disclosure. All permutations, improvements, equivalents, combinations, and enhancements thereto that would be apparent to one skilled in the art upon reading the specification and studying the drawings are intended to be included within the true spirit and scope of the present disclosure. It should also be noted that elements of claims may be arranged differently, including multiple dependencies, configurations, and combinations.

Claims

[1] Dual-port circuit for single-wire communication, comprising: a first interface for communicating with a first circuit via a first single-wire connection in response to a voltage at the first single-wire connection being higher than a predetermined threshold voltage, wherein a charging activity is activated using the voltage at the first single-wire connection; a second interface for communicating with a second circuit via a second single-wire connection, wherein the first single-wire connection or the second single-wire connection is activated at a given time for single-wire data communication, wherein the first interface and the second interface, upon activation, establish a bidirectional level translation between the first single-wire connection and the second single-wire connection in a pass-through mode; and a buffer in communication with the first single-wire connection and the second single-wire connection for transferring data during the single-wire data communication. [2] The dual-port circuit of claim 1, wherein in passthrough mode, communication between the first interface and the second interface supports simplex or half-duplex universal asynchronous receiver / transmitter (UART) communication. [3] A dual-port circuit according to claim 1 or 2, wherein the bidirectional level translation is achieved by alternatively operating two inverter gate paths between the first interface and the second interface. [4] Dual-port circuit according to one of claims 1 to 3, wherein the pass-through mode is activated by a timer. [5] The dual-port circuit of any one of claims 1 to 4, wherein activation of the first single-wire connection or the second single-wire connection for single-wire data communication is controlled by a token pin, wherein when the token pin is set to a first logic level, the first single-wire connection is set for single-wire data communication, when the token pin is set to a second logic level opposite to the first logic level, the second single-wire connection is set for single-wire data communication. [6] The dual-port circuit of claim 5, wherein the token pin outputs a clock signal in passthrough mode. [7] The dual-port circuit of any one of claims 1 to 6, wherein the charging activity comprises coupling a voltage source to a battery charger, the battery charger being configured to charge at least one battery. [8] The dual-port circuit of claim 7, wherein the voltage source comprises a charging battery. [9] The dual-port circuit of claim 8, wherein the charging battery has a battery capacity greater than a battery capacity of the at least one battery. [10] A method for bridging single-wire communication, comprising: coupling a first interface of a dual-port circuit to a first circuit via a first single-wire connection; coupling a second interface of the dual-port circuit to a second circuit via a second single-wire connection; Coordinating the operation of the first single-wire connection and the second single-wire connection by activating the first single-wire connection or the second single-wire connection for single-wire data communication at a particular time, wherein a buffer is in communication with the first and second single-wire connections and is configured to transmit data during the single-wire data communication, and when activated, establishing a bidirectional level translation between the first single-wire connection and the second wire connection in a pass-through mode. [11] The method of claim 10, wherein in passthrough mode, communication between the first interface and the second interface supports universal simplex or half-duplex universal asynchronous receiver / transmitter (UART) communication. [12] The method of claim 10 or 11, further comprising: in response to a voltage at the first single-wire connection being higher than a predetermined threshold voltage, activating a charging activity using the voltage at the first single-wire connection. [13] A method according to any one of claims 10 to 12, wherein the activation of the first single-wire connection or the second single-wire connection for single-wire data communication is controlled by a token pin, wherein when the token pin is set to a first logic level, the first single-wire connection is set for single-wire communication, when the token pin is set to a second logic level opposite to the first logic level, the second single-wire connection is set for single-wire communication. [14] The method of claim 13, wherein in passthrough mode the token pin outputs a clock signal. [15] A single-wire communication system comprising: a first circuit comprising a first input / output interface for communicating over a first single-wire connection, wherein, in response to a voltage at the first single-wire connection being higher than a predetermined threshold voltage, a charging activity is activated using the voltage at the first single-wire connection; a second circuit having a second input / output interface for communication via a second single-wire connection; a dual-port circuit coupled between the first circuit and the second circuit, the dual-port circuit comprising a first interface for communicating with a first circuit via the first single-wire connection and a second interface for communicating with the second circuit via the second single-wire connection, the first single-wire connection or the second single-wire connection being activated for single-wire data communication at a given time, the first interface and the second interface establishing bidirectional level translation between the first circuit and the second circuit in a pass-through mode; and a buffer in communication with the first and second single-wire connections and configured to transmit data during the single-wire communication. [16] The system of claim 15, wherein the buffer and the dual-port circuit are integrated on a single chip. [17] The system of claim 16, wherein the single chip and the second circuit are contained together in a single device. [18] The system of claim 17, wherein the single device is a true wireless stereo (TWS) earphone. [19] The system of claim 18, wherein the first circuit is a microcontroller integrated into a charging case for the TWS earphone. [20] The system of claim 18 or 19, wherein the TWS earbud detects whether charging power is present at the first single-wire connection when the TWS earbud is placed in the charging case, wherein, in response to the charging power being applied to the first single-wire connection, the TWS earbud skips a power-on presence.

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