Three-dimensional storage device and method

Abstract

Component comprising: a first dielectric layer (106) having a first side wall; a second dielectric layer (106) having a second side wall; a word line (116) between the first dielectric layer (106) and the second dielectric layer (106), the word line (116) having an outer side wall (116S1) and an inner side wall (116S2), the inner side wall (116S2) being recessed relative to the outer side wall (116S1), the first side wall and the second side wall; a storage layer (120) extending along the outer side wall (116S1) of the word line (116), the inner side wall (116S2) of the word line (116), the first side wall of the first dielectric layer (106) and the second side wall of the second dielectric layer (106);and a semiconductor layer (122) extending along the storage layer (120), wherein the word line (116) has an I-carrier shape, and a bit line in contact with a side wall of the semiconductor layer (122) and a side wall of the storage layer (120); a source line in contact with the side wall of the semiconductor layer (122) and the side wall of the storage layer (120); and an insulating region (126) between the source line and the bit line, wherein the insulating region (126) is in contact with the side wall of the semiconductor layer (122) and the side wall of the storage layer (120).

Description

BACKGROUNDSemiconductor memories are used in integrated circuits for electronic applications, for example, in radios, televisions, mobile phones and personal computers (PCs). Semiconductor memories comprise two main categories. On the one hand, volatile memory and, on the other hand, nonvolatile memory. Volatile memories include random access memory (RAM) which can be further divided into two sub-categories, namely static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM and DRAM are both volatile because they lose the stored information when not energized.In contrast, non-volatile memories may hold the stored data. One type of nonvolatile semiconductor memory is ferroelectric random access memory (FeRAM). Among the advantages of FeRAM are its high read / write speed and its small size.US 2017 / 0 373 086 A1 relates to memory devices and their manufacture comprising a stack of alternating conductive and dielectric layers, wherein the conductive layers form word lines or control gates of memory cells.US 2012 / 0 132 981 A1 relates to a pillar-shaped semiconductor, wherein a floating gate electrode is formed on a side surface of the pillar-shaped semiconductor via a tunnel dielectric film, and a control gate electrode is formed so as to surround the floating gate electrode via a block dielectric film.US 2017 / 0 125 482 A1 relates to a semiconductor memory device: a semiconductor layer extending in a first direction; a wiring line extending in a second direction intersecting the first direction; a variable resistor layer provided between this first wiring line and the first semiconductor layer; and a first gate electrode extending in the first direction and facing the semiconductor layer via a first insulating layer.US 2011 / 0 298 037 A1 relates to a nonvolatile memory device having a vertical structure and a channel layer extending in a vertical direction on a substrate, wherein at least one of a plurality of transistors has at least one recess in a gate of the transistor, into which at least one protrusion containing the channel layer extends.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with common industry practice. Indeed, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. Figures 1A, 1B, and 1C are various views of a memory array. FIGS. 2-16D are views of intermediate stages in fabricating a memory array, in accordance with some embodiments. FIGS. 17A through 17J are views of intermediate stages in fabricating a staircase structure of a memory array, in accordance with some embodiments. FIGS. 18A and 18B are three-dimensional views of thin film transistors according to various embodiments. FIG. 19 is a three-dimensional view of a memory array at an intermediate stage in fabrication, in accordance with some other embodiments. FIG. 20 is a three-dimensional view of a memory array at an intermediate stage in fabrication, in accordance with some other embodiments. FIG. 21 is a view of an intermediate phase in fabricating a memory array according to some other embodiments. FIG. 22 is a three-dimensional view of a memory array at an intermediate stage in fabrication, in accordance with some other embodiments. FIG. 23 is a cross-sectional view of a semiconductor device according to some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments for implementing different features of the invention. In order to simplify the present disclosure, concrete examples of components and arrangements will be described below. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Further, spatially relative terms such as "below," "below," "lower / r / s," "above," "upper / r / s," and the like may be used herein to simplify the description to describe the relationship of an element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The object may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may also be interpreted accordingly.According to various embodiments, three-dimensional memory arrays are formed of transistors (such as programmable thin film transistors (TFTs)) having three-dimensional channel regions. Such channel regions may be formed from word lines having main portions and protruding portions. The film stacks for the transistors are then deposited along the main portions and the protruding portions of the word lines. The bit lines and the source lines are formed in contact with the film stacks for the transistors, thereby completing the formation of the transistors. Forming transistors having three-dimensional channel regions may enable improved performance of the transistors.FIGS. 1A, 1B, and 1C illustrate examples of a memory array 50, FIG. 1A illustrates an example of a portion of the memory array 50 in a three-dimensional view; FIG. 1B illustrates a circuit diagram of the memory array 50, and FIG. 1C illustrates a plan view of a portion of the memory array 50. the memory array 50 includes a plurality of memory cells 52 that may be arranged in a grid of rows and columns. The memory cells 52 may also be vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The memory array 50 may be disposed in a back-end-of-line (BEOL) of a semiconductor chip. For example, the memory array 50 may be disposed in the interconnect layers of the semiconductor chip, such as over one or more active devices (e.g., transistors) formed on a semiconductor substrate.The memory array 50 may be such a memory array as a NOR memory array or the like. Each memory cell 52 may include a transistor 54 (such as a TFT) with an isolation such that the memory layer 84 serves as a gate dielectric. The gate of each transistor 54 is electrically coupled to a respective wordline (e.g., conductive line 72), a first source / drain region of each transistor 54 is electrically coupled to a respective bitline (e.g., conductive line 64B), and a second source / drain region of each transistor 54 is electrically coupled to a respective source line (e.g., conductive line 64S) that electrically couples the second source / drain region to ground. The memory cells 52 in a same horizontal row of the memory array 50 may share a common word line, while the memory cells 52 in a same vertical column of the memory array 50 may share a common source line and a common bit line.The memory array 50 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines), with dielectric layers 62 disposed between adjacent conductive lines 72. The conductive lines 72 extend in a direction D 1, which is parallel to a main surface of an underlying substrate (not explicitly illustrated in FIGS. 1A and 1B ). The conductive lines 72 may be part of a staircase structure such that lower conductive lines 72 are longer than upper conductive lines 72 and extend laterally beyond their end points. For example, in FIG. 1A, a plurality of stacked layers of conductive lines 72 are illustrated, with the uppermost conductive lines 72 being the shortest and the lowermost conductive lines 72 being the longest. The respective lengths of the conductive lines 72 may increase toward the underlying substrate. In this manner, a portion of each of the conductive lines 72 may be accessible from above the memory array 50, and conductive contacts 66 (see FIG. 1C ) may be formed to an exposed portion of each of the conductive lines 72. When the memory array 50 is disposed in the interconnect layers of a semiconductor chip, the conductive contacts 66 may be, for example, vias that connect the exposed portions of the conductive lines 72 to interconnects 68 (see FIG. 1C ) of overlying interconnect layers.Memory array 50 further includes a plurality of conductive lines 64B (e.g., bit lines) and conductive lines 64S (e.g., source lines). The conductive lines 64B, 64S are arranged between the conductive lines 72 in a direction D 2 perpendicular to the direction D 1. The conductive lines 64B, 64S may each extend in a direction D 3 perpendicular to the direction D 1. Isolation regions 74 are disposed between and isolate the individual adjacent conductive lines 64B and 64S. Pairs of conductive lines 64B, 64S along with a crossing conductive line 72 define the boundaries of each memory cell 52, and an isolation region 76 is disposed between and isolates adjacent pairs of conductive lines 64B, 64S. The conductive lines 64S may be electrically coupled to ground. Although FIG. 1A shows a particular spatial arrangement of the conductive lines 64B with respect to the conductive lines 64S, it should be understood that the spatial arrangement of the conductive lines 64B, 64S may also be reversed.The memory array 50 may also include semiconductor layers 82. The semiconductor layers 82 may provide channel regions for the transistors 54 of the memory cells 52. For example, a portion of a semiconductor layer 82 that crosses the conductive line 72 may allow current to flow from the conductive lines 64B to the conductive lines 64S (e.g., in the direction indicated by the arrow 56) when an appropriate voltage (e.g., higher than a respective threshold voltage (V th) of a respective transistor 54) is applied via a respective conductive line 72. In FIG. 1A, each semiconductor layer 82 is in contact with a surface of each respective wordline (e.g., each conductive line 72), thereby providing planar channel regions for the transistors 54. As discussed in more detail below, according to various embodiments, the semiconductor layers 82 are formed to contact multiple surfaces of the respective word lines (e.g., the conductive lines 72), thereby providing three-dimensional channel regions for the transistors 54.A memory layer 84 is disposed between the conductive lines 72 and the semiconductor layers 82, and the memory layer 84 may provide gate dielectrics for the transistors 54. The memory layer 84 may comprise a ferroelectric material such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. Accordingly, memory array 50 may also be referred to as a ferroelectric random access memory (FeRAM) array. Alternatively, the memory layer 84 may be a multi-layer structure including a layer of silicon nitride between two silicon oxide layers (e.g., an oxide-nitride-oxide (ONO) structure), another ferroelectric material, another type of memory layer (e.g., capable of storing a bit), or the like.When the memory layer 84 comprises a ferroelectric material, the memory layer 84 may be polarized in one of two different directions, and the polarization direction may be changed by applying an appropriate voltage difference across the memory layer 84 and generating an appropriate electric field. Polarization may be relatively localized (e.g., generally only within the boundaries of the memory cells 52) and a contiguous region of the memory layer 84 may extend across a plurality of memory cells 52. Depending on a polarization direction of a particular region of the storage layer 84, the threshold voltage of a corresponding transistor 54 varies and a digital value (e.g., 0 or 1) may be stored. For example, the respective transistor 54 may have a relatively low threshold voltage when a portion of the storage layer 84 has a first direction of electrical polarization, and the respective transistor 54 may have a relatively high threshold voltage when the portion of the storage layer 84 has a second direction of electrical polarization. The difference between the two threshold voltages may be referred to as the threshold voltage offset. A larger threshold voltage offset makes reading the digital value stored in the corresponding memory cell 52 easier (e.g., less error prone).To perform a write operation on a memory cell 52, a write voltage is applied across a portion of the memory layer 84 corresponding to the memory cell 52. The write voltage may be applied, for example, by applying appropriate voltages to a corresponding conductive line 72 (e.g., the word line) and the corresponding conductive lines 64B, 64S (e.g., the bit / source line). By applying a write voltage across the portion of the storage layer 84, the polarization direction of the region of the storage layer 84 can be changed. As a result, the corresponding threshold voltage of the corresponding transistor 54 may also be switched from a low threshold voltage to a high threshold voltage or vice versa, and a digital value may be stored in the memory cell 52. Since the conductive lines 72 cross the conductive lines 64B, 64S, individual memory cells 52 may be selected for the write operation.To perform a read operation on the memory cell 52, a read voltage (a voltage between the low and high threshold voltages) is applied to the corresponding conductive line 72 (e.g., the word line). Depending on the polarization direction of the corresponding region of the memory layer 84, the transistor 54 of the memory cell 52 may or may not be turned on. As a result, the conductive line 64B may or may not be discharged via the conductive line 64S (e.g., a source line coupled to ground), and the digital value stored in the memory cell 52 may be determined. Since the conductive lines 72 cross the conductive lines 64B, 64S, individual memory cells 52 may be selected for the read operation.FIGS. 2-16D are views of intermediate stages in fabricating a memory array 50, in accordance with some embodiments. FIGS. 15D and 16D are three-dimensional views. FIGS. 2, 3, 4, 5, 6, 7A, 7B, 7C, 7D, 8, 9, and 10 are cross-sectional views taken along reference cross section B-B in FIG. 15D. FIGS. 11A, 12A, 13A, 14A, 15A, and 16A are plan views taken along the reference cross section A-A in FIG. 15D. FIGS. 11B, 12B, 13B, 14B, 15B, and 16B are plan views taken along the reference cross section B-B in FIG. 15D and also along the reference cross section B-B in the corresponding figures marked "A". FIGS. 15C and 16C are cross-sectional views along the reference cross-section C-C in FIG. 15D and also along the reference cross-section C-C in the corresponding figures labeled "A". A portion of a memory array 50 is illustrated. Some features, such as the staircase arrangement of the word lines (see FIG. 1A ), are not shown in some figures for clarity.In FIG. 2, a substrate 102 is provided. The substrate 102 may be any structure that will be below the memory array 50. The substrate 102 may be a semiconductor substrate, for example a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-type dopant) or undoped. The substrate 102 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an isolation layer. The isolation layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 102 may be, but is not limited to, silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, Aluminiumgalliumarsenid gallium indium arsenide, gallium indium phosphide, and / or Galliumindiumarsenidphosphid; or combinations thereof. The substrate 102 may be, among other things, a dielectric material. For example, the substrate 102 may be a dielectric layer or may include a dielectric layer on a semiconductor substrate. Acceptable dielectric materials for dielectric substrates include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like, or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. In some embodiments, the substrate 102 is formed of silicon carbide.A multilayer stack 104 is formed over the substrate 102. The multilayer stack 104 includes alternating dielectric layers 106 and conductive layers 108. The multilayer stack 104 is structured in the subsequent processing. As such, the materials of the dielectric layers 106 and the conductive layers 108 each have a high etch selectivity when etching the substrate 102. The patterned dielectric layers 106 are used to isolate subsequently formed transistors. The patterned conductive layers 108 will serve as word lines for the transistors and are subsequently recessed such that the channel regions of the transistors are in contact with multiple areas of the word lines, thereby providing three-dimensional channel regions for the transistors. As such, the material of the dielectric layers 106 also has a high etch selectivity in etching the material of the conductive layers 108.The dielectric layers 106 may each be formed of an oxide such as silicon oxide, a nitride such as silicon nitride, a carbide such as silicon carbide, combinations thereof such as silicon oxynitride or silicon oxycarbide, or the like. The dielectric material of the dielectric layers 106 may be formed by an acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The thickness of each of the dielectric layers 106 may range from about 40 nm to about 50 nm.The conductive layers 108 may each be formed of a metal such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, or the like; a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like; alloys thereof; multiple layers thereof; or the like. The conductive material of the conductive layers 108 may be formed by an acceptable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The thickness of each of the conductive layers 108 may range from about 40 nm to about 50 nm. In some embodiments, the conductive layers 108 are formed with a different thickness than the dielectric layers 106. For example, the conductive layers 108 may be formed with a greater thickness than the dielectric layers 106.In the illustrated embodiment, the multilayer stack 104 includes four dielectric layers 106 and three conductive layers 108. It should be understood that the multilayer stack 104 may include other numbers of the dielectric layers 106 and the conductive layers 108. The multilayer stack 104 may have a total height in the range of about 1,000 nm to about 10,000 nm.In FIG. 3, trenches 110 are formed in the multilayer stack 104. In the illustrated embodiment, the trenches 110 extend through the multilayer stack 104 and expose the substrate 102. In another embodiment, the trenches 110 extend through some, but not all, layers of the multilayer stack 104. The trenches 110 may be patterned using acceptable photolithography and etching techniques, such as using an etching process that is selective with respect to the multilayer stack 104 (e.g., that selectively removes the materials of the dielectric layers 106 and the conductive layers 108 at a higher speed than the material of the substrate 102). The patterning may be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. In embodiments where the substrate 102 is formed of silicon carbide, the dielectric layers 106 are formed of silicon oxide, and the conductive layers 108 are formed of tungsten, the trenches 110 may be formed by a dry etch using a fluorine-based gas (e.g., CF 6, SF 6 etc.) mixed with oxygen (O2). After patterning, the respective patterned portions of the multilayer stack 104 are disposed between respective pairs of trenches 110. Each patterned portion of the multilayer stack 104 has a width W 1 in the second direction D 2 that may range from about 100 nm to about 120 nm. Further, each patterned portion of the multilayer stack 104 is separated by a separation distance S 1 in the second direction D 2 which may range from about 75 nm to about 85 nm.In some embodiments, the conductive layers 108 are formed by a different process. Alternatively, the multilayer stack 104 may, for example, alternately comprise dielectric layers 106 and sacrificial layers. The sacrificial layers may be formed of a different material than the dielectric layers 106. After forming the trenches 110 in the multilayer stack 104, the sacrificial layers may be replaced with the conductive layers 108. The sacrificial layers may be removed using, for example, an etching process that selectively etches the material of the sacrificial layers at a higher rate than the material of the dielectric layers 106. One or more layers of the conductive material may then be conformally deposited in the resulting openings, e.g., between the dielectric layers 106. A removal process, such as anisotropic etching, may be performed to remove the portions of the conductive material that are not between the dielectric layers 106 (e.g., those portions in the trenches 110), with the remaining portions of the conductive material between the dielectric layers 106 defining the conductive layers 108.In FIG. 4, the trenches 110 are extended to form sidewall recesses 112. In particular, the portions of the sidewalls of the conductive layers 108 exposed by the trenches 110 are recessed relative to the portions of the sidewalls of the dielectric layer 106 exposed by the trenches 110, such that the sidewall recesses 112 are formed. Although the sidewalls of the conductive layers 108 are illustrated as being straight, the sidewalls may be concave or convex. The sidewall recesses 112 may be formed by an acceptable etching process, such as one that is selective with respect to the material of the conductive layers 108 (e.g., that removes the material of the conductive layers 108 at a higher rate than the material(s) of the dielectric layers 106 and the substrate 102). The etching may be isotropic. In embodiments where the substrate 102 is formed of silicon carbide, the dielectric layers 106 are formed of silicon oxide, and the conductive layers 108 are formed of tungsten, the trenches 110 may be extended by wet etching using dilute hydrofluoric acid (dHF) and nitric acid (HNO 3).After formation, the sidewall recesses 112 have a depth D 4 in the second direction D 2 that extends past the sidewalls of the dielectric layers 106. Timed etching processes may be used to stop etching the sidewall recesses 112 after the sidewall recesses 112 have reached a desired depth D 4. For example, when the sidewall recesses 112 are formed by a wet etch using dHF and HNO 3 the wet etch may be performed for a duration in the range of about 10 seconds to about 120 seconds, which may result in the sidewall recesses 112 having a depth D 4 in the range of about 20 nm to about 60 nm. By forming the sidewall recesses 112, the upper surface and the lower surface of the dielectric layers 106 are exposed. After forming the sidewall recesses 112, the remaining portions of the conductive layers 108 have a width ∂ the second direction D 2 that may range from about 10 nm to about 200 nm, and the dielectric layers have a width W 3 in the second direction D 2 that may range from about 50 nm to about 320 nm. By forming the sidewall recesses 112, the widths of the conductive layers 108 may be reduced by about 5% to about 40%.In FIG. 5, a conductive layer 114 is conformally formed in the trenches 110 and the sidewall recesses 112. The conductive layer 114 may be formed of a metal such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, or the like; a metal nitride such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like; alloys thereof; multiple layers thereof; or the like. The conductive material of the conductive layer 114 may be formed by an acceptable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. In some embodiments, the conductive layer 114 is formed of the same conductive material as the conductive layers 108. For example, the conductive layers 108, 114 may each be formed of tungsten. In some embodiments, the conductive layer 114 is formed of a different conductive material than the conductive layers 108. For example, the conductive layers 108 may each be formed of tungsten and the conductive layer 114 may be formed of titanium nitride or tantalum nitride.The conductive layer 114 lines each of the sidewall recesses 112, but does not completely fill them (e.g., but only partially). After being lined, the sidewall recesses 112 have a depth D 5 in the second direction D 2 that extends past the sidewalls of the dielectric layers 106. The depth D 5 is less than the depth D 4( discussed above for FIG. 4 ). The thickness T 1 of the conductive layer 114 is affected such that the remaining portions of the sidewall recesses 112 have a desired depth D 5. For example, the thickness T 1 of the conductive layer 114 may be in the range of about 5 nm to about 20 nm, which may result in the remaining portions of the sidewall recesses 112 having a depth D 5 in the range of about 10 nm to about 50 nm.In FIG. 6, the conductive layer 114 is patterned to remove the portions of the conductive layer 114 outside the sidewall recesses 112, such as the portions of the conductive layer 114 on the sidewalls of the dielectric layers 106, the top surfaces of the 106 and the top surface of the substrate 102. The patterning may be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may include, for example, dry etching using a fluorine-based gas (e.g., CF 6, SF 6 etc.) mixed with oxygen (O 2).After patterning, the remaining portions of the conductive layers 108, 114 represent wordlines 116. In other words: The word lines 116 are defined by the patterning, wherein each word line 116 comprises a conductive layer 108 and patterned portions of a conductive layer 114. In embodiments where the conductive layer 114 is formed of the same conductive material as the conductive layers 108, the various conductive layers of the word lines 116 may merge with one another such that there are no detectable interfaces therebetween. In embodiments where the conductive layer 114 is formed of a different conductive material than the conductive layers 108, the various conductive layers of the word lines 116 may not merge with one another, such that there are detectable interfaces therebetween. Thus, each wordline 116 may be a single conductive material extending in a contiguous manner between the outer sidewalls of the wordline 116, or may include multiple conductive materials (e.g., adjacent to each other) extending in a non-contiguous manner between the outer sidewalls of the wordline 116.After forming the word lines 116, the sidewall recesses 112 extend into the word lines 116. The sidewall recesses 112 may extend into the word lines 116 along the entire length of the word lines 116. The sidewall recesses 112 maintain the depth D 5( discussed above for FIG. 5 ) in the second direction D 2 that extends past the outer sidewalls of the word lines 116 and the dielectric layers 106. As discussed in more detail below, one or more layers are formed in the sidewall recesses 112 that provide channel regions for the subsequently formed transistors, thereby allowing the layers to contact a greater portion of the areas of the word lines 116 than planar transistors.FIGS. 7A, 7B, 7C, and 7D are detail views of wordlines 116 according to various embodiments. The word lines 116 have I-carrier shapes, each including a main portion 116M and a plurality (e.g., four) of protruding portions 116P. Two pairs of the protruding portions 116P extend away from opposite sides of the main portion 116M. The main portion 116M may have a width W 4 in the range of about 20 nm to about 240 nm and a thickness T 2 in the range of about 30 nm to about 200 nm. Each of the protruding portions 116P may have a width W 5 in the range of about 10 nm to about 50 nm and an average thickness T 3 in the range of about 5 nm to about 30 nm. The thickness T 3 is less than the thickness T 2, such as about 5% to about 30% of the thickness T 2.Each wordline 116 includes an outer sidewall 116S 1( corresponding to a sidewall of a protruding portion 116P) and an inner sidewall 116S 2( corresponding to a sidewall of a main portion 116M). The inner sidewalls 116S 2 are recessed relative to the outer sidewalls 116S 1 as well as relative to the sidewalls of the dielectric layers 106 (see FIG. 6 ). Each outer sidewall 116S 1 is connected by a connecting surface 116S 3 to a corresponding inner sidewall 116S 2.The sidewall recesses 112 may have various different profile shapes. In the embodiments of FIGS. 7A and 7B, the sidewall recesses 112 have trapezoidal profile shapes in which each connection surface 116S 3 forms an obtuse angle θ 1 with a corresponding inner sidewall 116S 2. The obtuse angle θ 1 may range from about 92 degrees to about 98 degrees. Each connecting surface 116S 3 similarly forms an obtuse angle with the corresponding outer side wall 116S 1. In the embodiments of FIGS. 7C and 7D, the sidewall recesses 112 have rectangular profile shapes in which each connection surface 116S 3 forms a right angle θ 2 with the corresponding inner sidewall 116S 2. Each connecting surface 116S 3 similarly forms a right angle with the corresponding outer side wall 116S 1.The sidewall recesses 112 have interior corners 116C at the intersection of the outer sidewalls 116S 2 and the connection surfaces 116S 3 respectively. The inner corners 116C may have various different corner shapes. In the embodiments of FIGS. 7A and 7C, the inner corners 116C of the sidewall recesses 112 have sharp corner shapes. Sharp corner shapes are those formed by an arc having a length less than about 3% of the thickness T 2 of the word lines 116, such as an arc length in the range of about 1.2 nm to about 1.5 nm. In the embodiments of FIGS. 7B and 7D, the inner corners 116C of the sidewall recesses 112 have rounded corner shapes. Rounded corner shapes are those formed by an arc having a length greater than about 3% of the thickness T 2 of the word lines 116, such as having a length in the range of about 1.2 nm to about 1.5 nm.The various profile shapes and inner corner shapes of the sidewall recesses 112 may be determined by the etch selectivity between the material of the dielectric layers 106 and the material of the conductive layer 114 during the etch process used to remove the portions of the conductive layer 114 external to the sidewall recesses 112 (discussed above with reference to FIG. 6 ). The sidewall recesses 112 may be formed with trapezoidal profile shapes and / or rounded corner shapes by performing an etch with a low etch selectivity, such as an etch process that selectively removes the material of the conductive layer 114 about 2 to about 5 times faster than the material of the dielectric layers 106. The sidewall recesses 112 may be formed with rectangular profile shapes and / or sharp corner shapes by performing an etch with a high etch selectivity, such as an etch process that selectively removes the material of the conductive layer 114 about 5 to about 20 times faster than the material of the dielectric layers 106.As discussed in more detail below, the channel regions of the subsequently formed transistors will extend along and in contact with each of the surfaces 116S 1, 116 S 2, 116 S 3 of the word lines 116, thereby providing three-dimensional channel regions for the transistors. Such channel regions are formed by forming film stacks for the transistors in the sidewall recesses 112, e.g., between pairs of protruding portions 116P. Between the protruding portions 116P, at least memory layers (discussed in more detail below for FIG. 8 ) are deposited. In some embodiments, semiconductor layers (discussed in more detail below for FIG. 9 ) are also disposed between the protruding portions 116P. In some embodiments, isolation regions (discussed in more detail below for FIGS. 11A and 11B ) are also disposed between the protruding portions 116P. In some embodiments, conductive lines (discussed in greater detail below for FIG. 18B ) are also disposed between the protruding portions 116P.In FIG. 8, a storage layer 120 is conformally formed in the trenches 110 and the sidewall recesses 112. The storage layer 120 only partially fills the sidewall recesses 112. Subsequently, the memory layer 120 is patterned to form a plurality of memory layers (also referred to as data storage layers). The memory layer 120 is formed of a material acceptable for storing digital values in the transistors. In some embodiments, the memory layer 120 is formed of a high-k ferroelectric material, such as hafnium zirconium oxide (HfZrO); zirconium oxide (ZrO); hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), aluminum (Al), or the like; undoped hafnium oxide (HfO), or the like. In some embodiments, the memory layer 120 includes one or more low-k dielectric materials, such as silicon nitride, silicon oxide, silicon oxynitride, or the like. The material of the storage layer 120 may be formed by an acceptable deposition process, such as ALD, CVD, physical vapor deposition (PVD), or the like. In some embodiments, the memory layer 120 is ALD deposited HfZrO. The thickness of the storage layer 120 may be in the range of about 9 nm to about 11 nm.In FIG. 9, a semiconductor layer 122 is conformally formed on the memory layer 120, e.g., in the trenches 110 and the sidewall recesses 112. In this embodiment, the semiconductor layer 122 completely fills the remaining portions of the sidewall recesses 112 that are not filled with the memory layer 120. In another embodiment (discussed in more detail below for FIG. 20 ), the memory layer 120 as well as the semiconductor layer 122 only partially fill the sidewall recesses 112. Subsequently, the semiconductor layer 122 is patterned to form a plurality of semiconductor layers (also referred to as channel layers). The semiconductor layer 122 is formed of a semiconductor material acceptable for providing channel regions for the transistors, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), polysilicon, amorphous silicon, or the like. The material of the semiconductor layer 122 may be formed by an acceptable deposition process, such as ALD, CVD, PVD, or the like. In some embodiments, the semiconductor layer 122 is IGZTO deposited by ALD. The thickness of the semiconductor layer 122 may be in the range of about 9 nm to about 11 nm.In FIG. 10, the semiconductor layer 122 is patterned to form semiconductor layers 124. The semiconductor layer 122 is etched to remove the portions of the semiconductor layer 122 at the bottom of the trenches 110, such as the portions of the semiconductor layer 122 on the substrate 102, thus exposing the substrate 102 and separating the semiconductor layers 124 from horizontally adjacent transistors. The patterning may be any acceptable etching process, such as reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etching may be anisotropic. In this embodiment, the etching is performed to also remove the portions of the semiconductor layer 122 that are outside the sidewall recesses 112, such as the portions of the semiconductor layer 122 on the outer sidewalls of the memory layer 120, thereby exposing the outer sidewalls of the memory layer 120 and separating the semiconductor layers 124 of vertically adjacent transistors. In some other embodiments (discussed in more detail below for FIGS. 19 and 20 ), the etching is performed only to remove the portions of the semiconductor layer 122 at the bottom of the trenches 110, such that the portions of the semiconductor layer 122 remain on the outer sidewalls of the memory layer 120. How much is removed from the semiconductor layer 122 may be determined by the duration of the etching process, wherein a longer etching process removes more from the semiconductor layer 122.In FIGS. 11A and 11B, isolation regions 126 are formed to fill the remaining portions of the trenches 110. In embodiments where the sidewall recesses 112 are not completely filled with the semiconductor layers 124 (discussed in greater detail below for FIG. 20 ), the isolation regions 126 are also formed to fill the remaining portions of the sidewall recesses 112. In embodiments where the semiconductor layers 124 are bounded on the sidewall recesses 112, the isolation regions 126 extend along and contact both the semiconductor layers 124 and the memory layers 128. In embodiments where the semiconductor layers 124 extend outside the sidewall recesses 112, the isolation regions 126 are separated from the memory layers 128 by the semiconductor layers 124. The isolation regions 126 are formed of an insulating material that can protect and galvanically isolate the underlying semiconductor layers 124 and the storage layer 120. Acceptable dielectric materials include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like, or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. The material of the isolation regions 126 may be formed by an acceptable deposition process, such as ALD, CVD, flowable CVD (FCVD), or the like.In some embodiments, after forming the isolation material for isolation regions 126 in trenches 110, a removal process is applied to the various layers to remove excess material over the top dielectric layer 106 / wordline 116. The removal process may be a planarization process, such as chemical mechanical polishing (CMP), etch back, combinations thereof, or the like. The portions of the isolation material and the storage layer 120 remaining in the trenches 110 form the isolation regions 126 and the storage layers 128, respectively. The planarization process exposes the top dielectric layer 106 / wordline 116 such that after the planarization process, the top surfaces of the top dielectric layer 106 / wordline 116, the semiconductor layers 124, the isolation regions 126, and the memory layers 128 are coplanar (within process variations).At least the semiconductor layers 124 and the memory layers 128 have portions in the sidewall recesses 112. The isolation regions 126 may also include portions in the sidewall recesses 112 (discussed in greater detail below for FIG. 20 ). These features may extend into the sidewalls of the word lines 116 along the entire length of the word lines 116. The semiconductor layers 124 and the memory layers 128 thus extend along multiple faces of the word lines 116, thereby providing three-dimensional channel regions 124C (see FIGS. 15A and 16A ) for the transistors. Thus, by increasing the contact area of the word lines 116, the lengths of the channel regions 124C for the transistors may be increased, thereby improving the performance and efficiency of the transistors compared to transistors having planar channel regions. For example, three-dimensional channel regions may cause a stronger electric field at lower gate voltages, a weaker ON current (I ON), improved ON / OFF current ratios, and fewer leakage currents than planar channel regions. Enhancing the electric field in the channel regions may help improve the writing speed of the memory array 50.In FIGS. 12A and 12B, conductive line openings 130 are formed through the isolation regions 126. The openings 130 may be formed during an etching process that is selective with respect to the isolation regions 126 (e.g., that removes the material of the isolation regions 126 at a higher speed than the materials of the semiconductor layers 124 and / or the memory layers 128). For example, the openings 130 may be formed through the isolation regions 126 by a dry etch using ammonia (NH 3) and hydrogen fluoride (HF), which may be performed using an etch mask having a pattern corresponding to the conductive lines formed subsequently. In this embodiment, the etch is non-selective with respect to the material of the semiconductor layers 124, and the portions of the semiconductor layers 124 in the openings 130 remain after the etch. Consequently, the sidewall recesses 112 remain filled after the etching so that the subsequently formed conductive lines do not extend into the sidewall recesses 112 (discussed in more detail below for FIG. 18A ). In another embodiment, the etch is also selective with respect to the material of the semiconductor layers 124, and the portions of the semiconductor layers 124 in the openings 130 are removed after the etch such that the openings 130 extend laterally into the semiconductor layers 124. Thus, the sidewall recesses 112 may be partially remodeled such that the subsequently formed conductive lines also extend into the sidewall recesses 112 (discussed in greater detail below for FIG. 18B ).In FIGS. 13A and 13B, conductive lines 132 are formed in the openings 130. The conductive lines 132 thus extend through the isolation regions 126. As discussed in more detail below, conductive lines 132 represent pillars that are divided into bit lines and source lines for the transistors. The bit lines and the source lines also serve as source / drain regions of the transistors. As such, the conductive lines 132 are formed in contact with at least the semiconductor layers 124, such that the bit lines and the source lines are adjacent to the channel regions 124C (see FIGS. 15A and 16A ) of the transistors. In embodiments where the semiconductor layers 124 are bounded on the sidewall recesses 112, the conductive lines 132 (and thus the subsequently formed bitlines and source lines) extend along and contact both the semiconductor layers 124 and the memory layers 128. In embodiments where the semiconductor layers 124 extend outside the sidewall recesses 112, the conductive lines 132 (and thus the subsequently formed bit lines and source lines) are separated from the memory layers 128 by the semiconductor layers 124.As an example of forming the conductive lines 132, a liner such as a diffusion barrier layer, an adhesive layer, or the like and a main layer are formed in the openings 130. The liner may be formed of a conductive material such as titanium, titanium nitride, tantalum, tantalum nitride, or the like, which may be deposited by a conformal deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. In some embodiments, the liner may be, inter alia, an adhesion layer, and at least a portion of the adhesion layer may be treated to form a diffusion barrier layer. The main layer may be formed of a conductive material such as tungsten, cobalt, ruthenium, aluminum, nickel, copper, a copper alloy, silver, gold, or the like, which may be deposited by ALD, CVD, PVD, etc. In some embodiments, the conductive lines 132 include a liner formed of titanium nitride and a main layer formed of tungsten. A removal process is then applied to the various layers to remove excess material of the conductive lines 132 over the memory layers 128, isolation regions 126, semiconductor layers 124, and the top dielectric layer 106 / wordline 116. The removal process may be a planarization process, such as chemical mechanical polishing (CMP), etch back, combinations thereof, or the like. The remaining material forms the conductive lines 132 in the openings 130.In FIGS. 14A and 14B, openings 134 for isolation structures are formed through the conductive lines 132, the memory layers 128, and the semiconductor layers 124. The openings 134 divide the semiconductor layers 124 and the conductive lines 132 to form transistors 54 (see FIGS. 15A, 15C, 16A, and 16C ). Specifically, the conductive lines 132 are divided so as to form bit lines 132B and source lines 132S. The openings 134 may divide the conductive lines 132 into bit lines 132B and source lines 132S of equal or unequal width. As mentioned above, bit lines 132B and source lines 132S serve as source / drain regions of transistors 54. After forming the openings 134, each transistor 54 includes a portion of a semiconductor layer 124, a portion of a storage layer 128, a bit line 132B, and a source line 132S. The openings 134 are wider than the conductive lines 132 such that the openings 134 also extend laterally into the dielectric layers 106 and the word lines 116. The word lines 116 are not divided by the openings 134. The openings 134 may be formed during an etching process that removes the conductive and dielectric materials of the layers of the memory array 50. For example, the openings 134 may be formed by a dry etch using, for example, C 4 F 6, mixed with hydrogen (H 2) or oxygen (O 2) which may be performed using an etch mask having a pattern corresponding to the isolation structures formed subsequently.In FIGS. 15A, 15B, 15C, and 15D, isolation structures 136 are formed in the openings 134. Thus, the isolation structures 136 extend through the conductive lines 132, the memory layers 128, and the semiconductor layers 124. In addition, the isolation structures 136 extend laterally into the dielectric layers 106 and the word lines 116.As an example of forming the isolation structures 136, an isolation material is formed in the openings 134. The isolation material may be formed of oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like, or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like, which may be deposited by CVD, ALD, or the like. In some embodiments, the isolation structures 136 are formed of silicon oxide. A removal process is then applied to the various layers to remove excess isolation material of the isolation structures 136 over the source lines 132S, the bit lines 132B, the storage layers 128, the isolation regions 126, the semiconductor layers 124, and the top dielectric layer 106 / word line 116. The removal process may be a planarization process, such as chemical mechanical polishing (CMP), etch back, combinations thereof, or the like. The remaining insulation material forms the insulation structures 136 in the openings.In FIGS. 16A, 16B, 16C, and 16D, an interconnect structure 160 is formed over the intermediate structure. The interconnect structure 160 may include, for example, metallization structures 162 in a dielectric material 164 (not shown in FIG. 16D, see FIGS. 16B and 16C ). The dielectric material 164 may include one or more dielectric layers, such as one or more layers of low-k (LK) or extra low-k (ELK) dielectric material. The metallization structures 162 may be metallic interconnects (e.g., metallic lines and vias) formed in the one or more dielectric layers. The interconnect structure 160 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. The metallization structures 162 of the interconnect structure 160 are electrically connected to the bit lines 132B and the source lines 132S and interconnect the transistors 54 to form operable memories.As shown in FIG. 16A, bit lines 132B and source lines 132S are alternately formed along the rows and columns of the memory array 50. Forming the bit lines 132B and the source lines 132S in an alternating pattern helps avoid shorting adjacent bit lines 132B / source lines 132S in the cross-section of FIG. 16C when a word line 116 is activated.As mentioned above, the dielectric layers 106 and the word lines 116 may be formed in a staircase structure. The dielectric layers 106 and the word lines 11616 may be patterned in a desired step prior to forming the interconnect structure 160 to form the staircase structure. Forming the interconnect structure 160 includes forming conductive contacts connected to the exposed portions of each of the wordlines 116.FIGS. 17A through 17J are views of intermediate stages in fabricating a staircase structure of a memory array 50, in accordance with some embodiments. FIGS. 17A to 17J are illustrated along the reference cross section D-D illustrated in FIG. 16D. Some features of the transistors, such as the memory layers 128, the semiconductor layers 124, and the like (FIGS. 2-16D ) are not shown for clarity.In FIG. 17A, a mask 202 is formed over the multilayer stack 104. In this processing step, the multilayer stack 104 may alternately include dielectric layers 204 (such as the dielectric layers 106 referenced 204A, 204B, 204C, 204D discussed above) and conductive layers 206 (such as the word lines 116 referenced 206A, 206B, 206C discussed above). The mask 202 may be a resist or the like and may be formed by a spin-on technique or the like.In FIG. 17B, the mask 202 is patterned to expose the multi-layer stack 104 in the regions 210A while masking the remaining portions of the multi-layer stack 104. For example, the top layer (e.g., dielectric layer 204D) of multilayer stack 104 may be exposed in regions 210A. The mask 202 may be patterned using acceptable photolithography techniques.In FIG. 17C, the exposed portions of the multilayer stack 104 in the regions 210A are etched using the mask 202 as an etch mask. The etching may be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may remove portions of the dielectric layer 204D and the conductive layer 206C in the regions 210A and define openings 212. Because the dielectric layer 204D and the conductive layer 206C have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, the conductive layer 206C acts as an etch stop layer when the dielectric layer 204D is etched, and the dielectric layer 204C acts as an etch stop layer when the conductive layer 206C is etched. As a result, the portions of the conductive layer 206C and the dielectric layer 204D may be selectively removed without removing the remaining layers of the multilayer stack 104, and the openings 212 may extend to a desired depth. Alternatively, timed etching processes may be used to stop etching the openings 212 after the openings 212 have reached a desired depth. In the resulting structure, the dielectric layer 204C is exposed in the regions 210A.In FIG. 17D, the mask 202 is trimmed to expose additional portions of the multilayer stack 104. The mask 202 may be trimmed using acceptable photolithography and / or etching techniques. As a result of trimming, a width of the mask 202 is reduced, and also portions of the multilayer stack 104 may be exposed in the regions 210B. For example, a top surface of the dielectric layer 204C may be exposed in the regions 210A, and a top surface of the dielectric layer 204D may be exposed in the regions 210B.In FIG. 17E, portions of the dielectric layer 204D, the conductive layer 206C, the dielectric layer 204C, and the conductive layer 206B in the regions 210A and 210B are removed by acceptable etching processes using the mask 202 as an etch mask. The etching may be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may cause the openings 212 to extend further into the multi-layer stack 104. Because the dielectric layers 204D / 204C and the conductive layers 206C / 206B have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, conductive layer 206C acts as an etch stop layer when etching dielectric layer 204D; dielectric layer 204C acts as an etch stop layer when etching conductive layer 206C; conductive layer 206B acts as an etch stop layer when etching dielectric layer 204C; and dielectric layer 204B acts as an etch stop layer when etching conductive layer 206B. As a result, portions of the dielectric layers 204D / 204C and the conductive layer 206C / 206B may be selectively removed without removing the remaining layers of the multilayer stack 104, and the openings 212 may extend to a desired depth. Further, during the etching processes, unetched portions of the dielectric layers 204 and the conductive layers 206 act as an etch mask for underlying layers, and as a result, a prior patterning of the dielectric layer 204D and the conductive layer 206C (see FIG. 17D ) may be transferred to the underlying dielectric layer 204C and the conductive layer 206B. In the resulting structure, the dielectric layer 204B is exposed in the regions 210A, and the dielectric layer 204C is exposed in the regions 210B.In FIG. 17F, the mask 202 is trimmed to expose additional portions of the multilayer stack 104. The photoresist may be trimmed using acceptable photolithography techniques. As a result of trimming, the width of the mask 202 is reduced and, in addition, portions of the multilayer stack 104 may be exposed in the regions 210C. For example, a top surface of the dielectric layer 204B may be exposed in the regions 210A, a top surface of the dielectric layer 204C may be exposed in the regions 210B, and a top surface of the dielectric layer 204D may be exposed in the regions 210C.In FIG. 17G, portions of the dielectric layers 204D, 204C, 204B in the regions 210A, 210B, 210C are removed by acceptable etching processes using the mask 202 as an etch mask. The etching may be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic. The etching may cause the openings 212 to extend further into the multi-layer stack 104. In some embodiments, conductive layer 206C acts as an etch stop layer when etching dielectric layer 204D; conductive layer 206B acts as an etch stop layer when etching dielectric layer 204C; and conductive layer 206A acts as an etch stop layer when etching dielectric layer 204B. As a result, portions of the dielectric layers 204D, 204C, 204B may be selectively removed without removing the remaining layers of the multilayer stack 104, and the openings 212 may extend to a desired depth. Further, during the etching processes, each of the conductive layers 206 acts as an etch mask for underlying layers, and as a result, a previous patterning of the conductive layers 206C / 206B (see FIG. 17F ) may be transferred to the underlying dielectric layers 204C / 204B. In the resulting structure, conductive layer 206A is exposed in regions 210A; conductive layer 206B is exposed in regions 210B; and conductive layer 206C is exposed in regions 210C.In FIG. 17H, the mask 202 may be removed, such as by an acceptable ashing or wet stripping process. Thus, a staircase structure 214 is formed. The staircase structure comprises a stack of alternating dielectric layers 204 and conductive layers 206. The lower conductive layers 206 are wider and extend laterally beyond the upper conductive layers 206, and a width of the individual conductive layers 206 increases in the direction toward the substrate 102. For example, conductive layer 206A may be longer than conductive layer 206B; and conductive layer 206B may be longer than conductive layer 206C. As a result, in subsequent processing steps, conductive contacts may be formed from above the staircase structure 214 to each of the conductive layers 206.In FIG. 17I, an inter-metal dielectric (IMD) 216 is deposited over the multilayer stack 104. The IMD 216 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. The IMD 216 extends along sidewalls of the dielectric layers 204 as well as sidewalls of the conductive layers 206. Further, the IMD 216 may be in contact with top surfaces of each of the conductive layers 206.As further illustrated in FIG. 17I, the IMD 216 is then subjected to a removal process to remove excess dielectric material over the multilayer stack 104. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch back process, combinations thereof, or the like may be used. The planarization process exposes the multilayer stack 104 such that the top surfaces of the multilayer stack 104 and the IMD 216 are planar after the planarization process is completed.In FIG. 17J, portions of the interconnect structure 160 are formed. For simplifying the illustration, only one layer of the interconnection structure 160 is shown. In this embodiment, forming the interconnect structure 160 includes forming conductive contacts 166 through the IMD 216. The conductive contacts 166 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. The conductive contacts 166 are connected to the exposed portions of each of the conductive layers 206 (e.g., the word lines 116, discussed above).FIGS. 18A and 18B are three-dimensional views of transistors 54 according to various embodiments. Some features, such as dielectric layers 106, isolation regions 126, etc. (see FIGS. 16A through 16D ) are not shown for clarity. As already mentioned, the openings 130 (see FIGS. 12A and 12B ) for the bit lines 132B and the source lines 132S may be formed to extend laterally into the semiconductor layers 124, but need not. In the embodiment of FIG. 18A, the openings 130 (see FIGS. 12A and 12B ) for the bit lines 132B and the source lines 132S are not formed through the semiconductor layers 124, and thus the bit lines 132B and the source lines 132S are conductive pillars with smooth sidewalls that do not extend into the sidewall recess 112 and that are separated from portions of the memory layers 128 by the semiconductor layers 124 / isolation regions 126. In the embodiment of FIG. 18B, openings 130 (see FIGS. 12A and 12B ) for the bit lines 132B and the source lines 132S are formed through the semiconductor layers 124, and thus the bit lines 132B and the source lines 132S include protruding portions that extend into the sidewall recesses 112.FIG. 19 is a three-dimensional view of a memory array 50 at an intermediate stage in fabrication, in accordance with some other embodiments. This embodiment is similar to the embodiment of FIG. 15D, except that when patterning the semiconductor layer 122 (see FIG. 10 ) to form the semiconductor layers 124, the portions of the semiconductor layer 122 (see FIG. 10 ) outside of the sidewall recesses 112 are not removed. Consequently, the semiconductor layers 124 are not separated from vertically adjacent transistors. It should be understood that over the intermediate structure of FIG. 19, an interconnect structure may be formed in a similar manner as described with reference to FIGS. 16A-17J. Further, this embodiment may be formed with bit lines 132B and source lines 132S that are conductive pillars with smooth sidewalls (see FIG. 18A ) or that include protruding portions that extend into the sidewall recesses 112 (see FIG. 18B ).FIG. 20 is a three-dimensional view of a memory array 50 at an intermediate stage in fabrication, in accordance with some other embodiments. This embodiment is similar to the embodiment of FIG. 15D, except that both the semiconductor layers 124 and the memory layers 128 only partially fill the sidewall recesses 112. Therefore, the isolation regions 126 are also formed to fill the remaining portions of the sidewall recess 112. It should be understood that over the intermediate structure of FIG. 20, an interconnect structure may be formed in a similar manner as described with reference to FIGS. 16A-17J. Further, this embodiment may be formed with bit lines 132B and source lines 132S that are conductive pillars with smooth sidewalls (see FIG. 18A ) or that include protruding portions that extend into the sidewall recesses 112 (see FIG. 18B ).FIG. 21 is a view of an intermediate phase in fabricating a memory array 50 in accordance with some other embodiments. FIG. 21 is a cross-sectional view taken along reference cross section B-B in FIG. 15D. A portion of a memory array 50 is illustrated. Some features, such as the staircase arrangement of the word lines (see FIG. 1A ), are not shown in some figures for clarity.FIG. 21 illustrates a similar processing step to FIG. 6, e.g., showing the definition of word lines 116. However, in this embodiment, the sidewall recesses 112 are formed in a manner different from the steps described with reference to Figs. 4 to 6. In particular, each of the conductive layers 108 alternately includes first conductive sub-layers 108A and second conductive sub-layers 108B. For example, FIG. 21 illustrates that each conductive layer 108 includes a first one of the conductive sub-layers 108A disposed between two of the second conductive sub-layers 108B. As will be described in more detail below with reference to FIG. 22, the conductive layers 108 may include any desired number of conductive sub-layers 108A, 108B. The first conductive sub-layers 108A are formed of a first conductive material (which may be formed of the candidate materials of the conductive layers 108 as described with reference to FIG. 2 ) and the second conductive sub-layers 108B are formed of a second conductive material (which may be formed of the candidate materials of the conductive layers 108 as described with reference to FIG. 2 ), wherein the first conductive material is different from the second conductive material. In particular, the material of the first conductive sub-layers 108A has a high etch selectivity when etching the material of the second conductive sub-layer 108B. As such, in this embodiment, the sidewall recesses 112 may be formed after the processing step shown in FIG. 3. The sidewall recesses 112 may be formed by an acceptable etching process, such as one that is selective with respect to the material of the first conductive sub-layers 108A (e.g., that selectively removes the material of the first conductive sub-layers 108A at a higher rate than the materials of the second conductive sub-layers 108B). The etching may be isotropic. As a result of such processing, the protruding portions 116P of the word lines 116 (see FIGS. 7A, 7B, 7C, and 7D ) are formed of a different conductive material than the main portions 116M of the word lines 116 (see FIGS. 7A, 7B, 7C, and 7D ).FIG. 22 is a three-dimensional view of a memory array 50 at an intermediate stage in fabrication, in accordance with some other embodiments. This embodiment is similar to the embodiment of FIG. 15D, except that the word lines 116 include a plurality of sidewall recesses 112. By a process including the step described with reference to FIG. 21, the word lines 116 may be formed with a plurality of sidewall recesses 112. For example, each of the word lines 116 may be formed with a plurality of sidewall recesses 112 by forming each of the conductive layers 108 with two of the first conductive sub-layers 108A and three of the second conductive sub-layers 108B.In the embodiments described with reference to Figures 1 through 22, memory array 50 is formed over a substrate 102, such as a dielectric substrate. In some embodiments, memory array 50 is formed as part of a stand-alone device (e.g., a memory chip) that is integrated with other devices (e.g., a logic chip) by device packaging. In some embodiments, memory array 50 is embedded in another device, such as a logic chip. In such embodiments, the substrate 102 may be omitted or may be an underlying layer, such as an underlying dielectric layer, an underlying semiconductor substrate, or the like.FIG. 23 is a cross-sectional view of a semiconductor device 300 according to some embodiments. FIG. 23 is a cross-sectional view taken along reference cross section C-C in FIG. 16D. Figure 23 is a simplified representation with some features omitted for clarity. The semiconductor device 300 includes a logic region 300L and a memory region 300M. Memory devices (e.g., memories) are formed in the memory region 300M, and logic devices (e.g., logic circuits) are formed in the logic region 300L. For example, a memory array 50 (see FIG. 1 ) may be formed in the memory region 300M, and logic devices may be formed in the logic region 300L. The memory area 300M may be disposed at an edge of the logic area 300L, or the logic area 300L may surround the memory area 300M.The logic region 300L and the memory region 300M are formed over the same semiconductor substrate 302. The semiconductor substrate 302 may be doped or undoped silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 302 may include other semiconductor materials such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.The devices 304 are formed on the active surface of the semiconductor substrate 302. The devices 304 may be active devices or passive devices. For example, the electrical components may be transistors, diodes, capacitors, resistors or the like, which are formed by any suitable manufacturing method. The devices 304 are interconnected to form the memory devices and logic devices of the semiconductor device 300.One or more inter-layer dielectric layers (ILD) 306 are formed on the semiconductor substrate 302, and electrically conductive features, such as contact plugs 308, are electrically connected to the devices 304. The ILD layer(s) 306 may be(can) formed of any suitable dielectric material, for example, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), or the like, nitride such as silicon nitride, or the like. The ILD layer(s) may be(can) formed by any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), the like, or a combination thereof. The electrically conductive features in the ILD layer(s) may be formed by any suitable process, such as deposition, damascene process (e.g., single damascene process, dual damascene process, etc.), the like, or combinations thereof.Over the semiconductor substrate 302, an interconnection structure 310 is formed. The interconnect structure 310 interconnects the devices 304 to form integrated circuits in both the logic region 300L and the memory region 300M. The interconnection structure 310 comprises a plurality of metallization layers M 1 to M 5. Although five metallization layers are illustrated, it should be understood that more or fewer metallization layers may be included. Each of the metallization layers M 1 to M 5 includes metallization structures in dielectric layers. The metallization structures are connected to the devices 304 of the semiconductor substrate 302 and include metal lines L 1 to L 5 and metal vias V 1 to V 5, respectively, formed in one or more inter-metal dielectric (IMD) layers. The interconnect structure 310 may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like. In some embodiments, the contact plugs 308 are also part of the metallization structures, such as part of the lowermost layer of the metal vias V 1.In this embodiment, memory array 50 is formed in interconnect structure 310. The memory array 50 may be formed in one of the metallization layers M 1 to M 5 and is illustrated as being formed in a middle metallization layer M 4, but could also be formed in the lower metallization layers M 1 to M 3 or in the upper metallization layer M 5. Memory array 50 is electrically connected to devices 304. In this embodiment, a metallization layer overlying memory array 50 (e.g., metallization layer M 5) includes interconnects to source lines 132S and bit lines 132B. The metallization layer covering memory array 50 (e.g., metallization layer M 5) may also include interconnects to word lines 116, such as via conductive contacts 166 (see FIG. 17J ). In another embodiment, a metallization layer underlying memory array 50 (e.g., metallization layer M 3) includes interconnects to source lines 132S, bit lines 132B, and / or word lines 116.In some embodiments, the interconnect structure 310 may be formed by first forming the layers under the memory array 50, e.g., metallization layers M 1 to M 3. Thereafter, the memory array 50 may be formed on the metallization layer M 3, wherein the substrate 102 is an etch stop layer on the IMD of the metallization layer M 3. After forming the memory array 50, the remainder of the metallization layer M 4 may be formed, such as by depositing and planarizing the IMD for the metallization layer M 4 and then forming the metal lines M 4 and the metal vias M 4 (which may include the IMD 216 and the conductive contacts 166, see FIG. 17J ). Then, the layers (if present) covering the memory array 50, e.g., metallization layer M 5, may be formed.Embodiments may achieve advantages. Prior to forming the film stacks for the transistors 54, each wordline 116 may be formed with sidewall recesses by recessing sidewalls of the wordline 116 and re-depositing the conductive material of the wordline 116. The word lines 116 may be used to form the transistors 54 with three-dimensional channel regions 124C. Forming the transistors 54 with three-dimensional channel regions may enable improved performance of the transistors 54. For example, three-dimensional channel regions may cause stronger electric fields at lower gate voltages, a weaker ON current (I ON), improved ON / OFF current ratios, and fewer leakage currents than planar channel regions. Thus, memory arrays can be formed that are suitable for applications requiring high performance memories (e.g., artificial intelligence, high performance computing, etc.). Moreover, the read / write window of the memories and the reliability of the memories can be improved. Further, forming memory arrays having three-dimensional channel regions may allow for a reduction in the average size of the devices (e.g., transistors) in the memory arrays while maintaining sufficient performance. Thus, the density of memories can be improved.In one embodiment, a device includes a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a wordline between the first dielectric layer and the second dielectric layer, the wordline having an outer sidewall and an inner sidewall, the inner sidewall recessed relative to the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the wordline, the inner sidewall of the wordline, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.In some embodiments of the device, the wordline includes a connection surface extending between the outer sidewall and the inner sidewall, wherein the connection surface and the inner sidewall form a right angle. In some embodiments of the device, the wordline includes a connection surface extending between the outer sidewall and the inner sidewall, wherein the connection surface and the inner sidewall form an obtuse angle. In some embodiments of the device, the wordline includes a connection surface extending between the outer sidewall and the inner sidewall, the connection surface and the inner sidewall forming a sharp corner. In some embodiments of the device, the wordline includes a connection surface extending between the outer sidewall and the inner sidewall, the connection surface and the inner sidewall forming a rounded corner. In some embodiments of the device, the inner sidewall is recessed relative to the outer sidewall by a depth in the range of 10 nm to 50 nm. In some embodiments, the device further comprises: a bit line in contact with a sidewall of the semiconductor layer and a sidewall of the memory layer; a source line in contact with the sidewall of the semiconductor layer and the sidewall of the memory layer; and an isolation region between the source line and the bit line, the isolation region in contact with the sidewall of the semiconductor layer and the sidewall of the memory layer. In some embodiments, the device further comprises: a bit line contacting a sidewall of the semiconductor layer; a source line contacting the sidewall of the semiconductor layer; and an isolation region between the source line and the bit line, wherein the semiconductor layer separates a sidewall of the storage layer from both the source line and the bit line and from the isolation region. In some embodiments, the device further comprises: a bit line in contact with a sidewall of the semiconductor layer; a source line in contact with the sidewall of the semiconductor layer; and an isolation region between the source line and the bit line, wherein the semiconductor layer and the isolation region separate a sidewall of the memory layer from both the source line and the bit line.In an embodiment, a device comprises: a word line comprising a main portion, a first protruding portion, and a second protruding portion, the first protruding portion and the second protruding portion respectively extending away from opposite sides of the main portion; a memory layer extending along the word line, a portion of the memory layer being disposed between the first protruding portion and the second protruding portion of the word line; a semiconductor layer extending along the memory layer, a portion of the semiconductor layer being disposed between the first protruding portion and the second protruding portion of the word line; and a conductive line extending along the semiconductor layer.In some embodiments of the device, a portion of the conductive line is arranged between the first protruding portion and the second protruding portion of the word line. In some embodiments of the device, a portion of the semiconductor layer is disposed between the conductive line and the main portion of the word line. In some embodiments of the device, the thickness of the first protruding portion and the second protruding portion, respectively, is 5% to 30% of the thickness of the main portion.In one embodiment, a method includes: forming a first conductive material between layers of a dielectric material; recessing a sidewall of the first conductive material relative to the sidewalls of the dielectric material to form a sidewall recess; depositing a second conductive material in the sidewall recess; patterning the second conductive material to define a word line including the first conductive material and the second conductive material; forming a memory layer in the sidewall recess, the memory layer in contact with the word line; and forming a semiconductor layer in contact with the memory layer.In some embodiments of the method, the first conductive material and the second conductive material are the same conductive material. In some embodiments of the method, the first conductive material and the second conductive material are different conductive materials. In some embodiments of the method, patterning the second conductive material comprises: etching the second conductive material to remove portions of the second conductive material on the sidewalls of the dielectric material. In some embodiments of the method, the etching the second conductive material comprises: performing anisotropic dry etching using a fluorine-based gas mixed with oxygen. In some embodiments of the method, the anisotropic dry etch removes the second conductive material 2 to 5 times faster than the dielectric material. In some embodiments of the method, the sidewall recess has a depth in the range of 10 nm to 50 nm after depositing the second conductive material.

Claims

A device comprising: a first dielectric layer (106) having a first sidewall; a second dielectric layer (106) having a second sidewall; a word line (116) between the first dielectric layer (106) and the second dielectric layer (106), the word line (116) having an outer sidewall (116S 1) and an inner sidewall (116S 2) the inner sidewall (116S 2) being recessed relative to the outer sidewall (116S 1), the first sidewall and the second sidewall; a memory layer (120) extending along the outer sidewall (116S 1) of the word line (116), the inner sidewall (116S 2) of the word line (116), the first sidewall of the first dielectric layer (106), and the second sidewall of the second dielectric layer (106); and a semiconductor layer (122) extending along the memory layer (120), the word line (116) having an I-carrier shape, and a bit line contacting a sidewall of the semiconductor layer (122) and a sidewall of the memory layer (120); a source line contacting the sidewall of the semiconductor layer (122) and the sidewall of the memory layer (120); an isolation region (126) between the source line and the bit line, the isolation region (126) being in contact with the sidewall of the semiconductor layer (122) and the sidewall of the memory layer (120).The device of claim 1, wherein the wordline (116) includes a connection surface (116S 3) extending between the outer sidewall (116S 1) and the inner sidewall (116S 2) wherein the connection surface (116S 3) and the inner sidewall (116S 2) form a right angle.The device of claim 1, wherein the wordline (116) has a connection surface extending between the outer sidewall (116S 1) and the inner sidewall (116S 2) wherein the connection surface (116S 3) and the inner sidewall (116S 2) form an obtuse angle.The device of claim 1, wherein the wordline (116) includes a connection surface (116S 3) extending between the outer sidewall (116S 1) and the inner sidewall (116S 2) wherein the connection surface (116S 3) and the inner sidewall (116S 2) form a sharp corner.The device of claim 1, wherein the wordline (116) includes a connection surface (116S 3) extending between the outer sidewall (116S 1) and the inner sidewall (116S 2) wherein the connection surface (116S 3) and the inner sidewall (116S 2) form a rounded corner.The device of any of claims 1 to 5, wherein the inner sidewall (116S 2) is recessed relative to the outer sidewall (116S 1) by a depth in the range of 10 nm to 50 nm.The device of any of claims 1 to 6, wherein the semiconductor layer (122) separates another sidewall of the memory layer (120) from both the source line and the bit line and the isolation region (126).The device of any of claims 1 to 6, wherein the semiconductor layer (122) and the isolation region (126) separate another sidewall of the storage layer (120) from both the source line and the bit line.A device comprising: a word line (116) comprising a main portion (116M), a pair of first protruding portions (116P), and a pair of second protruding portions (116P), the first protruding portions (116P) and the second protruding portions (116P) each extending away from opposite sides of the main portion (116M); a memory layer (120) extending along the word line (116), a portion of the memory layer (120) each being disposed between a first protruding portion (116P) and a second protruding portion (116P) of the word line (116); a semiconductor layer (122) extending along the memory layer (122), a portion of the semiconductor layer (122) being disposed between a first protruding portion (116P) and a second protruding portion (116P) of the word line (116), respectively; and a conductive line (132) extending along the semiconductor layer (122), a portion of the conductive line (132) being disposed between the first protruding portion (116P) and the second protruding portion (116P) of the word line (116).The device of claim 9, wherein the thickness of the first protruding portion (116P) and the second protruding portion (116P), respectively, is 5% to 30% of the thickness of the main portion (116M).A method comprising: forming a first conductive material (108) between layers of a dielectric material (106); recessing a sidewall of the first conductive material (108) relative to the sidewalls of the dielectric material (106) to form a sidewall recess (112); depositing a second conductive material (114) in the sidewall recess (112); patterning the second conductive material (114) to define a wordline (116) comprising the first conductive material (108) and the second conductive material (114); forming a memory layer (120) in the sidewall recess (112), wherein the memory layer (120) is in contact with the wordline (116); and forming a semiconductor layer (122) in contact with the memory layer (120).The method of claim 11, wherein the first conductive material (108) and the second conductive material (114) are the same conductive material.The method of claim 11, wherein the first conductive material (108) and the second conductive material (114) are different conductive materials.The method of any of claims 11 to 13, wherein patterning the second conductive material (114) comprises: etching the second conductive material (114) to remove portions of the second conductive material (114) on the sidewalls of the dielectric material (106).The method of claim 14, wherein the etching of the second conductive material (114) comprises: performing anisotropic dry etching using a fluorine-based gas mixed with oxygen.The method of claim 15, wherein the anisotropic dry etch removes the second conductive material (114) 2 to 5 times faster than the dielectric material (106).The method of any of claims 11 to 16, wherein the sidewall recess (112) has a depth in the range of 10 nm to 50 nm after depositing the second conductive material (114).

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